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Fixed MTP to work with TWRP

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This commit is contained in:
awab228 2018-06-19 23:16:04 +02:00
commit f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
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1068
drivers/soc/samsung/pwrcal/S5E7570/S5E7570-asv.c Normal file
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File diff suppressed because it is too large Load diff

1059
drivers/soc/samsung/pwrcal/S5E7570/S5E7570-cmu.c Normal file
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File diff suppressed because it is too large Load diff

810
drivers/soc/samsung/pwrcal/S5E7570/S5E7570-cmu.h Normal file
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#ifndef __EXYNOS7570_CMU_H__
#define __EXYNOS7570_CMU_H__
#include "../pwrcal-clk.h"
enum clk_id {
OSCCLK = fixed_rate_type,
OSCCLK_FM_52M,
CLK_MIF_DDRPHY0,
TCXO, /*52MHZ*/
WIFI2AP_USBPLL_CLK,
CLKPHY_FSYS_USB20DRD_PHYCLOCK,
CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS,
CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0,
CLKIO_DISPAUD_MIXER_BCLK_CP,
CLKPHY_ISP_S_RXBYTECLKHS0_S4,
NUM_OF_FIXED_RATE_TYPE = CLKPHY_ISP_S_RXBYTECLKHS0_S4 - fixed_rate_type + 1,
MIF_FF_SHARED0_PLL_DIV2 = fixed_factor_type,
MIF_FF_SHARED1_PLL_DIV2,
MIF_FF_SHARED2_PLL_DIV2,
NUM_OF_FIXED_FACTOR_TYPE = MIF_FF_SHARED2_PLL_DIV2 - fixed_factor_type + 1,
CPUCL0_PLL = pll_type,
SHARED0_PLL,
SHARED1_PLL,
SHARED2_PLL,
AUD_PLL,
WPLL_USB_PLL,
NUM_OF_PLL_TYPE = WPLL_USB_PLL - pll_type + 1,
CPUCL0_MUX_CPUCL0_PLL = mux_type,
CPUCL0_MUX_CLK_CPUCL0,
DISPAUD_MUX_AUD_PLL,
MIF_MUX_SHARED0_PLL,
MIF_MUX_SHARED1_PLL,
MIF_MUX_SHARED2_PLL,
MIF_MUX_CLK_MIF_PHY_CLK,
MIF_MUX_CLK_MIF_PHY_CLK_A,
MIF_MUX_CLK_MIF_PHY_CLK_B,
MIF_MUX_CLK_MIF_BUSD,
MIF_MUX_CLKCMU_G3D,
MIF_MUX_CLKCMU_ISP_VRA,
MIF_MUX_CLKCMU_ISP_CAM,
MIF_MUX_CLKCMU_DISPAUD_BUS,
MIF_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK,
MIF_MUX_CLKCMU_MFCMSCL_MSCL,
MIF_MUX_CLKCMU_MFCMSCL_MFC,
MIF_MUX_CLKCMU_FSYS_BUS,
MIF_MUX_CLKCMU_FSYS_MMC0,
MIF_MUX_CLKCMU_FSYS_MMC2,
MIF_MUX_CLKCMU_FSYS_USB20DRD_REFCLK,
MIF_MUX_CLKCMU_PERI_BUS,
MIF_MUX_CLKCMU_PERI_UART_DEBUG,
MIF_MUX_CLKCMU_PERI_UART_SENSOR,
MIF_MUX_CLKCMU_PERI_SPI_REARFROM,
MIF_MUX_CLKCMU_PERI_SPI_ESE,
MIF_MUX_CLKCMU_PERI_USI_0,
MIF_MUX_CLKCMU_PERI_USI_1,
MIF_MUX_CLKCMU_APM,
MIF_MUX_CLKCMU_ISP_SENSOR0,
/* user_mux_type */
APM_MUX_CLKCMU_APM_USER = MIF_MUX_CLKCMU_ISP_SENSOR0 + 0x1001,
CPUCL0_MUX_CLKCMU_CPUCL0_SWITCH_USER,
DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER,
DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER,
DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER,
DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER,
DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER,
FSYS_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER,
G3D_MUX_CLKCMU_G3D_USER,
ISP_MUX_CLKCMU_ISP_VRA_USER,
ISP_MUX_CLKCMU_ISP_CAM_USER,
ISP_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER,
MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER,
MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER,
NUM_OF_MUX_TYPE = MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER - 0x1000 - mux_type + 1,
CPUCL0_DIV_CLK_CPUCL0_1 = div_type,
CPUCL0_DIV_CLK_CPUCL0_2,
CPUCL0_DIV_CLK_CPUCL0_ACLK,
CPUCL0_DIV_CLK_CPUCL0_PCLK,
CPUCL0_DIV_CLK_CPUCL0_ATCLK,
CPUCL0_DIV_CLK_CPUCL0_PCLKDBG,
CPUCL0_DIV_CLK_CPUCL0_CNTCLK,
CPUCL0_DIV_CLK_CPUCL0_RUN_MONITOR,
CPUCL0_DIV_CLK_CPUCL0_HPM,
CPUCL0_DIV_CLK_CPUCL0_PLL,
DISPAUD_DIV_CLK_DISPAUD_APB,
DISPAUD_DIV_CLK_DISPAUD_DECON_INT_VCLK,
DISPAUD_DIV_CLK_DISPAUD_DECON_INT_ECLK,
DISPAUD_DIV_CLK_DISPAUD_MI2S,
DISPAUD_DIV_CLK_DISPAUD_MIXER,
DISPAUD_DIV_CLK_DISPAUD_OSCCLK_FM_52M_DIV,
G3D_DIV_CLK_G3D_BUS,
G3D_DIV_CLK_G3D_APB,
ISP_DIV_CLK_ISP_CAM_HALF,
MFCMSCL_DIV_CLK_MFCMSCL_APB,
MIF_DIV_CLK_MIF_PHY_CLK2X,
MIF_DIV_CLK_MIF_PHY_CLKM,
MIF_DIV_CLKCMU_CP_SHARED0_PLL,
MIF_DIV_CLKCMU_CP_SHARED1_PLL,
MIF_DIV_CLKCMU_CP_SHARED2_PLL,
MIF_DIV_CLK_MIF_BUSD,
MIF_DIV_CLK_MIF_APB,
MIF_DIV_CLKCMU_CPUCL0_SWITCH,
MIF_DIV_CLKCMU_G3D,
MIF_DIV_CLKCMU_ISP_VRA,
MIF_DIV_CLKCMU_ISP_CAM,
MIF_DIV_CLKCMU_DISPAUD_BUS,
MIF_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK,
MIF_DIV_CLKCMU_MFCMSCL_MSCL,
MIF_DIV_CLKCMU_MFCMSCL_MFC,
MIF_DIV_CLKCMU_FSYS_BUS,
MIF_DIV_CLKCMU_FSYS_MMC0,
MIF_DIV_CLKCMU_FSYS_MMC2,
MIF_DIV_CLKCMU_FSYS_USB20DRD_REFCLK,
MIF_DIV_CLKCMU_PERI_BUS,
MIF_DIV_CLKCMU_PERI_UART_DEBUG,
MIF_DIV_CLKCMU_PERI_UART_SENSOR,
MIF_DIV_CLKCMU_PERI_SPI_REARFROM,
MIF_DIV_CLKCMU_PERI_SPI_ESE,
MIF_DIV_CLKCMU_PERI_USI_0,
MIF_DIV_CLKCMU_PERI_USI_1,
MIF_DIV_CLKCMU_APM,
MIF_DIV_CLKCMU_ISP_SENSOR0,
MIF_DIV_CLKCMU_GNSS_EXTPLL_SCAN,
PERI_DIV_CLK_PERI_USI_0_SPI,
PERI_DIV_CLK_PERI_USI_1_SPI,
NUM_OF_DIV_TYPE = PERI_DIV_CLK_PERI_USI_1_SPI - div_type + 1,
APM_GATE_CLK_APM_UID_APM_IPCLKPORT_ACLK_SYS = gate_type,
APM_GATE_CLK_APM_UID_APM_IPCLKPORT_ACLK_CPU,
APM_GATE_CLK_APM_UID_ASYNCS_APM_IPCLKPORT_I_CLK,
APM_GATE_CLK_APM_UID_ASYNCM_APM_IPCLKPORT_I_CLK,
CPUCL0_GATE_CLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_CLK,
CPUCL0_GATE_CLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_I_CLK__PMU_CPUCL0,
CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_D_CPUCL0_IPCLKPORT_I_CLK,
CPUCL0_GATE_CLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK,
CPUCL0_GATE_CLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_PCLK,
CPUCL0_GATE_CLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_I_PCLK,
CPUCL0_GATE_CLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK,
CPUCL0_GATE_CLK_CPUCL0_UID_BUSP1_CPUCL0_IPCLKPORT_ACLK,
CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCM_P_CPUCL0_IPCLKPORT_I_CLK,
CPUCL0_GATE_CLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_ATCLK,
CPUCL0_GATE_CLK_CPUCL0_UID_SECJTAG_IPCLKPORT_i_clk,
CPUCL0_GATE_CLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLKDBG,
CPUCL0_GATE_CLK_CPUCL0_UID_DBG_MUX_CPUCL0_IPCLKPORT_I_CLK,
CPUCL0_GATE_CLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG,
CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_CSSYS_DBG_IPCLKPORT_PCLKS,
CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_T_CSSYS_DBG_IPCLKPORT_ACLK,
CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCM_P_CSSYS_DBG_IPCLKPORT_PCLKM,
CPUCL0_GATE_CLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_I_HPM_TARGETCLK_C,
DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_OSCCLK,
DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_PPMU,
DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_DISP,
DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_VPP,
DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS,
DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_FM,
DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD_AMP,
DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD,
DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_DISP,
DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB,
DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_APB_SECURE_SMMU_DISP,
DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_VCLK,
DISPAUD_GATE_CLK_DISPAUD_UID_DSIM0_IPCLKPORT_I_TXBYTECLKHS,
DISPAUD_GATE_CLK_DISPAUD_UID_DSIM0_IPCLKPORT_I_RXCLKESC0,
DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AMP_IPCLKPORT_I2SCODCLKI,
DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AUD_IPCLKPORT_I2SCODCLKI,
DISPAUD_GATE_CLK_DISPAUD_UID_MIXER_AUD_IPCLKPORT_SYSCLK,
DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_CP2AUD_BCK,
DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_OSCCLK_FM_52M,
DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_OSCCLK_FM_52M_DIV,
FSYS_GATE_CLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_CLK,
FSYS_GATE_CLK_FSYS_UID_PMU_FSYS_IPCLKPORT_I_CLK__PMU_FSYS,
FSYS_GATE_CLK_FSYS_UID_BUSD1_FSYS_IPCLKPORT_ACLK,
FSYS_GATE_CLK_FSYS_UID_BUSD0_FSYS_IPCLKPORT_ACLK,
FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HCLK_USB20_CTRL,
FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_HSDRD,
FSYS_GATE_CLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK,
FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK,
FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK,
FSYS_GATE_CLK_FSYS_UID_PMU_FSYS_IPCLKPORT_I_PCLK,
FSYS_GATE_CLK_FSYS_UID_ASYNCS_D_FSYS_IPCLKPORT_I_CLK,
FSYS_GATE_CLK_FSYS_UID_ASYNCM_P_FSYS_IPCLKPORT_I_CLK,
FSYS_GATE_CLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK,
FSYS_GATE_CLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK,
FSYS_GATE_CLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK,
FSYS_GATE_CLK_FSYS_UID_BR_BUSP1_FSYS_IPCLKPORT_aclk,
FSYS_GATE_CLK_FSYS_UID_BUSP5_FSYS_IPCLKPORT_HCLK,
FSYS_GATE_CLK_FSYS_UID_BUSP3_FSYS_IPCLKPORT_HCLK,
FSYS_GATE_CLK_FSYS_UID_BUSP2_FSYS_IPCLKPORT_HCLK,
FSYS_GATE_CLK_FSYS_UID_BUSP1_FSYS_IPCLKPORT_HCLK,
FSYS_GATE_CLK_FSYS_UID_RTIC_IPCLKPORT_i_PCLK,
FSYS_GATE_CLK_FSYS_UID_RTIC_IPCLKPORT_i_ACLK,
FSYS_GATE_CLK_FSYS_UID_SSS_IPCLKPORT_i_PCLK,
FSYS_GATE_CLK_FSYS_UID_SSS_IPCLKPORT_i_ACLK,
FSYS_GATE_CLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN,
FSYS_GATE_CLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_ref_clk,
FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_PHYCLOCK,
FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_USB20_CLKCORE_0,
G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_CLK,
G3D_GATE_CLK_G3D_UID_PMU_G3D_IPCLKPORT_I_CLK__PMU_G3D,
G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_ACLK,
G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_ACLK,
G3D_GATE_CLK_G3D_UID_G3D_IPCLKPORT_CLK,
G3D_GATE_CLK_G3D_UID_REGSLICE_D1_G3D_IPCLKPORT_aclk,
G3D_GATE_CLK_G3D_UID_REGSLICE_D0_G3D_IPCLKPORT_aclk,
G3D_GATE_CLK_G3D_UID_IXIU_D_G3D_IPCLKPORT_ACLK,
G3D_GATE_CLK_G3D_UID_ASYNCS_D1_G3D_IPCLKPORT_I_CLK,
G3D_GATE_CLK_G3D_UID_ASYNCS_D0_G3D_IPCLKPORT_I_CLK,
G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKM,
G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK,
G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_PCLK,
G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_PCLK,
G3D_GATE_CLK_G3D_UID_PMU_G3D_IPCLKPORT_I_PCLK,
G3D_GATE_CLK_G3D_UID_BUSP_G3D_IPCLKPORT_ACLK,
G3D_GATE_CLK_G3D_UID_ASYNCM_P_G3D_IPCLKPORT_I_CLK,
G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKS,
G3D_GATE_CLK_G3D_UID_CFW_G3D_IPCLKPORT_ACLK,
G3D_GATE_CLK_G3D_UID_CFW_G3D_IPCLKPORT_PCLK,
ISP_GATE_CLK_ISP_UID_CLK_ISP_OSCCLK,
ISP_GATE_CLK_ISP_UID_CLK_ISP_VRA,
ISP_GATE_CLK_ISP_UID_CLK_ISP_CAM,
ISP_GATE_CLK_ISP_UID_CLKPHY_ISP_S_RXBYTECLKHS0_S4,
MFCMSCL_GATE_CLK_MFCMSCL_UID_CLK_MFCMSCL_OSCCLK,
MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_BI,
MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_D,
MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_JPEG,
MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_POLY,
MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_MFC,
MFCMSCL_GATE_CLK_MFCMSCL_UID_CLK_MFCMSCL_APB,
MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_APB_SMMU_MSCL,
MIF_GATE_CLK_MIF_UID_OTP_DESERIAL_MIF_IPCLKPORT_I_CLK,
MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_RCLK,
MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_I_OSC_SYS,
MIF_GATE_CLK_MIF_UID_SYSREG_MIF_IPCLKPORT_CLK,
MIF_GATE_CLK_MIF_UID_PMU_MIF_IPCLKPORT_I_CLK__PMU_MIF_JV,
MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_clk,
MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_clkm,
MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_APB_ACLK,
MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_SECURE_APB_ACLK,
MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PEREV_CLK,
MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_MEMIF_WR_CLK,
MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_MEMIF_RD_CLK,
MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_MEMIF_CLK,
MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_SCH_SLICE1_CLK,
MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_SCH_SLICE0_CLK,
MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_SCH_CLK,
MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_VCF_WR_CLK,
MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_VCF_RD_CLK,
MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_VCF_CLK,
MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_ACLK,
MIF_GATE_CLK_MIF_UID_PPMU_CPU_IPCLKPORT_ACLK,
MIF_GATE_CLK_MIF_UID_QE_DMC0_CPU_IPCLKPORT_ACLK,
MIF_GATE_CLK_MIF_UID_ASYNCM_CPUCL0_IPCLKPORT_ACLK,
MIF_GATE_CLK_MIF_UID_ASYNCM_DBG_IPCLKPORT_ACLK,
MIF_GATE_CLK_MIF_UID_PDMA_MIF_IPCLKPORT_ACLK_PDMA0,
MIF_GATE_CLK_MIF_UID_CLEANY_WLBT_IPCLKPORT_ACLK,
MIF_GATE_CLK_MIF_UID_CLEANY_GNSS_IPCLKPORT_ACLK,
MIF_GATE_CLK_MIF_UID_CLEANY_CEL_IPCLKPORT_ACLK,
MIF_GATE_CLK_MIF_UID_CPU0_MO_MON_IPCLKPORT_I_ACLK,
MIF_GATE_CLK_MIF_UID_PPMU_CPU_IPCLKPORT_PCLK,
MIF_GATE_CLK_MIF_UID_SPEEDY_BATCHER_WRAPPER_IPCLKPORT_PCLK_BATCHER_SPEEDY,
MIF_GATE_CLK_MIF_UID_SPEEDY_BATCHER_WRAPPER_IPCLKPORT_PCLK_BATCHER_CP,
MIF_GATE_CLK_MIF_UID_SPEEDY_BATCHER_WRAPPER_IPCLKPORT_PCLK_BATCHER_AP,
MIF_GATE_CLK_MIF_UID_SPEEDY_MIF_IPCLKPORT_PCLK,
MIF_GATE_CLK_MIF_UID_MAILBOX_WLBT_IPCLKPORT_CLK,
MIF_GATE_CLK_MIF_UID_MAILBOX_GNSS_IPCLKPORT_CLK,
MIF_GATE_CLK_MIF_UID_MAILBOX_CEL_IPCLKPORT_CLK,
MIF_GATE_CLK_MIF_UID_ASYNCAPB_MIF_CSSYS_IPCLKPORT_PCLKS,
MIF_GATE_CLK_MIF_UID_SYNC_INTC_SOC_IPCLKPORT_CLK,
MIF_GATE_CLK_MIF_UID_INTC_SOC_IPCLKPORT_CLK,
MIF_GATE_CLK_MIF_UID_AXI2APB_MIF_TREX_IPCLKPORT_ACLK,
MIF_GATE_CLK_MIF_UID_AXI2AHB_MIF_P_IPCLKPORT_HCLK,
MIF_GATE_CLK_MIF_UID_AHB2APB_MIF2_IPCLKPORT_HCLK,
MIF_GATE_CLK_MIF_UID_AHB2APB_MIF1_IPCLKPORT_HCLK,
MIF_GATE_CLK_MIF_UID_AHB2APB_MIF0_IPCLKPORT_HCLK,
MIF_GATE_CLK_MIF_UID_AHB_BRIDGE_MIF_IPCLKPORT_HCLK,
MIF_GATE_CLK_MIF_UID_QE_DMC0_CPU_IPCLKPORT_PCLK,
MIF_GATE_CLK_MIF_UID_DDRDMC0_APB_IPCLKPORT_PCLK,
MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_PF,
MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK,
MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_PCLK,
MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1,
MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0,
MIF_GATE_CLK_MIF_UID_GPIO_MIF_IPCLKPORT_PCLK,
MIF_GATE_CLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK,
MIF_GATE_CLK_MIF_UID_PMU_MIF_IPCLKPORT_I_PCLK,
MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_PF_SECURE,
MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_SECURE,
MIF_GATE_CLK_MIF_UID_MAILBOX_SECURE_IPCLKPORT_CLK,
MIF_GATE_CLKCMU_CP_SHARED0_PLL,
MIF_GATE_CLKCMU_CP_SHARED1_PLL,
MIF_GATE_CLKCMU_CP_SHARED2_PLL,
MIF_GATE_CLKCMU_CPUCL0_SWITCH,
MIF_GATE_CLKCMU_G3D,
MIF_GATE_CLKCMU_ISP_VRA,
MIF_GATE_CLKCMU_ISP_CAM,
MIF_GATE_CLKCMU_DISPAUD_BUS,
MIF_GATE_CLKCMU_DISPAUD_DECON_INT_VCLK,
MIF_GATE_CLKCMU_MFCMSCL_MFC,
MIF_GATE_CLKCMU_MFCMSCL_MSCL,
MIF_GATE_CLKCMU_FSYS_BUS,
MIF_GATE_CLKCMU_FSYS_MMC0,
MIF_GATE_CLKCMU_FSYS_MMC2,
MIF_GATE_CLKCMU_FSYS_USB20DRD_REFCLK,
MIF_GATE_CLKCMU_PERI_BUS,
MIF_GATE_CLKCMU_PERI_UART_DEBUG,
MIF_GATE_CLKCMU_PERI_UART_SENSOR,
MIF_GATE_CLKCMU_PERI_SPI_REARFROM,
MIF_GATE_CLKCMU_PERI_SPI_ESE,
MIF_GATE_CLKCMU_PERI_USI_0,
MIF_GATE_CLKCMU_PERI_USI_1,
MIF_GATE_CLKCMU_APM,
MIF_GATE_CLKCMU_ISP_SENSOR0,
MIF_GATE_CLKCMU_GNSS_TEST_EXTPLL_SCAN_CLK,
MIF_GATE_CLK_MIF_UID_SPEEDY_MIF_IPCLKPORT_CLK,
PERI_GATE_CLK_PERI_UID_TMU_CPUCL0_IPCLKPORT_I_CLK,
PERI_GATE_CLK_PERI_UID_SYSREG_PERI_IPCLKPORT_CLK,
PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_OSCCLK,
PERI_GATE_CLK_PERI_UID_PMU_PERI_IPCLKPORT_I_CLK__PMU_PERI,
PERI_GATE_CLK_PERI_UID_CHIPID_IPCLKPORT_CLK,
PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_PCLK_S0,
PERI_GATE_CLK_PERI_UID_PMU_PERI_IPCLKPORT_I_PCLK,
PERI_GATE_CLK_PERI_UID_MCT_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_I2C_SENSOR2_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_I2C_SENSOR1_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_I2C_TSP_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_I2C_FUELGAUGE_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_I2C_NFC_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_I2C_MUIC_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_HSI2C_FRONTCAM_IPCLKPORT_iPCLK,
PERI_GATE_CLK_PERI_UID_HSI2C_MAINCAM_IPCLKPORT_iPCLK,
PERI_GATE_CLK_PERI_UID_HSI2C_FRONTSENSOR_IPCLKPORT_iPCLK,
PERI_GATE_CLK_PERI_UID_HSI2C_REARAF_IPCLKPORT_iPCLK,
PERI_GATE_CLK_PERI_UID_HSI2C_REARSENSOR_IPCLKPORT_iPCLK,
PERI_GATE_CLK_PERI_UID_GPIO_TOUCH_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_GPIO_TOP_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_GPIO_NFC_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_GPIO_ESE_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_BUSP1_PERIS1_IPCLKPORT_HCLK,
PERI_GATE_CLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK,
PERI_GATE_CLK_PERI_UID_BUSP1_PERIC1_IPCLKPORT_HCLK,
PERI_GATE_CLK_PERI_UID_BUSP1_PERIC0_IPCLKPORT_HCLK,
PERI_GATE_CLK_PERI_UID_BUSP_BR_PERIC_IPCLKPORT_HCLK,
PERI_GATE_CLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_aclk,
PERI_GATE_CLK_PERI_UID_ASYNCM_PERI_IPCLKPORT_I_CLK,
PERI_GATE_CLK_PERI_UID_USI_1_IPCLKPORT_i_PCLK,
PERI_GATE_CLK_PERI_UID_USI_0_IPCLKPORT_i_PCLK,
PERI_GATE_CLK_PERI_UID_WDT_CPUCL0_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_SFRIF_TMU_CPUCL0_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_SFRIF_GPIO_ALIVE_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_TZPC10_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_TZPC9_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_TZPC8_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_TZPC7_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_TZPC6_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_TZPC5_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_TZPC4_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_TZPC3_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_TZPC2_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_TZPC1_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_TZPC0_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_SFRIF_CHIPID_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_SFRIF_RTC_ALIVE_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_SFRIF_RTC_TOP_IPCLKPORT_PCLK,
PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_EXT_UCLK,
PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_EXT_UCLK,
PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_SPI_EXT_CLK,
PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_SPI_EXT_CLK,
PERI_GATE_CLK_PERI_UID_USI_0_IPCLKPORT_i_SCLK_UART,
PERI_GATE_CLK_PERI_UID_USI_1_IPCLKPORT_i_SCLK_UART,
PERI_GATE_CLK_PERI_UID_USI_0_IPCLKPORT_i_SCLK_SPI,
PERI_GATE_CLK_PERI_UID_USI_1_IPCLKPORT_i_SCLK_SPI,
MIF_MUXGATE_CLKCMU_ISP_VRA,
MIF_MUXGATE_CLKCMU_ISP_CAM,
MIF_MUXGATE_CLKCMU_DISPAUD_BUS,
MIF_MUXGATE_CLKCMU_DISPAUD_DECON_INT_VCLK,
MIF_MUXGATE_CLKCMU_MFCMSCL_MSCL,
MIF_MUXGATE_CLKCMU_MFCMSCL_MFC,
MIF_MUXGATE_CLKCMU_FSYS_BUS,
MIF_MUXGATE_CLKCMU_FSYS_MMC0,
MIF_MUXGATE_CLKCMU_FSYS_MMC2,
MIF_MUXGATE_CLKCMU_FSYS_USB20DRD_REFCLK,
MIF_MUXGATE_CLKCMU_PERI_BUS,
MIF_MUXGATE_CLKCMU_PERI_UART_DEBUG,
MIF_MUXGATE_CLKCMU_PERI_UART_SENSOR,
MIF_MUXGATE_CLKCMU_PERI_SPI_REARFROM,
MIF_MUXGATE_CLKCMU_PERI_SPI_ESE,
MIF_MUXGATE_CLKCMU_PERI_USI_0,
MIF_MUXGATE_CLKCMU_PERI_USI_1,
MIF_MUXGATE_CLKCMU_APM,
MIF_MUXGATE_CLKCMU_ISP_SENSOR0,
PMU_DEBUG_CLKOUT_SEL08,
PMU_DEBUG_CLKOUT_SEL09,
PMU_DEBUG_CLKOUT_SEL10,
PMU_DEBUG_CLKOUT_SEL11,
PMU_DEBUG_CLKOUT_SEL12,
PMU_DEBUG_CLKOUT_DISABLE,
NUM_OF_GATE_TYPE = PMU_DEBUG_CLKOUT_DISABLE - gate_type + 1,
};
FIXEDRATE_EXTERN(OSCCLK)
FIXEDRATE_EXTERN(OSCCLK_FM_52M)
FIXEDRATE_EXTERN(CLK_MIF_DDRPHY0)
FIXEDRATE_EXTERN(TCXO)
FIXEDRATE_EXTERN(WIFI2AP_USBPLL_CLK)
FIXEDRATE_EXTERN(CLKPHY_FSYS_USB20DRD_PHYCLOCK)
FIXEDRATE_EXTERN(CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS)
FIXEDRATE_EXTERN(CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0)
FIXEDRATE_EXTERN(CLKIO_DISPAUD_MIXER_BCLK_CP)
FIXEDRATE_EXTERN(CLKPHY_ISP_S_RXBYTECLKHS0_S4)
FIXEDFACTOR_EXTERN(MIF_FF_SHARED0_PLL_DIV2)
FIXEDFACTOR_EXTERN(MIF_FF_SHARED1_PLL_DIV2)
FIXEDFACTOR_EXTERN(MIF_FF_SHARED2_PLL_DIV2)
PLL_EXTERN(CPUCL0_PLL)
PLL_EXTERN(SHARED0_PLL)
PLL_EXTERN(SHARED1_PLL)
PLL_EXTERN(SHARED2_PLL)
PLL_EXTERN(AUD_PLL)
PLL_EXTERN(WPLL_USB_PLL)
DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_1)
DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_2)
DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_ACLK)
DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_PCLK)
DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_ATCLK)
DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_PCLKDBG)
DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_CNTCLK)
DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_RUN_MONITOR)
DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_HPM)
DIV_EXTERN(CPUCL0_DIV_CLK_CPUCL0_PLL)
DIV_EXTERN(DISPAUD_DIV_CLK_DISPAUD_APB)
DIV_EXTERN(DISPAUD_DIV_CLK_DISPAUD_DECON_INT_VCLK)
DIV_EXTERN(DISPAUD_DIV_CLK_DISPAUD_DECON_INT_ECLK)
DIV_EXTERN(DISPAUD_DIV_CLK_DISPAUD_MI2S)
DIV_EXTERN(DISPAUD_DIV_CLK_DISPAUD_MIXER)
DIV_EXTERN(DISPAUD_DIV_CLK_DISPAUD_OSCCLK_FM_52M_DIV)
DIV_EXTERN(G3D_DIV_CLK_G3D_BUS)
DIV_EXTERN(G3D_DIV_CLK_G3D_APB)
DIV_EXTERN(ISP_DIV_CLK_ISP_CAM_HALF)
DIV_EXTERN(MFCMSCL_DIV_CLK_MFCMSCL_APB)
DIV_EXTERN(MIF_DIV_CLK_MIF_PHY_CLK2X)
DIV_EXTERN(MIF_DIV_CLK_MIF_PHY_CLKM)
DIV_EXTERN(MIF_DIV_CLKCMU_CP_SHARED0_PLL)
DIV_EXTERN(MIF_DIV_CLKCMU_CP_SHARED1_PLL)
DIV_EXTERN(MIF_DIV_CLKCMU_CP_SHARED2_PLL)
DIV_EXTERN(MIF_DIV_CLK_MIF_BUSD)
DIV_EXTERN(MIF_DIV_CLK_MIF_APB)
DIV_EXTERN(MIF_DIV_CLKCMU_CPUCL0_SWITCH)
DIV_EXTERN(MIF_DIV_CLKCMU_G3D)
DIV_EXTERN(MIF_DIV_CLKCMU_ISP_VRA)
DIV_EXTERN(MIF_DIV_CLKCMU_ISP_CAM)
DIV_EXTERN(MIF_DIV_CLKCMU_DISPAUD_BUS)
DIV_EXTERN(MIF_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK)
DIV_EXTERN(MIF_DIV_CLKCMU_MFCMSCL_MSCL)
DIV_EXTERN(MIF_DIV_CLKCMU_MFCMSCL_MFC)
DIV_EXTERN(MIF_DIV_CLKCMU_FSYS_BUS)
DIV_EXTERN(MIF_DIV_CLKCMU_FSYS_MMC0)
DIV_EXTERN(MIF_DIV_CLKCMU_FSYS_MMC2)
DIV_EXTERN(MIF_DIV_CLKCMU_FSYS_USB20DRD_REFCLK)
DIV_EXTERN(MIF_DIV_CLKCMU_PERI_BUS)
DIV_EXTERN(MIF_DIV_CLKCMU_PERI_UART_DEBUG)
DIV_EXTERN(MIF_DIV_CLKCMU_PERI_UART_SENSOR)
DIV_EXTERN(MIF_DIV_CLKCMU_PERI_SPI_REARFROM)
DIV_EXTERN(MIF_DIV_CLKCMU_PERI_SPI_ESE)
DIV_EXTERN(MIF_DIV_CLKCMU_PERI_USI_0)
DIV_EXTERN(MIF_DIV_CLKCMU_PERI_USI_1)
DIV_EXTERN(MIF_DIV_CLKCMU_APM)
DIV_EXTERN(MIF_DIV_CLKCMU_ISP_SENSOR0)
DIV_EXTERN(MIF_DIV_CLKCMU_GNSS_EXTPLL_SCAN)
DIV_EXTERN(PERI_DIV_CLK_PERI_USI_0_SPI)
DIV_EXTERN(PERI_DIV_CLK_PERI_USI_1_SPI)
MUX_EXTERN(APM_MUX_CLKCMU_APM_USER)
MUX_EXTERN(CPUCL0_MUX_CPUCL0_PLL)
MUX_EXTERN(CPUCL0_MUX_CLKCMU_CPUCL0_SWITCH_USER)
MUX_EXTERN(CPUCL0_MUX_CLK_CPUCL0)
MUX_EXTERN(DISPAUD_MUX_AUD_PLL)
MUX_EXTERN(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER)
MUX_EXTERN(DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER)
MUX_EXTERN(DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER)
MUX_EXTERN(DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER)
MUX_EXTERN(DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER)
MUX_EXTERN(FSYS_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER)
MUX_EXTERN(G3D_MUX_CLKCMU_G3D_USER)
MUX_EXTERN(ISP_MUX_CLKCMU_ISP_VRA_USER)
MUX_EXTERN(ISP_MUX_CLKCMU_ISP_CAM_USER)
MUX_EXTERN(ISP_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER)
MUX_EXTERN(MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER)
MUX_EXTERN(MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER)
MUX_EXTERN(MIF_MUX_SHARED0_PLL)
MUX_EXTERN(MIF_MUX_SHARED1_PLL)
MUX_EXTERN(MIF_MUX_SHARED2_PLL)
MUX_EXTERN(MIF_MUX_CLK_MIF_PHY_CLK)
MUX_EXTERN(MIF_MUX_CLK_MIF_PHY_CLK_A)
MUX_EXTERN(MIF_MUX_CLK_MIF_PHY_CLK_B)
MUX_EXTERN(MIF_MUX_CLK_MIF_BUSD)
MUX_EXTERN(MIF_MUX_CLKCMU_G3D)
MUX_EXTERN(MIF_MUX_CLKCMU_ISP_VRA)
MUX_EXTERN(MIF_MUX_CLKCMU_ISP_CAM)
MUX_EXTERN(MIF_MUX_CLKCMU_DISPAUD_BUS)
MUX_EXTERN(MIF_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK)
MUX_EXTERN(MIF_MUX_CLKCMU_MFCMSCL_MSCL)
MUX_EXTERN(MIF_MUX_CLKCMU_MFCMSCL_MFC)
MUX_EXTERN(MIF_MUX_CLKCMU_FSYS_BUS)
MUX_EXTERN(MIF_MUX_CLKCMU_FSYS_MMC0)
MUX_EXTERN(MIF_MUX_CLKCMU_FSYS_MMC2)
MUX_EXTERN(MIF_MUX_CLKCMU_FSYS_USB20DRD_REFCLK)
MUX_EXTERN(MIF_MUX_CLKCMU_PERI_BUS)
MUX_EXTERN(MIF_MUX_CLKCMU_PERI_UART_DEBUG)
MUX_EXTERN(MIF_MUX_CLKCMU_PERI_UART_SENSOR)
MUX_EXTERN(MIF_MUX_CLKCMU_PERI_SPI_REARFROM)
MUX_EXTERN(MIF_MUX_CLKCMU_PERI_SPI_ESE)
MUX_EXTERN(MIF_MUX_CLKCMU_PERI_USI_0)
MUX_EXTERN(MIF_MUX_CLKCMU_PERI_USI_1)
MUX_EXTERN(MIF_MUX_CLKCMU_APM)
MUX_EXTERN(MIF_MUX_CLKCMU_ISP_SENSOR0)
GATE_EXTERN(APM_GATE_CLK_APM_UID_APM_IPCLKPORT_ACLK_SYS)
GATE_EXTERN(APM_GATE_CLK_APM_UID_APM_IPCLKPORT_ACLK_CPU)
GATE_EXTERN(APM_GATE_CLK_APM_UID_ASYNCS_APM_IPCLKPORT_I_CLK)
GATE_EXTERN(APM_GATE_CLK_APM_UID_ASYNCM_APM_IPCLKPORT_I_CLK)
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_CLK)
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_I_CLK__PMU_CPUCL0)
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_D_CPUCL0_IPCLKPORT_I_CLK)
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK)
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_PCLK)
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_I_PCLK)
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK)
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_BUSP1_CPUCL0_IPCLKPORT_ACLK)
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCM_P_CPUCL0_IPCLKPORT_I_CLK)
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_ATCLK)
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_SECJTAG_IPCLKPORT_i_clk)
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLKDBG)
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_DBG_MUX_CPUCL0_IPCLKPORT_I_CLK)
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG)
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_CSSYS_DBG_IPCLKPORT_PCLKS)
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_T_CSSYS_DBG_IPCLKPORT_ACLK)
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCM_P_CSSYS_DBG_IPCLKPORT_PCLKM)
GATE_EXTERN(CPUCL0_GATE_CLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_I_HPM_TARGETCLK_C)
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_OSCCLK)
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_PPMU)
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_DISP)
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_VPP)
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS)
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_FM)
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD_AMP)
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD)
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_DISP)
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB)
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_APB_SECURE_SMMU_DISP)
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_VCLK)
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_DSIM0_IPCLKPORT_I_TXBYTECLKHS)
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_DSIM0_IPCLKPORT_I_RXCLKESC0)
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AMP_IPCLKPORT_I2SCODCLKI)
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AUD_IPCLKPORT_I2SCODCLKI)
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_MIXER_AUD_IPCLKPORT_SYSCLK)
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_CP2AUD_BCK)
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_OSCCLK_FM_52M)
GATE_EXTERN(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_OSCCLK_FM_52M_DIV)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_CLK)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_PMU_FSYS_IPCLKPORT_I_CLK__PMU_FSYS)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_BUSD1_FSYS_IPCLKPORT_ACLK)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_BUSD0_FSYS_IPCLKPORT_ACLK)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HCLK_USB20_CTRL)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_HSDRD)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_PMU_FSYS_IPCLKPORT_I_PCLK)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_ASYNCS_D_FSYS_IPCLKPORT_I_CLK)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_ASYNCM_P_FSYS_IPCLKPORT_I_CLK)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_BR_BUSP1_FSYS_IPCLKPORT_aclk)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_BUSP5_FSYS_IPCLKPORT_HCLK)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_BUSP3_FSYS_IPCLKPORT_HCLK)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_BUSP2_FSYS_IPCLKPORT_HCLK)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_BUSP1_FSYS_IPCLKPORT_HCLK)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_RTIC_IPCLKPORT_i_PCLK)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_RTIC_IPCLKPORT_i_ACLK)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_SSS_IPCLKPORT_i_PCLK)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_SSS_IPCLKPORT_i_ACLK)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_ref_clk)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_PHYCLOCK)
GATE_EXTERN(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_USB20_CLKCORE_0)
GATE_EXTERN(G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_CLK)
GATE_EXTERN(G3D_GATE_CLK_G3D_UID_PMU_G3D_IPCLKPORT_I_CLK__PMU_G3D)
GATE_EXTERN(G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_ACLK)
GATE_EXTERN(G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_ACLK)
GATE_EXTERN(G3D_GATE_CLK_G3D_UID_G3D_IPCLKPORT_CLK)
GATE_EXTERN(G3D_GATE_CLK_G3D_UID_REGSLICE_D1_G3D_IPCLKPORT_aclk)
GATE_EXTERN(G3D_GATE_CLK_G3D_UID_REGSLICE_D0_G3D_IPCLKPORT_aclk)
GATE_EXTERN(G3D_GATE_CLK_G3D_UID_IXIU_D_G3D_IPCLKPORT_ACLK)
GATE_EXTERN(G3D_GATE_CLK_G3D_UID_ASYNCS_D1_G3D_IPCLKPORT_I_CLK)
GATE_EXTERN(G3D_GATE_CLK_G3D_UID_ASYNCS_D0_G3D_IPCLKPORT_I_CLK)
GATE_EXTERN(G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKM)
GATE_EXTERN(G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK)
GATE_EXTERN(G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_PCLK)
GATE_EXTERN(G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_PCLK)
GATE_EXTERN(G3D_GATE_CLK_G3D_UID_PMU_G3D_IPCLKPORT_I_PCLK)
GATE_EXTERN(G3D_GATE_CLK_G3D_UID_BUSP_G3D_IPCLKPORT_ACLK)
GATE_EXTERN(G3D_GATE_CLK_G3D_UID_ASYNCM_P_G3D_IPCLKPORT_I_CLK)
GATE_EXTERN(G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKS)
GATE_EXTERN(G3D_GATE_CLK_G3D_UID_CFW_G3D_IPCLKPORT_ACLK)
GATE_EXTERN(G3D_GATE_CLK_G3D_UID_CFW_G3D_IPCLKPORT_PCLK)
GATE_EXTERN(ISP_GATE_CLK_ISP_UID_CLK_ISP_OSCCLK)
GATE_EXTERN(ISP_GATE_CLK_ISP_UID_CLK_ISP_VRA)
GATE_EXTERN(ISP_GATE_CLK_ISP_UID_CLK_ISP_CAM)
GATE_EXTERN(ISP_GATE_CLK_ISP_UID_CLKPHY_ISP_S_RXBYTECLKHS0_S4)
GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLK_MFCMSCL_OSCCLK)
GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_BI)
GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_D)
GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_JPEG)
GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_POLY)
GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_MFC)
GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLK_MFCMSCL_APB)
GATE_EXTERN(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_APB_SMMU_MSCL)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_OTP_DESERIAL_MIF_IPCLKPORT_I_CLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_RCLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_I_OSC_SYS)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_SYSREG_MIF_IPCLKPORT_CLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_PMU_MIF_IPCLKPORT_I_CLK__PMU_MIF_JV)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_clk)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_clkm)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_APB_ACLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_SECURE_APB_ACLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PEREV_CLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_MEMIF_WR_CLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_MEMIF_RD_CLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_MEMIF_CLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_SCH_SLICE1_CLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_SCH_SLICE0_CLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_SCH_CLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_VCF_WR_CLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_VCF_RD_CLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_VCF_CLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_ACLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_PPMU_CPU_IPCLKPORT_ACLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_QE_DMC0_CPU_IPCLKPORT_ACLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNCM_CPUCL0_IPCLKPORT_ACLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNCM_DBG_IPCLKPORT_ACLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_PDMA_MIF_IPCLKPORT_ACLK_PDMA0)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_CLEANY_WLBT_IPCLKPORT_ACLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_CLEANY_GNSS_IPCLKPORT_ACLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_CLEANY_CEL_IPCLKPORT_ACLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_CPU0_MO_MON_IPCLKPORT_I_ACLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_PPMU_CPU_IPCLKPORT_PCLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_SPEEDY_BATCHER_WRAPPER_IPCLKPORT_PCLK_BATCHER_SPEEDY)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_SPEEDY_BATCHER_WRAPPER_IPCLKPORT_PCLK_BATCHER_CP)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_SPEEDY_BATCHER_WRAPPER_IPCLKPORT_PCLK_BATCHER_AP)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_SPEEDY_MIF_IPCLKPORT_PCLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_MAILBOX_WLBT_IPCLKPORT_CLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_MAILBOX_GNSS_IPCLKPORT_CLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_MAILBOX_CEL_IPCLKPORT_CLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_ASYNCAPB_MIF_CSSYS_IPCLKPORT_PCLKS)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_SYNC_INTC_SOC_IPCLKPORT_CLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_INTC_SOC_IPCLKPORT_CLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_AXI2APB_MIF_TREX_IPCLKPORT_ACLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_AXI2AHB_MIF_P_IPCLKPORT_HCLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_AHB2APB_MIF2_IPCLKPORT_HCLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_AHB2APB_MIF1_IPCLKPORT_HCLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_AHB2APB_MIF0_IPCLKPORT_HCLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_AHB_BRIDGE_MIF_IPCLKPORT_HCLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_QE_DMC0_CPU_IPCLKPORT_PCLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DDRDMC0_APB_IPCLKPORT_PCLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_PF)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_PCLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_GPIO_MIF_IPCLKPORT_PCLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_PMU_MIF_IPCLKPORT_I_PCLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_PF_SECURE)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_SECURE)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_MAILBOX_SECURE_IPCLKPORT_CLK)
GATE_EXTERN(MIF_GATE_CLKCMU_CP_SHARED0_PLL)
GATE_EXTERN(MIF_GATE_CLKCMU_CP_SHARED1_PLL)
GATE_EXTERN(MIF_GATE_CLKCMU_CP_SHARED2_PLL)
GATE_EXTERN(MIF_GATE_CLKCMU_CPUCL0_SWITCH)
GATE_EXTERN(MIF_GATE_CLKCMU_G3D)
GATE_EXTERN(MIF_GATE_CLKCMU_ISP_VRA)
GATE_EXTERN(MIF_GATE_CLKCMU_ISP_CAM)
GATE_EXTERN(MIF_GATE_CLKCMU_DISPAUD_BUS)
GATE_EXTERN(MIF_GATE_CLKCMU_DISPAUD_DECON_INT_VCLK)
GATE_EXTERN(MIF_GATE_CLKCMU_MFCMSCL_MFC)
GATE_EXTERN(MIF_GATE_CLKCMU_MFCMSCL_MSCL)
GATE_EXTERN(MIF_GATE_CLKCMU_FSYS_BUS)
GATE_EXTERN(MIF_GATE_CLKCMU_FSYS_MMC0)
GATE_EXTERN(MIF_GATE_CLKCMU_FSYS_MMC2)
GATE_EXTERN(MIF_GATE_CLKCMU_FSYS_USB20DRD_REFCLK)
GATE_EXTERN(MIF_GATE_CLKCMU_PERI_BUS)
GATE_EXTERN(MIF_GATE_CLKCMU_PERI_UART_DEBUG)
GATE_EXTERN(MIF_GATE_CLKCMU_PERI_UART_SENSOR)
GATE_EXTERN(MIF_GATE_CLKCMU_PERI_SPI_REARFROM)
GATE_EXTERN(MIF_GATE_CLKCMU_PERI_SPI_ESE)
GATE_EXTERN(MIF_GATE_CLKCMU_PERI_USI_0)
GATE_EXTERN(MIF_GATE_CLKCMU_PERI_USI_1)
GATE_EXTERN(MIF_GATE_CLKCMU_APM)
GATE_EXTERN(MIF_GATE_CLKCMU_ISP_SENSOR0)
GATE_EXTERN(MIF_GATE_CLKCMU_GNSS_TEST_EXTPLL_SCAN_CLK)
GATE_EXTERN(MIF_GATE_CLK_MIF_UID_SPEEDY_MIF_IPCLKPORT_CLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TMU_CPUCL0_IPCLKPORT_I_CLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SYSREG_PERI_IPCLKPORT_CLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_OSCCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_PMU_PERI_IPCLKPORT_I_CLK__PMU_PERI)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_CHIPID_IPCLKPORT_CLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_PCLK_S0)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_PMU_PERI_IPCLKPORT_I_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_MCT_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_I2C_SENSOR2_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_I2C_SENSOR1_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_I2C_TSP_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_I2C_FUELGAUGE_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_I2C_NFC_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_I2C_MUIC_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_HSI2C_FRONTCAM_IPCLKPORT_iPCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_HSI2C_MAINCAM_IPCLKPORT_iPCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_HSI2C_FRONTSENSOR_IPCLKPORT_iPCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_HSI2C_REARAF_IPCLKPORT_iPCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_HSI2C_REARSENSOR_IPCLKPORT_iPCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_GPIO_TOUCH_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_GPIO_TOP_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_GPIO_NFC_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_GPIO_ESE_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_BUSP1_PERIS1_IPCLKPORT_HCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_BUSP1_PERIC1_IPCLKPORT_HCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_BUSP1_PERIC0_IPCLKPORT_HCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_BUSP_BR_PERIC_IPCLKPORT_HCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_aclk)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_ASYNCM_PERI_IPCLKPORT_I_CLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_USI_1_IPCLKPORT_i_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_USI_0_IPCLKPORT_i_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_WDT_CPUCL0_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SFRIF_TMU_CPUCL0_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SFRIF_GPIO_ALIVE_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC10_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC9_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC8_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC7_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC6_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC5_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC4_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC3_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC2_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC1_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_TZPC0_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SFRIF_CHIPID_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SFRIF_RTC_ALIVE_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SFRIF_RTC_TOP_IPCLKPORT_PCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_EXT_UCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_EXT_UCLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_SPI_EXT_CLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_SPI_EXT_CLK)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_USI_0_IPCLKPORT_i_SCLK_UART)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_USI_1_IPCLKPORT_i_SCLK_UART)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_USI_0_IPCLKPORT_i_SCLK_SPI)
GATE_EXTERN(PERI_GATE_CLK_PERI_UID_USI_1_IPCLKPORT_i_SCLK_SPI)
GATE_EXTERN(MIF_MUXGATE_CLKCMU_ISP_VRA)
GATE_EXTERN(MIF_MUXGATE_CLKCMU_ISP_CAM)
GATE_EXTERN(MIF_MUXGATE_CLKCMU_DISPAUD_BUS)
GATE_EXTERN(MIF_MUXGATE_CLKCMU_DISPAUD_DECON_INT_VCLK)
GATE_EXTERN(MIF_MUXGATE_CLKCMU_MFCMSCL_MSCL)
GATE_EXTERN(MIF_MUXGATE_CLKCMU_MFCMSCL_MFC)
GATE_EXTERN(MIF_MUXGATE_CLKCMU_FSYS_BUS)
GATE_EXTERN(MIF_MUXGATE_CLKCMU_FSYS_MMC0)
GATE_EXTERN(MIF_MUXGATE_CLKCMU_FSYS_MMC2)
GATE_EXTERN(MIF_MUXGATE_CLKCMU_FSYS_USB20DRD_REFCLK)
GATE_EXTERN(MIF_MUXGATE_CLKCMU_PERI_BUS)
GATE_EXTERN(MIF_MUXGATE_CLKCMU_PERI_UART_DEBUG)
GATE_EXTERN(MIF_MUXGATE_CLKCMU_PERI_UART_SENSOR)
GATE_EXTERN(MIF_MUXGATE_CLKCMU_PERI_SPI_REARFROM)
GATE_EXTERN(MIF_MUXGATE_CLKCMU_PERI_SPI_ESE)
GATE_EXTERN(MIF_MUXGATE_CLKCMU_PERI_USI_0)
GATE_EXTERN(MIF_MUXGATE_CLKCMU_PERI_USI_1)
GATE_EXTERN(MIF_MUXGATE_CLKCMU_APM)
GATE_EXTERN(MIF_MUXGATE_CLKCMU_ISP_SENSOR0)
GATE_EXTERN(PMU_DEBUG_CLKOUT_SEL08)
GATE_EXTERN(PMU_DEBUG_CLKOUT_SEL09)
GATE_EXTERN(PMU_DEBUG_CLKOUT_SEL10)
GATE_EXTERN(PMU_DEBUG_CLKOUT_SEL11)
GATE_EXTERN(PMU_DEBUG_CLKOUT_SEL12)
GATE_EXTERN(PMU_DEBUG_CLKOUT_DISABLE)
#endif

403
drivers/soc/samsung/pwrcal/S5E7570/S5E7570-cmusfr.h Normal file
View file

@ -0,0 +1,403 @@
/*
* Copyright (c) 2015 Samsung Electronics Co., Ltd. All rights reserved.
* http://www.samsung.com
*
* Chip Abstraction Layer for local/system power down support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __EXYNOS7570_CMUSFR_H__
#define __EXYNOS7570_CMUSFR_H__
#include "S5E7570-sfrbase.h"
#define CLK_CON_MUX_CLKCMU_APM_USER ((void *)(CMU_APM_BASE + 0x0200))
#define CLK_STAT_MUX_CLKCMU_APM_USER ((void *)(CMU_APM_BASE + 0x0600))
#define CLK_ENABLE_CLKCMU_APM_USER ((void *)(CMU_APM_BASE + 0x080C))
#define CLKOUT_CMU_APM ((void *)(CMU_APM_BASE + 0x0D00))
#define CLKOUT_CMU_APM_DIV_STAT ((void *)(CMU_APM_BASE + 0x0D04))
#define CMU_APM_SPARE0 ((void *)(CMU_APM_BASE + 0x0D08))
#define CMU_APM_SPARE1 ((void *)(CMU_APM_BASE + 0x0D0C))
#define CLK_ENABLE_PDN_APM ((void *)(CMU_APM_BASE + 0x0E00))
#define APM_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_APM_BASE + 0x0F00))
#define CPUCL0_PLL_LOCK ((void *)(CMU_CPUCL0_BASE + 0x0000))
#define CPUCL0_PLL_CON0 ((void *)(CMU_CPUCL0_BASE + 0x0100))
#define CPUCL0_PLL_CON1 ((void *)(CMU_CPUCL0_BASE + 0x0104))
#define CLK_CON_MUX_CPUCL0_PLL ((void *)(CMU_CPUCL0_BASE + 0x0200))
#define CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH_USER ((void *)(CMU_CPUCL0_BASE + 0x0204))
#define CLK_CON_MUX_CLK_CPUCL0 ((void *)(CMU_CPUCL0_BASE + 0x0208))
#define CLK_CON_DIV_CLK_CPUCL0_1 ((void *)(CMU_CPUCL0_BASE + 0x0400))
#define CLK_CON_DIV_CLK_CPUCL0_2 ((void *)(CMU_CPUCL0_BASE + 0x0404))
#define CLK_CON_DIV_CLK_CPUCL0_ACLK ((void *)(CMU_CPUCL0_BASE + 0x0408))
#define CLK_CON_DIV_CLK_CPUCL0_PCLK ((void *)(CMU_CPUCL0_BASE + 0x040C))
#define CLK_CON_DIV_CLK_CPUCL0_ATCLK ((void *)(CMU_CPUCL0_BASE + 0x0410))
#define CLK_CON_DIV_CLK_CPUCL0_PCLKDBG ((void *)(CMU_CPUCL0_BASE + 0x0414))
#define CLK_CON_DIV_CLK_CPUCL0_CNTCLK ((void *)(CMU_CPUCL0_BASE + 0x0418))
#define CLK_CON_DIV_CLK_CPUCL0_RUN_MONITOR ((void *)(CMU_CPUCL0_BASE + 0x041C))
#define CLK_CON_DIV_CLK_CPUCL0_HPM ((void *)(CMU_CPUCL0_BASE + 0x0420))
#define CLK_CON_DIV_CLK_CPUCL0_PLL ((void *)(CMU_CPUCL0_BASE + 0x0424))
#define CLK_STAT_MUX_CPUCL0_PLL ((void *)(CMU_CPUCL0_BASE + 0x0600))
#define CLK_STAT_MUX_CLKCMU_CPUCL0_SWITCH_USER ((void *)(CMU_CPUCL0_BASE + 0x0604))
#define CLK_STAT_MUX_CLK_CPUCL0 ((void *)(CMU_CPUCL0_BASE + 0x0608))
#define CLK_ENABLE_CLK_CPUCL0_OSCCLK ((void *)(CMU_CPUCL0_BASE + 0x0800))
#define CLK_ENABLE_CLK_CPUCL0_ACLK ((void *)(CMU_CPUCL0_BASE + 0x0808))
#define CLK_ENABLE_CLK_CPUCL0_PCLK ((void *)(CMU_CPUCL0_BASE + 0x080C))
#define CLK_ENABLE_CLK_CPUCL0_ATCLK ((void *)(CMU_CPUCL0_BASE + 0x0810))
#define CLK_ENABLE_CLK_CPUCL0_PCLKDBG ((void *)(CMU_CPUCL0_BASE + 0x0814))
#define CLK_ENABLE_CLK_CPUCL0_HPM ((void *)(CMU_CPUCL0_BASE + 0x0820))
#define CLKOUT_CMU_CPUCL0 ((void *)(CMU_CPUCL0_BASE + 0x0D00))
#define CLKOUT_CMU_CPUCL0_DIV_STAT ((void *)(CMU_CPUCL0_BASE + 0x0D04))
#define CMU_CPUCL0_SPARE0 ((void *)(CMU_CPUCL0_BASE + 0x0D08))
#define CMU_CPUCL0_SPARE1 ((void *)(CMU_CPUCL0_BASE + 0x0D0C))
#define CLK_ENABLE_PDN_CPUCL0 ((void *)(CMU_CPUCL0_BASE + 0x0E00))
#define CPUCL0_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_CPUCL0_BASE + 0x0F00))
#define ARMCLK_STOPCTRL ((void *)(CMU_CPUCL0_BASE + 0x1000))
#define PWR_CTRL ((void *)(CMU_CPUCL0_BASE + 0x1020))
#define PWR_CTRL2 ((void *)(CMU_CPUCL0_BASE + 0x1024))
#define PWR_CTRL3 ((void *)(CMU_CPUCL0_BASE + 0x1028))
#define INTR_SPREAD_ENABLE ((void *)(CMU_CPUCL0_BASE + 0x1080))
#define INTR_SPREAD_USE_STANDBYWFI ((void *)(CMU_CPUCL0_BASE + 0x1084))
#define INTR_SPREAD_BLOCKING_DURATION ((void *)(CMU_CPUCL0_BASE + 0x1088))
#define AUD_PLL_LOCK ((void *)(CMU_DISPAUD_BASE + 0x00C0))
#define AUD_PLL_CON0 ((void *)(CMU_DISPAUD_BASE + 0x01C0))
#define AUD_PLL_CON1 ((void *)(CMU_DISPAUD_BASE + 0x01C4))
#define AUD_PLL_CON2 ((void *)(CMU_DISPAUD_BASE + 0x01C8))
#define CLK_CON_MUX_AUD_PLL ((void *)(CMU_DISPAUD_BASE + 0x0204))
#define CLK_CON_MUX_CLKCMU_DISPAUD_BUS_USER ((void *)(CMU_DISPAUD_BASE + 0x0210))
#define CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER ((void *)(CMU_DISPAUD_BASE + 0x0214))
#define CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER ((void *)(CMU_DISPAUD_BASE + 0x0218))
#define CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER ((void *)(CMU_DISPAUD_BASE + 0x0224))
#define CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER ((void *)(CMU_DISPAUD_BASE + 0x0228))
#define CLK_CON_DIV_CLK_DISPAUD_APB ((void *)(CMU_DISPAUD_BASE + 0x0400))
#define CLK_CON_DIV_CLK_DISPAUD_DECON_INT_VCLK ((void *)(CMU_DISPAUD_BASE + 0x0404))
#define CLK_CON_DIV_CLK_DISPAUD_DECON_INT_ECLK ((void *)(CMU_DISPAUD_BASE + 0x0408))
#define CLK_CON_DIV_CLK_DISPAUD_MI2S ((void *)(CMU_DISPAUD_BASE + 0x040C))
#define CLK_CON_DIV_CLK_DISPAUD_MIXER ((void *)(CMU_DISPAUD_BASE + 0x0410))
#define CLK_CON_DIV_CLK_DISPAUD_OSCCLK_FM_52M_DIV ((void *)(CMU_DISPAUD_BASE + 0x0414))
#define CLK_STAT_MUX_AUD_PLL ((void *)(CMU_DISPAUD_BASE + 0x0604))
#define CLK_STAT_MUX_CLKCMU_DISPAUD_BUS_USER ((void *)(CMU_DISPAUD_BASE + 0x0610))
#define CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER ((void *)(CMU_DISPAUD_BASE + 0x0614))
#define CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER ((void *)(CMU_DISPAUD_BASE + 0x0618))
#define CLK_STAT_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER ((void *)(CMU_DISPAUD_BASE + 0x0624))
#define CLK_STAT_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER ((void *)(CMU_DISPAUD_BASE + 0x0628))
#define CLK_ENABLE_CLK_DISPAUD_OSCCLK ((void *)(CMU_DISPAUD_BASE + 0x0800))
#define CLK_ENABLE_CLK_DISPAUD_BUS ((void *)(CMU_DISPAUD_BASE + 0x0810))
#define CLK_ENABLE_CLK_DISPAUD_APB ((void *)(CMU_DISPAUD_BASE + 0x0814))
#define CLK_ENABLE_CLK_DISPAUD_APB_SECURE_SMMU_DISP ((void *)(CMU_DISPAUD_BASE + 0x0818))
#define SECURE_ENABLE_SMMU_DISP ((void *)(CMU_DISPAUD_BASE + 0x081C))
#define CLK_ENABLE_CLK_DISPAUD_DECON_INT_VCLK ((void *)(CMU_DISPAUD_BASE + 0x0820))
#define CLK_ENABLE_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS ((void *)(CMU_DISPAUD_BASE + 0x0824))
#define CLK_ENABLE_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0 ((void *)(CMU_DISPAUD_BASE + 0x0828))
#define CLK_ENABLE_CLK_DISPAUD_MI2S ((void *)(CMU_DISPAUD_BASE + 0x082C))
#define CLK_ENABLE_CLK_DISPAUD_MIXER ((void *)(CMU_DISPAUD_BASE + 0x0830))
#define CLK_ENABLE_CLKIO_DISPAUD_MIXER_BCLK_CP ((void *)(CMU_DISPAUD_BASE + 0x083C))
#define CLK_ENABLE_CLK_OSCCLK_FM_52M ((void *)(CMU_DISPAUD_BASE + 0x0844))
#define CLK_ENABLE_CLK_OSCCLK_FM_52M_DIV ((void *)(CMU_DISPAUD_BASE + 0x0848))
#define CLKOUT_CMU_DISPAUD ((void *)(CMU_DISPAUD_BASE + 0x0D00))
#define CLKOUT_CMU_DISPAUD_DIV_STAT ((void *)(CMU_DISPAUD_BASE + 0x0D04))
#define CMU_DISPAUD_SPARE0 ((void *)(CMU_DISPAUD_BASE + 0x0D08))
#define CMU_DISPAUD_SPARE1 ((void *)(CMU_DISPAUD_BASE + 0x0D0C))
#define CLK_ENABLE_PDN_DISPAUD ((void *)(CMU_DISPAUD_BASE + 0x0E00))
#define DISPAUD_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_DISPAUD_BASE + 0x0F00))
#define CLK_CON_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER ((void *)(CMU_FSYS_BASE + 0x0230))
#define CLK_STAT_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER ((void *)(CMU_FSYS_BASE + 0x0630))
#define CLK_ENABLE_CLK_FSYS_OSCCLK ((void *)(CMU_FSYS_BASE + 0x0800))
#define CLK_ENABLE_CLK_FSYS_BUS ((void *)(CMU_FSYS_BASE + 0x0804))
#define CLK_ENABLE_CLK_FSYS_SECURE_RTIC ((void *)(CMU_FSYS_BASE + 0x0808))
#define CLK_ENABLE_CLK_FSYS_SECURE_SSS ((void *)(CMU_FSYS_BASE + 0x080C))
#define CLK_ENABLE_CLK_FSYS_MMC_EMBD ((void *)(CMU_FSYS_BASE + 0x0814))
#define CLK_ENABLE_CLK_FSYS_MMC_CARD ((void *)(CMU_FSYS_BASE + 0x081C))
#define CLK_ENABLE_CLK_FSYS_USB20DRD_REFCLK ((void *)(CMU_FSYS_BASE + 0x0828))
#define CLK_ENABLE_CLKPHY_FSYS_USB20DRD_PHYCLOCK ((void *)(CMU_FSYS_BASE + 0x0830))
#define CLK_ENABLE_CLK_FSYS_USB20PHY_CLKCORE ((void *)(CMU_FSYS_BASE + 0x083C))
#define SECURE_ENABLE_BUSD0_FSYS ((void *)(CMU_FSYS_BASE + 0x08D0))
#define CLKOUT_CMU_FSYS ((void *)(CMU_FSYS_BASE + 0x0D00))
#define CLKOUT_CMU_FSYS_DIV_STAT ((void *)(CMU_FSYS_BASE + 0x0D04))
#define CMU_FSYS_SPARE0 ((void *)(CMU_FSYS_BASE + 0x0D08))
#define CMU_FSYS_SPARE1 ((void *)(CMU_FSYS_BASE + 0x0D0C))
#define CLK_ENABLE_PDN_FSYS ((void *)(CMU_FSYS_BASE + 0x0E00))
#define FSYS_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_FSYS_BASE + 0x0F00))
#define USBPLL_CON0 ((void *)(CMU_FSYS_BASE + 0x1000))
#define USBPLL_CON1 ((void *)(CMU_FSYS_BASE + 0x1004))
#define CLK_CON_MUX_CLKCMU_G3D_USER ((void *)(CMU_G3D_BASE + 0x0204))
#define CLK_CON_DIV_CLK_G3D_BUS ((void *)(CMU_G3D_BASE + 0x0400))
#define CLK_CON_DIV_CLK_G3D_APB ((void *)(CMU_G3D_BASE + 0x0404))
#define CLK_STAT_MUX_CLKCMU_G3D_USER ((void *)(CMU_G3D_BASE + 0x0604))
#define CLK_ENABLE_CLK_G3D_OSCCLK ((void *)(CMU_G3D_BASE + 0x0800))
#define CLK_ENABLE_CLK_G3D_BUS ((void *)(CMU_G3D_BASE + 0x0804))
#define CLK_ENABLE_CLK_G3D_APB ((void *)(CMU_G3D_BASE + 0x0808))
#define CLK_ENABLE_CLK_G3D_BUS_SECURE_CFW_G3D ((void *)(CMU_G3D_BASE + 0x0810))
#define CLK_ENABLE_CLK_G3D_APB_SECURE_CFW_G3D ((void *)(CMU_G3D_BASE + 0x0814))
#define CLKOUT_CMU_G3D ((void *)(CMU_G3D_BASE + 0x0D00))
#define CLKOUT_CMU_G3D_DIV_STAT ((void *)(CMU_G3D_BASE + 0x0D04))
#define CMU_G3D_SPARE0 ((void *)(CMU_G3D_BASE + 0x0D08))
#define CMU_G3D_SPARE1 ((void *)(CMU_G3D_BASE + 0x0D0C))
#define CLK_ENABLE_PDN_G3D ((void *)(CMU_G3D_BASE + 0x0E00))
#define G3D_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_G3D_BASE + 0x0F00))
#define CLK_STOPCTRL ((void *)(CMU_G3D_BASE + 0x1000))
#define CLK_CON_MUX_CLKCMU_ISP_VRA_USER ((void *)(CMU_ISP_BASE + 0x0210))
#define CLK_CON_MUX_CLKCMU_ISP_CAM_USER ((void *)(CMU_ISP_BASE + 0x0214))
#define CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER ((void *)(CMU_ISP_BASE + 0x0230))
#define CLK_CON_DIV_CLK_ISP_CAM_HALF ((void *)(CMU_ISP_BASE + 0x0404))
#define CLK_STAT_MUX_CLKCMU_ISP_VRA_USER ((void *)(CMU_ISP_BASE + 0x0610))
#define CLK_STAT_MUX_CLKCMU_ISP_CAM_USER ((void *)(CMU_ISP_BASE + 0x0614))
#define CLK_STAT_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER ((void *)(CMU_ISP_BASE + 0x0630))
#define CLK_ENABLE_CLK_ISP_OSCCLK ((void *)(CMU_ISP_BASE + 0x0800))
#define CLK_ENABLE_CLK_ISP_VRA ((void *)(CMU_ISP_BASE + 0x0810))
#define CLK_ENABLE_CLK_ISP_CAM ((void *)(CMU_ISP_BASE + 0x081C))
#define CLK_ENABLE_CLKPHY_ISP_S_RXBYTECLKHS0_S4 ((void *)(CMU_ISP_BASE + 0x0828))
#define CLKOUT_CMU_ISP ((void *)(CMU_ISP_BASE + 0x0D00))
#define CLKOUT_CMU_ISP_DIV_STAT ((void *)(CMU_ISP_BASE + 0x0D04))
#define CMU_ISP_SPARE0 ((void *)(CMU_ISP_BASE + 0x0D08))
#define CMU_ISP_SPARE1 ((void *)(CMU_ISP_BASE + 0x0D0C))
#define CLK_ENABLE_PDN_ISP ((void *)(CMU_ISP_BASE + 0x0E00))
#define ISP_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_ISP_BASE + 0x0F00))
#define CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL_USER ((void *)(CMU_MFCMSCL_BASE + 0x0200))
#define CLK_CON_MUX_CLKCMU_MFCMSCL_MFC_USER ((void *)(CMU_MFCMSCL_BASE + 0x0204))
#define CLK_CON_DIV_CLK_MFCMSCL_APB ((void *)(CMU_MFCMSCL_BASE + 0x0400))
#define CLK_STAT_MUX_CLKCMU_MFCMSCL_MSCL_USER ((void *)(CMU_MFCMSCL_BASE + 0x0600))
#define CLK_STAT_MUX_CLKCMU_MFCMSCL_MFC_USER ((void *)(CMU_MFCMSCL_BASE + 0x0604))
#define CLK_ENABLE_CLK_MFCMSCL_OSCCLK ((void *)(CMU_MFCMSCL_BASE + 0x0800))
#define CLK_ENABLE_CLK_MFCMSCL_MSCL ((void *)(CMU_MFCMSCL_BASE + 0x0804))
#define CLK_ENABLE_CLK_MFCMSCL_MFC ((void *)(CMU_MFCMSCL_BASE + 0x0808))
#define CLK_ENABLE_CLK_MFCMSCL_APB ((void *)(CMU_MFCMSCL_BASE + 0x080C))
#define CLK_ENABLE_CLK_MFCMSCL_APB_SMMU_MSCL ((void *)(CMU_MFCMSCL_BASE + 0x0810))
#define SECURE_ENABLE_SMMU_MSCL ((void *)(CMU_MFCMSCL_BASE + 0x0814))
#define CLKOUT_CMU_MFCMSCL ((void *)(CMU_MFCMSCL_BASE + 0x0D00))
#define CLKOUT_CMU_MFCMSCL_DIV_STAT ((void *)(CMU_MFCMSCL_BASE + 0x0D04))
#define CMU_MFCMSCL_SPARE0 ((void *)(CMU_MFCMSCL_BASE + 0x0D08))
#define CMU_MFCMSCL_SPARE1 ((void *)(CMU_MFCMSCL_BASE + 0x0D0C))
#define CLK_ENABLE_PDN_MFCMSCL ((void *)(CMU_MFCMSCL_BASE + 0x0E00))
#define MFCMSCL_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_MFCMSCL_BASE + 0x0F00))
#define SHARED0_PLL_LOCK ((void *)(CMU_MIF_BASE + 0x0000))
#define SHARED1_PLL_LOCK ((void *)(CMU_MIF_BASE + 0x0020))
#define SHARED2_PLL_LOCK ((void *)(CMU_MIF_BASE + 0x0040))
#define SHARED0_PLL_CON0 ((void *)(CMU_MIF_BASE + 0x0100))
#define SHARED0_PLL_CON1 ((void *)(CMU_MIF_BASE + 0x0104))
#define SHARED1_PLL_CON0 ((void *)(CMU_MIF_BASE + 0x0120))
#define SHARED1_PLL_CON1 ((void *)(CMU_MIF_BASE + 0x0124))
#define SHARED2_PLL_CON0 ((void *)(CMU_MIF_BASE + 0x0140))
#define SHARED2_PLL_CON1 ((void *)(CMU_MIF_BASE + 0x0144))
#define CLK_CON_MUX_SHARED0_PLL ((void *)(CMU_MIF_BASE + 0x0200))
#define CLK_CON_MUX_SHARED1_PLL ((void *)(CMU_MIF_BASE + 0x0204))
#define CLK_CON_MUX_SHARED2_PLL ((void *)(CMU_MIF_BASE + 0x0208))
#define CLK_CON_MUX_CLK_MIF_PHY_CLK_A ((void *)(CMU_MIF_BASE + 0x0210))
#define CLK_CON_MUX_CLK_MIF_PHY_CLK_B ((void *)(CMU_MIF_BASE + 0x0214))
#define CLK_CON_MUX_CLK_MIF_BUSD ((void *)(CMU_MIF_BASE + 0x0220))
#define CLK_CON_MUX_CLKCMU_G3D ((void *)(CMU_MIF_BASE + 0x0228))
#define CLK_CON_MUX_CLKCMU_ISP_VRA ((void *)(CMU_MIF_BASE + 0x022C))
#define CLK_CON_MUX_CLKCMU_ISP_CAM ((void *)(CMU_MIF_BASE + 0x0230))
#define CLK_CON_MUX_CLKCMU_DISPAUD_BUS ((void *)(CMU_MIF_BASE + 0x0234))
#define CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK ((void *)(CMU_MIF_BASE + 0x0238))
#define CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL ((void *)(CMU_MIF_BASE + 0x0240))
#define CLK_CON_MUX_CLKCMU_MFCMSCL_MFC ((void *)(CMU_MIF_BASE + 0x0244))
#define CLK_CON_MUX_CLKCMU_FSYS_BUS ((void *)(CMU_MIF_BASE + 0x0248))
#define CLK_CON_MUX_CLKCMU_FSYS_MMC0 ((void *)(CMU_MIF_BASE + 0x024C))
#define CLK_CON_MUX_CLKCMU_FSYS_MMC2 ((void *)(CMU_MIF_BASE + 0x0250))
#define CLK_CON_MUX_CLKCMU_FSYS_USB20DRD_REFCLK ((void *)(CMU_MIF_BASE + 0x0254))
#define CLK_CON_MUX_CLKCMU_PERI_BUS ((void *)(CMU_MIF_BASE + 0x0258))
#define CLK_CON_MUX_CLKCMU_PERI_UART_DEBUG ((void *)(CMU_MIF_BASE + 0x0260))
#define CLK_CON_MUX_CLKCMU_PERI_UART_SENSOR ((void *)(CMU_MIF_BASE + 0x0264))
#define CLK_CON_MUX_CLKCMU_PERI_SPI_REARFROM ((void *)(CMU_MIF_BASE + 0x026C))
#define CLK_CON_MUX_CLKCMU_PERI_SPI_ESE ((void *)(CMU_MIF_BASE + 0x0270))
#define CLK_CON_MUX_CLKCMU_PERI_USI_0 ((void *)(CMU_MIF_BASE + 0x0274))
#define CLK_CON_MUX_CLKCMU_PERI_USI_1 ((void *)(CMU_MIF_BASE + 0x0278))
#define CLK_CON_MUX_CLKCMU_APM ((void *)(CMU_MIF_BASE + 0x027C))
#define CLK_CON_MUX_CLKCMU_ISP_SENSOR0 ((void *)(CMU_MIF_BASE + 0x0280))
#define CLK_CON_DIV_CLK_MIF_PHY_CLK2X ((void *)(CMU_MIF_BASE + 0x0400))
#define CLK_CON_DIV_CLK_MIF_PHY_CLKM ((void *)(CMU_MIF_BASE + 0x0404))
#define CLK_CON_DIV_CLKCMU_CP_SHARED0_PLL ((void *)(CMU_MIF_BASE + 0x0408))
#define CLK_CON_DIV_CLKCMU_CP_SHARED1_PLL ((void *)(CMU_MIF_BASE + 0x040C))
#define CLK_CON_DIV_CLKCMU_CP_SHARED2_PLL ((void *)(CMU_MIF_BASE + 0x0410))
#define CLK_CON_DIV_CLK_MIF_BUSD ((void *)(CMU_MIF_BASE + 0x0414))
#define CLK_CON_DIV_CLK_MIF_APB ((void *)(CMU_MIF_BASE + 0x0418))
#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH ((void *)(CMU_MIF_BASE + 0x0420))
#define CLK_CON_DIV_CLKCMU_G3D ((void *)(CMU_MIF_BASE + 0x0424))
#define CLK_CON_DIV_CLKCMU_ISP_VRA ((void *)(CMU_MIF_BASE + 0x0428))
#define CLK_CON_DIV_CLKCMU_ISP_CAM ((void *)(CMU_MIF_BASE + 0x042C))
#define CLK_CON_DIV_CLKCMU_DISPAUD_BUS ((void *)(CMU_MIF_BASE + 0x0430))
#define CLK_CON_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK ((void *)(CMU_MIF_BASE + 0x0434))
#define CLK_CON_DIV_CLKCMU_MFCMSCL_MSCL ((void *)(CMU_MIF_BASE + 0x043C))
#define CLK_CON_DIV_CLKCMU_MFCMSCL_MFC ((void *)(CMU_MIF_BASE + 0x0440))
#define CLK_CON_DIV_CLKCMU_FSYS_BUS ((void *)(CMU_MIF_BASE + 0x0444))
#define CLK_CON_DIV_CLKCMU_FSYS_MMC0 ((void *)(CMU_MIF_BASE + 0x0448))
#define CLK_CON_DIV_CLKCMU_FSYS_MMC2 ((void *)(CMU_MIF_BASE + 0x044C))
#define CLK_CON_DIV_CLKCMU_FSYS_USB20DRD_REFCLK ((void *)(CMU_MIF_BASE + 0x0450))
#define CLK_CON_DIV_CLKCMU_PERI_BUS ((void *)(CMU_MIF_BASE + 0x0454))
#define CLK_CON_DIV_CLKCMU_PERI_UART_DEBUG ((void *)(CMU_MIF_BASE + 0x045C))
#define CLK_CON_DIV_CLKCMU_PERI_UART_SENSOR ((void *)(CMU_MIF_BASE + 0x0460))
#define CLK_CON_DIV_CLKCMU_PERI_SPI_REARFROM ((void *)(CMU_MIF_BASE + 0x0468))
#define CLK_CON_DIV_CLKCMU_PERI_SPI_ESE ((void *)(CMU_MIF_BASE + 0x046C))
#define CLK_CON_DIV_CLKCMU_PERI_USI_0 ((void *)(CMU_MIF_BASE + 0x0470))
#define CLK_CON_DIV_CLKCMU_PERI_USI_1 ((void *)(CMU_MIF_BASE + 0x0474))
#define CLK_CON_DIV_CLKCMU_APM ((void *)(CMU_MIF_BASE + 0x0478))
#define CLK_CON_DIV_CLKCMU_ISP_SENSOR0 ((void *)(CMU_MIF_BASE + 0x04C4))
#define CLK_CON_DIV_CLKCMU_GNSS_EXTPLL_SCAN ((void *)(CMU_MIF_BASE + 0x04C8))
#define CLK_CON_DIV_CLKCMU_WLBT_EXTPLL_SCAN ((void *)(CMU_MIF_BASE + 0x04CC))
#define CLK_STAT_MUX_SHARED0_PLL ((void *)(CMU_MIF_BASE + 0x0600))
#define CLK_STAT_MUX_SHARED1_PLL ((void *)(CMU_MIF_BASE + 0x0604))
#define CLK_STAT_MUX_SHARED2_PLL ((void *)(CMU_MIF_BASE + 0x0608))
#define CLK_STAT_MUX_CLK_MIF_PHY_CLK_A ((void *)(CMU_MIF_BASE + 0x0610))
#define CLK_STAT_MUX_CLK_MIF_PHY_CLK_B ((void *)(CMU_MIF_BASE + 0x0614))
#define CLK_STAT_MUX_CLK_MIF_BUSD ((void *)(CMU_MIF_BASE + 0x0620))
#define CLK_STAT_MUX_CLKCMU_G3D ((void *)(CMU_MIF_BASE + 0x0628))
#define CLK_STAT_MUX_CLKCMU_ISP_VRA ((void *)(CMU_MIF_BASE + 0x062C))
#define CLK_STAT_MUX_CLKCMU_ISP_CAM ((void *)(CMU_MIF_BASE + 0x0630))
#define CLK_STAT_MUX_CLKCMU_DISPAUD_BUS ((void *)(CMU_MIF_BASE + 0x0634))
#define CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK ((void *)(CMU_MIF_BASE + 0x0638))
#define CLK_STAT_MUX_CLKCMU_MFCMSCL_MSCL ((void *)(CMU_MIF_BASE + 0x0640))
#define CLK_STAT_MUX_CLKCMU_MFCMSCL_MFC ((void *)(CMU_MIF_BASE + 0x0644))
#define CLK_STAT_MUX_CLKCMU_FSYS_BUS ((void *)(CMU_MIF_BASE + 0x0648))
#define CLK_STAT_MUX_CLKCMU_FSYS_MMC0 ((void *)(CMU_MIF_BASE + 0x064C))
#define CLK_STAT_MUX_CLKCMU_FSYS_MMC2 ((void *)(CMU_MIF_BASE + 0x0650))
#define CLK_STAT_MUX_CLKCMU_FSYS_USB20DRD_REFCLK ((void *)(CMU_MIF_BASE + 0x0654))
#define CLK_STAT_MUX_CLKCMU_PERI_BUS ((void *)(CMU_MIF_BASE + 0x0658))
#define CLK_STAT_MUX_CLKCMU_PERI_UART_DEBUG ((void *)(CMU_MIF_BASE + 0x0660))
#define CLK_STAT_MUX_CLKCMU_PERI_UART_SENSOR ((void *)(CMU_MIF_BASE + 0x0664))
#define CLK_STAT_MUX_CLKCMU_PERI_SPI_REARFROM ((void *)(CMU_MIF_BASE + 0x066C))
#define CLK_STAT_MUX_CLKCMU_PERI_SPI_ESE ((void *)(CMU_MIF_BASE + 0x0670))
#define CLK_STAT_MUX_CLKCMU_PERI_USI_0 ((void *)(CMU_MIF_BASE + 0x0674))
#define CLK_STAT_MUX_CLKCMU_PERI_USI_1 ((void *)(CMU_MIF_BASE + 0x0678))
#define CLK_STAT_MUX_CLKCMU_APM ((void *)(CMU_MIF_BASE + 0x067C))
#define CLK_STAT_MUX_CLKCMU_ISP_SENSOR0 ((void *)(CMU_MIF_BASE + 0x0680))
#define CLK_ENABLE_CLK_MIF_OSCCLK ((void *)(CMU_MIF_BASE + 0x0800))
#define CLK_ENABLE_CLK_MIF_PHY_CLK2X ((void *)(CMU_MIF_BASE + 0x0804))
#define CLK_ENABLE_CLK_MIF_PHY_CLKM ((void *)(CMU_MIF_BASE + 0x0808))
#define CLK_ENABLE_CLK_MIF_DDRPHY0 ((void *)(CMU_MIF_BASE + 0x080C))
#define CLK_ENABLE_CLK_MIF_BUSD ((void *)(CMU_MIF_BASE + 0x0810))
#define CLK_ENABLE_CLK_MIF_APB ((void *)(CMU_MIF_BASE + 0x0814))
#define CLK_ENABLE_CLK_MIF_APB_SECURE_DMC0 ((void *)(CMU_MIF_BASE + 0x0818))
#define CLK_ENABLE_CLK_MIF_APB_SECURE_MAILBOX_SECURE ((void *)(CMU_MIF_BASE + 0x081C))
#define CLK_ENABLE_CLKCMU_CP_SHARED0_PLL ((void *)(CMU_MIF_BASE + 0x0820))
#define CLK_ENABLE_CLKCMU_CP_SHARED1_PLL ((void *)(CMU_MIF_BASE + 0x0824))
#define CLK_ENABLE_CLKCMU_CP_SHARED2_PLL ((void *)(CMU_MIF_BASE + 0x0828))
#define CLK_ENABLE_CLKCMU_CPUCL0_SWITCH ((void *)(CMU_MIF_BASE + 0x082C))
#define CLK_ENABLE_CLKCMU_G3D ((void *)(CMU_MIF_BASE + 0x0830))
#define CLK_ENABLE_CLKCMU_ISP_VRA ((void *)(CMU_MIF_BASE + 0x0834))
#define CLK_ENABLE_CLKCMU_ISP_CAM ((void *)(CMU_MIF_BASE + 0x0838))
#define CLK_ENABLE_CLKCMU_DISPAUD_BUS ((void *)(CMU_MIF_BASE + 0x083C))
#define CLK_ENABLE_CLKCMU_DISPAUD_DECON_INT_VCLK ((void *)(CMU_MIF_BASE + 0x0840))
#define CLK_ENABLE_CLKCMU_MFCMSCL_MFC ((void *)(CMU_MIF_BASE + 0x0848))
#define CLK_ENABLE_CLKCMU_MFCMSCL_MSCL ((void *)(CMU_MIF_BASE + 0x084C))
#define CLK_ENABLE_CLKCMU_FSYS_BUS ((void *)(CMU_MIF_BASE + 0x0850))
#define CLK_ENABLE_CLKCMU_FSYS_MMC0 ((void *)(CMU_MIF_BASE + 0x0854))
#define CLK_ENABLE_CLKCMU_FSYS_MMC2 ((void *)(CMU_MIF_BASE + 0x0858))
#define CLK_ENABLE_CLKCMU_FSYS_USB20DRD_REFCLK ((void *)(CMU_MIF_BASE + 0x085C))
#define CLK_ENABLE_CLKCMU_PERI_BUS ((void *)(CMU_MIF_BASE + 0x0860))
#define CLK_ENABLE_CLKCMU_PERI_UART_DEBUG ((void *)(CMU_MIF_BASE + 0x0868))
#define CLK_ENABLE_CLKCMU_PERI_UART_SENSOR ((void *)(CMU_MIF_BASE + 0x086C))
#define CLK_ENABLE_CLKCMU_PERI_SPI_REARFROM ((void *)(CMU_MIF_BASE + 0x0874))
#define CLK_ENABLE_CLKCMU_PERI_SPI_ESE ((void *)(CMU_MIF_BASE + 0x0878))
#define CLK_ENABLE_CLKCMU_PERI_USI_0 ((void *)(CMU_MIF_BASE + 0x087C))
#define CLK_ENABLE_CLKCMU_PERI_USI_1 ((void *)(CMU_MIF_BASE + 0x0880))
#define CLK_ENABLE_CLKCMU_APM ((void *)(CMU_MIF_BASE + 0x0884))
#define CLK_ENABLE_CLKCMU_ISP_SENSOR0 ((void *)(CMU_MIF_BASE + 0x0888))
#define CLK_ENABLE_CLKCMU_GNSS_EXTPLL_SCAN ((void *)(CMU_MIF_BASE + 0x088C))
#define CLK_ENABLE_CLKCMU_WLBT_EXTPLL_SCAN ((void *)(CMU_MIF_BASE + 0x0890))
#define SECURE_ENABLE_CLKCMU_FSYS_BUS ((void *)(CMU_MIF_BASE + 0x0894))
#define CLK_ENABLE_CLK_MIF_TCXO ((void *)(CMU_MIF_BASE + 0x089C))
#define CLKOUT_CMU_MIF ((void *)(CMU_MIF_BASE + 0x0D00))
#define CLKOUT_CMU_MIF_DIV_STAT ((void *)(CMU_MIF_BASE + 0x0D04))
#define CMU_MIF_SPARE0 ((void *)(CMU_MIF_BASE + 0x0D08))
#define CMU_MIF_SPARE1 ((void *)(CMU_MIF_BASE + 0x0D0C))
#define CLK_ENABLE_PDN_MIF ((void *)(CMU_MIF_BASE + 0x0E00))
#define MIF_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_MIF_BASE + 0x0F00))
#define MIF_ROOTCLKEN ((void *)(CMU_MIF_BASE + 0x0F04))
#define MIF_ROOTCLKEN_ON_GATE ((void *)(CMU_MIF_BASE + 0x0F10))
#define DREX_FREQ_CTRL0 ((void *)(CMU_MIF_BASE + 0x1000))
#define DREX_FREQ_CTRL1 ((void *)(CMU_MIF_BASE + 0x1004))
#define PAUSE ((void *)(CMU_MIF_BASE + 0x1008))
#define DDRPHY_LOCK_CTRL ((void *)(CMU_MIF_BASE + 0x100C))
#define CP_CTRL_SPEEDY_ENABLE ((void *)(CMU_MIF_BASE + 0x1014))
#define CP_CTRL_ADCIF_ENABLE ((void *)(CMU_MIF_BASE + 0x1018))
#define FAKE_PAUSE ((void *)(CMU_MIF_BASE + 0x1020))
#define CG_CTRL_VAL_CLK_MIF_DDRPHY0 ((void *)(CMU_MIF_BASE + 0x1800))
#define CG_CTRL_VAL_CLK_MIF_BUSD ((void *)(CMU_MIF_BASE + 0x1804))
#define CG_CTRL_VAL_CLK_MIF_APB ((void *)(CMU_MIF_BASE + 0x1808))
#define CG_CTRL_MAN_CLK_MIF_DDRPHY0 ((void *)(CMU_MIF_BASE + 0x1900))
#define CG_CTRL_MAN_CLK_MIF_BUSD ((void *)(CMU_MIF_BASE + 0x1904))
#define CG_CTRL_MAN_CLK_MIF_APB ((void *)(CMU_MIF_BASE + 0x1908))
#define CG_CTRL_STAT_CLK_MIF_DDRPHY0 ((void *)(CMU_MIF_BASE + 0x1A00))
#define CG_CTRL_STAT_CLK_MIF_BUSD_1 ((void *)(CMU_MIF_BASE + 0x1A04))
#define CG_CTRL_STAT_CLK_MIF_BUSD_2 ((void *)(CMU_MIF_BASE + 0x1A08))
#define CG_CTRL_STAT_CLK_MIF_APB_1 ((void *)(CMU_MIF_BASE + 0x1A0C))
#define CG_CTRL_STAT_CLK_MIF_APB_2 ((void *)(CMU_MIF_BASE + 0x1A10))
#define QCH_CTRL_UID_TREX_MIF_D ((void *)(CMU_MIF_BASE + 0x2000))
#define QCH_CTRL_UID_ASYNCM_LH_G3D0_MIF_D_NRT ((void *)(CMU_MIF_BASE + 0x2004))
#define QCH_CTRL_UID_ASYNCM_LH_MFCMSCL0_MIF_D_NRT ((void *)(CMU_MIF_BASE + 0x2008))
#define QCH_CTRL_UID_ASYNCM_LH_FSYS_MIF_D_NRT ((void *)(CMU_MIF_BASE + 0x200C))
#define QCH_CTRL_UID_ASYNCM_LH_ISP_MIF_D_RT ((void *)(CMU_MIF_BASE + 0x2010))
#define QCH_CTRL_UID_ASYNCM_LH_DISPAUD_MIF_D_RT ((void *)(CMU_MIF_BASE + 0x2014))
#define QCH_CTRL_UID_ASYNCM_LH_WFBT_MIF_D_CP ((void *)(CMU_MIF_BASE + 0x201C))
#define QCH_CTRL_UID_ASYNCS_LH_APM_P ((void *)(CMU_MIF_BASE + 0x2024))
#define QCH_CTRL_UID_ASYNCM_LH_CP_MIF_D_CP ((void *)(CMU_MIF_BASE + 0x2028))
#define QCH_CTRL_UID_ASYNCM_LH_GNSS_MIF_D_CP ((void *)(CMU_MIF_BASE + 0x202C))
#define QCH_CTRL_UID_TREX_MIF_P ((void *)(CMU_MIF_BASE + 0x2030))
#define QCH_CTRL_UID_ASYNCM_LH_APM_D ((void *)(CMU_MIF_BASE + 0x2034))
#define QCH_CTRL_UID_ASYNCS_LH_MIF_P_CPUCL0 ((void *)(CMU_MIF_BASE + 0x2038))
#define QCH_CTRL_UID_ASYNCS_LH_MIF_P_DISPAUD ((void *)(CMU_MIF_BASE + 0x203C))
#define QCH_CTRL_UID_ASYNCS_LH_MIF_P_FSYS ((void *)(CMU_MIF_BASE + 0x2040))
#define QCH_CTRL_UID_ASYNCS_LH_MIF_P_G3D ((void *)(CMU_MIF_BASE + 0x2044))
#define QCH_CTRL_UID_ASYNCS_LH_MIF_P_ISP ((void *)(CMU_MIF_BASE + 0x2048))
#define QCH_CTRL_UID_ASYNCS_LH_MIF_P_MFCMSCL ((void *)(CMU_MIF_BASE + 0x204C))
#define QCH_CTRL_UID_ASYNCS_LH_MIF_P_PERI ((void *)(CMU_MIF_BASE + 0x2050))
#define CLK_CON_DIV_CLK_PERI_USI_0_SPI ((void *)(CMU_PERI_BASE + 0x0400))
#define CLK_CON_DIV_CLK_PERI_USI_1_SPI ((void *)(CMU_PERI_BASE + 0x0404))
#define CLK_ENABLE_CLK_PERI_OSCCLK ((void *)(CMU_PERI_BASE + 0x0800))
#define CLK_ENABLE_CLK_PERI_OSCCLK_SECURE_CHIPID ((void *)(CMU_PERI_BASE + 0x0804))
#define CLK_ENABLE_CLK_PERI_BUS0 ((void *)(CMU_PERI_BASE + 0x0810))
#define CLK_ENABLE_CLK_PERI_BUS1 ((void *)(CMU_PERI_BASE + 0x0814))
#define CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC ((void *)(CMU_PERI_BASE + 0x0818))
#define CLK_ENABLE_CLK_PERI_BUS_SECURE_CHIPID ((void *)(CMU_PERI_BASE + 0x081C))
#define CLK_ENABLE_CLK_PERI_BUS_SECURE_OTP_CON_TOP ((void *)(CMU_PERI_BASE + 0x0820))
#define CLK_ENABLE_CLK_PERI_BUS_SECURE_RTC_ALIVE ((void *)(CMU_PERI_BASE + 0x0824))
#define CLK_ENABLE_CLK_PERI_BUS_SECURE_RTC_TOP ((void *)(CMU_PERI_BASE + 0x0828))
#define CLK_ENABLE_CLK_PERI_UART_DEBUG ((void *)(CMU_PERI_BASE + 0x0834))
#define CLK_ENABLE_CLK_PERI_UART_SENSOR ((void *)(CMU_PERI_BASE + 0x0838))
#define CLK_ENABLE_CLK_PERI_SPI_REARFROM ((void *)(CMU_PERI_BASE + 0x0840))
#define CLK_ENABLE_CLK_PERI_SPI_ESE ((void *)(CMU_PERI_BASE + 0x0844))
#define CLK_ENABLE_CLK_PERI_USI_0 ((void *)(CMU_PERI_BASE + 0x0850))
#define CLK_ENABLE_CLK_PERI_USI_1 ((void *)(CMU_PERI_BASE + 0x0854))
#define CLK_ENABLE_CLK_PERI_USI_0_SPI ((void *)(CMU_PERI_BASE + 0x0858))
#define CLK_ENABLE_CLK_PERI_USI_1_SPI ((void *)(CMU_PERI_BASE + 0x085C))
#define CLKOUT_CMU_PERI ((void *)(CMU_PERI_BASE + 0x0D00))
#define CLKOUT_CMU_PERI_DIV_STAT ((void *)(CMU_PERI_BASE + 0x0D04))
#define CMU_PERI_SPARE0 ((void *)(CMU_PERI_BASE + 0x0D08))
#define CMU_PERI_SPARE1 ((void *)(CMU_PERI_BASE + 0x0D0C))
#define CLK_ENABLE_PDN_PERI ((void *)(CMU_PERI_BASE + 0x0E00))
#define CPUCL0_EMA_CON ((void *)(SYSREG_CPUCL0_BASE + 0x0330))
#define CPUCL0_EMA ((void *)(SYSREG_CPUCL0_BASE + 0x0340))
#define G3D_EMA_RA1_HS_CON ((void *)(SYSREG_G3D_BASE + 0x0304))
#define G3D_EMA_RF1_HS_CON ((void *)(SYSREG_G3D_BASE + 0x0314))
#define G3D_EMA_RF2_HS_CON ((void *)(SYSREG_G3D_BASE + 0x031C))
#define G3D_EMA_UHD_CON ((void *)(SYSREG_G3D_BASE + 0x0320))
#if !defined(CONFIG_PM_RUNTIME) && !defined(CONFIG_CAL_SYS_PWRDOWN)
struct exynos_pd_clk {
void __iomem *reg;
u8 bit_offset;
char *domain_name;
};
struct exynos_pd_reg {
void __iomem *reg;
u8 bit_offset;
};
struct sfr_save {
void __iomem *reg;
};
#endif
#endif

506
drivers/soc/samsung/pwrcal/S5E7570/S5E7570-dfs.c Normal file
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#include "../pwrcal.h"
#include "../pwrcal-env.h"
#include "../pwrcal-clk.h"
#include "../pwrcal-pmu.h"
#include "../pwrcal-dfs.h"
#include "../pwrcal-rae.h"
#include "../pwrcal-asv.h"
#include "S5E7570-cmusfr.h"
#include "S5E7570-pmusfr.h"
#include "S5E7570-cmu.h"
#include "S5E7570-vclk-internal.h"
extern unsigned int dfscpucl0_rate_table[];
extern unsigned int dfsg3d_rate_table[];
extern unsigned int dfsmif_rate_table[];
extern unsigned int dfsint_rate_table[];
extern unsigned int dfsdisp_rate_table[];
extern unsigned int dfscam_rate_table[];
static struct dfs_switch dfscpucl0_switches[] = {
#ifdef CONFIG_SOC_EXYNOS7570_DUAL
{840000, 0, 0},
{840000 / 2, 0, 1},
{840000 / 3, 0, 2},
{840000 / 4, 0, 3},
#else
{830000, 0, 0},
{830000 / 2, 0, 1},
{830000 / 3, 0, 2},
{830000 / 4, 0, 3},
#endif
};
static struct dfs_table dfscpucl0_table = {
.switches = dfscpucl0_switches,
.num_of_switches = ARRAY_SIZE(dfscpucl0_switches),
.switch_mux = CLK(CPUCL0_MUX_CLK_CPUCL0),
.switch_use = 1,
.switch_notuse = 0,
.switch_src_div = CLK(MIF_DIV_CLKCMU_CPUCL0_SWITCH),
.switch_src_gate = CLK(MIF_GATE_CLKCMU_CPUCL0_SWITCH),
.switch_src_usermux = CLK(CPUCL0_MUX_CLKCMU_CPUCL0_SWITCH_USER),
};
struct pwrcal_clk_set dfscpucl0_en_list[] = {
{CLK_NONE, 0, -1},
};
static struct dfs_switch dfsg3d_switches[] = {
};
static struct dfs_table dfsg3d_table = {
.switches = dfsg3d_switches,
.num_of_switches = ARRAY_SIZE(dfsg3d_switches),
.switch_use = 1,
.switch_notuse = 0,
};
struct pwrcal_clk_set dfsg3d_en_list[] = {
{CLK(G3D_MUX_CLKCMU_G3D_USER), 1, 0},
{CLK(G3D_DIV_CLK_G3D_BUS), 3, -1},
{CLK(G3D_DIV_CLK_G3D_APB), 3, -1},
{CLK_NONE, 0, -1},
};
static struct dfs_switch dfsmif_switches[] = {
};
extern void pwrcal_dmc_set_dvfs(unsigned long long target_mif_freq, unsigned int timing_set_idx);
extern void pwrcal_dmc_set_pre_dvfs(void);
extern void pwrcal_dmc_set_post_dvfs(unsigned long long target_freq);
extern void pwrcal_dmc_set_vtmon_on_swithing(void);
extern void pwrcal_dmc_set_refresh_method_pre_dvfs(unsigned long long current_rate, unsigned long long target_rate);
extern void pwrcal_dmc_set_refresh_method_post_dvfs(unsigned long long current_rate, unsigned long long target_rate);
extern void pwrcal_dmc_set_dsref_cycle(unsigned long long target_rate);
static int pwrcal_clk_set_mif_pause_enable(int enable)
{
pwrcal_writel(PAUSE, (enable<<0)); /* CMU Pause enable */
return 0;
}
static int pwrcal_clk_wait_mif_pause(void)
{
int timeout;
unsigned int status;
for (timeout = 0;; timeout++) {
status = pwrcal_getf(PAUSE, 16, 0x3);
if (status == 0x0)
break;
if (timeout > CLK_WAIT_CNT)
pr_err("PAUSE staus(0x%X) is not stable", status);
cpu_relax();
}
return 0;
}
static int is_dll_on_status = 1;
static void dfsmif_trans_pre(unsigned int rate_from, unsigned int rate_to)
{
static unsigned int paraset;
unsigned long long from, to;
is_dll_on_status = 1;
from = (unsigned long long)rate_from * 1000;
to = (unsigned long long)rate_to * 1000;
pwrcal_dmc_set_refresh_method_pre_dvfs(from, to);
pwrcal_clk_set_mif_pause_enable(1);
/* VTMON disable before MIF DFS sequence*/
pwrcal_dmc_set_pre_dvfs();
paraset = (paraset + 1) % 2;
pwrcal_dmc_set_dvfs(to, paraset);
}
static void dfsmif_trans_post(unsigned int rate_from, unsigned int rate_to)
{
unsigned long long from, to;
from = (unsigned long long)rate_from * 1000;
to = (unsigned long long)rate_to * 1000;
pwrcal_clk_wait_mif_pause();
/* VTMON enable before MIF DFS sequence*/
pwrcal_dmc_set_post_dvfs(to);
pwrcal_dmc_set_refresh_method_post_dvfs(from, to);
pwrcal_dmc_set_dsref_cycle(to);
if (rate_to >= 416000)
is_dll_on_status = 1;
else
is_dll_on_status = 0;
}
static int dfsmif_transition(unsigned int rate_from, unsigned int rate_to, struct dfs_table *table)
{
int lv_from, lv_to;
lv_from = dfs_get_lv(rate_from, table);
if (lv_from >= table->num_of_lv)
goto errorout;
lv_to = dfs_get_lv(rate_to, table);
if (lv_to >= table->num_of_lv)
goto errorout;
dfsmif_trans_pre(rate_from, rate_to);
if (dfs_trans_div(lv_from, lv_to, table, TRANS_HIGH))
goto errorout;
if (dfs_trans_mux(lv_from, lv_to, table, TRANS_DIFF))
goto errorout;
if (dfs_trans_div(lv_from, lv_to, table, TRANS_LOW))
goto errorout;
dfsmif_trans_post(rate_from, rate_to);
return 0;
errorout:
return -1;
}
static unsigned long dfs_mif_get_rate(struct dfs_table *table)
{
int l, m;
unsigned int cur[128] = {0, };
unsigned long long rate;
struct pwrcal_clk *clk;
unsigned int drex_freq = 0;
unsigned int value[4], temp;
for (m = 1; m < table->num_of_members; m++) {
clk = table->members[m];
if (is_pll(clk)) {
rate = pwrcal_pll_get_rate(clk);
do_div(rate, 1000);
cur[m] = (unsigned int)rate;
}
if (is_mux(clk)) {
if (clk->id == MIF_MUX_CLK_MIF_PHY_CLK) {
temp = pwrcal_getf(clk->offset, 0, 0xffffffff);
value[0] = (unsigned char)((temp & (0x1 << 4)) >> 4);
value[1] = (unsigned char)((temp & (0x1 << 5)) >> 5);
value[2] = (unsigned char)((temp & (0xf << 16)) >> 16);
value[3] = (unsigned char)((temp & (0xf << 20)) >> 20);
drex_freq |= (value[0] & 0x1) << 7;
drex_freq |= (value[1] & 0x1) << 6;
drex_freq |= (value[2] & 0x7) << 3;
drex_freq |= (value[3] & 0x7) << 0;
cur[m] = drex_freq;
} else
cur[m] = pwrcal_mux_get_src(clk);
}
if (is_div(clk))
cur[m] = pwrcal_div_get_ratio(clk) - 1;
if (is_gate(clk))
cur[m] = pwrcal_gate_is_enabled(clk);
}
for (l = 0; l < table->num_of_lv; l++) {
for (m = 1; m < table->num_of_members; m++)
if (cur[m] != get_value(table, l, m))
break;
if (m == table->num_of_members)
return get_value(table, l, 0);
}
for (m = 1; m < table->num_of_members; m++) {
clk = table->members[m];
pr_err("dfs_get_rate mid : %s : %d\n", clk->name, cur[m]);
}
return 0;
}
static struct dfs_table dfsmif_table = {
.switches = dfsmif_switches,
.num_of_switches = ARRAY_SIZE(dfsmif_switches),
.switch_use = 1,
.switch_notuse = 0,
.private_trans = dfsmif_transition,
.private_getrate = dfs_mif_get_rate,
};
struct pwrcal_clk_set dfsmif_en_list[] = {
{ CLK_NONE, 0, -1},
};
static struct dfs_switch dfsint_switches[] = {
};
static struct dfs_table dfsint_table = {
.switches = dfsint_switches,
.num_of_switches = ARRAY_SIZE(dfsint_switches),
.switch_use = 1,
.switch_notuse = 0,
};
struct pwrcal_clk_set dfsint_en_list[] = {
{CLK_NONE, 0, -1},
};
static struct dfs_switch dfsdisp_switches[] = {
};
static struct dfs_table dfsdisp_table = {
.switches = dfsdisp_switches,
.num_of_switches = ARRAY_SIZE(dfsdisp_switches),
.switch_use = 1,
.switch_notuse = 0,
};
struct pwrcal_clk_set dfsdisp_en_list[] = {
{CLK_NONE, 0, -1},
};
static struct dfs_switch dfscam_switches[] = {
};
static struct dfs_table dfscam_table = {
.switches = dfscam_switches,
.num_of_switches = ARRAY_SIZE(dfscam_switches),
.switch_use = 1,
.switch_notuse = 0,
};
struct pwrcal_clk_set dfscam_en_list[] = {
{CLK_NONE, 0, -1},
};
static int dfscpucl0_get_rate_table(unsigned long *table)
{
return dfs_get_rate_table(&dfscpucl0_table, table);
}
static int dfscpucl0_idle_clock_down(unsigned int enable)
{
return 0;
}
static struct vclk_dfs_ops dfscpucl0_dfsops = {
.get_rate_table = dfscpucl0_get_rate_table,
.cpu_idle_clock_down = dfscpucl0_idle_clock_down,
};
static int dfsg3d_dvs(int on)
{
return 0;
}
static int dfsg3d_get_rate_table(unsigned long *table)
{
return dfs_get_rate_table(&dfsg3d_table, table);
}
static struct vclk_dfs_ops dfsg3d_dfsops = {
.dvs = dfsg3d_dvs,
.get_rate_table = dfsg3d_get_rate_table,
};
static int dfsmif_get_rate_table(unsigned long *table)
{
return dfs_get_rate_table(&dfsmif_table, table);
}
static int dfsmif_is_dll_on(void)
{
return 1;
}
static struct vclk_dfs_ops dfsmif_dfsops = {
.get_rate_table = dfsmif_get_rate_table,
.is_dll_on = dfsmif_is_dll_on,
};
static int dfsint_get_rate_table(unsigned long *table)
{
return dfs_get_rate_table(&dfsint_table, table);
}
static struct vclk_dfs_ops dfsint_dfsops = {
.get_rate_table = dfsint_get_rate_table,
};
static int dfsdisp_get_rate_table(unsigned long *table)
{
return dfs_get_rate_table(&dfsdisp_table, table);
}
static struct vclk_dfs_ops dfsdisp_dfsops = {
.get_rate_table = dfsdisp_get_rate_table,
};
static int dfscam_get_rate_table(unsigned long *table)
{
return dfs_get_rate_table(&dfscam_table, table);
}
static struct vclk_dfs_ops dfscam_dfsops = {
.get_rate_table = dfscam_get_rate_table,
};
static DEFINE_SPINLOCK(dvfs_cpucl0_lock);
static DEFINE_SPINLOCK(dvfs_g3d_lock);
static DEFINE_SPINLOCK(dvfs_mif_lock);
static DEFINE_SPINLOCK(dvfs_int_lock);
static DEFINE_SPINLOCK(dvfs_disp_lock);
static DEFINE_SPINLOCK(dvfs_cam_lock);
DFS(dvfs_cpucl0) = {
.vclk.type = vclk_group_dfs,
.vclk.parent = VCLK(pxmxdx_top),
.vclk.ref_count = 1,
.vclk.vfreq = 0,
.vclk.name = "dvfs_cpucl0",
.vclk.ops = &dfs_ops,
.lock = &dvfs_cpucl0_lock,
.en_clks = dfscpucl0_en_list,
.table = &dfscpucl0_table,
.dfsops = &dfscpucl0_dfsops,
};
DFS(dvfs_g3d) = {
.vclk.type = vclk_group_dfs,
.vclk.parent = VCLK(pxmxdx_top),
.vclk.ref_count = 0,
.vclk.vfreq = 350000,
.vclk.name = "dvfs_g3d",
.vclk.ops = &dfs_ops,
.lock = &dvfs_g3d_lock,
.en_clks = dfsg3d_en_list,
.table = &dfsg3d_table,
.dfsops = &dfsg3d_dfsops,
};
DFS(dvfs_mif) = {
.vclk.type = vclk_group_dfs,
.vclk.parent = VCLK(pxmxdx_top),
.vclk.ref_count = 1,
.vclk.vfreq = 0,
.vclk.name = "dvfs_mif",
.vclk.ops = &dfs_ops,
.lock = &dvfs_mif_lock,
.en_clks = dfsmif_en_list,
.table = &dfsmif_table,
.dfsops = &dfsmif_dfsops,
};
DFS(dvfs_int) = {
.vclk.type = vclk_group_dfs,
.vclk.parent = VCLK(pxmxdx_top),
.vclk.ref_count = 1,
.vclk.vfreq = 0,
.vclk.name = "dvfs_int",
.vclk.ops = &dfs_ops,
.lock = &dvfs_int_lock,
.en_clks = dfsint_en_list,
.table = &dfsint_table,
.dfsops = &dfsint_dfsops,
};
DFS(dvfs_disp) = {
.vclk.type = vclk_group_dfs,
.vclk.parent = VCLK(pxmxdx_top),
.vclk.ref_count = 0,
.vclk.vfreq = 0,
.vclk.name = "dvfs_disp",
.vclk.ops = &dfs_ops,
.lock = &dvfs_disp_lock,
.en_clks = dfsdisp_en_list,
.table = &dfsdisp_table,
.dfsops = &dfsdisp_dfsops,
};
DFS(dvfs_cam) = {
.vclk.type = vclk_group_dfs,
.vclk.parent = VCLK(pxmxdx_top),
.vclk.ref_count = 0,
#ifdef CONFIG_SOC_EXYNOS7570_DUAL
.vclk.vfreq = 560000,
#else
.vclk.vfreq = 554000,
#endif
.vclk.name = "dvfs_cam",
.vclk.ops = &dfs_ops,
.lock = &dvfs_cam_lock,
.en_clks = dfscam_en_list,
.table = &dfscam_table,
.dfsops = &dfscam_dfsops,
};
void dfs_set_clk_information(struct pwrcal_vclk_dfs *dfs)
{
int i, j;
void *dvfs_block;
struct ect_dvfs_domain *dvfs_domain;
struct dfs_table *dvfs_table;
dvfs_block = ect_get_block("DVFS");
if (dvfs_block == NULL)
return;
dvfs_domain = ect_dvfs_get_domain(dvfs_block, dfs->vclk.name);
if (dvfs_domain == NULL)
return;
dvfs_table = dfs->table;
dvfs_table->num_of_lv = dvfs_domain->num_of_level;
dvfs_table->num_of_members = dvfs_domain->num_of_clock + 1;
dvfs_table->max_freq = dvfs_domain->max_frequency;
dvfs_table->min_freq = dvfs_domain->min_frequency;
dvfs_table->members = kzalloc(sizeof(struct pwrcal_clk *) * (dvfs_domain->num_of_clock + 1), GFP_KERNEL);
if (dvfs_table->members == NULL)
return;
dvfs_table->members[0] = REPRESENT_RATE;
for (i = 0; i < dvfs_domain->num_of_clock; ++i) {
dvfs_table->members[i + 1] = clk_find(dvfs_domain->list_clock[i]);
if (dvfs_table->members[i] == NULL)
return;
}
dvfs_table->rate_table = kzalloc(sizeof(unsigned int) * (dvfs_domain->num_of_clock + 1) * dvfs_domain->num_of_level, GFP_KERNEL);
if (dvfs_table->rate_table == NULL)
return;
for (i = 0; i < dvfs_domain->num_of_level; ++i) {
dvfs_table->rate_table[i * (dvfs_domain->num_of_clock + 1)] = dvfs_domain->list_level[i].level;
for (j = 0; j <= dvfs_domain->num_of_clock; ++j) {
dvfs_table->rate_table[i * (dvfs_domain->num_of_clock + 1) + j + 1] =
dvfs_domain->list_dvfs_value[i * dvfs_domain->num_of_clock + j];
}
}
}
void dfs_init(void)
{
dfs_set_clk_information(&vclk_dvfs_cpucl0);
dfs_set_clk_information(&vclk_dvfs_g3d);
dfs_set_clk_information(&vclk_dvfs_mif);
dfs_set_clk_information(&vclk_dvfs_int);
dfs_set_clk_information(&vclk_dvfs_cam);
dfs_set_clk_information(&vclk_dvfs_disp);
dfs_dram_init();
}

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#include "../pwrcal-env.h"
#include "../pwrcal-rae.h"
#include "S5E7570-sfrbase.h"
#include "S5E7570-vclk-internal.h"
#include "S5E7570-pmusfr.h"
#ifdef PWRCAL_TARGET_LINUX
#include <soc/samsung/ect_parser.h>
#else
#include <mach/ect_parser.h>
#endif
#ifndef MHZ
#define MHZ ((unsigned long long)1000000)
#endif
#define DMC_WAIT_CNT 10000
#define DREX0_MEMORY_CONTROL0 ((void *)(DREX0_BASE + 0x0010))
#define DREX0_POWER_DOWN_CONFIG ((void *)(DREX0_BASE + 0x0014))
#define DREX0_CG_CONTROL ((void *)(DREX0_BASE + 0x0018))
#define DREX0_TICK_GRANULARITY_S0 ((void *)(DREX0_BASE + 0x0100))
#define DREX0_TEMP_SENSING_S0 ((void *)(DREX0_BASE + 0x0108))
#define DREX0_DQS_OSC_CON1_S0 ((void *)(DREX0_BASE + 0x0110))
#define DREX0_TERMINATION_CONTROL_S0 ((void *)(DREX0_BASE + 0x0114))
#define DREX0_WINCONFIG_WRITE_ODT_S0 ((void *)(DREX0_BASE + 0x0118))
#define DREX0_TIMING_ROW0_S0 ((void *)(DREX0_BASE + 0x0140))
#define DREX0_TIMING_ROW1_S0 ((void *)(DREX0_BASE + 0x0144))
#define DREX0_TIMING_DATA_ACLK_S0 ((void *)(DREX0_BASE + 0x0148))
#define DREX0_TIMING_DATA_MCLK_S0 ((void *)(DREX0_BASE + 0x014C))
#define DREX0_TIMING_POWER0_S0 ((void *)(DREX0_BASE + 0x0150))
#define DREX0_TIMING_POWER1_S0 ((void *)(DREX0_BASE + 0x0154))
#define DREX0_TIMING_ETC1_S0 ((void *)(DREX0_BASE + 0x015c))
#define DREX0_TICK_GRANULARITY_S1 ((void *)(DREX0_BASE + 0x0180))
#define DREX0_TEMP_SENSING_S1 ((void *)(DREX0_BASE + 0x0188))
#define DREX0_DQS_OSC_CON1_S1 ((void *)(DREX0_BASE + 0x0190))
#define DREX0_TERMINATION_CONTROL_S1 ((void *)(DREX0_BASE + 0x0194))
#define DREX0_WINCONFIG_WRITE_ODT_S1 ((void *)(DREX0_BASE + 0x0198))
#define DREX0_TIMING_ROW0_S1 ((void *)(DREX0_BASE + 0x01c0))
#define DREX0_TIMING_ROW1_S1 ((void *)(DREX0_BASE + 0x01c4))
#define DREX0_TIMING_DATA_ACLK_S1 ((void *)(DREX0_BASE + 0x01c8))
#define DREX0_TIMING_DATA_MCLK_S1 ((void *)(DREX0_BASE + 0x01cC))
#define DREX0_TIMING_POWER0_S1 ((void *)(DREX0_BASE + 0x01d0))
#define DREX0_TIMING_POWER1_S1 ((void *)(DREX0_BASE + 0x01d4))
#define DREX0_TIMING_ETC1_S1 ((void *)(DREX0_BASE + 0x01dc))
#define PHY0_CAL_CON0 ((void *)(DREXPHY0_BASE + 0x0004))
#define PHY0_DVFS_CON0 ((void *)(DREXPHY0_BASE + 0x00B8))
#define PHY0_DVFS_CON1 ((void *)(DREXPHY0_BASE + 0x00E0))
#define PHY0_DVFS_CON2 ((void *)(DREXPHY0_BASE + 0x00BC))
#define PHY0_DVFS_CON3 ((void *)(DREXPHY0_BASE + 0x00C0))
#define PHY0_DVFS_CON4 ((void *)(DREXPHY0_BASE + 0x00C4))
#define PHY0_DVFS_CON5 ((void *)(DREXPHY0_BASE + 0x00C8))
#define PHY0_DVFS_CON6 ((void *)(DREXPHY0_BASE + 0x00CC))
#define PHY0_ZQ_CON9 ((void *)(DREXPHY0_BASE + 0x03EC))
#define DREX0_PAUSE_MRS0 ((void *)(DREX0_BASE + 0x0080))
#define DREX0_PAUSE_MRS1 ((void *)(DREX0_BASE + 0x0084))
#define DREX0_PAUSE_MRS2 ((void *)(DREX0_BASE + 0x0088))
#define DREX0_PAUSE_MRS3 ((void *)(DREX0_BASE + 0x008C))
#define DREX0_PAUSE_MRS4 ((void *)(DREX0_BASE + 0x0090))
#define DREX0_TIMING_SET_SW ((void *)(DREX0_BASE + 0x0020))
#define DREX0_PORT_TICK_GRANULARITY_S0 ((void *)(DREX0_PF_BASE + 0x0010))
#define DREX0_PORT_TICK_GRANULARITY_S1 ((void *)(DREX0_PF_BASE + 0x0014))
// PHY DVFS CON SFR BIT DEFINITION /
#define PHY_DVFS_CON0_SET1_MASK ((0x0)|(1<<31)|(1<<29)|(0x0<<24))
#define PHY_DVFS_CON0_SET0_MASK ((0x0)|(1<<30)|(1<<28)|(0x0<<24)|(0x7<<21)|(0x7<<18)|(0x7<<15)|(0x7<<12)|(0x7<<9)|(0x7<<6)|(0x7<<3)|(0x7<<0))
#define PHY_DVFS_CON0_DVFS_MODE_MASK ((0x0)|(0x3<<24))
#define PHY_DVFS_CON0_DVFS_MODE_POSITION 24
#define PHY_DVFS_CON1_SET1_MASK ((0x7<<21)|(0x7<<18)|(0x7<<15)|(0x7<<12)|(0x7<<9)|(0x7<<6)|(0x7<<3)|(0x7<<0))
#define PHY_DVFS_CON1_SET0_MASK ((0x0))
#define PHY_DVFS_CON2_SET1_MASK ((0x0)|(0x1<<31)|(0x1F<<24)|(0xF<<12)|(0xF<<8))
#define PHY_DVFS_CON2_SET0_MASK ((0x0)|(0x1<<30)|(0x1F<<16)|(0xF<<7)|(0xF<<0))
#define PHY_DVFS_CON3_SET1_MASK ((0x0)|(0x1<<30)|(0x1<<29)|(0x7<<23)|(0x1<<17)|(0xf<<12)|(0xf<<8))
#define PHY_DVFS_CON3_SET0_MASK ((0x0)|(0x1<<31)|(0x1<<28)|(0x7<<20)|(0x1<<16)|(0xf<<4)|(0xf<<0))
#define PHY_DVFS_CON4_SET1_MASK ((0x0)|(0x3F<<18)|(0x3F<<12))
#define PHY_DVFS_CON4_SET0_MASK ((0x0)|(0x3F<<6)|(0x3F<<0))
#define PHY_DVFS_CON5_SET1_MASK ((0x0)|(0x7<<24)|(0x7<<16)|(0x7<<8)|(0x7<<0))
#define PHY_DVFS_CON5_SET0_MASK ((0x0))
#define PHY_DVFS_CON6_SET1_MASK ((0x0))
#define PHY_DVFS_CON6_SET0_MASK ((0x0)|(0x7<<24)|(0x7<<16)|(0x7<<8)|(0x7<<0))
#define DREX0_DIRECTCMD ((void *)(DREX0_BASE + 0x001C))
#define DREX0_timing_set_sw_con 0 /* Pause triggered from CMU */
#define DQS_OSC_UPDATE_EN 0
#define PERIODIC_WR_TRAIN 0
#if DQS_OSC_UPDATE_EN
#define dvfs_dqs_osc_en 1
#else
#define dvfs_dqs_osc_en 0
#endif
#if PERIODIC_WR_TRAIN
#define dvfs_offset 16
#else
#define dvfs_offset 0
#endif
enum dmc_dvfs_mif_level_idx {
DMC_DVFS_MIF_L0,
DMC_DVFS_MIF_L1,
DMC_DVFS_MIF_L2,
DMC_DVFS_MIF_L3,
DMC_DVFS_MIF_L4,
DMC_DVFS_MIF_L5,
DMC_DVFS_MIF_L6,
DMC_DVFS_MIF_L7,
DMC_DVFS_MIF_L8,
COUNT_OF_CMU_DVFS_MIF_LEVEL,
CMU_DVFS_MIF_INVALID = 0xFF,
};
enum dmc_timing_set_idx {
DMC_TIMING_SET_0 = 0,
DMC_TIMING_SET_1
};
enum phy_timing_set_idx {
PHY_Normal_mode = 0 ,
PHY_DVFS0_mode,
PHY_DVFS1_mode
};
enum timing_parameter_column {
drex_Tick_Granularity,
drex_mr4_sensing_cyc,
drex_dqs_osc_start_cyc,
drex_Termination_Control,
drex_Winconfig_Write_Odt,
drex_Timing_Row0,
drex_Timing_Row1,
drex_Timing_Data_Aclk,
drex_Timing_Data_Mclk,
drex_Timing_Power0,
drex_Timing_Power1,
drex_Etcl,
drex_Puase_MRS0,
drex_Puase_MRS1,
drex_Puase_MRS2,
drex_Puase_MRS3,
drex_Puase_MRS4,
phy_Dvfs_Con0_set1,
phy_Dvfs_Con0_set0,
phy_Dvfs_Con0_set1_mask,
phy_Dvfs_Con0_set0_mask,
phy_Dvfs_Con1_set1,
phy_Dvfs_Con1_set0,
phy_Dvfs_Con1_set1_mask,
phy_Dvfs_Con1_set0_mask,
phy_Dvfs_Con2_set1,
phy_Dvfs_Con2_set0,
phy_Dvfs_Con2_set1_mask,
phy_Dvfs_Con2_set0_mask,
phy_Dvfs_Con3_set1,
phy_Dvfs_Con3_set0,
phy_Dvfs_Con3_set1_mask,
phy_Dvfs_Con3_set0_mask,
num_of_g_dmc_drex_dfs_mif_table_column = drex_Etcl - drex_Tick_Granularity + 1,
num_of_g_dmc_directcmd_dfs_mif_table_column = drex_Puase_MRS4 - drex_Puase_MRS0 + 1,
num_of_g_dmc_phy_dfs_mif_table_column = phy_Dvfs_Con3_set0_mask - phy_Dvfs_Con0_set1 + 1,
num_of_dram_parameter = num_of_g_dmc_drex_dfs_mif_table_column + num_of_g_dmc_directcmd_dfs_mif_table_column + num_of_g_dmc_phy_dfs_mif_table_column,
};
struct dmc_drex_dfs_mif_table {
unsigned int drex_Tick_Granularity;
unsigned int drex_mr4_sensing_cyc;
unsigned int drex_dqs_osc_start_cyc;
unsigned int drex_Termination_Control;
unsigned int drex_Winconfig_Write_Odt;
unsigned int drex_Timing_Row0;
unsigned int drex_Timing_Row1;
unsigned int drex_Timing_Data_Aclk;
unsigned int drex_Timing_Data_Mclk;
unsigned int drex_Timing_Power0;
unsigned int drex_Timing_Power1;
unsigned int drex_Etcl;
};
struct dmc_directcmd_dfs_mif_table {
unsigned int drex_Puase_MRS0;
unsigned int drex_Puase_MRS1;
unsigned int drex_Puase_MRS2;
unsigned int drex_Puase_MRS3;
unsigned int drex_Puase_MRS4;
};
struct dmc_phy_dfs_mif_table {
unsigned int phy_Dvfs_Con0_set1;
unsigned int phy_Dvfs_Con0_set0;
unsigned int phy_Dvfs_Con0_set1_mask;
unsigned int phy_Dvfs_Con0_set0_mask;
unsigned int phy_Dvfs_Con1_set1;
unsigned int phy_Dvfs_Con1_set0;
unsigned int phy_Dvfs_Con1_set1_mask;
unsigned int phy_Dvfs_Con1_set0_mask;
unsigned int phy_Dvfs_Con2_set1;
unsigned int phy_Dvfs_Con2_set0;
unsigned int phy_Dvfs_Con2_set1_mask;
unsigned int phy_Dvfs_Con2_set0_mask;
unsigned int phy_Dvfs_Con3_set1;
unsigned int phy_Dvfs_Con3_set0;
unsigned int phy_Dvfs_Con3_set1_mask;
unsigned int phy_Dvfs_Con3_set0_mask;
unsigned int phy_Dvfs_Con4_set1;
unsigned int phy_Dvfs_Con4_set0;
unsigned int phy_Dvfs_Con4_set1_mask;
unsigned int phy_Dvfs_Con4_set0_mask;
unsigned int phy_Dvfs_Con5_set1;
unsigned int phy_Dvfs_Con5_set0;
unsigned int phy_Dvfs_Con5_set1_mask;
unsigned int phy_Dvfs_Con5_set0_mask;
unsigned int phy_Dvfs_Con6_set1;
unsigned int phy_Dvfs_Con6_set0;
unsigned int phy_Dvfs_Con6_set1_mask;
unsigned int phy_Dvfs_Con6_set0_mask;
};
enum dmc_dvfs_mif_switching_level_idx {
DMC_DVFS_MIF__switching_L0,
DMC_DVFS_MIF__switching_L1,
};
#define LP4_RL 12
#define LP4_WL 6
#define LP4_RL_L10 6
#define LP4_WL_L10 4
#define DRAM_RLWL 0x09
#define DRAM_RLWL_L10 0x00
static struct dmc_drex_dfs_mif_table *pwrcal_dfs_drex_mif_table;
static struct dmc_directcmd_dfs_mif_table *pwrcal_pause_directcmd_dfs_mif_table;
static struct dmc_phy_dfs_mif_table *pwrcal_dfs_phy_mif_table;
static unsigned long long *mif_freq_to_level;
static int num_mif_freq_to_level;
static unsigned int convert_to_level(unsigned long long freq)
{
int idx;
int tablesize = num_mif_freq_to_level;
for (idx = tablesize - 1; idx >= 0; idx--)
if (freq <= mif_freq_to_level[idx])
return (unsigned int)idx;
return 0;
}
void pwrcal_dmc_set_dvfs(unsigned long long target_mif_freq, unsigned int timing_set_idx)
{
unsigned int uReg;
// unsigned int soc_vref[4];
unsigned int target_mif_level_idx, target_mif_level_switch_idx;
unsigned int offset;
target_mif_level_idx = convert_to_level(target_mif_freq);
target_mif_level_switch_idx = convert_to_level(target_mif_freq);
if (timing_set_idx == DMC_TIMING_SET_0) {
for (offset = 0; offset < 0x100000; offset += 0x100000) {
/* Phy & DREX Mode setting */
if (target_mif_level_idx != 0) {
uReg = pwrcal_readl(offset + PHY0_DVFS_CON0);
uReg &= ~(PHY_DVFS_CON0_DVFS_MODE_MASK);
uReg |= (PHY_DVFS0_mode<<PHY_DVFS_CON0_DVFS_MODE_POSITION);
pwrcal_writel(offset + PHY0_DVFS_CON0, uReg);
} else {
uReg = pwrcal_readl(offset + PHY0_DVFS_CON0);
uReg &= ~(PHY_DVFS_CON0_DVFS_MODE_MASK);
uReg |= (PHY_Normal_mode<<PHY_DVFS_CON0_DVFS_MODE_POSITION);
pwrcal_writel(offset + PHY0_DVFS_CON0, uReg);
}
pwrcal_writel(offset + DREX0_TIMING_SET_SW, DREX0_timing_set_sw_con);
pwrcal_writel((void *)CMU_MIF_BASE + 0x1004, DMC_TIMING_SET_0); /*cmu pause setting */
#define PHY_DVFS_CON0_DVFS_MODE_MASK ((0x0)|(0x3<<24))
#define PHY_DVFS_CON0_DVFS_MODE_POSITION 24
pwrcal_writel(offset + DREX0_TICK_GRANULARITY_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Tick_Granularity);
pwrcal_writel(offset + DREX0_PORT_TICK_GRANULARITY_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Tick_Granularity);
pwrcal_writel(offset + DREX0_TEMP_SENSING_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_mr4_sensing_cyc);
pwrcal_writel(offset + DREX0_DQS_OSC_CON1_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_dqs_osc_start_cyc);
pwrcal_writel(offset + DREX0_TERMINATION_CONTROL_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Termination_Control);
pwrcal_writel(offset + DREX0_WINCONFIG_WRITE_ODT_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Winconfig_Write_Odt);
pwrcal_writel(offset + DREX0_TIMING_ROW0_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Timing_Row0);
pwrcal_writel(offset + DREX0_TIMING_ROW1_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Timing_Row1);
pwrcal_writel(offset + DREX0_TIMING_DATA_ACLK_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Timing_Data_Aclk);
pwrcal_writel(offset + DREX0_TIMING_DATA_MCLK_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Timing_Data_Mclk);
pwrcal_writel(offset + DREX0_TIMING_POWER0_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Timing_Power0);
pwrcal_writel(offset + DREX0_TIMING_POWER1_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Timing_Power1);
pwrcal_writel(offset + DREX0_TIMING_ETC1_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Etcl);
uReg = pwrcal_readl(offset + PHY0_DVFS_CON0);
uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con0_set0_mask);
uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con0_set0;
pwrcal_writel(offset + PHY0_DVFS_CON0, uReg);
uReg = pwrcal_readl(offset + PHY0_DVFS_CON1);
uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con1_set0_mask);
uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con1_set0;
pwrcal_writel(offset + PHY0_DVFS_CON1, uReg);
uReg = pwrcal_readl(offset + PHY0_DVFS_CON2);
uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con2_set0_mask);
uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con2_set0;
pwrcal_writel(offset + PHY0_DVFS_CON2, uReg);
uReg = pwrcal_readl(offset + PHY0_DVFS_CON3);
uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con3_set0_mask);
uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con3_set0;
pwrcal_writel(offset + PHY0_DVFS_CON3, uReg);
pwrcal_writel(offset + DREX0_PAUSE_MRS0, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_idx].drex_Puase_MRS0);
pwrcal_writel(offset + DREX0_PAUSE_MRS1, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_idx].drex_Puase_MRS1);
pwrcal_writel(offset + DREX0_PAUSE_MRS2, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_idx].drex_Puase_MRS2);
pwrcal_writel(offset + DREX0_PAUSE_MRS3, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_idx].drex_Puase_MRS3);
pwrcal_writel(offset + DREX0_PAUSE_MRS4, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_idx].drex_Puase_MRS4);
}
} else if (timing_set_idx == DMC_TIMING_SET_1) {
for (offset = 0; offset < 0x100000; offset += 0x100000) {
/* Phy & DREX Mode setting */
uReg = pwrcal_readl(offset + PHY0_DVFS_CON0);
uReg &= ~(PHY_DVFS_CON0_DVFS_MODE_MASK);
uReg |= (PHY_DVFS1_mode<<PHY_DVFS_CON0_DVFS_MODE_POSITION);
pwrcal_writel(offset + PHY0_DVFS_CON0, uReg);
pwrcal_writel(offset + DREX0_TIMING_SET_SW, DREX0_timing_set_sw_con);
pwrcal_writel((void *)CMU_MIF_BASE + 0x1004, DMC_TIMING_SET_1); /*cmu pause setting */
pwrcal_writel(offset + DREX0_TICK_GRANULARITY_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Tick_Granularity);
pwrcal_writel(offset + DREX0_PORT_TICK_GRANULARITY_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Tick_Granularity);
pwrcal_writel(offset + DREX0_TEMP_SENSING_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_mr4_sensing_cyc);
pwrcal_writel(offset + DREX0_DQS_OSC_CON1_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_dqs_osc_start_cyc);
pwrcal_writel(offset + DREX0_TERMINATION_CONTROL_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Termination_Control);
pwrcal_writel(offset + DREX0_WINCONFIG_WRITE_ODT_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Winconfig_Write_Odt);
pwrcal_writel(offset + DREX0_TIMING_ROW0_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Timing_Row0);
pwrcal_writel(offset + DREX0_TIMING_ROW1_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Timing_Row1);
pwrcal_writel(offset + DREX0_TIMING_DATA_ACLK_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Timing_Data_Aclk);
pwrcal_writel(offset + DREX0_TIMING_DATA_MCLK_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Timing_Data_Mclk);
pwrcal_writel(offset + DREX0_TIMING_POWER0_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Timing_Power0);
pwrcal_writel(offset + DREX0_TIMING_POWER1_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Timing_Power1);
pwrcal_writel(offset + DREX0_TIMING_ETC1_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Etcl);
uReg = pwrcal_readl(offset + PHY0_DVFS_CON0);
uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con0_set1_mask);
uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con0_set1;
pwrcal_writel(offset + PHY0_DVFS_CON0, uReg);
uReg = pwrcal_readl(offset + PHY0_DVFS_CON1);
uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con1_set1_mask);
uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con1_set1;
pwrcal_writel(offset + PHY0_DVFS_CON1, uReg);
uReg = pwrcal_readl(offset + PHY0_DVFS_CON2);
uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con2_set1_mask);
uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con2_set1;
pwrcal_writel(offset + PHY0_DVFS_CON2, uReg);
uReg = pwrcal_readl(offset + PHY0_DVFS_CON3);
uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con3_set1_mask);
uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con3_set1;
pwrcal_writel(offset + PHY0_DVFS_CON3, uReg);
pwrcal_writel(offset + DREX0_PAUSE_MRS0, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_switch_idx].drex_Puase_MRS0);
pwrcal_writel(offset + DREX0_PAUSE_MRS1, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_switch_idx].drex_Puase_MRS1);
pwrcal_writel(offset + DREX0_PAUSE_MRS2, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_switch_idx].drex_Puase_MRS2);
pwrcal_writel(offset + DREX0_PAUSE_MRS3, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_switch_idx].drex_Puase_MRS3);
pwrcal_writel(offset + DREX0_PAUSE_MRS4, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_switch_idx].drex_Puase_MRS4);
}
} else {
pr_err("wrong DMC timing set selection on DVFS\n");
return;
}
}
void pwrcal_dmc_set_pre_dvfs(void)
{
}
void pwrcal_dmc_set_post_dvfs(unsigned long long target_freq)
{
}
void pwrcal_dmc_set_refresh_method_pre_dvfs(unsigned long long current_rate, unsigned long long target_rate)
{
/* target_rate is MIF clock rate */
unsigned int uReg;
uReg = pwrcal_readl(DREX0_CG_CONTROL);
uReg = ((uReg & ~(1 << 24)) | (0 << 24));
pwrcal_writel(DREX0_CG_CONTROL, uReg); //External Clock Gating - PHY Clock Gating disable
}
void pwrcal_dmc_set_refresh_method_post_dvfs(unsigned long long current_rate, unsigned long long target_rate)
{
/* target_rate is MIF clock rate */
unsigned int uReg;
uReg = pwrcal_readl(DREX0_CG_CONTROL);
uReg = ((uReg & ~(1 << 24)) | (1 << 24));
pwrcal_writel(DREX0_CG_CONTROL, uReg); //External Clock Gating - PHY Clock Gating enable
}
void pwrcal_dmc_set_dsref_cycle(unsigned long long target_rate)
{
unsigned int uReg, cycle;
/* target_rate is MIF clock rate */
if (target_rate > 800 * MHZ)
cycle = 0x3ff;
else if (target_rate > 400 * MHZ)
cycle = 0x1ff;
else if (target_rate > 200 * MHZ)
cycle = 0x90;
else
cycle = 0x90;
/* dsref disable */
uReg = pwrcal_readl(DREX0_MEMORY_CONTROL0);
uReg &= ~(1 << 4);
pwrcal_writel(DREX0_MEMORY_CONTROL0, uReg);
uReg = pwrcal_readl(DREX0_POWER_DOWN_CONFIG);
uReg = ((uReg & ~(0xffff << 16)) | (cycle << 16));
pwrcal_writel(DREX0_POWER_DOWN_CONFIG, uReg);
/* dsref enable */
uReg = pwrcal_readl(DREX0_MEMORY_CONTROL0);
uReg |= (1 << 4);
pwrcal_writel(DREX0_MEMORY_CONTROL0, uReg);
}
void dfs_dram_param_init(void)
{
int i;
void *dram_block;
u32 uMem_type;
// int memory_size = 2; // means 3GB
struct ect_timing_param_size *size;
// uMem_type = (pwrcal_readl(DREX_CALIBRATION2) & 0xFFFF);
uMem_type = 2; // 2GB
dram_block = ect_get_block(BLOCK_TIMING_PARAM);
if (dram_block == NULL)
return;
size = ect_timing_param_get_size(dram_block, uMem_type);
if (size == NULL)
return;
if (num_of_dram_parameter != size->num_of_timing_param)
return;
pwrcal_dfs_drex_mif_table = kzalloc(sizeof(struct dmc_drex_dfs_mif_table) * num_of_g_dmc_drex_dfs_mif_table_column * size->num_of_level, GFP_KERNEL);
if (pwrcal_dfs_drex_mif_table == NULL)
return;
pwrcal_pause_directcmd_dfs_mif_table = kzalloc(sizeof(struct dmc_directcmd_dfs_mif_table) * num_of_g_dmc_directcmd_dfs_mif_table_column * size->num_of_level, GFP_KERNEL);
if (pwrcal_pause_directcmd_dfs_mif_table == NULL)
return;
pwrcal_dfs_phy_mif_table = kzalloc(sizeof(struct dmc_phy_dfs_mif_table) * num_of_g_dmc_phy_dfs_mif_table_column * size->num_of_level, GFP_KERNEL);
if (pwrcal_dfs_phy_mif_table == NULL)
return;
for (i = 0; i < size->num_of_level; ++i) {
pwrcal_dfs_drex_mif_table[i].drex_Tick_Granularity = size->timing_parameter[i * num_of_dram_parameter + drex_Tick_Granularity];
pwrcal_dfs_drex_mif_table[i].drex_mr4_sensing_cyc = size->timing_parameter[i * num_of_dram_parameter + drex_mr4_sensing_cyc];
pwrcal_dfs_drex_mif_table[i].drex_dqs_osc_start_cyc = size->timing_parameter[i * num_of_dram_parameter + drex_dqs_osc_start_cyc];
pwrcal_dfs_drex_mif_table[i].drex_Termination_Control = size->timing_parameter[i * num_of_dram_parameter + drex_Termination_Control];
pwrcal_dfs_drex_mif_table[i].drex_Winconfig_Write_Odt = size->timing_parameter[i * num_of_dram_parameter + drex_Winconfig_Write_Odt];
pwrcal_dfs_drex_mif_table[i].drex_Timing_Row0 = size->timing_parameter[i * num_of_dram_parameter + drex_Timing_Row0];
pwrcal_dfs_drex_mif_table[i].drex_Timing_Row1 = size->timing_parameter[i * num_of_dram_parameter + drex_Timing_Row1];
pwrcal_dfs_drex_mif_table[i].drex_Timing_Data_Aclk = size->timing_parameter[i * num_of_dram_parameter + drex_Timing_Data_Aclk];
pwrcal_dfs_drex_mif_table[i].drex_Timing_Data_Mclk = size->timing_parameter[i * num_of_dram_parameter + drex_Timing_Data_Mclk];
pwrcal_dfs_drex_mif_table[i].drex_Timing_Power0 = size->timing_parameter[i * num_of_dram_parameter + drex_Timing_Power0];
pwrcal_dfs_drex_mif_table[i].drex_Timing_Power1 = size->timing_parameter[i * num_of_dram_parameter + drex_Timing_Power1];
pwrcal_dfs_drex_mif_table[i].drex_Etcl = size->timing_parameter[i * num_of_dram_parameter + drex_Etcl];
pwrcal_pause_directcmd_dfs_mif_table[i].drex_Puase_MRS0 = size->timing_parameter[i * num_of_dram_parameter + drex_Puase_MRS0];
pwrcal_pause_directcmd_dfs_mif_table[i].drex_Puase_MRS1 = size->timing_parameter[i * num_of_dram_parameter + drex_Puase_MRS1];
pwrcal_pause_directcmd_dfs_mif_table[i].drex_Puase_MRS2 = size->timing_parameter[i * num_of_dram_parameter + drex_Puase_MRS2];
pwrcal_pause_directcmd_dfs_mif_table[i].drex_Puase_MRS3 = size->timing_parameter[i * num_of_dram_parameter + drex_Puase_MRS3];
pwrcal_pause_directcmd_dfs_mif_table[i].drex_Puase_MRS4 = size->timing_parameter[i * num_of_dram_parameter + drex_Puase_MRS4];
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con0_set1 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con0_set1];
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con0_set0 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con0_set0];
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con0_set1_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con0_set1_mask];
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con0_set0_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con0_set0_mask];
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con1_set1 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con1_set1];
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con1_set0 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con1_set0];
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con1_set1_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con1_set1_mask];
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con1_set0_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con1_set0_mask];
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con2_set1 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con2_set1];
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con2_set0 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con2_set0];
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con2_set1_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con2_set1_mask];
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con2_set0_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con2_set0_mask];
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con3_set1 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con3_set1];
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con3_set0 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con3_set0];
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con3_set1_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con3_set1_mask];
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con3_set0_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con3_set0_mask];
}
}
void dfs_mif_level_init(void)
{
int i;
void *dvfs_block;
struct ect_dvfs_domain *domain;
dvfs_block = ect_get_block(BLOCK_DVFS);
if (dvfs_block == NULL)
return;
domain = ect_dvfs_get_domain(dvfs_block, vclk_dvfs_mif.vclk.name);
if (domain == NULL)
return;
mif_freq_to_level = kzalloc(sizeof(unsigned long long) * domain->num_of_level, GFP_KERNEL);
if (mif_freq_to_level == NULL)
return;
num_mif_freq_to_level = domain->num_of_level;
for (i = 0; i < domain->num_of_level; ++i)
mif_freq_to_level[i] = domain->list_level[i].level * KHZ;
}
void dfs_dram_init(void)
{
dfs_dram_param_init();
dfs_mif_level_init();
}

864
drivers/soc/samsung/pwrcal/S5E7570/S5E7570-pll.c Normal file
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@ -0,0 +1,864 @@
#include "../pwrcal.h"
#include "../pwrcal-clk.h"
#include "../pwrcal-env.h"
#include "../pwrcal-rae.h"
#include "../pwrcal-pmu.h"
#include "S5E7570-cmusfr.h"
#include "S5E7570-pmusfr.h"
#include "S5E7570-cmu.h"
/* PLLs */
/* PLL141XX Clock Type */
#define PLL141XX_MDIV_SHIFT 16
#define PLL141XX_PDIV_SHIFT 8
#define PLL141XX_SDIV_SHIFT 0
#define PLL141XX_MDIV_MASK 0x3FF
#define PLL141XX_PDIV_MASK 0x3F
#define PLL141XX_SDIV_MASK 0x7
#define PLL141XX_ENABLE 31
#define PLL141XX_LOCKED 29
#define PLL141XX_BYPASS 22
/* PLL1431X Clock Type */
#define PLL1431X_MDIV_SHIFT 16
#define PLL1431X_PDIV_SHIFT 8
#define PLL1431X_SDIV_SHIFT 0
#define PLL1431X_K_SHIFT 0
#define PLL1431X_MDIV_MASK 0x3FF
#define PLL1431X_PDIV_MASK 0x3F
#define PLL1431X_SDIV_MASK 0x7
#define PLL1431X_K_MASK 0xFFFF
#define PLL1431X_ENABLE 31
#define PLL1431X_LOCKED 29
#define PLL1431X_BYPASS 4
/* WPLL_USB_PLL Clock Type */
#define WIFI2AP_USBPLL_ACK 1
#define AP2WIFI_USBPLL_REQ 0
#define AP2WLBT_SR7 ((void *)(0x1058009C))
#define USBPLL_WPLL_FREF_SEL 3
#define USBPLL_WPLL_AFC_START 2
#define USBPLL_WPLL_EN 1
#define USBPLL_WPLL_SEL 0
#define FIN_HZ_26M (26*MHZ)
static const struct pwrcal_pll_rate_table *_clk_get_pll_settings(
struct pwrcal_pll *pll_clk,
unsigned long long rate)
{
int i;
const struct pwrcal_pll_rate_table *prate_table = pll_clk->rate_table;
for (i = 0; i < pll_clk->rate_count; i++) {
if (rate == prate_table[i].rate)
return &prate_table[i];
}
return NULL;
}
static int _clk_pll141xx_find_pms(struct pll_spec *pll_spec,
struct pwrcal_pll_rate_table *rate_table,
unsigned long long rate)
{
unsigned int p, m, s;
unsigned long long fref, fvco, fout;
unsigned long long tmprate, tmpfout = 0;
unsigned long long mindiffrate = 0xFFFFFFFFFFFFFFFF;
unsigned int min_p = 0, min_m = 0, min_s = 0, min_fout = 0;
for (p = pll_spec->pdiv_min; p <= pll_spec->pdiv_max; p++) {
fref = FIN_HZ_26M / p;
if ((fref < pll_spec->fref_min) || (fref > pll_spec->fref_max))
continue;
for (s = pll_spec->sdiv_min; s <= pll_spec->sdiv_max; s++) {
tmprate = rate;
do_div(tmprate, KHZ);
tmprate = tmprate * p * (1 << s);
do_div(tmprate, (FIN_HZ_26M / KHZ));
m = (unsigned int)tmprate;
if ((m < pll_spec->mdiv_min)
|| (m > pll_spec->mdiv_max))
continue;
fvco = ((unsigned long long)FIN_HZ_26M) * m;
do_div(fvco, p);
if ((fvco < pll_spec->fvco_min)
|| (fvco > pll_spec->fvco_max))
continue;
fout = fvco >> s;
if ((fout >= pll_spec->fout_min)
&& (fout <= pll_spec->fout_max)) {
tmprate = rate;
do_div(tmprate, KHZ);
tmpfout = fout;
do_div(tmpfout, KHZ);
if (tmprate == tmpfout) {
rate_table->rate = fout;
rate_table->pdiv = p;
rate_table->mdiv = m;
rate_table->sdiv = s;
rate_table->kdiv = 0;
return 0;
}
if (tmpfout < tmprate && mindiffrate > tmprate - tmpfout) {
mindiffrate = tmprate - tmpfout;
min_fout = fout;
min_p = p;
min_m = m;
min_s = s;
}
}
}
}
if (mindiffrate != 0xFFFFFFFFFFFFFFFF) {
rate_table->rate = min_fout;
rate_table->pdiv = min_p;
rate_table->mdiv = min_m;
rate_table->sdiv = min_s;
rate_table->kdiv = 0;
return 0;
}
return -1;
}
static int _clk_pll1419x_find_pms(struct pll_spec *pll_spec,
struct pwrcal_pll_rate_table *rate_table,
unsigned long long rate)
{
unsigned int p, m, s;
unsigned long long fref, fvco, fout;
unsigned long long tmprate, tmpfout = 0;
unsigned long long mindiffrate = 0xFFFFFFFFFFFFFFFF;
unsigned int min_p = 0, min_m = 0, min_s = 0, min_fout = 0;
for (p = pll_spec->pdiv_min; p <= pll_spec->pdiv_max; p++) {
fref = FIN_HZ_26M / p;
if ((fref < pll_spec->fref_min) || (fref > pll_spec->fref_max))
continue;
for (s = pll_spec->sdiv_min; s <= pll_spec->sdiv_max; s++) {
/*tmprate = rate;*/
tmprate = rate/2; /*for PLL1419*/
do_div(tmprate, KHZ);
tmprate = tmprate * p * (1 << s);
do_div(tmprate, (FIN_HZ_26M / KHZ));
m = (unsigned int)tmprate;
if ((m < pll_spec->mdiv_min)
|| (m > pll_spec->mdiv_max))
continue;
fvco = ((unsigned long long)FIN_HZ_26M) * m;
do_div(fvco, p);
if ((fvco < pll_spec->fvco_min)
|| (fvco > pll_spec->fvco_max))
continue;
fout = fvco >> s;
if ((fout >= pll_spec->fout_min)
&& (fout <= pll_spec->fout_max)) {
tmprate = rate;
do_div(tmprate, KHZ);
tmpfout = fout;
do_div(tmpfout, KHZ);
if (tmprate == tmpfout) {
rate_table->rate = fout;
rate_table->pdiv = p;
rate_table->mdiv = m;
rate_table->sdiv = s;
rate_table->kdiv = 0;
return 0;
}
}
if (tmpfout < tmprate && mindiffrate > tmprate - tmpfout) {
mindiffrate = tmprate - tmpfout;
min_fout = fout;
min_p = p;
min_m = m;
min_s = s;
}
}
}
if (mindiffrate != 0xFFFFFFFFFFFFFFFF) {
rate_table->rate = min_fout;
rate_table->pdiv = min_p;
rate_table->mdiv = min_m;
rate_table->sdiv = min_s;
rate_table->kdiv = 0;
return 0;
}
return -1;
}
static int _clk_pll141xx_is_enabled(struct pwrcal_clk *clk)
{
return (int)(pwrcal_getbit(clk->offset, PLL141XX_ENABLE));
}
static int _clk_pll141xx_enable(struct pwrcal_clk *clk)
{
int timeout;
pwrcal_setbit(clk->offset, PLL141XX_ENABLE, 1);
for (timeout = 0;; timeout++) {
if (pwrcal_getbit(clk->offset, PLL141XX_LOCKED))
break;
if (timeout > CLK_WAIT_CNT)
return -1;
cpu_relax();
}
return 0;
}
static int _clk_pll1419x_enable(struct pwrcal_clk *clk)
{
int timeout;
pwrcal_setbit(clk->offset, PLL141XX_ENABLE, 1);
for (timeout = 0;; timeout++) {
if (pwrcal_getbit(clk->offset, PLL141XX_LOCKED))
break;
if (timeout > CLK_WAIT_CNT)
return -1;
cpu_relax();
}
return 0;
}
static int _clk_pll141xx_disable(struct pwrcal_clk *clk)
{
pwrcal_setbit(clk->offset, PLL141XX_ENABLE, 0);
return 0;
}
int _clk_pll141xx_is_disabled_bypass(struct pwrcal_clk *clk)
{
if (pwrcal_getbit(clk->offset + 1, PLL141XX_BYPASS))
return 0;
return 1;
}
int _clk_pll141xx_set_bypass(struct pwrcal_clk *clk, int bypass_disable)
{
if (bypass_disable == 0)
pwrcal_setbit(clk + 1, PLL141XX_BYPASS, 1);
else
pwrcal_setbit(clk + 1, PLL141XX_BYPASS, 0);
return 0;
}
static int _clk_pll141xx_set_pms(struct pwrcal_clk *clk,
const struct pwrcal_pll_rate_table *rate_table)
{
unsigned int mdiv, pdiv, sdiv, pll_con0;
int timeout;
pdiv = rate_table->pdiv;
mdiv = rate_table->mdiv;
sdiv = rate_table->sdiv;
pll_con0 = pwrcal_readl(clk->offset);
pll_con0 &= ~((PLL141XX_MDIV_MASK << PLL141XX_MDIV_SHIFT)
| (PLL141XX_PDIV_MASK << PLL141XX_PDIV_SHIFT)
| (PLL141XX_SDIV_MASK << PLL141XX_SDIV_SHIFT));
pll_con0 |= (mdiv << PLL141XX_MDIV_SHIFT)
| (pdiv << PLL141XX_PDIV_SHIFT)
| (sdiv << PLL141XX_SDIV_SHIFT);
pll_con0 &= ~(1<<26);
pll_con0 |= (1<<5);
pwrcal_writel(clk->status, pdiv*150);
pwrcal_writel(clk->offset, pll_con0);
if (pll_con0 & (1 << PLL141XX_ENABLE)) {
for (timeout = 0;; timeout++) {
if (pwrcal_getbit(clk->offset, PLL141XX_LOCKED))
break;
if (timeout > CLK_WAIT_CNT)
return -1;
cpu_relax();
}
}
return 0;
}
static int _clk_pll1419x_set_pms(struct pwrcal_clk *clk,
const struct pwrcal_pll_rate_table *rate_table)
{
unsigned int mdiv, pdiv, sdiv, pll_con0;
int timeout;
pdiv = rate_table->pdiv;
mdiv = rate_table->mdiv;
sdiv = rate_table->sdiv;
pll_con0 = pwrcal_readl(clk->offset);
pll_con0 &= ~((PLL141XX_MDIV_MASK << PLL141XX_MDIV_SHIFT)
| (PLL141XX_PDIV_MASK << PLL141XX_PDIV_SHIFT)
| (PLL141XX_SDIV_MASK << PLL141XX_SDIV_SHIFT));
pll_con0 |= (mdiv << PLL141XX_MDIV_SHIFT)
| (pdiv << PLL141XX_PDIV_SHIFT)
| (sdiv << PLL141XX_SDIV_SHIFT);
pwrcal_writel(clk->status, pdiv * 150);
pwrcal_writel(clk->offset, pll_con0);
if (pll_con0 & (1 << PLL141XX_ENABLE)) {
for (timeout = 0;; timeout++) {
if (pwrcal_getbit(clk->offset, PLL141XX_LOCKED))
break;
if (timeout > CLK_WAIT_CNT)
return -1;
cpu_relax();
}
}
return 0;
}
static int _clk_pll141xx_set_rate(struct pwrcal_clk *clk,
unsigned long long rate)
{
struct pwrcal_pll *pll = to_pll(clk);
struct pll_spec *pll_spec;
struct pwrcal_pll_rate_table tmp_rate_table;
const struct pwrcal_pll_rate_table *rate_table;
if (rate == 0) {
if (_clk_pll141xx_is_enabled(clk) != 0)
if (_clk_pll141xx_disable(clk))
goto errorout;
return 0;
}
rate_table = _clk_get_pll_settings(pll, rate);
if (rate_table == NULL) {
pll_spec = clk_pll_get_spec(clk);
if (pll_spec == NULL)
goto errorout;
if (_clk_pll141xx_find_pms(pll_spec, &tmp_rate_table, rate)) {
pr_err("can't find pms value for rate(%lldHz) of \'%s\'",
rate,
clk->name);
goto errorout;
}
rate_table = &tmp_rate_table;
pr_warn("not exist in rate table, p(%d), m(%d), s(%d), fout(%lldHz) %s",
rate_table->pdiv,
rate_table->mdiv,
rate_table->sdiv,
rate,
clk->name);
}
if (_clk_pll141xx_set_pms(clk, rate_table))
goto errorout;
if (rate != 0) {
if (_clk_pll141xx_is_enabled(clk) == 0)
_clk_pll141xx_enable(clk);
}
return 0;
errorout:
return -1;
}
static int _clk_pll1419x_set_rate(struct pwrcal_clk *clk,
unsigned long long rate)
{
struct pwrcal_pll *pll = to_pll(clk);
struct pll_spec *pll_spec;
struct pwrcal_pll_rate_table tmp_rate_table;
const struct pwrcal_pll_rate_table *rate_table;
if (rate == 0) {
if (_clk_pll141xx_is_enabled(clk) != 0)
if (_clk_pll141xx_disable(clk))
goto errorout;
return 0;
}
rate_table = _clk_get_pll_settings(pll, rate);
if (rate_table == NULL) {
pll_spec = clk_pll_get_spec(clk);
if (pll_spec == NULL)
goto errorout;
if (_clk_pll1419x_find_pms(pll_spec, &tmp_rate_table, rate)) {
pr_err("can't find pms value for rate(%lldHz) of \'%s\'",
rate,
clk->name);
goto errorout;
}
rate_table = &tmp_rate_table;
pr_warn("not exist in rate table, p(%d), m(%d), s(%d), fout(%lldHz) %s",
rate_table->pdiv,
rate_table->mdiv,
rate_table->sdiv,
rate,
clk->name);
}
_clk_pll141xx_disable(clk);
if (_clk_pll1419x_set_pms(clk, rate_table))
goto errorout;
if (rate != 0) {
if (_clk_pll141xx_is_enabled(clk) == 0)
_clk_pll1419x_enable(clk);
}
return 0;
errorout:
return -1;
}
static unsigned long long _clk_pll141xx_get_rate(struct pwrcal_clk *clk)
{
unsigned int mdiv, pdiv, sdiv, pll_con0;
unsigned long long fout;
if (_clk_pll141xx_is_enabled(clk) == 0)
return 0;
pll_con0 = pwrcal_readl(clk->offset);
mdiv = (pll_con0 >> PLL141XX_MDIV_SHIFT) & PLL141XX_MDIV_MASK;
pdiv = (pll_con0 >> PLL141XX_PDIV_SHIFT) & PLL141XX_PDIV_MASK;
sdiv = (pll_con0 >> PLL141XX_SDIV_SHIFT) & PLL141XX_SDIV_MASK;
if (pdiv == 0) {
pr_err("pdiv is 0, id(%s)", clk->name);
return 0;
}
fout = FIN_HZ_26M * mdiv;
do_div(fout, (pdiv << sdiv));
return (unsigned long long)fout;
}
static unsigned long long _clk_pll1419x_get_rate(struct pwrcal_clk *clk)
{
unsigned int mdiv, pdiv, sdiv, pll_con0;
unsigned long long fout;
if (_clk_pll141xx_is_enabled(clk) == 0)
return 0;
pll_con0 = pwrcal_readl(clk->offset);
mdiv = (pll_con0 >> PLL141XX_MDIV_SHIFT) & PLL141XX_MDIV_MASK;
pdiv = (pll_con0 >> PLL141XX_PDIV_SHIFT) & PLL141XX_PDIV_MASK;
sdiv = (pll_con0 >> PLL141XX_SDIV_SHIFT) & PLL141XX_SDIV_MASK;
if (pdiv == 0) {
pr_err("pdiv is 0, id(%s)", clk->name);
return 0;
}
fout = FIN_HZ_26M * 2 * mdiv;
do_div(fout, (pdiv << sdiv));
return (unsigned long long)fout;
}
static int _clk_pll1431x_find_pms(struct pll_spec *pll_spec,
struct pwrcal_pll_rate_table *rate_table,
unsigned long long rate)
{
unsigned int p, m, s;
signed short k;
unsigned long long fref, fvco, fout;
unsigned long long tmprate, tmpfout;
for (p = pll_spec->pdiv_min; p <= pll_spec->pdiv_max; p++) {
fref = FIN_HZ_26M / p;
if ((fref < pll_spec->fref_min) || (fref > pll_spec->fref_max))
continue;
for (s = pll_spec->sdiv_min; s <= pll_spec->sdiv_max; s++) {
tmprate = rate;
do_div(tmprate, KHZ);
tmprate = tmprate * p * (1 << s);
do_div(tmprate, (FIN_HZ_26M / KHZ));
m = (unsigned int)tmprate;
if ((m < pll_spec->mdiv_min)
|| (m > pll_spec->mdiv_max))
continue;
tmprate = rate;
do_div(tmprate, KHZ);
tmprate = tmprate * p * (1 << s);
do_div(tmprate, (FIN_HZ_26M / KHZ));
tmprate = (tmprate - m) * 65536;
k = (unsigned int)tmprate;
if ((k < pll_spec->kdiv_min)
|| (k > pll_spec->kdiv_max))
continue;
fvco = FIN_HZ_26M * ((m << 16) + k);
do_div(fvco, p);
fvco >>= 16;
if ((fvco < pll_spec->fvco_min)
|| (fvco > pll_spec->fvco_max))
continue;
fout = fvco >> s;
if ((fout >= pll_spec->fout_min)
&& (fout <= pll_spec->fout_max)) {
tmprate = rate;
do_div(tmprate, KHZ);
tmpfout = fout;
do_div(tmpfout, KHZ);
if (tmprate == tmpfout) {
rate_table->rate = fout;
rate_table->pdiv = p;
rate_table->mdiv = m;
rate_table->sdiv = s;
rate_table->kdiv = k;
return 0;
}
}
}
}
return -1;
}
static int _clk_pll1431x_is_enabled(struct pwrcal_clk *clk)
{
return (int)(pwrcal_getbit(clk->offset, PLL1431X_ENABLE));
}
static int _clk_pll1431x_enable(struct pwrcal_clk *clk)
{
int timeout;
pwrcal_setbit(clk->offset, PLL1431X_ENABLE, 1);
for (timeout = 0;; timeout++) {
if (pwrcal_getbit(clk->offset, PLL1431X_LOCKED))
break;
if (timeout > CLK_WAIT_CNT)
return -1;
cpu_relax();
}
return 0;
}
static int _clk_pll1431x_disable(struct pwrcal_clk *clk)
{
pwrcal_setbit(clk->offset, PLL1431X_ENABLE, 0);
return 0;
}
int _clk_pll1431x_is_disabled_bypass(struct pwrcal_clk *clk)
{
if (pwrcal_getbit(clk->offset + 2, PLL1431X_BYPASS))
return 0;
return 1;
}
int _clk_pll1431x_set_bypass(struct pwrcal_clk *clk, int bypass_disable)
{
if (bypass_disable == 0)
pwrcal_setbit(clk->offset + 2, PLL1431X_BYPASS, 1);
else
pwrcal_setbit(clk->offset + 2, PLL1431X_BYPASS, 0);
return 0;
}
static int _clk_pll1431x_set_pms(struct pwrcal_clk *clk,
const struct pwrcal_pll_rate_table *rate_table)
{
unsigned int mdiv, pdiv, sdiv, pll_con0, pll_con1;
signed short kdiv;
int timeout;
pdiv = rate_table->pdiv;
mdiv = rate_table->mdiv;
sdiv = rate_table->sdiv;
kdiv = rate_table->kdiv;
pll_con0 = pwrcal_readl(clk->offset);
pll_con1 = pwrcal_readl(clk->offset + 1);
pll_con0 &= ~((PLL1431X_MDIV_MASK << PLL1431X_MDIV_SHIFT)
| (PLL1431X_PDIV_MASK << PLL1431X_PDIV_SHIFT)
| (PLL1431X_SDIV_MASK << PLL1431X_SDIV_SHIFT));
pll_con0 |= (mdiv << PLL1431X_MDIV_SHIFT)
| (pdiv << PLL1431X_PDIV_SHIFT)
| (sdiv << PLL1431X_SDIV_SHIFT);
pll_con0 &= ~(1<<26);
pll_con0 |= (1<<5);
pll_con1 &= ~(PLL1431X_K_MASK << PLL1431X_K_SHIFT);
pll_con1 |= (kdiv << PLL1431X_K_SHIFT);
if (kdiv == 0)
pwrcal_writel(clk->status, pdiv*3000);
else
pwrcal_writel(clk->status, pdiv*3000);
pwrcal_writel(clk->offset, pll_con0);
pwrcal_writel(clk->offset + 1, pll_con1);
if (pll_con0 & (1 << PLL1431X_ENABLE)) {
for (timeout = 0;; timeout++) {
if (pwrcal_getbit(clk->offset, PLL1431X_LOCKED))
break;
if (timeout > CLK_WAIT_CNT)
return -1;
cpu_relax();
}
}
return 0;
}
static int _clk_pll1431x_set_rate(struct pwrcal_clk *clk,
unsigned long long rate)
{
struct pwrcal_pll *pll = to_pll(clk);
struct pwrcal_pll_rate_table tmp_rate_table;
const struct pwrcal_pll_rate_table *rate_table;
struct pll_spec *pll_spec;
if (rate == 0) {
if (_clk_pll1431x_is_enabled(clk) != 0)
if (_clk_pll1431x_disable(clk))
goto errorout;
return 0;
}
rate_table = _clk_get_pll_settings(pll, rate);
if (rate_table == NULL) {
pll_spec = clk_pll_get_spec(clk);
if (pll_spec == NULL)
goto errorout;
if (_clk_pll1431x_find_pms(pll_spec, &tmp_rate_table, rate) < 0) {
pr_err("can't find pms value for rate(%lldHz) of %s",
rate,
clk->name);
goto errorout;
}
rate_table = &tmp_rate_table;
pr_warn("not exist in rate table, p(%d) m(%d) s(%d) k(%d) fout(%lld Hz) of %s",
rate_table->pdiv,
rate_table->mdiv,
rate_table->sdiv,
rate_table->kdiv,
rate,
clk->name);
}
if (_clk_pll1431x_set_pms(clk, rate_table))
goto errorout;
if (rate != 0) {
if (_clk_pll1431x_is_enabled(clk) == 0)
_clk_pll1431x_enable(clk);
}
return 0;
errorout:
return -1;
}
static unsigned long long _clk_pll1431x_get_rate(struct pwrcal_clk *clk)
{
unsigned int mdiv, pdiv, sdiv, pll_con0, pll_con1;
signed short kdiv;
unsigned long long fout;
if (_clk_pll1431x_is_enabled(clk) == 0)
return 0;
pll_con0 = pwrcal_readl(clk->offset);
pll_con1 = pwrcal_readl(clk->offset + 1);
mdiv = (pll_con0 >> PLL1431X_MDIV_SHIFT) & PLL1431X_MDIV_MASK;
pdiv = (pll_con0 >> PLL1431X_PDIV_SHIFT) & PLL1431X_PDIV_MASK;
sdiv = (pll_con0 >> PLL1431X_SDIV_SHIFT) & PLL1431X_SDIV_MASK;
kdiv = (short)(pll_con1 >> PLL1431X_K_SHIFT) & PLL1431X_K_MASK;
if (pdiv == 0) {
pr_err("pdiv is 0, id(%s)", clk->name);
return 0;
}
fout = FIN_HZ_26M * ((mdiv << 16) + kdiv);
do_div(fout, (pdiv << sdiv));
fout >>= 16;
return (unsigned long long)fout;
}
static int _clk_wpll_usbpll_is_enabled(struct pwrcal_clk *clk)
{
if (pwrcal_getbit(clk->offset, USBPLL_WPLL_SEL) == 1) {
pr_err("%s: USBPLL_WPLL_SEL==1\n", __func__);
return (int)(pwrcal_getbit(clk->offset, USBPLL_WPLL_EN));
}
pr_err("%s: USBPLL_WPLL_SEL==0\n", __func__);
return (int)pwrcal_getbit(clk->status, WIFI2AP_USBPLL_ACK);
}
static int _clk_wpll_usbpll_enable(struct pwrcal_clk *clk)
{
int timeout;
/* check changed WPLL input selection to AP (AP2WLBT_USBPLL_WPLL_SEL). */
if (pwrcal_getbit(clk->offset, USBPLL_WPLL_SEL) == 0x1) {
pr_info("%s AP %p\n", __func__, clk->offset);
if (pwrcal_getbit(clk->offset, USBPLL_WPLL_EN) == 0x1) {
pr_info("%s USBPLL_WPLL_EN==1\n", __func__);
return 0;
}
/* pwrcal_setbit(clk->offset, 0, 0x1); */
if (pwrcal_getbit(TCXO_SHARED_STATUS, 8) == 1)
pwrcal_setbit(clk->offset, USBPLL_WPLL_FREF_SEL, 0x1); /* TCXO_SHARED_STATUS = 52Mhz */
else
pwrcal_setbit(clk->offset, USBPLL_WPLL_FREF_SEL, 0x0); /* 26Mhz */
/* Set WPLL enable (AP2WLBT_USBPLL_WPLL_EN) */
pwrcal_setbit(clk->offset, USBPLL_WPLL_EN, 0x1);
/* wait 20us for power settle time. */
for (timeout = 0;; timeout++) {
if (timeout >= 20)
break;
cpu_relax();
}
/* Set WPLL AFC Start (AP2WLBT_USBPLL_WPLL_AFC_START) */
pwrcal_setbit(clk->offset, USBPLL_WPLL_AFC_START, 0x1);
/* wait 60us for clock stabilization. */
for (timeout = 0;; timeout++) {
if (timeout >= 60)
break;
cpu_relax();
}
} else {
pr_info("%s WLBT\n", __func__);
/* WPLL input selection to WLBT */
/* (IP) use ack */
if (pwrcal_getbit(clk->status, WIFI2AP_USBPLL_ACK) == 0x1) {
pr_info("%s USBPLL_ACK==1, already\n", __func__);
return 0;
}
/* AP2WIFI_USBPLL_REQ */
pwrcal_setbit(clk->status, AP2WIFI_USBPLL_REQ, 0x1);
pr_info("%s AP2WIFI_USBPLL_REQ=1\n", __func__);
}
return 0;
}
static int _clk_wpll_usbpll_disable(struct pwrcal_clk *clk)
{
if (pwrcal_getbit(clk->offset, USBPLL_WPLL_SEL) == 0) {
pwrcal_setbit(clk->status, AP2WIFI_USBPLL_REQ, 0x0);
pr_err("%s AP2WIFI_USBPLL_REQ=0\n", __func__);
}
return 0;
}
static int _clk_wpll_usbpll_set_rate(struct pwrcal_clk *clk,
unsigned long long rate)
{
if (rate == 0) {
if (_clk_wpll_usbpll_is_enabled(clk) != 0)
if (_clk_wpll_usbpll_disable(clk))
goto errorout;
} else { /* rate != 0 */
if (_clk_wpll_usbpll_is_enabled(clk) == 0)
_clk_wpll_usbpll_enable(clk);
/* pr_warn("WPLL_USBPLL set 20Mhz"); */
}
return 0;
errorout:
return -1;
}
static unsigned long long _clk_wpll_usbpll_get_rate(struct pwrcal_clk *clk)
{
unsigned long long fout;
if (_clk_wpll_usbpll_is_enabled(clk) == 0)
return 0;
fout = (20*MHZ);
return (unsigned long long)fout;
}
struct pwrcal_pll_ops pll141xx_ops = {
.is_enabled = _clk_pll141xx_is_enabled,
.enable = _clk_pll141xx_enable,
.disable = _clk_pll141xx_disable,
.set_rate = _clk_pll141xx_set_rate,
.get_rate = _clk_pll141xx_get_rate,
};
struct pwrcal_pll_ops pll1419x_ops = {
.is_enabled = _clk_pll141xx_is_enabled,
.enable = _clk_pll1419x_enable,
.disable = _clk_pll141xx_disable,
.set_rate = _clk_pll1419x_set_rate,
.get_rate = _clk_pll1419x_get_rate,
};
struct pwrcal_pll_ops pll1431x_ops = {
.is_enabled = _clk_pll1431x_is_enabled,
.enable = _clk_pll1431x_enable,
.disable = _clk_pll1431x_disable,
.set_rate = _clk_pll1431x_set_rate,
.get_rate = _clk_pll1431x_get_rate,
};
struct pwrcal_pll_ops wpll_usbpll_ops = {
.is_enabled = _clk_wpll_usbpll_is_enabled,
.enable = _clk_wpll_usbpll_enable,
.disable = _clk_wpll_usbpll_disable,
.set_rate = _clk_wpll_usbpll_set_rate,
.get_rate = _clk_wpll_usbpll_get_rate,
};

104
drivers/soc/samsung/pwrcal/S5E7570/S5E7570-pmu.c Normal file
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#include "../pwrcal.h"
#include "../pwrcal-env.h"
#include "../pwrcal-rae.h"
#include "../pwrcal-pmu.h"
#include "S5E7570-cmusfr.h"
#include "S5E7570-pmusfr.h"
#include "S5E7570-cmu.h"
static void dispaud_prev(int enable)
{
pwrcal_setbit(CLKRUN_CMU_DISPAUD_SYS_PWR_REG, 0, 0);
pwrcal_setbit(CLKSTOP_CMU_DISPAUD_SYS_PWR_REG, 0, 0);
pwrcal_setbit(DISABLE_PLL_CMU_DISPAUD_SYS_PWR_REG, 0, 0);
pwrcal_setf(RESET_LOGIC_DISPAUD_SYS_PWR_REG, 0, 0x3, 0);
pwrcal_setf(RESET_CMU_DISPAUD_SYS_PWR_REG, 0, 0x3, 0);
}
static void g3d_prev(int enable)
{
pwrcal_setbit(CLKRUN_CMU_G3D_SYS_PWR_REG, 0, 0);
pwrcal_setbit(CLKSTOP_CMU_G3D_SYS_PWR_REG, 0, 0);
pwrcal_setbit(DISABLE_PLL_CMU_G3D_SYS_PWR_REG, 0, 0);
pwrcal_setf(RESET_LOGIC_G3D_SYS_PWR_REG, 0, 0x3, 0);
pwrcal_setf(RESET_CMU_G3D_SYS_PWR_REG, 0, 0x3, 0);
}
static void isp_prev(int enable)
{
pwrcal_setbit(CLKRUN_CMU_ISP_SYS_PWR_REG, 0, 0);
pwrcal_setbit(CLKSTOP_CMU_ISP_SYS_PWR_REG, 0, 0);
pwrcal_setbit(DISABLE_PLL_CMU_ISP_SYS_PWR_REG, 0, 0);
pwrcal_setf(RESET_LOGIC_ISP_SYS_PWR_REG, 0, 0x3, 0);
pwrcal_setf(RESET_CMU_ISP_SYS_PWR_REG, 0, 0x3, 0);
}
static void mfcmscl_prev(int enable)
{
pwrcal_setbit(CLKRUN_CMU_MFCMSCL_SYS_PWR_REG, 0, 0);
pwrcal_setbit(CLKSTOP_CMU_MFCMSCL_SYS_PWR_REG, 0, 0);
pwrcal_setbit(DISABLE_PLL_CMU_MFCMSCL_SYS_PWR_REG, 0, 0);
pwrcal_setf(RESET_LOGIC_MFCMSCL_SYS_PWR_REG, 0, 0x3, 0);
pwrcal_setf(RESET_CMU_MFCMSCL_SYS_PWR_REG, 0, 0x3, 0);
}
static void dispaud_post(int enable)
{
pwrcal_setbit(PAD_RETENTION_AUD_OPTION, 28, 1);
}
static void g3d_post(int enable)
{
}
static void isp_post(int enable)
{
}
static void mfcmscl_post(int enable)
{
}
static void dispaud_config(int enable)
{
pwrcal_setf(DISPAUD_OPTION, 0, 0xFFFFFFFF, 0x2);
}
static void g3d_config(int enable)
{
pwrcal_setf(G3D_OPTION, 0, 0xFFFFFFFF, 0x1);
}
static void isp_config(int enable)
{
pwrcal_setf(ISP_OPTION, 0, 0xFFFFFFFF, 0x2);
}
static void mfcmscl_config(int enable)
{
pwrcal_setf(MFCMSCL_OPTION, 0, 0xFFFFFFFF, 0x2);
}
BLKPWR(blkpwr_dispaud, DISPAUD_CONFIGURATION, 0, 0xF, DISPAUD_STATUS, 0, 0xF, dispaud_config, dispaud_prev, dispaud_post);
BLKPWR(blkpwr_g3d, G3D_CONFIGURATION, 0, 0xF, G3D_STATUS, 0, 0xF, g3d_config, g3d_prev, g3d_post);
BLKPWR(blkpwr_isp, ISP_CONFIGURATION, 0, 0xF, ISP_STATUS, 0, 0xF, isp_config, isp_prev, isp_post);
BLKPWR(blkpwr_mfcmscl, MFCMSCL_CONFIGURATION, 0, 0xF, MFCMSCL_STATUS, 0, 0xF, mfcmscl_config, mfcmscl_prev, mfcmscl_post);
struct cal_pd *pwrcal_blkpwr_list[4];
unsigned int pwrcal_blkpwr_size = 4;
static int blkpwr_init(void)
{
pwrcal_blkpwr_list[0] = &blkpwr_blkpwr_dispaud;
pwrcal_blkpwr_list[1] = &blkpwr_blkpwr_g3d;
pwrcal_blkpwr_list[2] = &blkpwr_blkpwr_isp;
pwrcal_blkpwr_list[3] = &blkpwr_blkpwr_mfcmscl;
return 0;
}
struct cal_pd_ops cal_pd_ops = {
.pd_control = blkpwr_control,
.pd_status = blkpwr_status,
.pd_init = blkpwr_init,
};

1756
drivers/soc/samsung/pwrcal/S5E7570/S5E7570-pmusfr.h Normal file
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File diff suppressed because it is too large Load diff

47
drivers/soc/samsung/pwrcal/S5E7570/S5E7570-rae.c Normal file
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#include "../pwrcal-rae.h"
#include "S5E7570-sfrbase.h"
#ifdef PWRCAL_TARGET_LINUX
struct v2p_sfr v2psfrmap[] = {
DEFINE_V2P(CMU_APM_BASE, 0x11CE0000),
DEFINE_V2P(CMU_MIF_BASE, 0x10460000),
DEFINE_V2P(CMU_PERI_BASE, 0x101F0000),
DEFINE_V2P(CMU_G3D_BASE, 0x11460000),
DEFINE_V2P(CMU_CPUCL0_BASE, 0x10900000),
DEFINE_V2P(CMU_MFCMSCL_BASE, 0x12CB0000),
DEFINE_V2P(CMU_FSYS_BASE, 0x13730000),
DEFINE_V2P(CMU_ISP_BASE, 0x144D0000),
DEFINE_V2P(CMU_DISPAUD_BASE, 0x148D0000),
DEFINE_V2P(PMU_CPUCL0_BASE, 0x10920000),
DEFINE_V2P(PMU_FSYS_BASE, 0x13740000),
DEFINE_V2P(PMU_G3D_BASE, 0x11470000),
DEFINE_V2P(PMU_ISP_BASE, 0x144E0000),
DEFINE_V2P(PMU_MFCMSCL_BASE, 0x12CC0000),
DEFINE_V2P(PMU_MIF_BASE, 0x10470000),
DEFINE_V2P(PMU_PERI_BASE, 0x101E0000),
DEFINE_V2P(PMU_IF_BASE, 0x11C70000),
DEFINE_V2P(PMU_ALIVE_BASE, 0x11C80000),
DEFINE_V2P(PMU_APM_BASE, 0x11CF0000),
DEFINE_V2P(PMU_DISPAUD_BASE, 0x148E0000),
DEFINE_V2P(DREX0_BASE, 0x10400000),
DEFINE_V2P(DREX0_PF_BASE, 0x10410000),
DEFINE_V2P(DREX0_SECURE_BASE, 0x10420000),
DEFINE_V2P(DREX0_PF_SECURE_BASE, 0x10430000),
DEFINE_V2P(DREXPHY0_BASE, 0x10440000),
DEFINE_V2P(SYSREG_CPUCL0_BASE, 0x10910000),
DEFINE_V2P(SYSREG_G3D_BASE, 0x11450000),
DEFINE_V2P(SYSREG_FSYS_BASE, 0x13720000),
DEFINE_V2P(SYSREG_MIF_BASE, 0x10450000),
DEFINE_V2P(SYSREG_PERI_BASE, 0x101D0000),
DEFINE_V2P(SYSREG_MFCMSCL_BASE, 0x12CA0000),
DEFINE_V2P(SYSREG_ISP_BASE, 0x144F0000),
DEFINE_V2P(SYSREG_DISPAUD_BASE, 0x148F0000),
};
int num_of_v2psfrmap = sizeof(v2psfrmap) / sizeof(v2psfrmap[0]);
void *spinlock_enable_offset = (void *)PMU_CPUCL0_BASE;
#endif

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drivers/soc/samsung/pwrcal/S5E7570/S5E7570-sfrbase.h Normal file
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#ifndef __EXYNOS7570_SFRBASE_H__
#define __EXYNOS7570_SFRBASE_H__
#include "../pwrcal-env.h"
#ifdef PWRCAL_TARGET_FW
#define CMU_APM_BASE 0x11CE0000
#define CMU_MIF_BASE 0x10460000
#define CMU_PERI_BASE 0x101F0000
#define CMU_G3D_BASE 0x11460000
#define CMU_CPUCL0_BASE 0x10900000
#define CMU_MFCMSCL_BASE 0x12CB0000
#define CMU_FSYS_BASE 0x13730000
#define CMU_ISP_BASE 0x144D0000
#define CMU_DISPAUD_BASE 0x148D0000
#define PMU_CPUCL0_BASE 0x10920000
#define PMU_FSYS_BASE 0x13740000
#define PMU_G3D_BASE 0x11470000
#define PMU_ISP_BASE 0x144E0000
#define PMU_MFCMSCL_BASE 0x12CC0000
#define PMU_MIF_BASE 0x10470000
#define PMU_PERI_BASE 0x101E0000
#define PMU_IF_BASE 0x11C70000
#define PMU_ALIVE_BASE 0x11C80000
#define PMU_APM_BASE 0x11CF0000
#define PMU_DISPAUD_BASE 0x148E0000
#define DREX0_BASE 0x10400000
#define DREX0_PF_BASE 0x10410000
#define DREX0_SECURE_BASE 0x10420000
#define DREX0_PF_SECURE_BASE 0x10430000
#define DREXPHY0_BASE 0x10440000
#define SYSREG_CPUCL0_BASE 0x10910000
#define SYSREG_G3D_BASE 0x11450000
#define SYSREG_FSYS_BASE 0x13720000
#define SYSREG_MIF_BASE 0x10450000
#define SYSREG_PERI_BASE 0x101D0000
#define SYSREG_MFCMSCL_BASE 0x12CA0000
#define SYSREG_ISP_BASE 0x144F0000
#define SYSREG_DISPAUD_BASE 0x148F0000
#endif
#ifdef PWRCAL_TARGET_LINUX
#define CMU_APM_BASE 0x00010000
#define CMU_MIF_BASE 0x00020000
#define CMU_PERI_BASE 0x00030000
#define CMU_G3D_BASE 0x00040000
#define CMU_CPUCL0_BASE 0x00050000
#define CMU_MFCMSCL_BASE 0x00060000
#define CMU_FSYS_BASE 0x00070000
#define CMU_ISP_BASE 0x00080000
#define CMU_DISPAUD_BASE 0x00090000
#define PMU_CPUCL0_BASE 0x000A0000
#define PMU_FSYS_BASE 0x000B0000
#define PMU_G3D_BASE 0x000C0000
#define PMU_ISP_BASE 0x000D0000
#define PMU_MFCMSCL_BASE 0x000E0000
#define PMU_MIF_BASE 0x000F0000
#define PMU_PERI_BASE 0x00100000
#define PMU_IF_BASE 0x00110000
#define PMU_ALIVE_BASE 0x00120000
#define PMU_APM_BASE 0x00130000
#define PMU_DISPAUD_BASE 0x00140000
#define DREX0_BASE 0x00150000
#define DREX0_PF_BASE 0x00160000
#define DREX0_SECURE_BASE 0x00170000
#define DREX0_PF_SECURE_BASE 0x00180000
#define DREXPHY0_BASE 0x00190000
#define SYSREG_CPUCL0_BASE 0x001A0000
#define SYSREG_G3D_BASE 0x001B0000
#define SYSREG_FSYS_BASE 0x001C0000
#define SYSREG_MIF_BASE 0x001D0000
#define SYSREG_PERI_BASE 0x001E0000
#define SYSREG_MFCMSCL_BASE 0x001F0000
#define SYSREG_ISP_BASE 0x00200000
#define SYSREG_DISPAUD_BASE 0x00210000
#endif
#endif

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/*
* Copyright (c) 2015 Samsung Electronics Co., Ltd. All rights reserved.
* http://www.samsung.com
*
* Chip Abstraction Layer for System power down support
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "../pwrcal-env.h"
#include "../pwrcal.h"
#include "../pwrcal-pmu.h"
#include "../pwrcal-rae.h"
#include "S5E7570-cmusfr.h"
#include "S5E7570-pmusfr.h"
#include "S5E7570-cmu.h"
enum sys_powerdown {
SYS_SICD,
SYS_AFTR,
SYS_STOP,
SYS_LPD,
SYS_LPA,
SYS_DSTOP,
SYS_SLEEP,
NUM_SYS_POWERDOWN,
};
struct exynos_pmu_conf {
unsigned int *reg;
unsigned int val[NUM_SYS_POWERDOWN];
};
/* init_pmu_l2_option */
#define MANUAL_ACINACTM_VALUE (0x1 << 3)
#define MANUAL_ACINACTM_CONTROL (0x1 << 2)
#define MANUAL_AINACTS_VALUE (0x1 << 1)
#define MANUAL_AINACTS_CONTROL (0x1 << 0)
#define USE_AUTOMATIC_L2FLUSHREQ (0x1 << 17)
#define USE_STANDBYWFIL2 (0x1 << 16)
#define USE_RETENTION (0x1 << 4)
/* CPU option */
#define USE_SMPEN (0x1 << 28)
#define USE_STANDBYWFE (0x1 << 24)
#define USE_STANDBYWFI (0x1 << 16)
#define USE_IRQCPU_FOR_PWR (0x3 << 4)
#define USE_MEMPWRDOWN_FEEDBACK (0x1 << 3)
#define USE_MEMPWRDOWN_COUNTER (0x1 << 2)
#define USE_SC_FEEDBACK (0x1 << 1)
#define USE_SC_COUNTER (0x1 << 0)
#define DUR_WAIT_RESET (0xF << 20)
#define DUR_SCALL (0xF << 4)
#define DUR_SCALL_VALUE (0x1 << 4)
/* init_pmu_up_scheduler */
#define ENABLE_CPUCL0_CPU (0x1 << 0)
/* init_set_duration */
#define DUR_STABLE_MASK_AT_RESET 0xFFFFF
#define DUR_STABLE_MASK 0x3FF
#define TCXO_DUR_STABLE 0x140 /* 10ms in 32Khz */
#define EXTREG_SHARED_DUR_STABLE 0x140 /* 10ms in 32Khz */
#define EXTREG_SHARED_DUR_STABLE_AT_RESET 0x3F7A0 /* 10ms in 26Mhz */
/* init_pshold_setting_value*/
#define ENABLE_HW_TRIP (0x1 << 31)
#define PS_HOLD_OUTPUT_HIGH (0x3 << 8)
#define PAD_INITIATE_WAKEUP (0x1 << 28)
struct system_power_backup_reg {
void *reg;
unsigned int backup;
void *reg_stat;
unsigned int backup_stat;
void *pwr_stat_reg; /* if pwr_check true, this reg should be set */
unsigned int valid;
};
#define SYS_PWR_BACK_REG(_reg, _reg_stat, _pwr_stat_reg) \
{ \
.reg = _reg, \
.backup = 0, \
.reg_stat = _reg_stat, \
.backup_stat = 0, \
.pwr_stat_reg = _pwr_stat_reg, \
.valid = 0, \
}
static unsigned int *pmu_cpuoption_sfrlist[] = {
CPUCL0_CPU0_OPTION,
CPUCL0_CPU1_OPTION,
CPUCL0_CPU2_OPTION,
CPUCL0_CPU3_OPTION,
};
static void init_pmu_cpu_option(void)
{
int cpu;
unsigned int tmp;
/* use both sc_counter and sc_feedback */
/* enable to wait for low SMP-bit at sys power down */
for (cpu = 0; cpu < sizeof(pmu_cpuoption_sfrlist) / sizeof(pmu_cpuoption_sfrlist[0]); cpu++) {
tmp = pwrcal_readl(pmu_cpuoption_sfrlist[cpu]);
tmp |= USE_SC_FEEDBACK;
tmp |= USE_SMPEN;
tmp &= ~USE_SC_COUNTER;
tmp |= USE_STANDBYWFI;
tmp |= USE_MEMPWRDOWN_FEEDBACK;
tmp &= ~USE_STANDBYWFE;
pwrcal_writel(pmu_cpuoption_sfrlist[cpu], tmp);
}
}
static void set_pmu_enable_reset_lpi_timeout(void)
{
pwrcal_setbit(RESET_LPI_TIMEOUT, 0, 1);
}
static void init_pmu_apm_option(void)
{
pwrcal_setbit(CENTRAL_SEQ_APM_OPTION, 1, 1); /*USE STANDBYWFI*/
pwrcal_setbit(CORTEXM0_APM_OPTION, 16, 1); /*USE StandbyWFI*/
}
static void init_pmu_l2_option(void)
{
unsigned int tmp;
/* disable automatic L2 flush */
/* disable L2 retention */
tmp = pwrcal_readl(CPUCL0_L2_OPTION);
tmp &= ~(USE_AUTOMATIC_L2FLUSHREQ | USE_RETENTION);
tmp |= USE_STANDBYWFIL2;
pwrcal_writel(CPUCL0_L2_OPTION, tmp);
}
static void init_pmu_cpuseq_option(void)
{
}
static void init_pmu_up_scheduler(void)
{
unsigned int tmp;
/* limit in-rush current for CPUCL0/1 local power up */
tmp = pwrcal_readl(UP_SCHEDULER);
tmp |= ENABLE_CPUCL0_CPU;
pwrcal_writel(UP_SCHEDULER, tmp);
}
/* init_pmu_feedback */
static unsigned int *pmu_feedback_sfrlist[] = {
CPUCL0_NONCPU_OPTION,
TOP_PWR_OPTION,
TOP_PWR_MIF_OPTION,
DISPAUD_OPTION,
MFCMSCL_OPTION,
ISP_OPTION,
};
static void init_set_duration(void)
{
unsigned int tmp;
tmp = pwrcal_readl(TCXO_SHARED_DURATION3);
tmp &= ~DUR_STABLE_MASK;
tmp |= TCXO_DUR_STABLE;
pwrcal_writel(TCXO_SHARED_DURATION3, tmp);
tmp = pwrcal_readl(EXT_REGULATOR_SHARED_DURATION1);
tmp &= ~DUR_STABLE_MASK_AT_RESET;
tmp |= EXTREG_SHARED_DUR_STABLE_AT_RESET;
pwrcal_writel(EXT_REGULATOR_SHARED_DURATION1, tmp);
tmp = pwrcal_readl(EXT_REGULATOR_SHARED_DURATION3);
tmp &= ~DUR_STABLE_MASK;
tmp |= EXTREG_SHARED_DUR_STABLE;
pwrcal_writel(EXT_REGULATOR_SHARED_DURATION3, tmp);
}
static void init_pmu_feedback(void)
{
int i;
unsigned int tmp;
for (i = 0; i < sizeof(pmu_feedback_sfrlist) / sizeof(pmu_feedback_sfrlist[0]); i++) {
tmp = pwrcal_readl(pmu_feedback_sfrlist[i]);
tmp &= ~USE_SC_COUNTER;
tmp |= USE_SC_FEEDBACK;
pwrcal_writel(pmu_feedback_sfrlist[i], tmp);
}
}
static void init_ps_hold_setting(void)
{
unsigned int tmp;
tmp = pwrcal_readl(PS_HOLD_CONTROL);
tmp |= (ENABLE_HW_TRIP | PS_HOLD_OUTPUT_HIGH);
pwrcal_writel(PS_HOLD_CONTROL, tmp);
}
static void enable_armidleclockdown(void);
static void syspwr_init(void)
{
init_pmu_feedback();
init_pmu_l2_option();
init_pmu_cpu_option();
init_pmu_cpuseq_option();
init_pmu_up_scheduler();
init_ps_hold_setting();
init_set_duration();
init_pmu_apm_option();
set_pmu_enable_reset_lpi_timeout();
enable_armidleclockdown();
}
static struct exynos_pmu_conf exynos_syspwr_pmu_config[] = {
/* { .addr = address, .val = { SICD, AFTR, STOP, LPD, LPA, DSTOP, SLEEP } } */
{ CPUCL0_CPU0_SYS_PWR_REG, { 0xF, 0x0, 0xF, 0x0, 0x0, 0x0, 0x8} },
{ DIS_IRQ_CPUCL0_CPU0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ DIS_IRQ_CPUCL0_CPU0_CENTRAL_SYS_PWR_REG, { 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ DIS_IRQ_CPUCL0_CPU0_CPUSEQUENCER_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ CPUCL0_CPU1_SYS_PWR_REG, { 0xF, 0x0, 0xF, 0x0, 0x0, 0x0, 0x8} },
{ DIS_IRQ_CPUCL0_CPU1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ DIS_IRQ_CPUCL0_CPU1_CENTRAL_SYS_PWR_REG, { 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ DIS_IRQ_CPUCL0_CPU1_CPUSEQUENCER_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ CPUCL0_CPU2_SYS_PWR_REG, { 0xF, 0x0, 0xF, 0x0, 0x0, 0x0, 0x8} },
{ DIS_IRQ_CPUCL0_CPU2_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ DIS_IRQ_CPUCL0_CPU2_CENTRAL_SYS_PWR_REG, { 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ DIS_IRQ_CPUCL0_CPU2_CPUSEQUENCER_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ CPUCL0_CPU3_SYS_PWR_REG, { 0xF, 0x0, 0xF, 0x0, 0x0, 0x0, 0x8} },
{ DIS_IRQ_CPUCL0_CPU3_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ DIS_IRQ_CPUCL0_CPU3_CENTRAL_SYS_PWR_REG, { 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ DIS_IRQ_CPUCL0_CPU3_CPUSEQUENCER_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ CPUCL1_CPU0_SYS_PWR_REG, { 0xF, 0xF, 0xF, 0xF, 0xF, 0xF, 0xF} },
{ DIS_IRQ_CPUCL1_CPU0_LOCAL_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
{ DIS_IRQ_CPUCL1_CPU0_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
{ DIS_IRQ_CPUCL1_CPU0_CPUSEQUENCER_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
{ CPUCL1_CPU1_SYS_PWR_REG, { 0xF, 0xF, 0xF, 0xF, 0xF, 0xF, 0xF} },
{ DIS_IRQ_CPUCL1_CPU1_LOCAL_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
{ DIS_IRQ_CPUCL1_CPU1_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
{ DIS_IRQ_CPUCL1_CPU1_CPUSEQUENCER_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
{ CPUCL1_CPU2_SYS_PWR_REG, { 0xF, 0xF, 0xF, 0xF, 0xF, 0xF, 0xF} },
{ DIS_IRQ_CPUCL1_CPU2_LOCAL_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
{ DIS_IRQ_CPUCL1_CPU2_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
{ DIS_IRQ_CPUCL1_CPU2_CPUSEQUENCER_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
{ CPUCL1_CPU3_SYS_PWR_REG, { 0xF, 0xF, 0xF, 0xF, 0xF, 0xF, 0xF} },
{ DIS_IRQ_CPUCL1_CPU3_LOCAL_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
{ DIS_IRQ_CPUCL1_CPU3_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
{ DIS_IRQ_CPUCL1_CPU3_CPUSEQUENCER_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
{ CPUCL0_NONCPU_SYS_PWR_REG, { 0xF, 0x0, 0xF, 0x0, 0x0, 0x0, 0x8} },
{ CPUCL1_NONCPU_SYS_PWR_REG, { 0xF, 0xF, 0xF, 0xF, 0xF, 0xF, 0xF} },
{ CPUCL0_L2_SYS_PWR_REG, { 0x7, 0x0, 0x7, 0x0, 0x0, 0x0, 0x7} },
{ CPUCL1_L2_SYS_PWR_REG, { 0x7, 0x7, 0x7, 0x7, 0x7, 0x7, 0x7} },
{ CLKSTOP_CMU_TOP_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
{ CLKRUN_CMU_TOP_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
{ RETENTION_CMU_TOP_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x0, 0x0, 0x0, 0x3} },
{ RESET_CMU_TOP_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x0} },
{ RESET_CPUCLKSTOP_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x0} },
{ CLKSTOP_CMU_MIF_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x0, 0x0, 0x0} },
{ CLKRUN_CMU_MIF_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x0, 0x0, 0x0} },
{ RETENTION_CMU_MIF_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x3} },
{ RESET_CMU_MIF_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x0} },
{ DDRPHY_CLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x0, 0x0, 0x1} },
{ DDRPHY_ISO_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x0, 0x0, 0x1} },
{ DDRPHY_DLL_CLK_SYS_PWR_REG, { 0x0, 0x1, 0x1, 0x1, 0x0, 0x0, 0x0} },
{ DISABLE_PLL_CMU_TOP_SYS_PWR_REG, { 0x0, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ DISABLE_PLL_AUD_PLL_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
{ DISABLE_PLL_CMU_MIF_SYS_PWR_REG, { 0x0, 0x1, 0x0, 0x1, 0x0, 0x0, 0x0} },
{ DISABLE_PLL_APM_MIF_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
{ RESET_AHEAD_CP_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
{ RESET_AHEAD_GNSS_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
{ TOP_BUS_SYS_PWR_REG, { 0x7, 0x7, 0x7, 0x0, 0x0, 0x0, 0x0} },
{ TOP_RETENTION_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x0, 0x0, 0x0, 0x3} },
{ TOP_PWR_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x0, 0x0, 0x0, 0x3} },
{ TOP_BUS_MIF_SYS_PWR_REG, { 0x0, 0x7, 0x7, 0x7, 0x0, 0x0, 0x0} },
{ TOP_RETENTION_MIF_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x3} },
{ TOP_PWR_MIF_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x3} },
{ LOGIC_RESET_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x0, 0x0, 0x0, 0x0} },
{ OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x1, 0x0, 0x0, 0x0, 0x0, 0x1} },
{ SLEEP_RESET_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x0} },
{ LOGIC_RESET_MIF_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x0} },
{ OSCCLK_GATE_MIF_SYS_PWR_REG, { 0x1, 0x1, 0x0, 0x1, 0x0, 0x0, 0x1} },
{ SLEEP_RESET_MIF_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x0} },
{ RESET_ASB_MIF_GNSS_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
{ MEMORY_TOP_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x0, 0x0, 0x0, 0x3} },
{ TCXO_GATE_GNSS_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
{ RESET_ASB_GNSS_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
{ CLEANY_BUS_CP_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
{ LOGIC_RESET_CP_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
{ TCXO_GATE_CP_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
{ RESET_ASB_CP_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
{ RESET_ASB_MIF_CP_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
{ MEMORY_MIF_ALIVEIRAM_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
{ MEMORY_MIF_TOP_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x0, 0x0, 0x3} },
{ CLEANY_BUS_GNSS_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
{ LOGIC_RESET_GNSS_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
{ PAD_RETENTION_LPDDR3_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x0, 0x0, 0x0} },
{ PAD_RETENTION_AUD_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x0, 0x0, 0x0} },
{ PAD_RETENTION_PEDOMETER_TOP_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
{ PAD_RETENTION_MMC2_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
{ PAD_RETENTION_TOP_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
{ PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
{ PAD_RETENTION_MMC0_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
{ PAD_RETENTION_MMC1_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
{ PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
{ PAD_RETENTION_MIF_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x0, 0x0, 0x0} },
{ PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x1} },
{ PAD_RETENTION_BOOTLDO_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
{ PAD_ISOLATION_MIF_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x0, 0x0, 0x1} },
{ EXT_REGULATOR_MIF_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x0} },
{ GPIO_MODE_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
{ GPIO_MODE_MIF_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x0, 0x0, 0x0} },
{ GPIO_MODE_DISPAUD_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x0, 0x0, 0x0} },
{ G3D_SYS_PWR_REG, { 0xF, 0xF, 0xF, 0x0, 0x0, 0x0, 0x0} },
{ DISPAUD_SYS_PWR_REG, { 0xF, 0xF, 0x0, 0xF, 0xF, 0x0, 0x0} },
{ ISP_SYS_PWR_REG, { 0xF, 0xF, 0xF, 0x0, 0x0, 0x0, 0x0} },
{ MFCMSCL_SYS_PWR_REG, { 0xF, 0xF, 0xF, 0x0, 0x0, 0x0, 0x0} },
{ CLKRUN_CMU_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ CLKRUN_CMU_DISPAUD_SYS_PWR_REG, { 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0} },
{ CLKRUN_CMU_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ CLKRUN_CMU_MFCMSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ CLKSTOP_CMU_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ CLKSTOP_CMU_DISPAUD_SYS_PWR_REG, { 0x0, 0x0, 0x1, 0x0, 0x0, 0x0, 0x0} },
{ CLKSTOP_CMU_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ CLKSTOP_CMU_MFCMSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ DISABLE_PLL_CMU_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ DISABLE_PLL_CMU_DISPAUD_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ DISABLE_PLL_CMU_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ DISABLE_PLL_CMU_MFCMSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ RESET_LOGIC_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ RESET_LOGIC_DISPAUD_SYS_PWR_REG, { 0x0, 0x0, 0x3, 0x0, 0x0, 0x0, 0x0} },
{ RESET_LOGIC_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ RESET_LOGIC_MFCMSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ MEMORY_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ MEMORY_DISPAUD_SYS_PWR_REG, { 0x0, 0x0, 0x3, 0x0, 0x0, 0x0, 0x0} },
{ MEMORY_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ MEMORY_MFCMSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ RESET_CMU_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ RESET_CMU_DISPAUD_SYS_PWR_REG, { 0x0, 0x0, 0x3, 0x0, 0x0, 0x0, 0x0} },
{ RESET_CMU_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ RESET_CMU_MFCMSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ RESET_AHEAD_WIFI_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
{ CLEANY_BUS_WIFI_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
{ LOGIC_RESET_WIFI_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
{ TCXO_GATE_WIFI_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
{ RESET_ASB_WIFI_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
{ RESET_ASB_MIF_WIFI_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
{ CORTEXM0_APM_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
{ CLKRUN_CMU_APM_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
{ TOP_BUS_APM_SYS_PWR_REG, { 0x7, 0x7, 0x7, 0x0, 0x0, 0x0, 0x0} },
{ CLKSTOP_CMU_APM_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
{ CLKSTOP_OPEN_CMU_APM_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
{ DISABLE_PLL_CMU_APM_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
{ TOP_RETENTION_APM_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x0, 0x0, 0x0, 0x0} },
{ OSCCLK_GATE_APM_SYS_PWR_REG, { 0x1, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0} },
{ MEMORY_APM_TOP_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x0, 0x0, 0x0, 0x0} },
{ LOGIC_RESET_APM_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x0, 0x0, 0x0, 0x0} },
{ SLEEP_RESET_APM_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
{ RETENTION_CMU_APM_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x0, 0x0, 0x0, 0x0} },
{ RESET_CMU_APM_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3} },
{ TOP_PWR_APM_SYS_PWR_REG, { 0x3, 0x3, 0x3, 0x0, 0x0, 0x0, 0x0} },
{ TCXO_SYS_PWR_REG, { 0x1, 0x1, 0x0, 0x1, 0x1, 0x0, 0x0} },
{ PAD_RETENTION_PEDOMETER_APM_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
{ PAD_RETENTION_PEDOMETER_TOP_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1} },
{ PAD_RETENTION_PEDOMETER_APM_SYS_PWR_REG, { 0x1, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0} },
{ 0, },
};
static struct exynos_pmu_conf exynos_syspwr_pmu_option[] = {
/* { .addr = address, .val = { SICD, AFTR, STOP, LPD, LPA, DSTOP, SLEEP } } */
{CENTRAL_SEQ_OPTION, {0x000F0000, 0x000F0000, 0x000F0000, 0x000F0000, 0x000F0000, 0x000F0000, 0x000F0000 } },
{CENTRAL_SEQ_OPTION1, {0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
{CENTRAL_SEQ_MIF_OPTION, {0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18 } },
{TOP_BUS_MIF_OPTION, {0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } },
{0, },
};
static void set_pmu_sys_pwr_reg(enum sys_powerdown mode)
{
int i;
for (i = 0; exynos_syspwr_pmu_config[i].reg != 0; i++)
pwrcal_writel(exynos_syspwr_pmu_config[i].reg, exynos_syspwr_pmu_config[i].val[mode]);
for (i = 0; exynos_syspwr_pmu_option[i].reg != 0; i++)
pwrcal_writel(exynos_syspwr_pmu_option[i].reg, exynos_syspwr_pmu_option[i].val[mode]);
}
#define PWRCAL_CENTRALSEQ_PWR_CFG 0x10000
static void set_pmu_central_seq(int mode, bool enable)
{
unsigned int tmp;
/* central sequencer */
tmp = pwrcal_readl(CENTRAL_SEQ_CONFIGURATION);
if (enable)
tmp &= ~PWRCAL_CENTRALSEQ_PWR_CFG;
else
tmp |= PWRCAL_CENTRALSEQ_PWR_CFG;
pwrcal_writel(CENTRAL_SEQ_CONFIGURATION, tmp);
/* central sequencer MIF */
if (mode == SYS_SICD) {
tmp = pwrcal_readl(CENTRAL_SEQ_MIF_CONFIGURATION);
if (enable)
tmp &= ~PWRCAL_CENTRALSEQ_PWR_CFG;
else
tmp |= PWRCAL_CENTRALSEQ_PWR_CFG;
pwrcal_writel(CENTRAL_SEQ_MIF_CONFIGURATION, tmp);
}
}
static struct system_power_backup_reg backup_reg[] = {
};
static int syspwr_clkpwr_backup(unsigned int power_mode)
{
int i;
for (i = 0; i < sizeof(backup_reg) / sizeof(backup_reg[0]); i++) {
backup_reg[i].valid = 0;
if (backup_reg[i].pwr_stat_reg && pwrcal_getf(backup_reg[i].pwr_stat_reg, 0, 0xF) != 0xF)
continue;
if (backup_reg[i].reg) {
backup_reg[i].backup = pwrcal_readl(backup_reg[i].reg);
if (backup_reg[i].reg_stat)
backup_reg[i].backup_stat = pwrcal_readl(backup_reg[i].reg_stat);
backup_reg[i].valid = 1;
}
}
return 0;
}
static int syspwr_clkpwr_restore(unsigned int power_mode)
{
int i;
int timeout;
for (i = 0; i < sizeof(backup_reg) / sizeof(backup_reg[0]); i++) {
if (backup_reg[i].valid == 1) {
if (backup_reg[i].pwr_stat_reg && pwrcal_getf(backup_reg[i].pwr_stat_reg, 0, 0xF) != 0xF)
continue;
if (backup_reg[i].reg) {
pwrcal_writel(backup_reg[i].reg, backup_reg[i].backup);
if (backup_reg[i].reg_stat) {
for (timeout = 0; timeout < CLK_WAIT_CNT; timeout++) {
timeout = pwrcal_readl(backup_reg[i].reg_stat);
if (timeout == backup_reg[i].backup_stat)
break;
}
if (timeout == CLK_WAIT_CNT)
pr_warn("[%s] timeout wait for (0x%08X)\n",
__func__, backup_reg[i].backup_stat);
}
}
}
}
return 0;
}
static void enable_armidleclockdown(void)
{
/*Use L2QACTIVE*/
pwrcal_setbit(PWR_CTRL3, 0, 1);
pwrcal_setbit(PWR_CTRL3, 1, 1);
}
inline void disable_armidleclockdown(void)
{
pwrcal_setbit(PWR_CTRL3, 0, 0);
}
static void syspwr_clock_config(int mode)
{
pwrcal_setbit(CLK_CON_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER, 12, 0);
pwrcal_setbit(CLK_CON_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER, 27, 1);
if (pwrcal_getf(ISP_STATUS, 0, 0xf) == 0xf) {
pwrcal_setbit(CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER, 12, 0);
pwrcal_setbit(CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER, 27, 1);
}
if ((pwrcal_getf(DISPAUD_STATUS, 0, 0xf) == 0xf) && (mode != SYS_LPD)) {
pwrcal_setbit(CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER, 12, 0); /* MIPIDPHY */
pwrcal_setbit(CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER, 12, 0); /* MIPIDPHY */
pwrcal_setbit(CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER, 27, 1); /* MIPIDPHY */
pwrcal_setbit(CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER, 27, 1); /* MIPIDPHY */
}
if (mode == SYS_LPD) {
/* PLL sharing is need to discuss, CP needs all PLL */
pwrcal_setbit(MIF_ROOTCLKEN, 0, 1);
pwrcal_setbit(CLK_ENABLE_CLKCMU_PERI_SPI_REARFROM, 0, 0);
pwrcal_setbit(CLK_ENABLE_CLKCMU_PERI_SPI_ESE, 0, 0);
pwrcal_setbit(CLK_ENABLE_CLKCMU_PERI_USI_0, 0, 0);
pwrcal_setbit(CLK_ENABLE_CLKCMU_PERI_USI_1, 0, 0);
}
/*LPI disable conditionally, when CP/GNSS/WIFI is disabled*/
}
static int syspwr_clkpwr_optimize(unsigned int power_mode)
{
disable_armidleclockdown();
return 0;
}
static void syspwr_set_additional_config(const enum sys_powerdown eMode)
{
/* USE_LEVEL_TRIGGER */
pwrcal_setf(WAKEUP_MASK, 30, 0x1, 0x1);
pwrcal_setf(WAKEUP_MASK_MIF, 30, 0x1, 0x1);
if (eMode == SYS_STOP) {
pwrcal_setf(DISPAUD_OPTION, 31, 0x1, 0x1);
pwrcal_setf(DISPAUD_OPTION, 21, 0x1, 0x1);
} else {
pwrcal_setf(DISPAUD_OPTION, 31, 0x1, 0x0);
pwrcal_setf(DISPAUD_OPTION, 21, 0x1, 0x0);
}
}
static void syspwr_prepare(int mode)
{
syspwr_clkpwr_backup(mode);
syspwr_clock_config(mode);
syspwr_clkpwr_optimize(mode);
set_pmu_sys_pwr_reg(mode);
syspwr_set_additional_config(mode);
set_pmu_central_seq(mode, true);
}
static void set_pmu_pad_retention_release(void)
{
pwrcal_writel(PAD_RETENTION_AUD_OPTION, PAD_INITIATE_WAKEUP);
pwrcal_writel(PAD_RETENTION_TOP_OPTION, PAD_INITIATE_WAKEUP);
pwrcal_writel(PAD_RETENTION_UART_OPTION, PAD_INITIATE_WAKEUP);
pwrcal_writel(PAD_RETENTION_MMC0_OPTION, PAD_INITIATE_WAKEUP);
pwrcal_writel(PAD_RETENTION_MMC2_OPTION, PAD_INITIATE_WAKEUP);
pwrcal_writel(PAD_RETENTION_SPI_OPTION, PAD_INITIATE_WAKEUP);
pwrcal_writel(PAD_RETENTION_BOOTLDO_OPTION, PAD_INITIATE_WAKEUP);
}
static void syspwr_post(int mode)
{
if (mode != SYS_SICD)
set_pmu_pad_retention_release();
switch (mode) {
case SYS_SICD:
case SYS_AFTR:
case SYS_DSTOP:
case SYS_STOP:
case SYS_LPD:
case SYS_LPA:
case SYS_SLEEP:
set_pmu_central_seq(mode, false);
break;
default:
return;
break;
}
enable_armidleclockdown();
syspwr_clkpwr_restore(mode);
}
static void syspwr_earlywakeup(int mode)
{
set_pmu_central_seq(mode, false);
enable_armidleclockdown();
syspwr_clkpwr_restore(mode);
}
struct cal_pm_ops cal_pm_ops = {
.pm_enter = syspwr_prepare,
.pm_exit = syspwr_post,
.pm_earlywakeup = syspwr_earlywakeup,
.pm_init = syspwr_init,
};

13
drivers/soc/samsung/pwrcal/S5E7570/S5E7570-sysreg.h Normal file
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@ -0,0 +1,13 @@
#ifndef __EXYNOS7570_H__
#define __EXYNOS7570_H__
#include "S5E7570-sfrbase.h"
#define CPUCL0_EMA_CON ((void *)(SYSREG_CPUCL0_BASE + 0x0330))
#define CPUCL0_EMA ((void *)(SYSREG_CPUCL0_BASE + 0x0340))
#define G3D_EMA_RA1_HS_CON ((void *)(SYSREG_G3D_BASE + 0x0304))
#define G3D_EMA_RF1_HS_CON ((void *)(SYSREG_G3D_BASE + 0x0314))
#define G3D_EMA_RF2_HS_CON ((void *)(SYSREG_G3D_BASE + 0x031C))
#define G3D_EMA_UHD_CON ((void *)(SYSREG_G3D_BASE + 0x0320))
#endif

131
drivers/soc/samsung/pwrcal/S5E7570/S5E7570-vclk-internal.h Normal file
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#ifndef __EXYNOS7870_VCLKS_H__
#define __EXYNOS7870_VCLKS_H__
#include "../pwrcal-vclk.h"
#include "../pwrcal-pmu.h"
#include "S5E7570-vclk.h"
M1D1G1_EXTERN(sclk_decon_vclk)
M1D1G1_EXTERN(sclk_mmc0)
M1D1G1_EXTERN(sclk_mmc2)
M1D1G1_EXTERN(sclk_usb20drd_refclk)
M1D1G1_EXTERN(sclk_uart_debug)
M1D1G1_EXTERN(sclk_uart_sensor)
M1D1G1_EXTERN(sclk_spi_rearfrom)
M1D1G1_EXTERN(sclk_spi_ese)
M1D1G1_EXTERN(sclk_usi0)
M1D1G1_EXTERN(sclk_usi1)
M1D1G1_EXTERN(sclk_apm)
M1D1G1_EXTERN(sclk_isp_sensor0)
PXMXDX_EXTERN(pxmxdx_top)
PXMXDX_EXTERN(pxmxdx_dispaud)
PXMXDX_EXTERN(pxmxdx_mfcmscl)
PXMXDX_EXTERN(pxmxdx_isp_vra)
PXMXDX_EXTERN(pxmxdx_isp_cam)
PXMXDX_EXTERN(pxmxdx_oscclk_aud)
P1_EXTERN(p1_aud_pll)
P1_EXTERN(p1_wpll_usb_pll)
M1_EXTERN(m1_dummy)
D1_EXTERN(sclk_decon_vclk_local)
D1_EXTERN(d1_dispaud_mi2s)
D1_EXTERN(d1_dispaud_mixer)
D1_EXTERN(d1_dispaud_oscclk_fm_52m)
GRPGATE_EXTERN(gate_mif_pdma)
GRPGATE_EXTERN(gate_mif_adcif)
GRPGATE_EXTERN(gate_mif_speedy)
GRPGATE_EXTERN(gate_apm_apm)
GRPGATE_EXTERN(gate_cpucl0_ppmu)
GRPGATE_EXTERN(gate_cpucl0_bts)
GRPGATE_EXTERN(gate_dispaud_common_disp)
GRPGATE_EXTERN(gate_dispaud_common_dsim0)
GRPGATE_EXTERN(gate_dispaud_common_aud)
GRPGATE_EXTERN(gate_dispaud_sysmmu)
GRPGATE_EXTERN(gate_dispaud_ppmu)
GRPGATE_EXTERN(gate_dispaud_bts)
GRPGATE_EXTERN(gate_dispaud_decon)
GRPGATE_EXTERN(gate_dispaud_dsim0)
GRPGATE_EXTERN(gate_dispaud_mixer)
GRPGATE_EXTERN(gate_dispaud_mi2s_aud)
GRPGATE_EXTERN(gate_dispaud_mi2s_amp)
GRPGATE_EXTERN(gate_peri_peris0)
GRPGATE_EXTERN(gate_peri_peric1)
GRPGATE_EXTERN(gate_peri_peric0)
GRPGATE_EXTERN(gate_peri_pwm_motor)
GRPGATE_EXTERN(gate_peri_sclk_pwm_motor)
GRPGATE_EXTERN(gate_peri_mct)
GRPGATE_EXTERN(gate_peri_i2c_sensor2)
GRPGATE_EXTERN(gate_peri_i2c_sensor1)
GRPGATE_EXTERN(gate_peri_i2c_tsp)
GRPGATE_EXTERN(gate_peri_i2c_fuelgauge)
GRPGATE_EXTERN(gate_peri_i2c_nfc)
GRPGATE_EXTERN(gate_peri_i2c_muic)
GRPGATE_EXTERN(gate_peri_hsi2c_frontcam)
GRPGATE_EXTERN(gate_peri_hsi2c_maincam)
GRPGATE_EXTERN(gate_peri_hsi2c_frontsensor)
GRPGATE_EXTERN(gate_peri_hsi2c_rearaf)
GRPGATE_EXTERN(gate_peri_hsi2c_rearsensor)
GRPGATE_EXTERN(gate_peri_gpio_touch)
GRPGATE_EXTERN(gate_peri_gpio_top)
GRPGATE_EXTERN(gate_peri_gpio_nfc)
GRPGATE_EXTERN(gate_peri_gpio_ese)
GRPGATE_EXTERN(gate_peri_wdt_cpucl0)
GRPGATE_EXTERN(gate_peri_uart_debug)
GRPGATE_EXTERN(gate_peri_uart_sensor)
GRPGATE_EXTERN(gate_peri_tmu_cpucl0)
GRPGATE_EXTERN(gate_peri_spi_ese)
GRPGATE_EXTERN(gate_peri_spi_rearfrom)
GRPGATE_EXTERN(gate_peri_gpio_alive)
GRPGATE_EXTERN(gate_peri_chipid)
GRPGATE_EXTERN(gate_peri_otp_con_top)
GRPGATE_EXTERN(gate_peri_rtc_alive)
GRPGATE_EXTERN(gate_peri_rtc_top)
GRPGATE_EXTERN(gate_peri_usi0)
GRPGATE_EXTERN(gate_peri_usi1)
GRPGATE_EXTERN(gate_fsys_common)
GRPGATE_EXTERN(gate_fsys_common_busp2)
GRPGATE_EXTERN(gate_fsys_common_busp3)
GRPGATE_EXTERN(gate_fsys_sysmmu)
GRPGATE_EXTERN(gate_fsys_ppmu)
GRPGATE_EXTERN(gate_fsys_bts)
GRPGATE_EXTERN(gate_fsys_usb20drd)
GRPGATE_EXTERN(gate_fsys_mmc0)
GRPGATE_EXTERN(gate_fsys_sclk_mmc0)
GRPGATE_EXTERN(gate_fsys_mmc2)
GRPGATE_EXTERN(gate_fsys_sclk_mmc2)
GRPGATE_EXTERN(gate_fsys_sss)
GRPGATE_EXTERN(gate_fsys_rtic)
GRPGATE_EXTERN(gate_g3d_common)
GRPGATE_EXTERN(gate_g3d_sysmmu)
GRPGATE_EXTERN(gate_g3d_ppmu)
GRPGATE_EXTERN(gate_g3d_bts)
GRPGATE_EXTERN(gate_g3d_g3d)
GRPGATE_EXTERN(gate_isp_sysmmu)
GRPGATE_EXTERN(gate_isp_ppmu)
GRPGATE_EXTERN(gate_isp_bts)
GRPGATE_EXTERN(gate_isp_cam)
GRPGATE_EXTERN(gate_isp_vra)
GRPGATE_EXTERN(gate_mfcmscl_sysmmu)
GRPGATE_EXTERN(gate_mfcmscl_ppmu)
GRPGATE_EXTERN(gate_mfcmscl_bts)
GRPGATE_EXTERN(gate_mfcmscl_mscl)
GRPGATE_EXTERN(gate_mfcmscl_jpeg)
GRPGATE_EXTERN(gate_mfcmscl_mfc)
UMUX_EXTERN(umux_dispaud_clkphy_dispaud_mipiphy_txbyteclkhs_user)
UMUX_EXTERN(umux_dispaud_clkphy_dispaud_mipiphy_rxclkesc0_user)
UMUX_EXTERN(umux_fsys_clkphy_fsys_usb20drd_phyclock_user)
UMUX_EXTERN(umux_isp_clkphy_isp_s_rxbyteclkhs0_s4_user)
DFS_EXTERN(dvfs_cpucl0)
DFS_EXTERN(dvfs_g3d)
DFS_EXTERN(dvfs_mif)
DFS_EXTERN(dvfs_int)
DFS_EXTERN(dvfs_disp)
DFS_EXTERN(dvfs_cam)
#endif

767
drivers/soc/samsung/pwrcal/S5E7570/S5E7570-vclk.c Normal file
View file

@ -0,0 +1,767 @@
#include "../pwrcal-pmu.h"
#include "../pwrcal-clk.h"
#include "../pwrcal-rae.h"
#include "S5E7570-cmu.h"
#include "S5E7570-cmusfr.h"
#include "S5E7570-vclk.h"
#include "S5E7570-vclk-internal.h"
struct pwrcal_vclk_grpgate *vclk_grpgate_list[num_of_grpgate];
struct pwrcal_vclk_m1d1g1 *vclk_m1d1g1_list[num_of_m1d1g1];
struct pwrcal_vclk_p1 *vclk_p1_list[num_of_p1];
struct pwrcal_vclk_m1 *vclk_m1_list[num_of_m1];
struct pwrcal_vclk_d1 *vclk_d1_list[num_of_d1];
struct pwrcal_vclk_pxmxdx *vclk_pxmxdx_list[num_of_pxmxdx];
struct pwrcal_vclk_umux *vclk_umux_list[num_of_umux];
struct pwrcal_vclk_dfs *vclk_dfs_list[num_of_dfs];
unsigned int vclk_grpgate_list_size = num_of_grpgate;
unsigned int vclk_m1d1g1_list_size = num_of_m1d1g1;
unsigned int vclk_p1_list_size = num_of_p1;
unsigned int vclk_m1_list_size = num_of_m1;
unsigned int vclk_d1_list_size = num_of_d1;
unsigned int vclk_pxmxdx_list_size = num_of_pxmxdx;
unsigned int vclk_umux_list_size = num_of_umux;
unsigned int vclk_dfs_list_size = num_of_dfs;
#define ADD_LIST(to, x) to[x & 0xFFF] = &(vclk_##x)
static struct pwrcal_clk_set pxmxdx_top_grp[] = {
{CLK_NONE, 0, 0},
};
static struct pwrcal_clk_set pxmxdx_dispaud_grp[] = {
{CLK(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER), 1, 0},
{CLK(DISPAUD_DIV_CLK_DISPAUD_APB), 1, -1},
{CLK_NONE, 0, 0},
};
static struct pwrcal_clk_set pxmxdx_mfcmscl_grp[] = {
{CLK(MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER), 1, 0},
{CLK(MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER), 1, 0},
{CLK(MFCMSCL_DIV_CLK_MFCMSCL_APB), 2, -1},
{CLK_NONE, 0, 0},
};
static struct pwrcal_clk_set pxmxdx_isp_vra_grp[] = {
{CLK(ISP_MUX_CLKCMU_ISP_VRA_USER), 1, 0},
{CLK_NONE, 0, 0},
};
static struct pwrcal_clk_set pxmxdx_isp_cam_grp[] = {
{CLK(ISP_MUX_CLKCMU_ISP_CAM_USER), 1, 0},
{CLK(ISP_DIV_CLK_ISP_CAM_HALF), 1, -1},
{CLK_NONE, 0, 0},
};
static struct pwrcal_clk_set pxmxdx_oscclk_aud_grp[] = {
{CLK(PMU_DEBUG_CLKOUT_SEL08), 1, -1},
{CLK(PMU_DEBUG_CLKOUT_SEL09), 1, -1},
{CLK(PMU_DEBUG_CLKOUT_SEL10), 1, -1},
{CLK(PMU_DEBUG_CLKOUT_SEL11), 1, -1},
{CLK(PMU_DEBUG_CLKOUT_SEL12), 1, -1},
{CLK(PMU_DEBUG_CLKOUT_DISABLE), 0, 1},
{CLK_NONE, 0, 0},
};
PXMXDX(pxmxdx_top, 0, pxmxdx_top_grp);
PXMXDX(pxmxdx_dispaud, dvfs_disp, pxmxdx_dispaud_grp);
PXMXDX(pxmxdx_mfcmscl, 0, pxmxdx_mfcmscl_grp);
PXMXDX(pxmxdx_isp_vra, 0, pxmxdx_isp_vra_grp);
PXMXDX(pxmxdx_isp_cam, 0, pxmxdx_isp_cam_grp);
PXMXDX(pxmxdx_oscclk_aud, 0, pxmxdx_oscclk_aud_grp);
P1(p1_aud_pll, 0, AUD_PLL);
P1(p1_wpll_usb_pll, 0, WPLL_USB_PLL);
/* USB PHY Ref CLK */
M1(m1_dummy, 0, 0);
D1(sclk_decon_vclk_local, sclk_decon_vclk, DISPAUD_DIV_CLK_DISPAUD_DECON_INT_VCLK);
D1(d1_dispaud_mi2s, 0, DISPAUD_DIV_CLK_DISPAUD_MI2S);
D1(d1_dispaud_mixer, 0, DISPAUD_DIV_CLK_DISPAUD_MIXER);
D1(d1_dispaud_oscclk_fm_52m, 0, DISPAUD_DIV_CLK_DISPAUD_OSCCLK_FM_52M_DIV);
M1D1G1(sclk_decon_vclk, 0, MIF_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK, MIF_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK, MIF_GATE_CLKCMU_DISPAUD_DECON_INT_VCLK, DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER);
M1D1G1(sclk_mmc0, 0, MIF_MUX_CLKCMU_FSYS_MMC0, MIF_DIV_CLKCMU_FSYS_MMC0, MIF_GATE_CLKCMU_FSYS_MMC0, 0);
M1D1G1(sclk_mmc2, 0, MIF_MUX_CLKCMU_FSYS_MMC2, MIF_DIV_CLKCMU_FSYS_MMC2, MIF_GATE_CLKCMU_FSYS_MMC2, 0);
M1D1G1(sclk_usb20drd_refclk, 0, MIF_MUX_CLKCMU_FSYS_USB20DRD_REFCLK, MIF_DIV_CLKCMU_FSYS_USB20DRD_REFCLK, MIF_GATE_CLKCMU_FSYS_USB20DRD_REFCLK, 0);
M1D1G1(sclk_uart_debug, gate_peri_peric0, MIF_MUX_CLKCMU_PERI_UART_DEBUG, MIF_DIV_CLKCMU_PERI_UART_DEBUG, MIF_GATE_CLKCMU_PERI_UART_DEBUG, 0);
M1D1G1(sclk_uart_sensor, gate_peri_peric0, MIF_MUX_CLKCMU_PERI_UART_SENSOR, MIF_DIV_CLKCMU_PERI_UART_SENSOR, MIF_GATE_CLKCMU_PERI_UART_SENSOR, 0);
M1D1G1(sclk_spi_ese, gate_peri_peris0, MIF_MUX_CLKCMU_PERI_SPI_ESE, MIF_DIV_CLKCMU_PERI_SPI_ESE, MIF_GATE_CLKCMU_PERI_SPI_ESE, 0);
M1D1G1(sclk_spi_rearfrom, gate_peri_peric1, MIF_MUX_CLKCMU_PERI_SPI_REARFROM, MIF_DIV_CLKCMU_PERI_SPI_REARFROM, MIF_GATE_CLKCMU_PERI_SPI_REARFROM, 0);
M1D1G1(sclk_usi0, gate_peri_peric1, MIF_MUX_CLKCMU_PERI_USI_0, MIF_DIV_CLKCMU_PERI_USI_0, MIF_GATE_CLKCMU_PERI_USI_0, 0);
M1D1G1(sclk_usi1, gate_peri_peric1, MIF_MUX_CLKCMU_PERI_USI_1, MIF_DIV_CLKCMU_PERI_USI_1, MIF_GATE_CLKCMU_PERI_USI_1, 0);
M1D1G1(sclk_apm, 0, MIF_MUX_CLKCMU_APM, MIF_DIV_CLKCMU_APM, MIF_GATE_CLKCMU_APM, APM_MUX_CLKCMU_APM_USER);
M1D1G1(sclk_isp_sensor0, 0, MIF_MUX_CLKCMU_ISP_SENSOR0, MIF_DIV_CLKCMU_ISP_SENSOR0, MIF_GATE_CLKCMU_ISP_SENSOR0, 0);
static struct pwrcal_clk *gategrp_mif_pdma[] = {
CLK(MIF_GATE_CLK_MIF_UID_PDMA_MIF_IPCLKPORT_ACLK_PDMA0),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_mif_adcif[] = {
CLK(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0),
CLK(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_mif_speedy[] = {
CLK(MIF_GATE_CLK_MIF_UID_SPEEDY_MIF_IPCLKPORT_PCLK),
CLK(MIF_GATE_CLK_MIF_UID_SPEEDY_BATCHER_WRAPPER_IPCLKPORT_PCLK_BATCHER_AP),
CLK(MIF_GATE_CLK_MIF_UID_SPEEDY_BATCHER_WRAPPER_IPCLKPORT_PCLK_BATCHER_SPEEDY),
CLK(MIF_GATE_CLK_MIF_UID_SPEEDY_MIF_IPCLKPORT_CLK), /* TCXO */
CLK_NONE,
};
static struct pwrcal_clk *gategrp_apm_apm[] = {
CLK(APM_GATE_CLK_APM_UID_ASYNCS_APM_IPCLKPORT_I_CLK),
CLK(APM_GATE_CLK_APM_UID_APM_IPCLKPORT_ACLK_CPU),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_cpucl0_bcm[] = {
CLK_NONE,
};
static struct pwrcal_clk *gategrp_cpucl0_bts[] = {
CLK_NONE,
};
static struct pwrcal_clk *gategrp_dispaud_common_disp[] = {
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_PPMU),
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_DISP),
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS),
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_DISP),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_dispaud_common_dsim0[] = {
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_DSIM0_IPCLKPORT_I_TXBYTECLKHS),
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_DSIM0_IPCLKPORT_I_RXCLKESC0),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_dispaud_common_aud[] = {
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_CP2AUD_BCK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_dispaud_sysmmu[] = {
CLK(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_dispaud_bcm[] = {
CLK(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_dispaud_bts[] = {
CLK(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_dispaud_decon[] = {
CLK(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER),
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_VCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_dispaud_dsim0[] = {
CLK(DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_dispaud_mixer[] = {
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_MIXER_AUD_IPCLKPORT_SYSCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_dispaud_mi2s_aud[] = {
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AUD_IPCLKPORT_I2SCODCLKI),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_dispaud_mi2s_amp[] = {
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD_AMP),
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AMP_IPCLKPORT_I2SCODCLKI),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_fsys_common[] = {
CLK(MIF_DIV_CLKCMU_FSYS_BUS),
/* CLK(FSYS_GATE_CLK_FSYS_UID_BUSD0_FSYS_IPCLKPORT_ACLK), clocks for secure IP*/
/* CLK(FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK), */
/* CLK(FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK), */
/* CLK(FSYS_GATE_CLK_FSYS_UID_ASYNCS_D_FSYS_IPCLKPORT_I_CLK), */
CLK_NONE,
};
static struct pwrcal_clk *gategrp_fsys_common_busp2[] = {
CLK(MIF_DIV_CLKCMU_FSYS_BUS),
/* CLK(FSYS_GATE_CLK_FSYS_UID_BUSP2_FSYS_IPCLKPORT_HCLK), clock for secure IP */
CLK_NONE,
};
static struct pwrcal_clk *gategrp_fsys_common_busp3[] = {
CLK(FSYS_GATE_CLK_FSYS_UID_BUSP3_FSYS_IPCLKPORT_HCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_fsys_sysmmu[] = {
CLK(MIF_DIV_CLKCMU_FSYS_BUS),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_fsys_bcm[] = {
CLK(MIF_DIV_CLKCMU_FSYS_BUS),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_fsys_bts[] = {
CLK(MIF_DIV_CLKCMU_FSYS_BUS),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_fsys_usb20drd[] = {
CLK(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HCLK_USB20_CTRL),
CLK(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_HSDRD),
CLK(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_ref_clk),
CLK(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_PHYCLOCK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_fsys_mmc0[] = {
CLK(FSYS_GATE_CLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_fsys_sclk_mmc0[] = {
CLK(MIF_DIV_CLKCMU_FSYS_MMC0),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_fsys_mmc2[] = {
CLK(FSYS_GATE_CLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_fsys_sclk_mmc2[] = {
CLK(MIF_DIV_CLKCMU_FSYS_MMC2),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_fsys_sss[] = {
CLK(MIF_DIV_CLKCMU_FSYS_BUS),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_fsys_rtic[] = {
CLK(MIF_DIV_CLKCMU_FSYS_BUS),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_g3d_common[] = {
CLK(G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_ACLK),
CLK(G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_PCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_g3d_sysmmu[] = {
CLK(G3D_DIV_CLK_G3D_BUS),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_g3d_bcm[] = {
CLK(G3D_DIV_CLK_G3D_BUS),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_g3d_bts[] = {
CLK(G3D_DIV_CLK_G3D_BUS),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_g3d_g3d[] = {
CLK(G3D_GATE_CLK_G3D_UID_G3D_IPCLKPORT_CLK),
CLK(G3D_GATE_CLK_G3D_UID_ASYNCS_D0_G3D_IPCLKPORT_I_CLK),
CLK(G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKM),
CLK(G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_isp_sysmmu[] = {
CLK(ISP_MUX_CLKCMU_ISP_CAM_USER),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_isp_bcm[] = {
CLK(ISP_MUX_CLKCMU_ISP_CAM_USER),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_isp_bts[] = {
CLK(ISP_MUX_CLKCMU_ISP_CAM_USER),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_isp_cam[] = {
CLK(ISP_MUX_CLKCMU_ISP_CAM_USER),
CLK(ISP_GATE_CLK_ISP_UID_CLKPHY_ISP_S_RXBYTECLKHS0_S4),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_isp_vra[] = {
CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_VRA),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_mfcmscl_sysmmu[] = {
CLK(MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_mfcmscl_bcm[] = {
CLK(MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_mfcmscl_bts[] = {
CLK(MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_mfcmscl_mscl[] = {
CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_POLY),
CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_BI),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_mfcmscl_jpeg[] = {
CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_JPEG),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_mfcmscl_mfc[] = {
CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_MFC),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_peris0[] = {
CLK(MIF_DIV_CLKCMU_PERI_BUS),
/* CLK(PERI_GATE_CLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK), clock for secure IP */
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_peric1[] = {
CLK(PERI_GATE_CLK_PERI_UID_BUSP1_PERIC1_IPCLKPORT_HCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_peric0[] = {
CLK(PERI_GATE_CLK_PERI_UID_BUSP1_PERIC0_IPCLKPORT_HCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_pwm_motor[] = {
CLK(PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_PCLK_S0),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_sclk_pwm_motor[] = {
CLK(PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_OSCCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_mct[] = {
CLK(PERI_GATE_CLK_PERI_UID_MCT_IPCLKPORT_PCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_i2c_sensor2[] = {
CLK(PERI_GATE_CLK_PERI_UID_I2C_SENSOR2_IPCLKPORT_PCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_i2c_sensor1[] = {
CLK(PERI_GATE_CLK_PERI_UID_I2C_SENSOR1_IPCLKPORT_PCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_i2c_tsp[] = {
CLK(PERI_GATE_CLK_PERI_UID_I2C_TSP_IPCLKPORT_PCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_i2c_fuelgauge[] = {
CLK(PERI_GATE_CLK_PERI_UID_I2C_FUELGAUGE_IPCLKPORT_PCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_i2c_nfc[] = {
CLK(PERI_GATE_CLK_PERI_UID_I2C_NFC_IPCLKPORT_PCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_i2c_muic[] = {
CLK(PERI_GATE_CLK_PERI_UID_I2C_MUIC_IPCLKPORT_PCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_hsi2c_frontcam[] = {
CLK(PERI_GATE_CLK_PERI_UID_HSI2C_FRONTCAM_IPCLKPORT_iPCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_hsi2c_maincam[] = {
CLK(PERI_GATE_CLK_PERI_UID_HSI2C_MAINCAM_IPCLKPORT_iPCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_hsi2c_frontsensor[] = {
CLK(PERI_GATE_CLK_PERI_UID_HSI2C_FRONTSENSOR_IPCLKPORT_iPCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_hsi2c_rearaf[] = {
CLK(PERI_GATE_CLK_PERI_UID_HSI2C_REARAF_IPCLKPORT_iPCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_hsi2c_rearsensor[] = {
CLK(PERI_GATE_CLK_PERI_UID_HSI2C_REARSENSOR_IPCLKPORT_iPCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_gpio_touch[] = {
CLK(PERI_GATE_CLK_PERI_UID_GPIO_TOUCH_IPCLKPORT_PCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_gpio_top[] = {
CLK(PERI_GATE_CLK_PERI_UID_GPIO_TOP_IPCLKPORT_PCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_gpio_nfc[] = {
CLK(PERI_GATE_CLK_PERI_UID_GPIO_NFC_IPCLKPORT_PCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_gpio_ese[] = {
CLK(PERI_GATE_CLK_PERI_UID_GPIO_ESE_IPCLKPORT_PCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_wdt_cpucl0[] = {
CLK(PERI_GATE_CLK_PERI_UID_WDT_CPUCL0_IPCLKPORT_PCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_uart_debug[] = {
CLK(PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_PCLK),
CLK(PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_EXT_UCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_uart_sensor[] = {
CLK(PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_PCLK),
/* TEMP CLK(PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_EXT_UCLK),*/
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_tmu_cpucl0[] = {
CLK(PERI_GATE_CLK_PERI_UID_SFRIF_TMU_CPUCL0_IPCLKPORT_PCLK),
CLK(PERI_GATE_CLK_PERI_UID_TMU_CPUCL0_IPCLKPORT_I_CLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_spi_ese[] = {
CLK(PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_PCLK),
CLK(PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_SPI_EXT_CLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_spi_rearfrom[] = {
CLK(PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_PCLK),
CLK(PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_SPI_EXT_CLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_gpio_alive[] = {
CLK(MIF_DIV_CLKCMU_PERI_BUS),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_chipid[] = {
CLK(MIF_DIV_CLKCMU_PERI_BUS),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_otp_con_top[] = {
CLK(MIF_DIV_CLKCMU_PERI_BUS),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_rtc_alive[] = {
CLK(MIF_DIV_CLKCMU_PERI_BUS),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_rtc_top[] = {
CLK(MIF_DIV_CLKCMU_PERI_BUS),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_usi0[] = {
CLK(PERI_GATE_CLK_PERI_UID_USI_0_IPCLKPORT_i_PCLK),
CLK_NONE,
};
static struct pwrcal_clk *gategrp_peri_usi1[] = {
CLK(PERI_GATE_CLK_PERI_UID_USI_1_IPCLKPORT_i_PCLK),
CLK_NONE,
};
GRPGATE(gate_mif_pdma, 0, gategrp_mif_pdma);
GRPGATE(gate_mif_adcif, 0, gategrp_mif_adcif);
GRPGATE(gate_mif_speedy, 0, gategrp_mif_speedy);
GRPGATE(gate_apm_apm, 0, gategrp_apm_apm);
GRPGATE(gate_cpucl0_bcm, 0, gategrp_cpucl0_bcm);
GRPGATE(gate_cpucl0_bts, 0, gategrp_cpucl0_bts);
GRPGATE(gate_dispaud_common_disp, pxmxdx_dispaud, gategrp_dispaud_common_disp);
GRPGATE(gate_dispaud_common_dsim0, gate_dispaud_common_disp, gategrp_dispaud_common_dsim0);
GRPGATE(gate_dispaud_common_aud, 0, gategrp_dispaud_common_aud);
GRPGATE(gate_dispaud_sysmmu, gate_dispaud_common_disp, gategrp_dispaud_sysmmu);
GRPGATE(gate_dispaud_bcm, gate_dispaud_common_disp, gategrp_dispaud_bcm);
GRPGATE(gate_dispaud_bts, gate_dispaud_common_disp, gategrp_dispaud_bts);
GRPGATE(gate_dispaud_decon, gate_dispaud_common_disp, gategrp_dispaud_decon);
GRPGATE(gate_dispaud_dsim0, gate_dispaud_common_dsim0, gategrp_dispaud_dsim0);
GRPGATE(gate_dispaud_mixer, gate_dispaud_common_aud, gategrp_dispaud_mixer);
GRPGATE(gate_dispaud_mi2s_aud, gate_dispaud_common_aud, gategrp_dispaud_mi2s_aud);
GRPGATE(gate_dispaud_mi2s_amp, gate_dispaud_common_aud, gategrp_dispaud_mi2s_amp);
GRPGATE(gate_fsys_common, 0, gategrp_fsys_common);
GRPGATE(gate_fsys_common_busp2, gate_fsys_common, gategrp_fsys_common_busp2);
GRPGATE(gate_fsys_common_busp3, gate_fsys_common, gategrp_fsys_common_busp3);
GRPGATE(gate_fsys_sysmmu, gate_fsys_common, gategrp_fsys_sysmmu);
GRPGATE(gate_fsys_bcm, gate_fsys_common, gategrp_fsys_bcm);
GRPGATE(gate_fsys_bts, gate_fsys_common, gategrp_fsys_bts);
GRPGATE(gate_fsys_usb20drd, gate_fsys_common_busp3, gategrp_fsys_usb20drd);
GRPGATE(gate_fsys_mmc0, gate_fsys_common_busp3, gategrp_fsys_mmc0);
GRPGATE(gate_fsys_sclk_mmc0, sclk_mmc0, gategrp_fsys_sclk_mmc0);
GRPGATE(gate_fsys_mmc2, gate_fsys_common_busp3, gategrp_fsys_mmc2);
GRPGATE(gate_fsys_sclk_mmc2, sclk_mmc2, gategrp_fsys_sclk_mmc2);
GRPGATE(gate_fsys_sss, gate_fsys_common_busp2, gategrp_fsys_sss);
GRPGATE(gate_fsys_rtic, gate_fsys_common_busp2, gategrp_fsys_rtic);
GRPGATE(gate_g3d_common, dvfs_g3d, gategrp_g3d_common);
GRPGATE(gate_g3d_sysmmu, gate_g3d_common, gategrp_g3d_sysmmu);
GRPGATE(gate_g3d_bcm, gate_g3d_common, gategrp_g3d_bcm);
GRPGATE(gate_g3d_bts, gate_g3d_common, gategrp_g3d_bts);
GRPGATE(gate_g3d_g3d, gate_g3d_common, gategrp_g3d_g3d);
GRPGATE(gate_isp_sysmmu, dvfs_cam, gategrp_isp_sysmmu);
GRPGATE(gate_isp_bcm, dvfs_cam, gategrp_isp_bcm);
GRPGATE(gate_isp_bts, dvfs_cam, gategrp_isp_bts);
GRPGATE(gate_isp_cam, pxmxdx_isp_cam, gategrp_isp_cam);
GRPGATE(gate_isp_vra, pxmxdx_isp_vra, gategrp_isp_vra);
GRPGATE(gate_mfcmscl_sysmmu, pxmxdx_mfcmscl, gategrp_mfcmscl_sysmmu);
GRPGATE(gate_mfcmscl_bcm, pxmxdx_mfcmscl, gategrp_mfcmscl_bcm);
GRPGATE(gate_mfcmscl_bts, pxmxdx_mfcmscl, gategrp_mfcmscl_bts);
GRPGATE(gate_mfcmscl_mscl, pxmxdx_mfcmscl, gategrp_mfcmscl_mscl);
GRPGATE(gate_mfcmscl_jpeg, pxmxdx_mfcmscl, gategrp_mfcmscl_jpeg);
GRPGATE(gate_mfcmscl_mfc, pxmxdx_mfcmscl, gategrp_mfcmscl_mfc);
GRPGATE(gate_peri_peris0, 0, gategrp_peri_peris0);
GRPGATE(gate_peri_peric1, 0, gategrp_peri_peric1);
GRPGATE(gate_peri_peric0, 0, gategrp_peri_peric0);
GRPGATE(gate_peri_pwm_motor, gate_peri_peric1, gategrp_peri_pwm_motor);
GRPGATE(gate_peri_sclk_pwm_motor, gate_peri_peric1, gategrp_peri_sclk_pwm_motor);
GRPGATE(gate_peri_mct, 0, gategrp_peri_mct);
GRPGATE(gate_peri_i2c_sensor2, gate_peri_peric0, gategrp_peri_i2c_sensor2);
GRPGATE(gate_peri_i2c_sensor1, gate_peri_peric0, gategrp_peri_i2c_sensor1);
GRPGATE(gate_peri_i2c_tsp, gate_peri_peric0, gategrp_peri_i2c_tsp);
GRPGATE(gate_peri_i2c_fuelgauge, gate_peri_peric0, gategrp_peri_i2c_fuelgauge);
GRPGATE(gate_peri_i2c_nfc, gate_peri_peric0, gategrp_peri_i2c_nfc);
GRPGATE(gate_peri_i2c_muic, gate_peri_peric0, gategrp_peri_i2c_muic);
GRPGATE(gate_peri_hsi2c_frontcam, gate_peri_peric1, gategrp_peri_hsi2c_frontcam);
GRPGATE(gate_peri_hsi2c_maincam, gate_peri_peric1, gategrp_peri_hsi2c_maincam);
GRPGATE(gate_peri_hsi2c_frontsensor, gate_peri_peric0, gategrp_peri_hsi2c_frontsensor);
GRPGATE(gate_peri_hsi2c_rearaf, gate_peri_peric0, gategrp_peri_hsi2c_rearaf);
GRPGATE(gate_peri_hsi2c_rearsensor, gate_peri_peric0, gategrp_peri_hsi2c_rearsensor);
GRPGATE(gate_peri_gpio_touch, gate_peri_peric1, gategrp_peri_gpio_touch);
GRPGATE(gate_peri_gpio_top, gate_peri_peric1, gategrp_peri_gpio_top);
GRPGATE(gate_peri_gpio_nfc, gate_peri_peric1, gategrp_peri_gpio_nfc);
GRPGATE(gate_peri_gpio_ese, gate_peri_peric1, gategrp_peri_gpio_ese);
GRPGATE(gate_peri_wdt_cpucl0, 0, gategrp_peri_wdt_cpucl0);
GRPGATE(gate_peri_uart_debug, sclk_uart_debug, gategrp_peri_uart_debug);
GRPGATE(gate_peri_uart_sensor, sclk_uart_sensor, gategrp_peri_uart_sensor);
GRPGATE(gate_peri_tmu_cpucl0, 0, gategrp_peri_tmu_cpucl0);
GRPGATE(gate_peri_spi_ese, sclk_spi_ese, gategrp_peri_spi_ese);
GRPGATE(gate_peri_spi_rearfrom, sclk_spi_rearfrom, gategrp_peri_spi_rearfrom);
GRPGATE(gate_peri_gpio_alive, gate_peri_peric1, gategrp_peri_gpio_alive);
GRPGATE(gate_peri_chipid, 0, gategrp_peri_chipid);
GRPGATE(gate_peri_otp_con_top, gate_peri_peris0, gategrp_peri_otp_con_top);
GRPGATE(gate_peri_rtc_alive, 0, gategrp_peri_rtc_alive);
GRPGATE(gate_peri_rtc_top, 0, gategrp_peri_rtc_top);
GRPGATE(gate_peri_usi0, sclk_usi0, gategrp_peri_usi0);
GRPGATE(gate_peri_usi1, sclk_usi1, gategrp_peri_usi1);
UMUX(umux_dispaud_clkphy_dispaud_mipiphy_txbyteclkhs_user, 0, DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER);
UMUX(umux_dispaud_clkphy_dispaud_mipiphy_rxclkesc0_user, 0, DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER);
UMUX(umux_fsys_clkphy_fsys_usb20drd_phyclock_user, 0, FSYS_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER);
UMUX(umux_isp_clkphy_isp_s_rxbyteclkhs0_s4_user, 0, ISP_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER);
void vclk_unused_disable(void)
{
/* vclk_disable(VCLK(sclk_decon_vclk)); */
/* vclk_disable(VCLK(sclk_decon_vclk_local)); */
vclk_disable(VCLK(sclk_mmc0));
vclk_disable(VCLK(sclk_mmc2));
vclk_disable(VCLK(sclk_usb20drd_refclk));
vclk_disable(VCLK(sclk_spi_rearfrom));
vclk_disable(VCLK(sclk_spi_ese));
vclk_disable(VCLK(sclk_usi0));
vclk_disable(VCLK(sclk_usi1));
vclk_disable(VCLK(sclk_isp_sensor0));
vclk_disable(VCLK(gate_mif_pdma));
vclk_disable(VCLK(gate_mif_adcif));
/* vclk_disable(VCLK(gate_mif_speedy)); */
vclk_disable(VCLK(gate_cpucl0_bcm));
vclk_disable(VCLK(gate_cpucl0_bts));
/* vclk_disable(VCLK(gate_dispaud_common_disp)); */
/* vclk_disable(VCLK(gate_dispaud_common_dsim0)); */
/* vclk_disable(VCLK(gate_dispaud_common_aud)); */
/* vclk_disable(VCLK(gate_dispaud_sysmmu)); */
/* vclk_disable(VCLK(gate_dispaud_bcm)); */
/* vclk_disable(VCLK(gate_dispaud_bts)); */
/* vclk_disable(VCLK(gate_dispaud_decon)); */
/* vclk_disable(VCLK(gate_dispaud_dsim0)); */
/* vclk_disable(VCLK(gate_dispaud_mixer)); */
/* vclk_disable(VCLK(gate_dispaud_mi2s_aud)); */
/* vclk_disable(VCLK(gate_dispaud_mi2s_amp)); */
vclk_disable(VCLK(gate_peri_i2c_sensor2));
vclk_disable(VCLK(gate_peri_i2c_sensor1));
vclk_disable(VCLK(gate_peri_i2c_tsp));
vclk_disable(VCLK(gate_peri_i2c_fuelgauge));
vclk_disable(VCLK(gate_peri_i2c_nfc));
vclk_disable(VCLK(gate_peri_i2c_muic));
vclk_disable(VCLK(gate_peri_hsi2c_frontcam));
vclk_disable(VCLK(gate_peri_hsi2c_maincam));
vclk_disable(VCLK(gate_peri_hsi2c_frontsensor));
vclk_disable(VCLK(gate_peri_hsi2c_rearaf));
vclk_disable(VCLK(gate_peri_hsi2c_rearsensor));
vclk_disable(VCLK(gate_peri_spi_ese));
vclk_disable(VCLK(gate_peri_spi_rearfrom));
vclk_disable(VCLK(gate_peri_usi0));
vclk_disable(VCLK(gate_peri_usi1));
vclk_disable(VCLK(gate_fsys_sysmmu));
vclk_disable(VCLK(gate_fsys_bcm));
vclk_disable(VCLK(gate_fsys_bts));
vclk_disable(VCLK(gate_fsys_usb20drd));
vclk_disable(VCLK(gate_fsys_mmc0));
vclk_disable(VCLK(gate_fsys_sclk_mmc0));
vclk_disable(VCLK(gate_fsys_mmc2));
vclk_disable(VCLK(gate_fsys_sclk_mmc2));
/* vclk_disable(VCLK(gate_fsys_sss)); */
/* vclk_disable(VCLK(gate_fsys_rtic)); */
vclk_disable(VCLK(gate_g3d_sysmmu));
vclk_disable(VCLK(gate_g3d_bcm));
vclk_disable(VCLK(gate_g3d_bts));
vclk_disable(VCLK(gate_g3d_g3d));
vclk_disable(VCLK(gate_isp_sysmmu));
vclk_disable(VCLK(gate_isp_bcm));
vclk_disable(VCLK(gate_isp_bts));
vclk_disable(VCLK(gate_isp_cam));
vclk_disable(VCLK(gate_isp_vra));
vclk_disable(VCLK(gate_mfcmscl_sysmmu));
vclk_disable(VCLK(gate_mfcmscl_bcm));
vclk_disable(VCLK(gate_mfcmscl_bts));
vclk_disable(VCLK(gate_mfcmscl_mscl));
vclk_disable(VCLK(gate_mfcmscl_jpeg));
vclk_disable(VCLK(gate_mfcmscl_mfc));
/* vclk_disable(VCLK(gate_peri_chipid)); */
/* vclk_disable(VCLK(gate_peri_otp_con_top)); */
/* vclk_disable(VCLK(gate_peri_rtc_alive)); */
/* vclk_disable(VCLK(gate_peri_rtc_top)); */
/* vclk_disable(VCLK(pxmxdx_dispaud)); */
vclk_disable(VCLK(pxmxdx_mfcmscl));
vclk_disable(VCLK(pxmxdx_isp_vra));
vclk_disable(VCLK(pxmxdx_isp_cam));
vclk_disable(VCLK(pxmxdx_oscclk_aud));
vclk_disable(VCLK(p1_aud_pll));
/* vclk_disable(VCLK(p1_wpll_usb_pll)); */
vclk_disable(VCLK(d1_dispaud_mi2s));
vclk_disable(VCLK(d1_dispaud_mixer));
vclk_disable(VCLK(d1_dispaud_oscclk_fm_52m));
return;
}
void vclk_init(void)
{
ADD_LIST(vclk_pxmxdx_list, pxmxdx_top);
ADD_LIST(vclk_pxmxdx_list, pxmxdx_dispaud);
ADD_LIST(vclk_pxmxdx_list, pxmxdx_mfcmscl);
ADD_LIST(vclk_pxmxdx_list, pxmxdx_isp_vra);
ADD_LIST(vclk_pxmxdx_list, pxmxdx_isp_cam);
ADD_LIST(vclk_pxmxdx_list, pxmxdx_oscclk_aud);
ADD_LIST(vclk_p1_list, p1_aud_pll);
ADD_LIST(vclk_p1_list, p1_wpll_usb_pll);
ADD_LIST(vclk_m1_list, m1_dummy);
ADD_LIST(vclk_d1_list, sclk_decon_vclk_local);
ADD_LIST(vclk_d1_list, d1_dispaud_mi2s);
ADD_LIST(vclk_d1_list, d1_dispaud_mixer);
ADD_LIST(vclk_d1_list, d1_dispaud_oscclk_fm_52m);
ADD_LIST(vclk_m1d1g1_list, sclk_decon_vclk);
ADD_LIST(vclk_m1d1g1_list, sclk_mmc0);
ADD_LIST(vclk_m1d1g1_list, sclk_mmc2);
ADD_LIST(vclk_m1d1g1_list, sclk_usb20drd_refclk);
ADD_LIST(vclk_m1d1g1_list, sclk_uart_debug);
ADD_LIST(vclk_m1d1g1_list, sclk_uart_sensor);
ADD_LIST(vclk_m1d1g1_list, sclk_spi_rearfrom);
ADD_LIST(vclk_m1d1g1_list, sclk_spi_ese);
ADD_LIST(vclk_m1d1g1_list, sclk_usi0);
ADD_LIST(vclk_m1d1g1_list, sclk_usi1);
ADD_LIST(vclk_m1d1g1_list, sclk_apm);
ADD_LIST(vclk_m1d1g1_list, sclk_isp_sensor0);
ADD_LIST(vclk_grpgate_list, gate_mif_pdma);
ADD_LIST(vclk_grpgate_list, gate_mif_adcif);
ADD_LIST(vclk_grpgate_list, gate_mif_speedy);
ADD_LIST(vclk_grpgate_list, gate_apm_apm);
ADD_LIST(vclk_grpgate_list, gate_cpucl0_bcm);
ADD_LIST(vclk_grpgate_list, gate_cpucl0_bts);
ADD_LIST(vclk_grpgate_list, gate_dispaud_common_disp);
ADD_LIST(vclk_grpgate_list, gate_dispaud_common_dsim0);
ADD_LIST(vclk_grpgate_list, gate_dispaud_common_aud);
ADD_LIST(vclk_grpgate_list, gate_dispaud_sysmmu);
ADD_LIST(vclk_grpgate_list, gate_dispaud_bcm);
ADD_LIST(vclk_grpgate_list, gate_dispaud_bts);
ADD_LIST(vclk_grpgate_list, gate_dispaud_decon);
ADD_LIST(vclk_grpgate_list, gate_dispaud_dsim0);
ADD_LIST(vclk_grpgate_list, gate_dispaud_mixer);
ADD_LIST(vclk_grpgate_list, gate_dispaud_mi2s_aud);
ADD_LIST(vclk_grpgate_list, gate_dispaud_mi2s_amp);
ADD_LIST(vclk_grpgate_list, gate_peri_peris0);
ADD_LIST(vclk_grpgate_list, gate_peri_peric1);
ADD_LIST(vclk_grpgate_list, gate_peri_peric0);
ADD_LIST(vclk_grpgate_list, gate_peri_pwm_motor);
ADD_LIST(vclk_grpgate_list, gate_peri_sclk_pwm_motor);
ADD_LIST(vclk_grpgate_list, gate_peri_mct);
ADD_LIST(vclk_grpgate_list, gate_peri_i2c_sensor2);
ADD_LIST(vclk_grpgate_list, gate_peri_i2c_sensor1);
ADD_LIST(vclk_grpgate_list, gate_peri_i2c_tsp);
ADD_LIST(vclk_grpgate_list, gate_peri_i2c_fuelgauge);
ADD_LIST(vclk_grpgate_list, gate_peri_i2c_nfc);
ADD_LIST(vclk_grpgate_list, gate_peri_i2c_muic);
ADD_LIST(vclk_grpgate_list, gate_peri_hsi2c_frontcam);
ADD_LIST(vclk_grpgate_list, gate_peri_hsi2c_maincam);
ADD_LIST(vclk_grpgate_list, gate_peri_hsi2c_frontsensor);
ADD_LIST(vclk_grpgate_list, gate_peri_hsi2c_rearaf);
ADD_LIST(vclk_grpgate_list, gate_peri_hsi2c_rearsensor);
ADD_LIST(vclk_grpgate_list, gate_peri_gpio_touch);
ADD_LIST(vclk_grpgate_list, gate_peri_gpio_top);
ADD_LIST(vclk_grpgate_list, gate_peri_gpio_nfc);
ADD_LIST(vclk_grpgate_list, gate_peri_gpio_ese);
ADD_LIST(vclk_grpgate_list, gate_peri_wdt_cpucl0);
ADD_LIST(vclk_grpgate_list, gate_peri_uart_debug);
ADD_LIST(vclk_grpgate_list, gate_peri_uart_sensor);
ADD_LIST(vclk_grpgate_list, gate_peri_tmu_cpucl0);
ADD_LIST(vclk_grpgate_list, gate_peri_spi_ese);
ADD_LIST(vclk_grpgate_list, gate_peri_spi_rearfrom);
ADD_LIST(vclk_grpgate_list, gate_peri_usi0);
ADD_LIST(vclk_grpgate_list, gate_peri_usi1);
ADD_LIST(vclk_grpgate_list, gate_fsys_common);
ADD_LIST(vclk_grpgate_list, gate_fsys_common_busp2);
ADD_LIST(vclk_grpgate_list, gate_fsys_common_busp3);
ADD_LIST(vclk_grpgate_list, gate_fsys_sysmmu);
ADD_LIST(vclk_grpgate_list, gate_fsys_bcm);
ADD_LIST(vclk_grpgate_list, gate_fsys_bts);
ADD_LIST(vclk_grpgate_list, gate_fsys_usb20drd);
ADD_LIST(vclk_grpgate_list, gate_fsys_mmc0);
ADD_LIST(vclk_grpgate_list, gate_fsys_sclk_mmc0);
ADD_LIST(vclk_grpgate_list, gate_fsys_mmc2);
ADD_LIST(vclk_grpgate_list, gate_fsys_sclk_mmc2);
ADD_LIST(vclk_grpgate_list, gate_fsys_sss);
ADD_LIST(vclk_grpgate_list, gate_fsys_rtic);
ADD_LIST(vclk_grpgate_list, gate_g3d_common);
ADD_LIST(vclk_grpgate_list, gate_g3d_sysmmu);
ADD_LIST(vclk_grpgate_list, gate_g3d_bcm);
ADD_LIST(vclk_grpgate_list, gate_g3d_bts);
ADD_LIST(vclk_grpgate_list, gate_g3d_g3d);
ADD_LIST(vclk_grpgate_list, gate_isp_sysmmu);
ADD_LIST(vclk_grpgate_list, gate_isp_bcm);
ADD_LIST(vclk_grpgate_list, gate_isp_bts);
ADD_LIST(vclk_grpgate_list, gate_isp_cam);
ADD_LIST(vclk_grpgate_list, gate_isp_vra);
ADD_LIST(vclk_grpgate_list, gate_mfcmscl_sysmmu);
ADD_LIST(vclk_grpgate_list, gate_mfcmscl_bcm);
ADD_LIST(vclk_grpgate_list, gate_mfcmscl_bts);
ADD_LIST(vclk_grpgate_list, gate_mfcmscl_mscl);
ADD_LIST(vclk_grpgate_list, gate_mfcmscl_jpeg);
ADD_LIST(vclk_grpgate_list, gate_mfcmscl_mfc);
ADD_LIST(vclk_grpgate_list, gate_peri_gpio_alive);
ADD_LIST(vclk_grpgate_list, gate_peri_chipid);
ADD_LIST(vclk_grpgate_list, gate_peri_otp_con_top);
ADD_LIST(vclk_grpgate_list, gate_peri_rtc_alive);
ADD_LIST(vclk_grpgate_list, gate_peri_rtc_top);
ADD_LIST(vclk_umux_list, umux_dispaud_clkphy_dispaud_mipiphy_txbyteclkhs_user);
ADD_LIST(vclk_umux_list, umux_dispaud_clkphy_dispaud_mipiphy_rxclkesc0_user);
ADD_LIST(vclk_umux_list, umux_fsys_clkphy_fsys_usb20drd_phyclock_user);
ADD_LIST(vclk_umux_list, umux_isp_clkphy_isp_s_rxbyteclkhs0_s4_user);
ADD_LIST(vclk_dfs_list, dvfs_cpucl0);
ADD_LIST(vclk_dfs_list, dvfs_g3d);
ADD_LIST(vclk_dfs_list, dvfs_mif);
ADD_LIST(vclk_dfs_list, dvfs_int);
ADD_LIST(vclk_dfs_list, dvfs_disp);
ADD_LIST(vclk_dfs_list, dvfs_cam);
vclk_enable(VCLK(gate_peri_peric0));
vclk_enable(VCLK(gate_peri_peric1));
return;
}

147
drivers/soc/samsung/pwrcal/S5E7570/S5E7570-vclk.h Normal file
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@ -0,0 +1,147 @@
#ifndef __EXYNOS7570_VCLK_H__
#define __EXYNOS7570_VCLK_H__
enum {
gate_mif_pdma = 0x0A000000,
gate_mif_adcif,
gate_mif_speedy,
gate_apm_apm,
gate_cpucl0_bcm,
gate_cpucl0_bts,
gate_dispaud_common_disp,
gate_dispaud_common_dsim0,
gate_dispaud_common_aud,
gate_dispaud_sysmmu,
gate_dispaud_bcm,
gate_dispaud_bts,
gate_dispaud_decon,
gate_dispaud_dsim0,
gate_dispaud_mixer,
gate_dispaud_mi2s_aud,
gate_dispaud_mi2s_amp,
gate_peri_peris0,
gate_peri_peric1,
gate_peri_peric0,
gate_peri_pwm_motor,
gate_peri_sclk_pwm_motor,
gate_peri_mct,
gate_peri_i2c_sensor2,
gate_peri_i2c_sensor1,
gate_peri_i2c_tsp,
gate_peri_i2c_fuelgauge,
gate_peri_i2c_nfc,
gate_peri_i2c_muic,
gate_peri_hsi2c_frontcam,
gate_peri_hsi2c_maincam,
gate_peri_hsi2c_frontsensor,
gate_peri_hsi2c_rearaf,
gate_peri_hsi2c_rearsensor,
gate_peri_gpio_touch,
gate_peri_gpio_top,
gate_peri_gpio_nfc,
gate_peri_gpio_ese,
gate_peri_wdt_cpucl0,
gate_peri_uart_debug,
gate_peri_uart_sensor,
gate_peri_tmu_cpucl0,
gate_peri_spi_ese,
gate_peri_spi_rearfrom,
gate_peri_gpio_alive,
gate_peri_chipid,
gate_peri_otp_con_top,
gate_peri_rtc_alive,
gate_peri_rtc_top,
gate_peri_usi0,
gate_peri_usi1,
gate_fsys_common,
gate_fsys_common_busp2,
gate_fsys_common_busp3,
gate_fsys_sysmmu,
gate_fsys_bcm,
gate_fsys_bts,
gate_fsys_usb20drd,
gate_fsys_mmc0,
gate_fsys_sclk_mmc0,
gate_fsys_mmc2,
gate_fsys_sclk_mmc2,
gate_fsys_sss,
gate_fsys_rtic,
gate_g3d_common,
gate_g3d_sysmmu,
gate_g3d_bcm,
gate_g3d_bts,
gate_g3d_g3d,
gate_isp_sysmmu,
gate_isp_bcm,
gate_isp_bts,
gate_isp_cam,
gate_isp_vra,
gate_mfcmscl_sysmmu,
gate_mfcmscl_bcm,
gate_mfcmscl_bts,
gate_mfcmscl_mscl,
gate_mfcmscl_jpeg,
gate_mfcmscl_mfc,
vclk_group_grpgate_end,
num_of_grpgate = vclk_group_grpgate_end - 0x0A000000,
sclk_decon_vclk = 0x0A010000,
sclk_mmc0,
sclk_mmc2,
sclk_usb20drd_refclk,
sclk_uart_debug,
sclk_uart_sensor,
sclk_spi_rearfrom,
sclk_spi_ese,
sclk_usi0,
sclk_usi1,
sclk_apm,
sclk_isp_sensor0,
vclk_group_m1d1g1_end,
num_of_m1d1g1 = vclk_group_m1d1g1_end - 0x0A010000,
p1_aud_pll = 0x0A020000,
p1_wpll_usb_pll,
vclk_group_p1_end,
num_of_p1 = vclk_group_p1_end - 0x0A020000,
m1_dummy = 0x0A030000,
vclk_group_m1_end,
num_of_m1 = vclk_group_m1_end - 0x0A030000,
sclk_decon_vclk_local = 0x0A040000,
d1_dispaud_mi2s,
d1_dispaud_mixer,
d1_dispaud_oscclk_fm_52m,
vclk_group_d1_end,
num_of_d1 = vclk_group_d1_end - 0x0A040000,
pxmxdx_top = 0x0A050000,
pxmxdx_dispaud,
pxmxdx_mfcmscl,
pxmxdx_isp_vra,
pxmxdx_isp_cam,
pxmxdx_oscclk_aud,
vclk_group_pxmxdx_end,
num_of_pxmxdx = vclk_group_pxmxdx_end - 0x0A050000,
umux_dispaud_clkphy_dispaud_mipiphy_txbyteclkhs_user = 0x0A060000,
umux_dispaud_clkphy_dispaud_mipiphy_rxclkesc0_user,
umux_fsys_clkphy_fsys_usb20drd_phyclock_user,
umux_isp_clkphy_isp_s_rxbyteclkhs0_s4_user,
vclk_group_umux_end,
num_of_umux = vclk_group_umux_end - 0x0A060000,
dvfs_cpucl0 = 0x0A070000,
dvfs_g3d,
dvfs_mif,
dvfs_int,
dvfs_disp,
dvfs_cam,
vclk_group_dfs_end,
num_of_dfs = vclk_group_dfs_end - 0x0A070000,
};
#endif