mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 16:18:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
1050
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-asv.c
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drivers/soc/samsung/pwrcal/S5E7870/S5E7870-asv.c
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Load diff
1293
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-cmu.c
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drivers/soc/samsung/pwrcal/S5E7870/S5E7870-cmu.c
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Load diff
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drivers/soc/samsung/pwrcal/S5E7870/S5E7870-cmu.h
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drivers/soc/samsung/pwrcal/S5E7870/S5E7870-cmu.h
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Load diff
484
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-cmusfr.h
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drivers/soc/samsung/pwrcal/S5E7870/S5E7870-cmusfr.h
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/*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd. All rights reserved.
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* http://www.samsung.com
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*
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* Chip Abstraction Layer for local/system power down support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __EXYNOS7870_CMUSFR_H__
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#define __EXYNOS7870_CMUSFR_H__
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#include "S5E7870-sfrbase.h"
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#define MEM_PLL_LOCK ((void *)(CMU_MIF_BASE + 0x0000))
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#define MEDIA_PLL_LOCK ((void *)(CMU_MIF_BASE + 0x0020))
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#define BUS_PLL_LOCK ((void *)(CMU_MIF_BASE + 0x0040))
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#define MEM_PLL_CON0 ((void *)(CMU_MIF_BASE + 0x0100))
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#define MEM_PLL_CON1 ((void *)(CMU_MIF_BASE + 0x0104))
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#define MEDIA_PLL_CON0 ((void *)(CMU_MIF_BASE + 0x0120))
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#define MEDIA_PLL_CON1 ((void *)(CMU_MIF_BASE + 0x0124))
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#define BUS_PLL_CON0 ((void *)(CMU_MIF_BASE + 0x0140))
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#define BUS_PLL_CON1 ((void *)(CMU_MIF_BASE + 0x0144))
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#define CLK_CON_MUX_MEM_PLL ((void *)(CMU_MIF_BASE + 0x0200))
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#define CLK_CON_MUX_MEDIA_PLL ((void *)(CMU_MIF_BASE + 0x0204))
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#define CLK_CON_MUX_BUS_PLL ((void *)(CMU_MIF_BASE + 0x0208))
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#define CLK_CON_MUX_CLK_MIF_PHY_CLK2X ((void *)(CMU_MIF_BASE + 0x0210))
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#define CLK_CON_MUX_CLK_MIF_PHY_SWITCH ((void *)(CMU_MIF_BASE + 0x0214))
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#define CLK_CON_MUX_CLK_MIF_BUSD ((void *)(CMU_MIF_BASE + 0x0220))
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#define CLK_CON_MUX_CLK_MIF_CCI ((void *)(CMU_MIF_BASE + 0x0228))
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#define CLK_CON_MUX_CLKCMU_ISP_VRA ((void *)(CMU_MIF_BASE + 0x0264))
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#define CLK_CON_MUX_CLKCMU_ISP_CAM ((void *)(CMU_MIF_BASE + 0x0268))
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#define CLK_CON_MUX_CLKCMU_ISP_ISP ((void *)(CMU_MIF_BASE + 0x026C))
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#define CLK_CON_MUX_CLKCMU_DISPAUD_BUS ((void *)(CMU_MIF_BASE + 0x0270))
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#define CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK ((void *)(CMU_MIF_BASE + 0x0274))
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#define CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK ((void *)(CMU_MIF_BASE + 0x0278))
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#define CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL ((void *)(CMU_MIF_BASE + 0x027C))
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#define CLK_CON_MUX_CLKCMU_MFCMSCL_MFC ((void *)(CMU_MIF_BASE + 0x0280))
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#define CLK_CON_MUX_CLKCMU_FSYS_BUS ((void *)(CMU_MIF_BASE + 0x0284))
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#define CLK_CON_MUX_CLKCMU_FSYS_MMC0 ((void *)(CMU_MIF_BASE + 0x0288))
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#define CLK_CON_MUX_CLKCMU_FSYS_MMC1 ((void *)(CMU_MIF_BASE + 0x028C))
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#define CLK_CON_MUX_CLKCMU_FSYS_MMC2 ((void *)(CMU_MIF_BASE + 0x0290))
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#define CLK_CON_MUX_CLKCMU_FSYS_UFSUNIPRO ((void *)(CMU_MIF_BASE + 0x0294))
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#define CLK_CON_MUX_CLKCMU_FSYS_UFSUNIPRO_CFG ((void *)(CMU_MIF_BASE + 0x0298))
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#define CLK_CON_MUX_CLKCMU_FSYS_USB20DRD_REFCLK ((void *)(CMU_MIF_BASE + 0x029C))
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#define CLK_CON_MUX_CLKCMU_PERI_BUS ((void *)(CMU_MIF_BASE + 0x02A0))
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#define CLK_CON_MUX_CLKCMU_PERI_UART_BTWIFIFM ((void *)(CMU_MIF_BASE + 0x02A4))
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#define CLK_CON_MUX_CLKCMU_PERI_UART_DEBUG ((void *)(CMU_MIF_BASE + 0x02A8))
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#define CLK_CON_MUX_CLKCMU_PERI_UART_SENSOR ((void *)(CMU_MIF_BASE + 0x02AC))
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#define CLK_CON_MUX_CLKCMU_PERI_SPI_FRONTFROM ((void *)(CMU_MIF_BASE + 0x02B0))
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#define CLK_CON_MUX_CLKCMU_PERI_SPI_REARFROM ((void *)(CMU_MIF_BASE + 0x02B4))
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#define CLK_CON_MUX_CLKCMU_PERI_SPI_ESE ((void *)(CMU_MIF_BASE + 0x02B8))
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#define CLK_CON_MUX_CLKCMU_PERI_SPI_VOICEPROCESSOR ((void *)(CMU_MIF_BASE + 0x02BC))
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#define CLK_CON_MUX_CLKCMU_PERI_SPI_SENSORHUB ((void *)(CMU_MIF_BASE + 0x02C0))
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#define CLK_CON_MUX_CLKCMU_ISP_SENSOR0 ((void *)(CMU_MIF_BASE + 0x02C4))
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#define CLK_CON_MUX_CLKCMU_ISP_SENSOR1 ((void *)(CMU_MIF_BASE + 0x02C8))
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#define CLK_CON_MUX_CLKCMU_ISP_SENSOR2 ((void *)(CMU_MIF_BASE + 0x02CC))
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#define CLK_CON_DIV_CLK_MIF_PHY_CLKM ((void *)(CMU_MIF_BASE + 0x0414))
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#define CLK_CON_DIV_CLK_MIF_BUSD ((void *)(CMU_MIF_BASE + 0x0420))
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#define CLK_CON_DIV_CLK_MIF_APB ((void *)(CMU_MIF_BASE + 0x0424))
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#define CLK_CON_DIV_CLK_MIF_CCI ((void *)(CMU_MIF_BASE + 0x0428))
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#define CLK_CON_DIV_CLK_MIF_BUSP ((void *)(CMU_MIF_BASE + 0x042C))
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#define CLK_CON_DIV_CLK_MIF_HSI2C ((void *)(CMU_MIF_BASE + 0x0430))
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#define CLK_CON_DIV_CLKCMU_CP_MEDIA_PLL ((void *)(CMU_MIF_BASE + 0x0450))
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#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH ((void *)(CMU_MIF_BASE + 0x0458))
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#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH ((void *)(CMU_MIF_BASE + 0x045C))
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#define CLK_CON_DIV_CLKCMU_G3D_SWITCH ((void *)(CMU_MIF_BASE + 0x0460))
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#define CLK_CON_DIV_CLKCMU_ISP_VRA ((void *)(CMU_MIF_BASE + 0x0464))
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#define CLK_CON_DIV_CLKCMU_ISP_CAM ((void *)(CMU_MIF_BASE + 0x0468))
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#define CLK_CON_DIV_CLKCMU_ISP_ISP ((void *)(CMU_MIF_BASE + 0x046C))
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#define CLK_CON_DIV_CLKCMU_DISPAUD_BUS ((void *)(CMU_MIF_BASE + 0x0470))
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#define CLK_CON_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK ((void *)(CMU_MIF_BASE + 0x0474))
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#define CLK_CON_DIV_CLKCMU_DISPAUD_DECON_INT_ECLK ((void *)(CMU_MIF_BASE + 0x0478))
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#define CLK_CON_DIV_CLKCMU_MFCMSCL_MSCL ((void *)(CMU_MIF_BASE + 0x047C))
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#define CLK_CON_DIV_CLKCMU_MFCMSCL_MFC ((void *)(CMU_MIF_BASE + 0x0480))
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#define CLK_CON_DIV_CLKCMU_FSYS_BUS ((void *)(CMU_MIF_BASE + 0x0484))
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#define CLK_CON_DIV_CLKCMU_FSYS_MMC0 ((void *)(CMU_MIF_BASE + 0x0488))
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#define CLK_CON_DIV_CLKCMU_FSYS_MMC1 ((void *)(CMU_MIF_BASE + 0x048C))
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#define CLK_CON_DIV_CLKCMU_FSYS_MMC2 ((void *)(CMU_MIF_BASE + 0x0490))
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#define CLK_CON_DIV_CLKCMU_FSYS_UFSUNIPRO ((void *)(CMU_MIF_BASE + 0x0494))
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#define CLK_CON_DIV_CLKCMU_FSYS_UFSUNIPRO_CFG ((void *)(CMU_MIF_BASE + 0x0498))
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#define CLK_CON_DIV_CLKCMU_FSYS_USB20DRD_REFCLK ((void *)(CMU_MIF_BASE + 0x049C))
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#define CLK_CON_DIV_CLKCMU_PERI_BUS ((void *)(CMU_MIF_BASE + 0x04A0))
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#define CLK_CON_DIV_CLKCMU_PERI_UART_BTWIFIFM ((void *)(CMU_MIF_BASE + 0x04A4))
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#define CLK_CON_DIV_CLKCMU_PERI_UART_DEBUG ((void *)(CMU_MIF_BASE + 0x04A8))
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#define CLK_CON_DIV_CLKCMU_PERI_UART_SENSOR ((void *)(CMU_MIF_BASE + 0x04AC))
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#define CLK_CON_DIV_CLKCMU_PERI_SPI_FRONTFROM ((void *)(CMU_MIF_BASE + 0x04B0))
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#define CLK_CON_DIV_CLKCMU_PERI_SPI_REARFROM ((void *)(CMU_MIF_BASE + 0x04B4))
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#define CLK_CON_DIV_CLKCMU_PERI_SPI_ESE ((void *)(CMU_MIF_BASE + 0x04B8))
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#define CLK_CON_DIV_CLKCMU_PERI_SPI_VOICEPROCESSOR ((void *)(CMU_MIF_BASE + 0x04BC))
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#define CLK_CON_DIV_CLKCMU_PERI_SPI_SENSORHUB ((void *)(CMU_MIF_BASE + 0x04C0))
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#define CLK_CON_DIV_CLKCMU_ISP_SENSOR0 ((void *)(CMU_MIF_BASE + 0x04C4))
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#define CLK_CON_DIV_CLKCMU_ISP_SENSOR1 ((void *)(CMU_MIF_BASE + 0x04C8))
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#define CLK_CON_DIV_CLKCMU_ISP_SENSOR2 ((void *)(CMU_MIF_BASE + 0x04CC))
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#define CLK_STAT_MUX_MEM_PLL ((void *)(CMU_MIF_BASE + 0x0600))
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#define CLK_STAT_MUX_MEDIA_PLL ((void *)(CMU_MIF_BASE + 0x0604))
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#define CLK_STAT_MUX_BUS_PLL ((void *)(CMU_MIF_BASE + 0x0608))
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#define CLK_STAT_MUX_CLK_MIF_PHY_CLK2X ((void *)(CMU_MIF_BASE + 0x0610))
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#define CLK_STAT_MUX_CLK_MIF_PHY_SWITCH ((void *)(CMU_MIF_BASE + 0x0614))
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#define CLK_STAT_MUX_CLK_MIF_BUSD ((void *)(CMU_MIF_BASE + 0x0620))
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#define CLK_STAT_MUX_CLK_MIF_CCI ((void *)(CMU_MIF_BASE + 0x0628))
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#define CLK_STAT_MUX_CLKCMU_ISP_VRA ((void *)(CMU_MIF_BASE + 0x0664))
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#define CLK_STAT_MUX_CLKCMU_ISP_CAM ((void *)(CMU_MIF_BASE + 0x0668))
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#define CLK_STAT_MUX_CLKCMU_ISP_ISP ((void *)(CMU_MIF_BASE + 0x066C))
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#define CLK_STAT_MUX_CLKCMU_DISPAUD_BUS ((void *)(CMU_MIF_BASE + 0x0670))
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#define CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK ((void *)(CMU_MIF_BASE + 0x0674))
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#define CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK ((void *)(CMU_MIF_BASE + 0x0678))
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#define CLK_STAT_MUX_CLKCMU_MFCMSCL_MSCL ((void *)(CMU_MIF_BASE + 0x067C))
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#define CLK_STAT_MUX_CLKCMU_MFCMSCL_MFC ((void *)(CMU_MIF_BASE + 0x0680))
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#define CLK_STAT_MUX_CLKCMU_FSYS_BUS ((void *)(CMU_MIF_BASE + 0x0684))
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#define CLK_STAT_MUX_CLKCMU_FSYS_MMC0 ((void *)(CMU_MIF_BASE + 0x0688))
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#define CLK_STAT_MUX_CLKCMU_FSYS_MMC1 ((void *)(CMU_MIF_BASE + 0x068C))
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#define CLK_STAT_MUX_CLKCMU_FSYS_MMC2 ((void *)(CMU_MIF_BASE + 0x0690))
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#define CLK_STAT_MUX_CLKCMU_FSYS_UFSUNIPRO ((void *)(CMU_MIF_BASE + 0x0694))
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#define CLK_STAT_MUX_CLKCMU_FSYS_UFSUNIPRO_CFG ((void *)(CMU_MIF_BASE + 0x0698))
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#define CLK_STAT_MUX_CLKCMU_FSYS_USB20DRD_REFCLK ((void *)(CMU_MIF_BASE + 0x069C))
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#define CLK_STAT_MUX_CLKCMU_PERI_BUS ((void *)(CMU_MIF_BASE + 0x06A0))
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#define CLK_STAT_MUX_CLKCMU_PERI_UART_BTWIFIFM ((void *)(CMU_MIF_BASE + 0x06A4))
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#define CLK_STAT_MUX_CLKCMU_PERI_UART_DEBUG ((void *)(CMU_MIF_BASE + 0x06A8))
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#define CLK_STAT_MUX_CLKCMU_PERI_UART_SENSOR ((void *)(CMU_MIF_BASE + 0x06AC))
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#define CLK_STAT_MUX_CLKCMU_PERI_SPI_FRONTFROM ((void *)(CMU_MIF_BASE + 0x06B0))
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#define CLK_STAT_MUX_CLKCMU_PERI_SPI_REARFROM ((void *)(CMU_MIF_BASE + 0x06B4))
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#define CLK_STAT_MUX_CLKCMU_PERI_SPI_ESE ((void *)(CMU_MIF_BASE + 0x06B8))
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#define CLK_STAT_MUX_CLKCMU_PERI_SPI_VOICEPROCESSOR ((void *)(CMU_MIF_BASE + 0x06BC))
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#define CLK_STAT_MUX_CLKCMU_PERI_SPI_SENSORHUB ((void *)(CMU_MIF_BASE + 0x06C0))
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#define CLK_STAT_MUX_CLKCMU_ISP_SENSOR0 ((void *)(CMU_MIF_BASE + 0x06C4))
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#define CLK_STAT_MUX_CLKCMU_ISP_SENSOR1 ((void *)(CMU_MIF_BASE + 0x06C8))
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#define CLK_STAT_MUX_CLKCMU_ISP_SENSOR2 ((void *)(CMU_MIF_BASE + 0x06CC))
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#define CLK_ENABLE_CLK_MIF_OSCCLK ((void *)(CMU_MIF_BASE + 0x080C))
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#define CLK_ENABLE_CLK_MIF_PHY_CLK2X ((void *)(CMU_MIF_BASE + 0x0810))
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#define CLK_ENABLE_CLK_MIF_PHY_CLKM ((void *)(CMU_MIF_BASE + 0x0814))
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#define CLK_ENABLE_CLK_MIF_DDRPHY0 ((void *)(CMU_MIF_BASE + 0x0818))
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#define CLK_ENABLE_CLK_MIF_BUSD ((void *)(CMU_MIF_BASE + 0x0820))
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#define CLK_ENABLE_CLK_MIF_APB0 ((void *)(CMU_MIF_BASE + 0x0824))
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#define CLK_ENABLE_CLK_MIF_APB1 ((void *)(CMU_MIF_BASE + 0x0828))
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#define CLK_ENABLE_CLK_MIF_APB_SECURE_DMC0 ((void *)(CMU_MIF_BASE + 0x082C))
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#define CLK_ENABLE_CLK_MIF_APB_SECURE_MODAPIF ((void *)(CMU_MIF_BASE + 0x0830))
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#define CLK_ENABLE_CLK_MIF_CCI ((void *)(CMU_MIF_BASE + 0x0834))
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#define CLK_ENABLE_CLK_MIF_BUSP ((void *)(CMU_MIF_BASE + 0x0838))
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#define CLK_ENABLE_CLK_MIF_BUSP_SECURE_INTMEM ((void *)(CMU_MIF_BASE + 0x083C))
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#define CLK_ENABLE_CLK_MIF_HSI2C ((void *)(CMU_MIF_BASE + 0x0840))
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#define CLK_ENABLE_CLKCMU_CP_MEDIA_PLL ((void *)(CMU_MIF_BASE + 0x0850))
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#define CLK_ENABLE_CLKCMU_CPUCL0_SWITCH ((void *)(CMU_MIF_BASE + 0x0858))
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#define CLK_ENABLE_CLKCMU_CPUCL1_SWITCH ((void *)(CMU_MIF_BASE + 0x085C))
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#define CLK_ENABLE_CLKCMU_G3D_SWITCH ((void *)(CMU_MIF_BASE + 0x0860))
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#define CLK_ENABLE_CLKCMU_ISP_VRA ((void *)(CMU_MIF_BASE + 0x0864))
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#define CLK_ENABLE_CLKCMU_ISP_CAM ((void *)(CMU_MIF_BASE + 0x0868))
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#define CLK_ENABLE_CLKCMU_ISP_ISP ((void *)(CMU_MIF_BASE + 0x086C))
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#define CLK_ENABLE_CLKCMU_DISPAUD_BUS ((void *)(CMU_MIF_BASE + 0x0870))
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#define CLK_ENABLE_CLKCMU_DISPAUD_DECON_INT_VCLK ((void *)(CMU_MIF_BASE + 0x0874))
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#define CLK_ENABLE_CLKCMU_DISPAUD_DECON_INT_ECLK ((void *)(CMU_MIF_BASE + 0x0878))
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#define CLK_ENABLE_CLKCMU_MFCMSCL_MSCL ((void *)(CMU_MIF_BASE + 0x087C))
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#define CLK_ENABLE_CLKCMU_MFCMSCL_MFC ((void *)(CMU_MIF_BASE + 0x0880))
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#define CLK_ENABLE_CLKCMU_FSYS_BUS ((void *)(CMU_MIF_BASE + 0x0884))
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#define CLK_ENABLE_CLKCMU_FSYS_MMC0 ((void *)(CMU_MIF_BASE + 0x0888))
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#define CLK_ENABLE_CLKCMU_FSYS_MMC1 ((void *)(CMU_MIF_BASE + 0x088C))
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#define CLK_ENABLE_CLKCMU_FSYS_MMC2 ((void *)(CMU_MIF_BASE + 0x0890))
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#define CLK_ENABLE_CLKCMU_FSYS_UFSUNIPRO ((void *)(CMU_MIF_BASE + 0x0894))
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#define CLK_ENABLE_CLKCMU_FSYS_UFSUNIPRO_CFG ((void *)(CMU_MIF_BASE + 0x0898))
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#define CLK_ENABLE_CLKCMU_FSYS_USB20DRD_REFCLK ((void *)(CMU_MIF_BASE + 0x089C))
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#define CLK_ENABLE_CLKCMU_PERI_BUS ((void *)(CMU_MIF_BASE + 0x08A0))
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#define CLK_ENABLE_CLKCMU_PERI_UART_BTWIFIFM ((void *)(CMU_MIF_BASE + 0x08A4))
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#define CLK_ENABLE_CLKCMU_PERI_UART_DEBUG ((void *)(CMU_MIF_BASE + 0x08A8))
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#define CLK_ENABLE_CLKCMU_PERI_UART_SENSOR ((void *)(CMU_MIF_BASE + 0x08AC))
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#define CLK_ENABLE_CLKCMU_PERI_SPI_FRONTFROM ((void *)(CMU_MIF_BASE + 0x08B0))
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#define CLK_ENABLE_CLKCMU_PERI_SPI_REARFROM ((void *)(CMU_MIF_BASE + 0x08B4))
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#define CLK_ENABLE_CLKCMU_PERI_SPI_ESE ((void *)(CMU_MIF_BASE + 0x08B8))
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#define CLK_ENABLE_CLKCMU_PERI_SPI_VOICEPROCESSOR ((void *)(CMU_MIF_BASE + 0x08BC))
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#define CLK_ENABLE_CLKCMU_PERI_SPI_SENSORHUB ((void *)(CMU_MIF_BASE + 0x08C0))
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#define CLK_ENABLE_CLKCMU_ISP_SENSOR0 ((void *)(CMU_MIF_BASE + 0x08C4))
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#define CLK_ENABLE_CLKCMU_ISP_SENSOR1 ((void *)(CMU_MIF_BASE + 0x08C8))
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#define CLK_ENABLE_CLKCMU_ISP_SENSOR2 ((void *)(CMU_MIF_BASE + 0x08CC))
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#define SECURE_ENABLE_CLKCMU_FSYS_BUS ((void *)(CMU_MIF_BASE + 0x08D0))
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#define CLKOUT_CMU_MIF ((void *)(CMU_MIF_BASE + 0x0D00))
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#define CLKOUT_CMU_MIF_DIV_STAT ((void *)(CMU_MIF_BASE + 0x0D04))
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#define CMU_MIF_SPARE0 ((void *)(CMU_MIF_BASE + 0x0D08))
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#define CMU_MIF_SPARE1 ((void *)(CMU_MIF_BASE + 0x0D0C))
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#define CLK_ENABLE_PDN_MIF ((void *)(CMU_MIF_BASE + 0x0E00))
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#define MIF_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_MIF_BASE + 0x0F00))
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#define MIF_ROOTCLKEN ((void *)(CMU_MIF_BASE + 0x0F04))
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#define MIF_ROOTCLKEN_ON_GATE ((void *)(CMU_MIF_BASE + 0x0F10))
|
||||
#define DREX_FREQ_CTRL1 ((void *)(CMU_MIF_BASE + 0x1004))
|
||||
#define PAUSE ((void *)(CMU_MIF_BASE + 0x1008))
|
||||
#define DDRPHY_LOCK_CTRL ((void *)(CMU_MIF_BASE + 0x100C))
|
||||
#define ACG_ENABLE ((void *)(CMU_MIF_BASE + 0x1010))
|
||||
#define CP_CTRL_HSI2C_ENABLE ((void *)(CMU_MIF_BASE + 0x1014))
|
||||
#define CP_CTRL_ADCIF_ENABLE ((void *)(CMU_MIF_BASE + 0x1018))
|
||||
#define FAKE_PAUSE ((void *)(CMU_MIF_BASE + 0x1020))
|
||||
#define CG_CTRL_VAL_CLK_MIF_BUSD ((void *)(CMU_MIF_BASE + 0x1800))
|
||||
#define CG_CTRL_VAL_CLK_MIF_APB ((void *)(CMU_MIF_BASE + 0x1804))
|
||||
#define CG_CTRL_VAL_CLK_MIF_CCI ((void *)(CMU_MIF_BASE + 0x1808))
|
||||
#define CG_CTRL_MAN_CLK_MIF_BUSD ((void *)(CMU_MIF_BASE + 0x1900))
|
||||
#define CG_CTRL_MAN_CLK_MIF_APB ((void *)(CMU_MIF_BASE + 0x1904))
|
||||
#define CG_CTRL_MAN_CLK_MIF_CCI ((void *)(CMU_MIF_BASE + 0x1908))
|
||||
#define CG_CTRL_STAT_CLK_MIF_BUSD ((void *)(CMU_MIF_BASE + 0x1A00))
|
||||
#define CG_CTRL_STAT_CLK_MIF_APB ((void *)(CMU_MIF_BASE + 0x1A04))
|
||||
#define CG_CTRL_STAT_CLK_MIF_CCI ((void *)(CMU_MIF_BASE + 0x1A08))
|
||||
#define QCH_CTRL_UID_MIF_D_CCI ((void *)(CMU_MIF_BASE + 0x2000))
|
||||
#define QCH_CTRL_UID_MIF_D_NRT ((void *)(CMU_MIF_BASE + 0x2004))
|
||||
#define QCH_CTRL_UID_MIF_D_RT ((void *)(CMU_MIF_BASE + 0x2008))
|
||||
#define QCH_CTRL_UID_ASYNCM_LH_G3D0_MIF_D_NRT ((void *)(CMU_MIF_BASE + 0x200C))
|
||||
#define QCH_CTRL_UID_ASYNCM_LH_MFCMSCL0_MIF_D_NRT ((void *)(CMU_MIF_BASE + 0x2010))
|
||||
#define QCH_CTRL_UID_ASYNCM_LH_FSYS_MIF_D_NRT ((void *)(CMU_MIF_BASE + 0x2014))
|
||||
#define QCH_CTRL_UID_ASYNCM_LH_ISP_MIF_D_NRT ((void *)(CMU_MIF_BASE + 0x2018))
|
||||
#define QCH_CTRL_UID_ASYNCM_LH_ISP_MIF_D_RT ((void *)(CMU_MIF_BASE + 0x201C))
|
||||
#define QCH_CTRL_UID_ASYNCM_LH_DISPAUD_MIF_D_RT ((void *)(CMU_MIF_BASE + 0x2020))
|
||||
|
||||
#define CPUCL0_PLL_LOCK ((void *)(CMU_CPUCL0_BASE + 0x0000))
|
||||
#define CPUCL0_PLL_CON0 ((void *)(CMU_CPUCL0_BASE + 0x0100))
|
||||
#define CPUCL0_PLL_CON1 ((void *)(CMU_CPUCL0_BASE + 0x0104))
|
||||
#define CLK_CON_MUX_CPUCL0_PLL ((void *)(CMU_CPUCL0_BASE + 0x0200))
|
||||
#define CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH_USER ((void *)(CMU_CPUCL0_BASE + 0x0204))
|
||||
#define CLK_CON_MUX_CLK_CPUCL0 ((void *)(CMU_CPUCL0_BASE + 0x0208))
|
||||
#define CLK_CON_DIV_CLK_CPUCL0_1 ((void *)(CMU_CPUCL0_BASE + 0x0400))
|
||||
#define CLK_CON_DIV_CLK_CPUCL0_2 ((void *)(CMU_CPUCL0_BASE + 0x0404))
|
||||
#define CLK_CON_DIV_CLK_CPUCL0_ACLK ((void *)(CMU_CPUCL0_BASE + 0x0408))
|
||||
#define CLK_CON_DIV_CLK_CPUCL0_PCLK ((void *)(CMU_CPUCL0_BASE + 0x040C))
|
||||
#define CLK_CON_DIV_CLK_CPUCL0_ATCLK ((void *)(CMU_CPUCL0_BASE + 0x0410))
|
||||
#define CLK_CON_DIV_CLK_CPUCL0_PCLKDBG ((void *)(CMU_CPUCL0_BASE + 0x0414))
|
||||
#define CLK_CON_DIV_CLK_CPUCL0_CNTCLK ((void *)(CMU_CPUCL0_BASE + 0x0418))
|
||||
#define CLK_CON_DIV_CLK_CPUCL0_RUN_MONITOR ((void *)(CMU_CPUCL0_BASE + 0x041C))
|
||||
#define CLK_CON_DIV_CLK_CPUCL0_HPM ((void *)(CMU_CPUCL0_BASE + 0x0420))
|
||||
#define CLK_CON_DIV_CLK_CPUCL0_PLL ((void *)(CMU_CPUCL0_BASE + 0x0424))
|
||||
#define CLK_STAT_MUX_CPUCL0_PLL ((void *)(CMU_CPUCL0_BASE + 0x0600))
|
||||
#define CLK_STAT_MUX_CLKCMU_CPUCL0_SWITCH_USER ((void *)(CMU_CPUCL0_BASE + 0x0604))
|
||||
#define CLK_STAT_MUX_CLK_CPUCL0 ((void *)(CMU_CPUCL0_BASE + 0x0608))
|
||||
#define CLK_ENABLE_CLK_CPUCL0_OSCCLK ((void *)(CMU_CPUCL0_BASE + 0x0800))
|
||||
#define CLK_ENABLE_CLK_CPUCL0_ACLK ((void *)(CMU_CPUCL0_BASE + 0x0808))
|
||||
#define CLK_ENABLE_CLK_CPUCL0_PCLK ((void *)(CMU_CPUCL0_BASE + 0x080C))
|
||||
#define CLK_ENABLE_CLK_CPUCL0_ATCLK ((void *)(CMU_CPUCL0_BASE + 0x0810))
|
||||
#define CLK_ENABLE_CLK_CPUCL0_PCLKDBG ((void *)(CMU_CPUCL0_BASE + 0x0814))
|
||||
#define CLK_ENABLE_CLK_CPUCL0_HPM ((void *)(CMU_CPUCL0_BASE + 0x0820))
|
||||
#define CLKOUT_CMU_CPUCL0 ((void *)(CMU_CPUCL0_BASE + 0x0D00))
|
||||
#define CLKOUT_CMU_CPUCL0_DIV_STAT ((void *)(CMU_CPUCL0_BASE + 0x0D04))
|
||||
#define CMU_CPUCL0_SPARE0 ((void *)(CMU_CPUCL0_BASE + 0x0D08))
|
||||
#define CMU_CPUCL0_SPARE1 ((void *)(CMU_CPUCL0_BASE + 0x0D0C))
|
||||
#define CLK_ENABLE_PDN_CPUCL0 ((void *)(CMU_CPUCL0_BASE + 0x0E00))
|
||||
#define CPUCL0_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_CPUCL0_BASE + 0x0F00))
|
||||
#define CPUCL0_ARMCLK_STOPCTRL ((void *)(CMU_CPUCL0_BASE + 0x1000))
|
||||
#define CPUCL0_PWR_CTRL ((void *)(CMU_CPUCL0_BASE + 0x1020))
|
||||
#define CPUCL0_PWR_CTRL2 ((void *)(CMU_CPUCL0_BASE + 0x1024))
|
||||
#define CPUCL0_PWR_CTRL3 ((void *)(CMU_CPUCL0_BASE + 0x1028))
|
||||
#define CPUCL0_INTR_SPREAD_ENABLE ((void *)(CMU_CPUCL0_BASE + 0x1080))
|
||||
#define CPUCL0_INTR_SPREAD_USE_STANDBYWFI ((void *)(CMU_CPUCL0_BASE + 0x1084))
|
||||
#define CPUCL0_INTR_SPREAD_BLOCKING_DURATION ((void *)(CMU_CPUCL0_BASE + 0x1088))
|
||||
|
||||
#define CPUCL1_PLL_LOCK ((void *)(CMU_CPUCL1_BASE + 0x0000))
|
||||
#define CPUCL1_PLL_CON0 ((void *)(CMU_CPUCL1_BASE + 0x0100))
|
||||
#define CPUCL1_PLL_CON1 ((void *)(CMU_CPUCL1_BASE + 0x0104))
|
||||
#define CLK_CON_MUX_CPUCL1_PLL ((void *)(CMU_CPUCL1_BASE + 0x0200))
|
||||
#define CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH_USER ((void *)(CMU_CPUCL1_BASE + 0x0204))
|
||||
#define CLK_CON_MUX_CLK_CPUCL1 ((void *)(CMU_CPUCL1_BASE + 0x0208))
|
||||
#define CLK_CON_DIV_CLK_CPUCL1_1 ((void *)(CMU_CPUCL1_BASE + 0x0400))
|
||||
#define CLK_CON_DIV_CLK_CPUCL1_2 ((void *)(CMU_CPUCL1_BASE + 0x0404))
|
||||
#define CLK_CON_DIV_CLK_CPUCL1_ACLK ((void *)(CMU_CPUCL1_BASE + 0x0408))
|
||||
#define CLK_CON_DIV_CLK_CPUCL1_PCLK ((void *)(CMU_CPUCL1_BASE + 0x040C))
|
||||
#define CLK_CON_DIV_CLK_CPUCL1_ATCLK ((void *)(CMU_CPUCL1_BASE + 0x0410))
|
||||
#define CLK_CON_DIV_CLK_CPUCL1_PCLKDBG ((void *)(CMU_CPUCL1_BASE + 0x0414))
|
||||
#define CLK_CON_DIV_CLK_CPUCL1_CNTCLK ((void *)(CMU_CPUCL1_BASE + 0x0418))
|
||||
#define CLK_CON_DIV_CLK_CPUCL1_RUN_MONITOR ((void *)(CMU_CPUCL1_BASE + 0x041C))
|
||||
#define CLK_CON_DIV_CLK_CPUCL1_HPM ((void *)(CMU_CPUCL1_BASE + 0x0420))
|
||||
#define CLK_CON_DIV_CLK_CPUCL1_PLL ((void *)(CMU_CPUCL1_BASE + 0x0424))
|
||||
#define CLK_STAT_MUX_CPUCL1_PLL ((void *)(CMU_CPUCL1_BASE + 0x0600))
|
||||
#define CLK_STAT_MUX_CLKCMU_CPUCL1_SWITCH_USER ((void *)(CMU_CPUCL1_BASE + 0x0604))
|
||||
#define CLK_STAT_MUX_CLK_CPUCL1 ((void *)(CMU_CPUCL1_BASE + 0x0608))
|
||||
#define CLK_ENABLE_CLK_CPUCL1_OSCCLK ((void *)(CMU_CPUCL1_BASE + 0x0800))
|
||||
#define CLK_ENABLE_CLK_CPUCL1_ACLK ((void *)(CMU_CPUCL1_BASE + 0x0808))
|
||||
#define CLK_ENABLE_CLK_CPUCL1_PCLK ((void *)(CMU_CPUCL1_BASE + 0x080C))
|
||||
#define CLK_ENABLE_CLK_CPUCL1_PCLKDBG ((void *)(CMU_CPUCL1_BASE + 0x0814))
|
||||
#define CLK_ENABLE_CLK_CPUCL1_HPM ((void *)(CMU_CPUCL1_BASE + 0x0820))
|
||||
#define CLKOUT_CMU_CPUCL1 ((void *)(CMU_CPUCL1_BASE + 0x0D00))
|
||||
#define CLKOUT_CMU_CPUCL1_DIV_STAT ((void *)(CMU_CPUCL1_BASE + 0x0D04))
|
||||
#define CMU_CPUCL1_SPARE0 ((void *)(CMU_CPUCL1_BASE + 0x0D08))
|
||||
#define CMU_CPUCL1_SPARE1 ((void *)(CMU_CPUCL1_BASE + 0x0D0C))
|
||||
#define CLK_ENABLE_PDN_CPUCL1 ((void *)(CMU_CPUCL1_BASE + 0x0E00))
|
||||
#define CPUCL1_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_CPUCL1_BASE + 0x0F00))
|
||||
#define CPUCL1_ARMCLK_STOPCTRL ((void *)(CMU_CPUCL1_BASE + 0x1000))
|
||||
#define CPUCL1_PWR_CTRL ((void *)(CMU_CPUCL1_BASE + 0x1020))
|
||||
#define CPUCL1_PWR_CTRL2 ((void *)(CMU_CPUCL1_BASE + 0x1024))
|
||||
#define CPUCL1_PWR_CTRL3 ((void *)(CMU_CPUCL1_BASE + 0x1028))
|
||||
#define CPUCL1_INTR_SPREAD_ENABLE ((void *)(CMU_CPUCL1_BASE + 0x1080))
|
||||
#define CPUCL1_INTR_SPREAD_USE_STANDBYWFI ((void *)(CMU_CPUCL1_BASE + 0x1084))
|
||||
#define CPUCL1_INTR_SPREAD_BLOCKING_DURATION ((void *)(CMU_CPUCL1_BASE + 0x1088))
|
||||
|
||||
#define G3D_PLL_LOCK ((void *)(CMU_G3D_BASE + 0x0000))
|
||||
#define G3D_PLL_CON0 ((void *)(CMU_G3D_BASE + 0x0100))
|
||||
#define G3D_PLL_CON1 ((void *)(CMU_G3D_BASE + 0x0104))
|
||||
#define CLK_CON_MUX_G3D_PLL ((void *)(CMU_G3D_BASE + 0x0200))
|
||||
#define CLK_CON_MUX_CLKCMU_G3D_SWITCH_USER ((void *)(CMU_G3D_BASE + 0x0204))
|
||||
#define CLK_CON_MUX_CLK_G3D ((void *)(CMU_G3D_BASE + 0x0208))
|
||||
#define CLK_CON_DIV_CLK_G3D_BUS ((void *)(CMU_G3D_BASE + 0x0400))
|
||||
#define CLK_CON_DIV_CLK_G3D_APB ((void *)(CMU_G3D_BASE + 0x0404))
|
||||
#define CLK_STAT_MUX_G3D_PLL ((void *)(CMU_G3D_BASE + 0x0600))
|
||||
#define CLK_STAT_MUX_CLKCMU_G3D_SWITCH_USER ((void *)(CMU_G3D_BASE + 0x0604))
|
||||
#define CLK_STAT_MUX_CLK_G3D ((void *)(CMU_G3D_BASE + 0x0608))
|
||||
#define CLK_ENABLE_CLK_G3D_OSCCLK ((void *)(CMU_G3D_BASE + 0x0800))
|
||||
#define CLK_ENABLE_CLK_G3D_BUS ((void *)(CMU_G3D_BASE + 0x0804))
|
||||
#define CLK_ENABLE_CLK_G3D_APB ((void *)(CMU_G3D_BASE + 0x0808))
|
||||
#define CLK_ENABLE_CLK_G3D_BUS_SECURE_CFW_G3D ((void *)(CMU_G3D_BASE + 0x0810))
|
||||
#define CLK_ENABLE_CLK_G3D_APB_SECURE_CFW_G3D ((void *)(CMU_G3D_BASE + 0x0814))
|
||||
#define CLKOUT_CMU_G3D ((void *)(CMU_G3D_BASE + 0x0D00))
|
||||
#define CLKOUT_CMU_G3D_DIV_STAT ((void *)(CMU_G3D_BASE + 0x0D04))
|
||||
#define CMU_G3D_SPARE0 ((void *)(CMU_G3D_BASE + 0x0D08))
|
||||
#define CMU_G3D_SPARE1 ((void *)(CMU_G3D_BASE + 0x0D0C))
|
||||
#define CLK_ENABLE_PDN_G3D ((void *)(CMU_G3D_BASE + 0x0E00))
|
||||
#define G3D_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_G3D_BASE + 0x0F00))
|
||||
#define CLK_STOPCTRL ((void *)(CMU_G3D_BASE + 0x1000))
|
||||
|
||||
#define CLK_ENABLE_CLK_PERI_OSCCLK ((void *)(CMU_PERI_BASE + 0x0800))
|
||||
#define CLK_ENABLE_CLK_PERI_OSCCLK_SECURE_CHIPID ((void *)(CMU_PERI_BASE + 0x0804))
|
||||
#define CLK_ENABLE_CLK_PERI_BUS0 ((void *)(CMU_PERI_BASE + 0x0810))
|
||||
#define CLK_ENABLE_CLK_PERI_BUS1 ((void *)(CMU_PERI_BASE + 0x0814))
|
||||
#define CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC ((void *)(CMU_PERI_BASE + 0x0818))
|
||||
#define CLK_ENABLE_CLK_PERI_BUS_SECURE_CHIPID ((void *)(CMU_PERI_BASE + 0x081C))
|
||||
#define CLK_ENABLE_CLK_PERI_BUS_SECURE_OTP_CON_TOP ((void *)(CMU_PERI_BASE + 0x0820))
|
||||
#define CLK_ENABLE_CLK_PERI_BUS_SECURE_RTC_ALIVE ((void *)(CMU_PERI_BASE + 0x0824))
|
||||
#define CLK_ENABLE_CLK_PERI_BUS_SECURE_RTC_TOP ((void *)(CMU_PERI_BASE + 0x0828))
|
||||
#define CLK_ENABLE_CLK_PERI_UART_BTWIFIFM ((void *)(CMU_PERI_BASE + 0x0830))
|
||||
#define CLK_ENABLE_CLK_PERI_UART_DEBUG ((void *)(CMU_PERI_BASE + 0x0834))
|
||||
#define CLK_ENABLE_CLK_PERI_UART_SENSOR ((void *)(CMU_PERI_BASE + 0x0838))
|
||||
#define CLK_ENABLE_CLK_PERI_SPI_FRONTFROM ((void *)(CMU_PERI_BASE + 0x083C))
|
||||
#define CLK_ENABLE_CLK_PERI_SPI_REARFROM ((void *)(CMU_PERI_BASE + 0x0840))
|
||||
#define CLK_ENABLE_CLK_PERI_SPI_ESE ((void *)(CMU_PERI_BASE + 0x0844))
|
||||
#define CLK_ENABLE_CLK_PERI_SPI_VOICEPROCESSOR ((void *)(CMU_PERI_BASE + 0x0848))
|
||||
#define CLK_ENABLE_CLK_PERI_SPI_SENSORHUB ((void *)(CMU_PERI_BASE + 0x084C))
|
||||
#define CLKOUT_CMU_PERI ((void *)(CMU_PERI_BASE + 0x0D00))
|
||||
#define CLKOUT_CMU_PERI_DIV_STAT ((void *)(CMU_PERI_BASE + 0x0D04))
|
||||
#define CMU_PERI_SPARE0 ((void *)(CMU_PERI_BASE + 0x0D08))
|
||||
#define CMU_PERI_SPARE1 ((void *)(CMU_PERI_BASE + 0x0D0C))
|
||||
#define CLK_ENABLE_PDN_PERI ((void *)(CMU_PERI_BASE + 0x0E00))
|
||||
|
||||
#define USB_PLL_LOCK ((void *)(CMU_FSYS_BASE + 0x0000))
|
||||
#define USB_PLL_CON0 ((void *)(CMU_FSYS_BASE + 0x0100))
|
||||
#define USB_PLL_CON1 ((void *)(CMU_FSYS_BASE + 0x0104))
|
||||
#define CLK_CON_MUX_USB_PLL ((void *)(CMU_FSYS_BASE + 0x0200))
|
||||
#define CLK_CON_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER ((void *)(CMU_FSYS_BASE + 0x0230))
|
||||
#define CLK_CON_MUX_CLKPHY_FSYS_UFS_TX0_SYMBOL_USER ((void *)(CMU_FSYS_BASE + 0x0234))
|
||||
#define CLK_CON_MUX_CLKPHY_FSYS_UFS_RX0_SYMBOL_USER ((void *)(CMU_FSYS_BASE + 0x0238))
|
||||
#define CLK_STAT_MUX_USB_PLL ((void *)(CMU_FSYS_BASE + 0x0600))
|
||||
#define CLK_STAT_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER ((void *)(CMU_FSYS_BASE + 0x0630))
|
||||
#define CLK_STAT_MUX_CLKPHY_FSYS_UFS_TX0_SYMBOL_USER ((void *)(CMU_FSYS_BASE + 0x0634))
|
||||
#define CLK_STAT_MUX_CLKPHY_FSYS_UFS_RX0_SYMBOL_USER ((void *)(CMU_FSYS_BASE + 0x0638))
|
||||
#define CLK_ENABLE_CLK_FSYS_OSCCLK ((void *)(CMU_FSYS_BASE + 0x0800))
|
||||
#define CLK_ENABLE_CLK_FSYS_BUS ((void *)(CMU_FSYS_BASE + 0x0804))
|
||||
#define CLK_ENABLE_CLK_FSYS_SECURE_RTIC ((void *)(CMU_FSYS_BASE + 0x0808))
|
||||
#define CLK_ENABLE_CLK_FSYS_SECURE_SSS ((void *)(CMU_FSYS_BASE + 0x080C))
|
||||
#define CLK_ENABLE_CLK_FSYS_SECURE_PDMA1 ((void *)(CMU_FSYS_BASE + 0x0810))
|
||||
#define CLK_ENABLE_CLK_FSYS_MMC0 ((void *)(CMU_FSYS_BASE + 0x0814))
|
||||
#define CLK_ENABLE_CLK_FSYS_MMC1 ((void *)(CMU_FSYS_BASE + 0x0818))
|
||||
#define CLK_ENABLE_CLK_FSYS_MMC2 ((void *)(CMU_FSYS_BASE + 0x081C))
|
||||
#define CLK_ENABLE_CLK_FSYS_UFSUNIPRO ((void *)(CMU_FSYS_BASE + 0x0820))
|
||||
#define CLK_ENABLE_CLK_FSYS_UFSUNIPRO_CFG ((void *)(CMU_FSYS_BASE + 0x0824))
|
||||
#define CLK_ENABLE_CLK_FSYS_USB20DRD_REFCLK ((void *)(CMU_FSYS_BASE + 0x0828))
|
||||
#define CLK_ENABLE_CLKPHY_FSYS_USB20DRD_PHYCLOCK ((void *)(CMU_FSYS_BASE + 0x0830))
|
||||
#define CLK_ENABLE_CLKPHY_FSYS_UFS_TX0_SYMBOL ((void *)(CMU_FSYS_BASE + 0x0834))
|
||||
#define CLK_ENABLE_CLKPHY_FSYS_UFS_RX0_SYMBOL ((void *)(CMU_FSYS_BASE + 0x0838))
|
||||
#define SECURE_ENABLE_BUSD0_FSYS ((void *)(CMU_FSYS_BASE + 0x08D0))
|
||||
#define CLKOUT_CMU_FSYS ((void *)(CMU_FSYS_BASE + 0x0D00))
|
||||
#define CLKOUT_CMU_FSYS_DIV_STAT ((void *)(CMU_FSYS_BASE + 0x0D04))
|
||||
#define CMU_FSYS_SPARE0 ((void *)(CMU_FSYS_BASE + 0x0D08))
|
||||
#define CMU_FSYS_SPARE1 ((void *)(CMU_FSYS_BASE + 0x0D0C))
|
||||
#define CLK_ENABLE_PDN_FSYS ((void *)(CMU_FSYS_BASE + 0x0E00))
|
||||
#define FSYS_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_FSYS_BASE + 0x0F00))
|
||||
|
||||
#define CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL_USER ((void *)(CMU_MFCMSCL_BASE + 0x0200))
|
||||
#define CLK_CON_MUX_CLKCMU_MFCMSCL_MFC_USER ((void *)(CMU_MFCMSCL_BASE + 0x0204))
|
||||
#define CLK_CON_DIV_CLK_MFCMSCL_APB ((void *)(CMU_MFCMSCL_BASE + 0x0400))
|
||||
#define CLK_STAT_MUX_CLKCMU_MFCMSCL_MSCL_USER ((void *)(CMU_MFCMSCL_BASE + 0x0600))
|
||||
#define CLK_STAT_MUX_CLKCMU_MFCMSCL_MFC_USER ((void *)(CMU_MFCMSCL_BASE + 0x0604))
|
||||
#define CLK_ENABLE_CLK_MFCMSCL_OSCCLK ((void *)(CMU_MFCMSCL_BASE + 0x0800))
|
||||
#define CLK_ENABLE_CLK_MFCMSCL_MSCL ((void *)(CMU_MFCMSCL_BASE + 0x0804))
|
||||
#define CLK_ENABLE_CLK_MFCMSCL_MFC ((void *)(CMU_MFCMSCL_BASE + 0x0808))
|
||||
#define CLK_ENABLE_CLK_MFCMSCL_APB ((void *)(CMU_MFCMSCL_BASE + 0x080C))
|
||||
#define CLK_ENABLE_CLK_MFCMSCL_SECURE_CFW_MSCL ((void *)(CMU_MFCMSCL_BASE + 0x0810))
|
||||
#define CLKOUT_CMU_MFCMSCL ((void *)(CMU_MFCMSCL_BASE + 0x0D00))
|
||||
#define CLKOUT_CMU_MFCMSCL_DIV_STAT ((void *)(CMU_MFCMSCL_BASE + 0x0D04))
|
||||
#define CMU_MFCMSCL_SPARE0 ((void *)(CMU_MFCMSCL_BASE + 0x0D08))
|
||||
#define CMU_MFCMSCL_SPARE1 ((void *)(CMU_MFCMSCL_BASE + 0x0D0C))
|
||||
#define CLK_ENABLE_PDN_MFCMSCL ((void *)(CMU_MFCMSCL_BASE + 0x0E00))
|
||||
#define MFCMSCL_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_MFCMSCL_BASE + 0x0F00))
|
||||
|
||||
#define DISP_PLL_LOCK ((void *)(CMU_DISPAUD_BASE + 0x0000))
|
||||
#define AUD_PLL_LOCK ((void *)(CMU_DISPAUD_BASE + 0x00C0))
|
||||
#define DISP_PLL_CON0 ((void *)(CMU_DISPAUD_BASE + 0x0100))
|
||||
#define DISP_PLL_CON1 ((void *)(CMU_DISPAUD_BASE + 0x0104))
|
||||
#define AUD_PLL_CON0 ((void *)(CMU_DISPAUD_BASE + 0x01C0))
|
||||
#define AUD_PLL_CON1 ((void *)(CMU_DISPAUD_BASE + 0x01C4))
|
||||
#define AUD_PLL_CON2 ((void *)(CMU_DISPAUD_BASE + 0x01C8))
|
||||
#define CLK_CON_MUX_DISP_PLL ((void *)(CMU_DISPAUD_BASE + 0x0200))
|
||||
#define CLK_CON_MUX_AUD_PLL ((void *)(CMU_DISPAUD_BASE + 0x0204))
|
||||
#define CLK_CON_MUX_CLKCMU_DISPAUD_BUS_USER ((void *)(CMU_DISPAUD_BASE + 0x0210))
|
||||
#define CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER ((void *)(CMU_DISPAUD_BASE + 0x0214))
|
||||
#define CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER ((void *)(CMU_DISPAUD_BASE + 0x0218))
|
||||
#define CLK_CON_MUX_CLK_DISPAUD_DECON_INT_VCLK ((void *)(CMU_DISPAUD_BASE + 0x021C))
|
||||
#define CLK_CON_MUX_CLK_DISPAUD_DECON_INT_ECLK ((void *)(CMU_DISPAUD_BASE + 0x0220))
|
||||
#define CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER ((void *)(CMU_DISPAUD_BASE + 0x0224))
|
||||
#define CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER ((void *)(CMU_DISPAUD_BASE + 0x0228))
|
||||
#define CLK_CON_MUX_CLK_DISPAUD_MI2S ((void *)(CMU_DISPAUD_BASE + 0x022C))
|
||||
#define CLK_CON_DIV_CLK_DISPAUD_APB ((void *)(CMU_DISPAUD_BASE + 0x0400))
|
||||
#define CLK_CON_DIV_CLK_DISPAUD_DECON_INT_VCLK ((void *)(CMU_DISPAUD_BASE + 0x0404))
|
||||
#define CLK_CON_DIV_CLK_DISPAUD_DECON_INT_ECLK ((void *)(CMU_DISPAUD_BASE + 0x0408))
|
||||
#define CLK_CON_DIV_CLK_DISPAUD_MI2S ((void *)(CMU_DISPAUD_BASE + 0x040C))
|
||||
#define CLK_CON_DIV_CLK_DISPAUD_MIXER ((void *)(CMU_DISPAUD_BASE + 0x0410))
|
||||
#define CLK_STAT_MUX_DISP_PLL ((void *)(CMU_DISPAUD_BASE + 0x0600))
|
||||
#define CLK_STAT_MUX_AUD_PLL ((void *)(CMU_DISPAUD_BASE + 0x0604))
|
||||
#define CLK_STAT_MUX_CLKCMU_DISPAUD_BUS_USER ((void *)(CMU_DISPAUD_BASE + 0x0610))
|
||||
#define CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER ((void *)(CMU_DISPAUD_BASE + 0x0614))
|
||||
#define CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER ((void *)(CMU_DISPAUD_BASE + 0x0618))
|
||||
#define CLK_STAT_MUX_CLK_DISPAUD_DECON_INT_VCLK ((void *)(CMU_DISPAUD_BASE + 0x061C))
|
||||
#define CLK_STAT_MUX_CLK_DISPAUD_DECON_INT_ECLK ((void *)(CMU_DISPAUD_BASE + 0x0620))
|
||||
#define CLK_STAT_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER ((void *)(CMU_DISPAUD_BASE + 0x0624))
|
||||
#define CLK_STAT_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER ((void *)(CMU_DISPAUD_BASE + 0x0628))
|
||||
#define CLK_ENABLE_CLK_DISPAUD_OSCCLK ((void *)(CMU_DISPAUD_BASE + 0x0800))
|
||||
#define CLK_ENABLE_CLK_DISPAUD_BUS ((void *)(CMU_DISPAUD_BASE + 0x0810))
|
||||
#define CLK_ENABLE_CLK_DISPAUD_APB ((void *)(CMU_DISPAUD_BASE + 0x0814))
|
||||
#define CLK_ENABLE_CLK_DISPAUD_SECURE_CFW_DISP ((void *)(CMU_DISPAUD_BASE + 0x0818))
|
||||
#define CLK_ENABLE_CLK_DISPAUD_DECON_INT_VCLK ((void *)(CMU_DISPAUD_BASE + 0x081C))
|
||||
#define CLK_ENABLE_CLK_DISPAUD_DECON_INT_ECLK ((void *)(CMU_DISPAUD_BASE + 0x0820))
|
||||
#define CLK_ENABLE_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS ((void *)(CMU_DISPAUD_BASE + 0x0824))
|
||||
#define CLK_ENABLE_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0 ((void *)(CMU_DISPAUD_BASE + 0x0828))
|
||||
#define CLK_ENABLE_CLK_DISPAUD_MI2S ((void *)(CMU_DISPAUD_BASE + 0x082C))
|
||||
#define CLK_ENABLE_CLK_DISPAUD_MIXER ((void *)(CMU_DISPAUD_BASE + 0x0830))
|
||||
#define CLK_ENABLE_CLKIO_DISPAUD_MIXER_SCLK_AP ((void *)(CMU_DISPAUD_BASE + 0x0834))
|
||||
#define CLK_ENABLE_CLKIO_DISPAUD_MIXER_BCLK_BT ((void *)(CMU_DISPAUD_BASE + 0x0838))
|
||||
#define CLK_ENABLE_CLKIO_DISPAUD_MIXER_BCLK_CP ((void *)(CMU_DISPAUD_BASE + 0x083C))
|
||||
#define CLK_ENABLE_CLKIO_DISPAUD_MIXER_BCLK_FM ((void *)(CMU_DISPAUD_BASE + 0x0840))
|
||||
#define CLKOUT_CMU_DISPAUD ((void *)(CMU_DISPAUD_BASE + 0x0D00))
|
||||
#define CLKOUT_CMU_DISPAUD_DIV_STAT ((void *)(CMU_DISPAUD_BASE + 0x0D04))
|
||||
#define CMU_DISPAUD_SPARE0 ((void *)(CMU_DISPAUD_BASE + 0x0D08))
|
||||
#define CMU_DISPAUD_SPARE1 ((void *)(CMU_DISPAUD_BASE + 0x0D0C))
|
||||
#define CLK_ENABLE_PDN_DISPAUD ((void *)(CMU_DISPAUD_BASE + 0x0E00))
|
||||
#define DISPAUD_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_DISPAUD_BASE + 0x0F00))
|
||||
|
||||
#define ISP_PLL_LOCK ((void *)(CMU_ISP_BASE + 0x0000))
|
||||
#define ISP_PLL_CON0 ((void *)(CMU_ISP_BASE + 0x0100))
|
||||
#define ISP_PLL_CON1 ((void *)(CMU_ISP_BASE + 0x0104))
|
||||
#define CLK_CON_MUX_ISP_PLL ((void *)(CMU_ISP_BASE + 0x0200))
|
||||
#define CLK_CON_MUX_CLKCMU_ISP_VRA_USER ((void *)(CMU_ISP_BASE + 0x0210))
|
||||
#define CLK_CON_MUX_CLKCMU_ISP_CAM_USER ((void *)(CMU_ISP_BASE + 0x0214))
|
||||
#define CLK_CON_MUX_CLKCMU_ISP_ISP_USER ((void *)(CMU_ISP_BASE + 0x0218))
|
||||
#define CLK_CON_MUX_CLK_ISP_VRA ((void *)(CMU_ISP_BASE + 0x0220))
|
||||
#define CLK_CON_MUX_CLK_ISP_CAM ((void *)(CMU_ISP_BASE + 0x0224))
|
||||
#define CLK_CON_MUX_CLK_ISP_ISP ((void *)(CMU_ISP_BASE + 0x0228))
|
||||
#define CLK_CON_MUX_CLK_ISP_ISPD ((void *)(CMU_ISP_BASE + 0x022C))
|
||||
#define CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER ((void *)(CMU_ISP_BASE + 0x0230))
|
||||
#define CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER ((void *)(CMU_ISP_BASE + 0x0234))
|
||||
#define CLK_CON_DIV_CLK_ISP_APB ((void *)(CMU_ISP_BASE + 0x0400))
|
||||
#define CLK_CON_DIV_CLK_ISP_CAM_HALF ((void *)(CMU_ISP_BASE + 0x0404))
|
||||
#define CLK_STAT_MUX_ISP_PLL ((void *)(CMU_ISP_BASE + 0x0600))
|
||||
#define CLK_STAT_MUX_CLKCMU_ISP_VRA_USER ((void *)(CMU_ISP_BASE + 0x0610))
|
||||
#define CLK_STAT_MUX_CLKCMU_ISP_CAM_USER ((void *)(CMU_ISP_BASE + 0x0614))
|
||||
#define CLK_STAT_MUX_CLKCMU_ISP_ISP_USER ((void *)(CMU_ISP_BASE + 0x0618))
|
||||
#define CLK_STAT_MUX_CLK_ISP_VRA ((void *)(CMU_ISP_BASE + 0x0620))
|
||||
#define CLK_STAT_MUX_CLK_ISP_ISP ((void *)(CMU_ISP_BASE + 0x0624))
|
||||
#define CLK_STAT_MUX_CLK_ISP_CAM ((void *)(CMU_ISP_BASE + 0x0628))
|
||||
#define CLK_STAT_MUX_CLK_ISP_ISPD ((void *)(CMU_ISP_BASE + 0x062C))
|
||||
#define CLK_STAT_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER ((void *)(CMU_ISP_BASE + 0x0630))
|
||||
#define CLK_STAT_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER ((void *)(CMU_ISP_BASE + 0x0634))
|
||||
#define CLK_ENABLE_CLK_ISP_OSCCLK ((void *)(CMU_ISP_BASE + 0x0800))
|
||||
#define CLK_ENABLE_CLK_ISP_VRA ((void *)(CMU_ISP_BASE + 0x0810))
|
||||
#define CLK_ENABLE_CLK_ISP_APB ((void *)(CMU_ISP_BASE + 0x0814))
|
||||
#define CLK_ENABLE_CLK_ISP_ISPD ((void *)(CMU_ISP_BASE + 0x0818))
|
||||
#define CLK_ENABLE_CLK_ISP_CAM ((void *)(CMU_ISP_BASE + 0x081C))
|
||||
#define CLK_ENABLE_CLK_ISP_CAM_HALF ((void *)(CMU_ISP_BASE + 0x0820))
|
||||
#define CLK_ENABLE_CLK_ISP_ISP ((void *)(CMU_ISP_BASE + 0x0824))
|
||||
#define CLK_ENABLE_CLKPHY_ISP_S_RXBYTECLKHS0_S4 ((void *)(CMU_ISP_BASE + 0x0828))
|
||||
#define CLK_ENABLE_CLKPHY_ISP_S_RXBYTECLKHS0_S4S ((void *)(CMU_ISP_BASE + 0x082C))
|
||||
#define CLKOUT_CMU_ISP ((void *)(CMU_ISP_BASE + 0x0D00))
|
||||
#define CLKOUT_CMU_ISP_DIV_STAT ((void *)(CMU_ISP_BASE + 0x0D04))
|
||||
#define CMU_ISP_SPARE0 ((void *)(CMU_ISP_BASE + 0x0D08))
|
||||
#define CMU_ISP_SPARE1 ((void *)(CMU_ISP_BASE + 0x0D0C))
|
||||
#define CLK_ENABLE_PDN_ISP ((void *)(CMU_ISP_BASE + 0x0E00))
|
||||
#define ISP_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_ISP_BASE + 0x0F00))
|
||||
|
||||
#define CPUCL0_EMA_CON ((void *)(SYSREG_CPUCL0_BASE + 0x0330))
|
||||
#define CPUCL1_EMA_CON ((void *)(SYSREG_CPUCL1_BASE + 0x0330))
|
||||
#define G3D_EMA_RA1_HS_CON ((void *)(SYSREG_G3D_BASE + 0x0304))
|
||||
#define G3D_EMA_RF1_HS_CON ((void *)(SYSREG_G3D_BASE + 0x0314))
|
||||
#define G3D_EMA_RF2_HS_CON ((void *)(SYSREG_G3D_BASE + 0x031C))
|
||||
|
||||
#endif
|
||||
564
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-dfs.c
Normal file
564
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-dfs.c
Normal file
|
|
@ -0,0 +1,564 @@
|
|||
#include "../pwrcal.h"
|
||||
#include "../pwrcal-env.h"
|
||||
#include "../pwrcal-clk.h"
|
||||
#include "../pwrcal-pmu.h"
|
||||
#include "../pwrcal-dfs.h"
|
||||
#include "../pwrcal-rae.h"
|
||||
#include "../pwrcal-asv.h"
|
||||
#include "S5E7870-cmusfr.h"
|
||||
#include "S5E7870-pmusfr.h"
|
||||
#include "S5E7870-cmu.h"
|
||||
#include "S5E7870-vclk-internal.h"
|
||||
|
||||
#ifdef PWRCAL_TARGET_LINUX
|
||||
#include <soc/samsung/ect_parser.h>
|
||||
#else
|
||||
#include <mach/ect_parser.h>
|
||||
#endif
|
||||
|
||||
static struct dfs_switch dfscpucl0_switches[] = {
|
||||
{ 800000, 0, 0 },
|
||||
{ 400000, 0, 1 },
|
||||
{ 266000, 0, 2 },
|
||||
{ 200000, 0, 3 },
|
||||
};
|
||||
|
||||
static struct dfs_table dfscpucl0_table = {
|
||||
.switches = dfscpucl0_switches,
|
||||
.num_of_switches = ARRAY_SIZE(dfscpucl0_switches),
|
||||
.switch_mux = CLK(CPUCL0_MUX_CLK_CPUCL0),
|
||||
.switch_use = 1,
|
||||
.switch_notuse = 0,
|
||||
.switch_src_div = CLK(MIF_DIV_CLKCMU_CPUCL0_SWITCH),
|
||||
.switch_src_gate = CLK(MIF_GATE_CLKCMU_CPUCL0_SWITCH),
|
||||
.switch_src_usermux = CLK(CPUCL0_MUX_CLKCMU_CPUCL0_SWITCH_USER),
|
||||
};
|
||||
|
||||
struct pwrcal_clk_set dfscpucl0_en_list[] = {
|
||||
{CLK_NONE, 0, -1},
|
||||
};
|
||||
|
||||
static struct dfs_switch dfscpucl1_switches[] = {
|
||||
{ 800000, 0, 0 },
|
||||
{ 400000, 0, 1 },
|
||||
{ 266000, 0, 2 },
|
||||
{ 200000, 0, 3 },
|
||||
};
|
||||
|
||||
static struct dfs_table dfscpucl1_table = {
|
||||
.switches = dfscpucl1_switches,
|
||||
.num_of_switches = ARRAY_SIZE(dfscpucl1_switches),
|
||||
.switch_mux = CLK(CPUCL1_MUX_CLK_CPUCL1),
|
||||
.switch_use = 1,
|
||||
.switch_notuse = 0,
|
||||
.switch_src_div = CLK(MIF_DIV_CLKCMU_CPUCL1_SWITCH),
|
||||
.switch_src_gate = CLK(MIF_GATE_CLKCMU_CPUCL1_SWITCH),
|
||||
.switch_src_usermux = CLK(CPUCL1_MUX_CLKCMU_CPUCL1_SWITCH_USER),
|
||||
};
|
||||
|
||||
struct pwrcal_clk_set dfscpucl1_en_list[] = {
|
||||
{CLK_NONE, 0, -1},
|
||||
};
|
||||
|
||||
static struct dfs_switch dfsg3d_switches[] = {
|
||||
{ 800000, 0, 0 },
|
||||
{ 400000, 0, 1 },
|
||||
{ 266000, 0, 2 },
|
||||
{ 200000, 0, 3 },
|
||||
};
|
||||
|
||||
static struct dfs_table dfsg3d_table = {
|
||||
.switches = dfsg3d_switches,
|
||||
.num_of_switches = ARRAY_SIZE(dfsg3d_switches),
|
||||
.switch_mux = CLK(G3D_MUX_CLK_G3D),
|
||||
.switch_use = 1,
|
||||
.switch_notuse = 0,
|
||||
.switch_src_div = CLK(MIF_DIV_CLKCMU_G3D_SWITCH),
|
||||
.switch_src_gate = CLK(MIF_GATE_CLKCMU_G3D_SWITCH),
|
||||
.switch_src_usermux = CLK(G3D_MUX_CLKCMU_G3D_SWITCH_USER),
|
||||
};
|
||||
|
||||
struct pwrcal_clk_set dfsg3d_en_list[] = {
|
||||
{CLK_NONE, 0, -1},
|
||||
};
|
||||
|
||||
extern void pwrcal_dmc_set_dvfs(unsigned long long target_mif_freq, unsigned int timing_set_idx);
|
||||
extern void pwrcal_dmc_set_pre_dvfs(void);
|
||||
extern void pwrcal_dmc_set_post_dvfs(unsigned long long target_freq);
|
||||
extern void pwrcal_dmc_set_vtmon_on_swithing(void);
|
||||
extern void pwrcal_dmc_set_refresh_method_pre_dvfs(unsigned long long current_rate, unsigned long long target_rate);
|
||||
extern void pwrcal_dmc_set_refresh_method_post_dvfs(unsigned long long current_rate, unsigned long long target_rate);
|
||||
extern void pwrcal_dmc_set_dsref_cycle(unsigned long long target_rate);
|
||||
|
||||
static int pwrcal_clk_set_mif_pause_enable(int enable)
|
||||
{
|
||||
pwrcal_writel(PAUSE, (enable<<0)); /* CMU Pause enable */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pwrcal_clk_wait_mif_pause(void)
|
||||
{
|
||||
int timeout;
|
||||
unsigned int status;
|
||||
|
||||
for (timeout = 0;; timeout++) {
|
||||
status = pwrcal_getf(PAUSE, 16, 0x3);
|
||||
if (status == 0x0)
|
||||
break;
|
||||
|
||||
if (timeout > CLK_WAIT_CNT)
|
||||
pr_err("PAUSE staus(0x%X) is not stable", status);
|
||||
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int is_dll_on_status = 1;
|
||||
|
||||
static void dfsmif_trans_pre(unsigned int rate_from, unsigned int rate_to)
|
||||
{
|
||||
unsigned long long from, to;
|
||||
|
||||
is_dll_on_status = 1;
|
||||
|
||||
from = (unsigned long long)rate_from * 1000;
|
||||
to = (unsigned long long)rate_to * 1000;
|
||||
|
||||
pwrcal_dmc_set_refresh_method_pre_dvfs(from, to);
|
||||
pwrcal_clk_set_mif_pause_enable(1);
|
||||
|
||||
/* VTMON disable before MIF DFS sequence*/
|
||||
pwrcal_dmc_set_pre_dvfs();
|
||||
}
|
||||
|
||||
static void dfsmif_trans_post(unsigned int rate_from, unsigned int rate_to)
|
||||
{
|
||||
unsigned long long from, to;
|
||||
|
||||
from = (unsigned long long)rate_from * 1000;
|
||||
to = (unsigned long long)rate_to * 1000;
|
||||
|
||||
/* VTMON enable before MIF DFS sequence*/
|
||||
pwrcal_dmc_set_post_dvfs(to);
|
||||
|
||||
pwrcal_dmc_set_refresh_method_post_dvfs(from, to);
|
||||
pwrcal_dmc_set_dsref_cycle(to);
|
||||
|
||||
if (rate_to >= 416000)
|
||||
is_dll_on_status = 1;
|
||||
else
|
||||
is_dll_on_status = 0;
|
||||
}
|
||||
|
||||
static void dfsmif_switch_pre(unsigned int rate_from, unsigned int rate_to)
|
||||
{
|
||||
static unsigned int paraset;
|
||||
unsigned long long rate;
|
||||
|
||||
paraset = (paraset + 1) % 2;
|
||||
rate = (unsigned long long)rate_to * 1000;
|
||||
pwrcal_dmc_set_dvfs(rate, paraset);
|
||||
}
|
||||
|
||||
static void dfsmif_switch_post(unsigned int rate_from, unsigned int rate_to)
|
||||
{
|
||||
pwrcal_clk_wait_mif_pause();
|
||||
}
|
||||
|
||||
static unsigned int cur_rate_switch;
|
||||
static int dfsmif_transition_switch(unsigned int rate_from, unsigned int rate_switch, struct dfs_table *table)
|
||||
{
|
||||
int lv_from, lv_switch;
|
||||
|
||||
lv_from = dfs_get_lv(rate_from, table);
|
||||
|
||||
if (lv_from >= table->num_of_lv)
|
||||
goto errorout;
|
||||
|
||||
lv_switch = dfs_get_lv(rate_switch, table);
|
||||
|
||||
dfsmif_trans_pre(rate_from, rate_switch);
|
||||
|
||||
if (dfs_trans_div(lv_from, lv_switch, table, TRANS_HIGH)) /* switching div setting */
|
||||
goto errorout;
|
||||
|
||||
if (dfs_trans_mux(lv_from, lv_switch, table, TRANS_DIFF)) /* switching mux setting */
|
||||
goto errorout;
|
||||
|
||||
dfsmif_switch_pre(rate_from, rate_switch); /* timing parameter setting for switching frequency */
|
||||
|
||||
if (dfs_use_switch(table))
|
||||
goto errorout;
|
||||
|
||||
dfsmif_switch_post(rate_from, rate_switch); /* Switching mux setting */
|
||||
|
||||
if (dfs_trans_div(lv_from, lv_switch, table, TRANS_LOW)) /* waiting for idle status of pause */
|
||||
goto errorout;
|
||||
|
||||
cur_rate_switch = rate_switch;
|
||||
|
||||
return 0;
|
||||
|
||||
errorout:
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int dfsmif_transition(unsigned int rate_switch, unsigned int rate_to, struct dfs_table *table)
|
||||
{
|
||||
int lv_to, lv_switch;
|
||||
|
||||
lv_to = dfs_get_lv(rate_to, table);
|
||||
|
||||
if (lv_to >= table->num_of_lv)
|
||||
goto errorout;
|
||||
|
||||
lv_switch = dfs_get_lv(cur_rate_switch, table);
|
||||
|
||||
if (dfs_trans_pll(lv_switch, lv_to, table, TRANS_FORCE))
|
||||
goto errorout;
|
||||
|
||||
if (dfs_trans_div(lv_switch, lv_to, table, TRANS_HIGH))
|
||||
goto errorout;
|
||||
if (dfs_trans_mux(lv_switch, lv_to, table, TRANS_DIFF))
|
||||
goto errorout;
|
||||
|
||||
dfsmif_switch_pre(rate_switch, rate_to);
|
||||
if (dfs_not_use_switch(table))
|
||||
goto errorout;
|
||||
dfsmif_switch_post(rate_switch, rate_to);
|
||||
|
||||
if (dfs_trans_div(lv_switch, lv_to, table, TRANS_LOW))
|
||||
goto errorout;
|
||||
|
||||
dfsmif_trans_post(lv_switch, rate_to);
|
||||
|
||||
return 0;
|
||||
|
||||
errorout:
|
||||
return -1;
|
||||
}
|
||||
|
||||
static struct dfs_switch dfsmif_switches[] = {
|
||||
{ 1334000, 0, 0 },
|
||||
};
|
||||
|
||||
static struct dfs_table dfsmif_table = {
|
||||
.switches = dfsmif_switches,
|
||||
.num_of_switches = ARRAY_SIZE(dfsmif_switches),
|
||||
.switch_mux = CLK(MIF_MUX_CLK_MIF_PHY_CLK2X),
|
||||
.switch_use = 1,
|
||||
.switch_notuse = 0,
|
||||
.private_trans = dfsmif_transition,
|
||||
.private_switch = dfsmif_transition_switch,
|
||||
};
|
||||
|
||||
struct pwrcal_clk_set dfsmif_en_list[] = {
|
||||
{ CLK_NONE, 0, -1},
|
||||
};
|
||||
|
||||
static struct dfs_switch dfsint_switches[] = {
|
||||
};
|
||||
|
||||
static struct dfs_table dfsint_table = {
|
||||
.switches = dfsint_switches,
|
||||
.num_of_switches = ARRAY_SIZE(dfsint_switches),
|
||||
.switch_use = 1,
|
||||
.switch_notuse = 0,
|
||||
};
|
||||
|
||||
struct pwrcal_clk_set dfsint_en_list[] = {
|
||||
{CLK_NONE, 0, -1},
|
||||
};
|
||||
|
||||
static struct dfs_switch dfsdisp_switches[] = {
|
||||
};
|
||||
|
||||
static struct dfs_table dfsdisp_table = {
|
||||
.switches = dfsdisp_switches,
|
||||
.num_of_switches = ARRAY_SIZE(dfsdisp_switches),
|
||||
.switch_use = 1,
|
||||
.switch_notuse = 0,
|
||||
};
|
||||
|
||||
struct pwrcal_clk_set dfsdisp_en_list[] = {
|
||||
{CLK_NONE, 0, -1},
|
||||
};
|
||||
|
||||
static struct dfs_switch dfscam_switches[] = {
|
||||
};
|
||||
|
||||
static struct dfs_table dfscam_table = {
|
||||
.switches = dfscam_switches,
|
||||
.num_of_switches = ARRAY_SIZE(dfscam_switches),
|
||||
.switch_use = 1,
|
||||
.switch_notuse = 0,
|
||||
};
|
||||
|
||||
struct pwrcal_clk_set dfscam_en_list[] = {
|
||||
{CLK_NONE, 0, -1},
|
||||
};
|
||||
|
||||
static int dfscpucl0_init_smpl(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dfscpucl0_set_smpl(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dfscpucl0_get_smpl(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dfscpucl0_get_rate_table(unsigned long *table)
|
||||
{
|
||||
return dfs_get_rate_table(&dfscpucl1_table, table);
|
||||
}
|
||||
|
||||
static int dfscpucl0_idle_clock_down(unsigned int enable)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static struct vclk_dfs_ops dfscpucl0_dfsops = {
|
||||
.init_smpl = dfscpucl0_init_smpl,
|
||||
.set_smpl = dfscpucl0_set_smpl,
|
||||
.get_smpl = dfscpucl0_get_smpl,
|
||||
.get_rate_table = dfscpucl0_get_rate_table,
|
||||
.cpu_idle_clock_down = dfscpucl0_idle_clock_down,
|
||||
};
|
||||
|
||||
static int dfscpucl1_get_rate_table(unsigned long *table)
|
||||
{
|
||||
return dfs_get_rate_table(&dfscpucl1_table, table);
|
||||
}
|
||||
|
||||
static int dfscpucl1_idle_clock_down(unsigned int enable)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct vclk_dfs_ops dfscpucl1_dfsops = {
|
||||
.get_rate_table = dfscpucl1_get_rate_table,
|
||||
.cpu_idle_clock_down = dfscpucl1_idle_clock_down,
|
||||
};
|
||||
|
||||
static int dfsg3d_dvs(int on)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dfsg3d_get_rate_table(unsigned long *table)
|
||||
{
|
||||
return dfs_get_rate_table(&dfsg3d_table, table);
|
||||
}
|
||||
|
||||
static struct vclk_dfs_ops dfsg3d_dfsops = {
|
||||
.dvs = dfsg3d_dvs,
|
||||
.get_rate_table = dfsg3d_get_rate_table,
|
||||
};
|
||||
|
||||
static int dfsmif_get_rate_table(unsigned long *table)
|
||||
{
|
||||
return dfs_get_rate_table(&dfsmif_table, table);
|
||||
}
|
||||
|
||||
static int dfsmif_is_dll_on(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
static struct vclk_dfs_ops dfsmif_dfsops = {
|
||||
.get_rate_table = dfsmif_get_rate_table,
|
||||
.is_dll_on = dfsmif_is_dll_on,
|
||||
};
|
||||
|
||||
static int dfsint_get_rate_table(unsigned long *table)
|
||||
{
|
||||
return dfs_get_rate_table(&dfsint_table, table);
|
||||
}
|
||||
|
||||
static struct vclk_dfs_ops dfsint_dfsops = {
|
||||
.get_rate_table = dfsint_get_rate_table,
|
||||
};
|
||||
|
||||
static int dfsdisp_get_rate_table(unsigned long *table)
|
||||
{
|
||||
return dfs_get_rate_table(&dfsdisp_table, table);
|
||||
}
|
||||
|
||||
static struct vclk_dfs_ops dfsdisp_dfsops = {
|
||||
.get_rate_table = dfsdisp_get_rate_table,
|
||||
};
|
||||
|
||||
static int dfscam_get_rate_table(unsigned long *table)
|
||||
{
|
||||
return dfs_get_rate_table(&dfscam_table, table);
|
||||
}
|
||||
|
||||
static struct vclk_dfs_ops dfscam_dfsops = {
|
||||
.get_rate_table = dfscam_get_rate_table,
|
||||
};
|
||||
|
||||
|
||||
static DEFINE_SPINLOCK(dvfs_cpucl0_lock);
|
||||
static DEFINE_SPINLOCK(dvfs_cpucl1_lock);
|
||||
static DEFINE_SPINLOCK(dvfs_g3d_lock);
|
||||
static DEFINE_SPINLOCK(dvfs_mif_lock);
|
||||
static DEFINE_SPINLOCK(dvfs_int_lock);
|
||||
static DEFINE_SPINLOCK(dvfs_disp_lock);
|
||||
static DEFINE_SPINLOCK(dvfs_cam_lock);
|
||||
|
||||
DFS(dvfs_cpucl0) = {
|
||||
.vclk.type = vclk_group_dfs,
|
||||
.vclk.parent = VCLK(pxmxdx_top),
|
||||
.vclk.ref_count = 1,
|
||||
.vclk.vfreq = 0,
|
||||
.vclk.name = "dvfs_cpucl0",
|
||||
.vclk.ops = &dfs_ops,
|
||||
.lock = &dvfs_cpucl0_lock,
|
||||
.en_clks = dfscpucl0_en_list,
|
||||
.table = &dfscpucl0_table,
|
||||
.dfsops = &dfscpucl0_dfsops,
|
||||
};
|
||||
|
||||
DFS(dvfs_cpucl1) = {
|
||||
.vclk.type = vclk_group_dfs,
|
||||
.vclk.parent = VCLK(pxmxdx_top),
|
||||
.vclk.ref_count = 1,
|
||||
.vclk.vfreq = 0,
|
||||
.vclk.name = "dvfs_cpucl1",
|
||||
.vclk.ops = &dfs_ops,
|
||||
.lock = &dvfs_cpucl1_lock,
|
||||
.en_clks = dfscpucl1_en_list,
|
||||
.table = &dfscpucl1_table,
|
||||
.dfsops = &dfscpucl1_dfsops,
|
||||
};
|
||||
|
||||
DFS(dvfs_g3d) = {
|
||||
.vclk.type = vclk_group_dfs,
|
||||
.vclk.parent = VCLK(pxmxdx_top),
|
||||
.vclk.ref_count = 0,
|
||||
.vclk.vfreq = 350000,
|
||||
.vclk.name = "dvfs_g3d",
|
||||
.vclk.ops = &dfs_ops,
|
||||
.lock = &dvfs_g3d_lock,
|
||||
.en_clks = dfsg3d_en_list,
|
||||
.table = &dfsg3d_table,
|
||||
.dfsops = &dfsg3d_dfsops,
|
||||
};
|
||||
|
||||
DFS(dvfs_mif) = {
|
||||
.vclk.type = vclk_group_dfs,
|
||||
.vclk.parent = VCLK(pxmxdx_top),
|
||||
.vclk.ref_count = 1,
|
||||
.vclk.vfreq = 0,
|
||||
.vclk.name = "dvfs_mif",
|
||||
.vclk.ops = &dfs_ops,
|
||||
.lock = &dvfs_mif_lock,
|
||||
.en_clks = dfsmif_en_list,
|
||||
.table = &dfsmif_table,
|
||||
.dfsops = &dfsmif_dfsops,
|
||||
};
|
||||
|
||||
DFS(dvfs_int) = {
|
||||
.vclk.type = vclk_group_dfs,
|
||||
.vclk.parent = VCLK(pxmxdx_top),
|
||||
.vclk.ref_count = 1,
|
||||
.vclk.vfreq = 0,
|
||||
.vclk.name = "dvfs_int",
|
||||
.vclk.ops = &dfs_ops,
|
||||
.lock = &dvfs_int_lock,
|
||||
.en_clks = dfsint_en_list,
|
||||
.table = &dfsint_table,
|
||||
.dfsops = &dfsint_dfsops,
|
||||
};
|
||||
|
||||
DFS(dvfs_disp) = {
|
||||
.vclk.type = vclk_group_dfs,
|
||||
.vclk.parent = VCLK(pxmxdx_top),
|
||||
.vclk.ref_count = 0,
|
||||
.vclk.vfreq = 0,
|
||||
.vclk.name = "dvfs_disp",
|
||||
.vclk.ops = &dfs_ops,
|
||||
.lock = &dvfs_disp_lock,
|
||||
.en_clks = dfsdisp_en_list,
|
||||
.table = &dfsdisp_table,
|
||||
.dfsops = &dfsdisp_dfsops,
|
||||
};
|
||||
|
||||
DFS(dvfs_cam) = {
|
||||
.vclk.type = vclk_group_dfs,
|
||||
.vclk.parent = VCLK(pxmxdx_top),
|
||||
.vclk.ref_count = 0,
|
||||
.vclk.vfreq = 533000,
|
||||
.vclk.name = "dvfs_cam",
|
||||
.vclk.ops = &dfs_ops,
|
||||
.lock = &dvfs_cam_lock,
|
||||
.en_clks = dfscam_en_list,
|
||||
.table = &dfscam_table,
|
||||
.dfsops = &dfscam_dfsops,
|
||||
};
|
||||
|
||||
void dfs_set_clk_information(struct pwrcal_vclk_dfs *dfs)
|
||||
{
|
||||
int i, j;
|
||||
void *dvfs_block;
|
||||
struct ect_dvfs_domain *dvfs_domain;
|
||||
struct dfs_table *dvfs_table;
|
||||
|
||||
dvfs_block = ect_get_block("DVFS");
|
||||
if (dvfs_block == NULL)
|
||||
return;
|
||||
|
||||
dvfs_domain = ect_dvfs_get_domain(dvfs_block, dfs->vclk.name);
|
||||
if (dvfs_domain == NULL)
|
||||
return;
|
||||
|
||||
dvfs_table = dfs->table;
|
||||
dvfs_table->num_of_lv = dvfs_domain->num_of_level;
|
||||
dvfs_table->num_of_members = dvfs_domain->num_of_clock + 1;
|
||||
dvfs_table->max_freq = dvfs_domain->max_frequency;
|
||||
dvfs_table->min_freq = dvfs_domain->min_frequency;
|
||||
|
||||
dvfs_table->members = kzalloc(sizeof(struct pwrcal_clk *) * (dvfs_domain->num_of_clock + 1), GFP_KERNEL);
|
||||
if (dvfs_table->members == NULL)
|
||||
return;
|
||||
|
||||
dvfs_table->members[0] = REPRESENT_RATE;
|
||||
for (i = 0; i < dvfs_domain->num_of_clock; ++i) {
|
||||
dvfs_table->members[i + 1] = clk_find(dvfs_domain->list_clock[i]);
|
||||
if (dvfs_table->members[i] == NULL)
|
||||
return;
|
||||
}
|
||||
|
||||
dvfs_table->rate_table = kzalloc(sizeof(unsigned int) * (dvfs_domain->num_of_clock + 1) * dvfs_domain->num_of_level, GFP_KERNEL);
|
||||
if (dvfs_table->rate_table == NULL)
|
||||
return;
|
||||
|
||||
for (i = 0; i < dvfs_domain->num_of_level; ++i) {
|
||||
|
||||
dvfs_table->rate_table[i * (dvfs_domain->num_of_clock + 1)] = dvfs_domain->list_level[i].level;
|
||||
for (j = 0; j <= dvfs_domain->num_of_clock; ++j) {
|
||||
dvfs_table->rate_table[i * (dvfs_domain->num_of_clock + 1) + j + 1] =
|
||||
dvfs_domain->list_dvfs_value[i * dvfs_domain->num_of_clock + j];
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
void dfs_init(void)
|
||||
{
|
||||
dfs_set_clk_information(&vclk_dvfs_cpucl0);
|
||||
dfs_set_clk_information(&vclk_dvfs_cpucl1);
|
||||
dfs_set_clk_information(&vclk_dvfs_g3d);
|
||||
dfs_set_clk_information(&vclk_dvfs_mif);
|
||||
dfs_set_clk_information(&vclk_dvfs_int);
|
||||
dfs_set_clk_information(&vclk_dvfs_cam);
|
||||
dfs_set_clk_information(&vclk_dvfs_disp);
|
||||
|
||||
dfs_dram_init();
|
||||
}
|
||||
566
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-drampara.c
Normal file
566
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-drampara.c
Normal file
|
|
@ -0,0 +1,566 @@
|
|||
#include "../pwrcal-env.h"
|
||||
#include "../pwrcal-rae.h"
|
||||
#include "S5E7870-sfrbase.h"
|
||||
#include "S5E7870-vclk-internal.h"
|
||||
#include "S5E7870-pmusfr.h"
|
||||
|
||||
#ifdef PWRCAL_TARGET_LINUX
|
||||
#include <soc/samsung/ect_parser.h>
|
||||
#else
|
||||
#include <mach/ect_parser.h>
|
||||
#endif
|
||||
|
||||
#ifndef MHZ
|
||||
#define MHZ ((unsigned long long)1000000)
|
||||
#endif
|
||||
|
||||
#define DMC_WAIT_CNT 10000
|
||||
|
||||
#if 1 /// joshua¿ëÀ¸·Î ¼öÁ¤ ÇÊ¿ä
|
||||
|
||||
#define DREX0_MEMORY_CONTROL0 ((void *)(DREX0_BASE + 0x0010))
|
||||
#define DREX0_POWER_DOWN_CONFIG ((void *)(DREX0_BASE + 0x0014))
|
||||
#define DREX0_CG_CONTROL ((void *)(DREX0_BASE + 0x0018))
|
||||
|
||||
#define DREX0_TICK_GRANULARITY_S0 ((void *)(DREX0_BASE + 0x0100))
|
||||
#define DREX0_TEMP_SENSING_S0 ((void *)(DREX0_BASE + 0x0108))
|
||||
#define DREX0_DQS_OSC_CON1_S0 ((void *)(DREX0_BASE + 0x0110))
|
||||
#define DREX0_TERMINATION_CONTROL_S0 ((void *)(DREX0_BASE + 0x0114))
|
||||
#define DREX0_WINCONFIG_WRITE_ODT_S0 ((void *)(DREX0_BASE + 0x0118))
|
||||
#define DREX0_TIMING_ROW0_S0 ((void *)(DREX0_BASE + 0x0140))
|
||||
#define DREX0_TIMING_ROW1_S0 ((void *)(DREX0_BASE + 0x0144))
|
||||
#define DREX0_TIMING_DATA_ACLK_S0 ((void *)(DREX0_BASE + 0x0148))
|
||||
#define DREX0_TIMING_DATA_MCLK_S0 ((void *)(DREX0_BASE + 0x014C))
|
||||
#define DREX0_TIMING_POWER0_S0 ((void *)(DREX0_BASE + 0x0150))
|
||||
#define DREX0_TIMING_POWER1_S0 ((void *)(DREX0_BASE + 0x0154))
|
||||
#define DREX0_TIMING_ETC1_S0 ((void *)(DREX0_BASE + 0x015c))
|
||||
|
||||
#define DREX0_TICK_GRANULARITY_S1 ((void *)(DREX0_BASE + 0x0180))
|
||||
#define DREX0_TEMP_SENSING_S1 ((void *)(DREX0_BASE + 0x0188))
|
||||
#define DREX0_DQS_OSC_CON1_S1 ((void *)(DREX0_BASE + 0x0190))
|
||||
#define DREX0_TERMINATION_CONTROL_S1 ((void *)(DREX0_BASE + 0x0194))
|
||||
#define DREX0_WINCONFIG_WRITE_ODT_S1 ((void *)(DREX0_BASE + 0x0198))
|
||||
#define DREX0_TIMING_ROW0_S1 ((void *)(DREX0_BASE + 0x01c0))
|
||||
#define DREX0_TIMING_ROW1_S1 ((void *)(DREX0_BASE + 0x01c4))
|
||||
#define DREX0_TIMING_DATA_ACLK_S1 ((void *)(DREX0_BASE + 0x01c8))
|
||||
#define DREX0_TIMING_DATA_MCLK_S1 ((void *)(DREX0_BASE + 0x01cC))
|
||||
#define DREX0_TIMING_POWER0_S1 ((void *)(DREX0_BASE + 0x01d0))
|
||||
#define DREX0_TIMING_POWER1_S1 ((void *)(DREX0_BASE + 0x01d4))
|
||||
#define DREX0_TIMING_ETC1_S1 ((void *)(DREX0_BASE + 0x01dc))
|
||||
|
||||
#define PHY0_CAL_CON0 ((void *)(DREXPHY0_BASE + 0x0004))
|
||||
#define PHY0_DVFS_CON0 ((void *)(DREXPHY0_BASE + 0x00B8))
|
||||
#define PHY0_DVFS_CON1 ((void *)(DREXPHY0_BASE + 0x00E0))
|
||||
#define PHY0_DVFS_CON2 ((void *)(DREXPHY0_BASE + 0x00BC))
|
||||
#define PHY0_DVFS_CON3 ((void *)(DREXPHY0_BASE + 0x00C0))
|
||||
#define PHY0_DVFS_CON4 ((void *)(DREXPHY0_BASE + 0x00C4))
|
||||
#define PHY0_DVFS_CON5 ((void *)(DREXPHY0_BASE + 0x00C8))
|
||||
#define PHY0_DVFS_CON6 ((void *)(DREXPHY0_BASE + 0x00CC))
|
||||
#define PHY0_ZQ_CON9 ((void *)(DREXPHY0_BASE + 0x03EC))
|
||||
|
||||
#define DREX0_PAUSE_MRS0 ((void *)(DREX0_BASE + 0x0080))
|
||||
#define DREX0_PAUSE_MRS1 ((void *)(DREX0_BASE + 0x0084))
|
||||
#define DREX0_PAUSE_MRS2 ((void *)(DREX0_BASE + 0x0088))
|
||||
#define DREX0_PAUSE_MRS3 ((void *)(DREX0_BASE + 0x008C))
|
||||
#define DREX0_PAUSE_MRS4 ((void *)(DREX0_BASE + 0x0090))
|
||||
|
||||
#define DREX0_TIMING_SET_SW ((void *)(DREX0_BASE + 0x0020))
|
||||
|
||||
#define DREX0_PORT_TICK_GRANULARITY_S0 ((void *)(DREX0_PF_BASE + 0x0010))
|
||||
#define DREX0_PORT_TICK_GRANULARITY_S1 ((void *)(DREX0_PF_BASE + 0x0014))
|
||||
|
||||
// PHY DVFS CON SFR BIT DEFINITION /
|
||||
#define PHY_DVFS_CON0_SET1_MASK ((0x0)|(1<<31)|(1<<29)|(0x0<<24))
|
||||
#define PHY_DVFS_CON0_SET0_MASK ((0x0)|(1<<30)|(1<<28)|(0x0<<24)|(0x7<<21)|(0x7<<18)|(0x7<<15)|(0x7<<12)|(0x7<<9)|(0x7<<6)|(0x7<<3)|(0x7<<0))
|
||||
#define PHY_DVFS_CON0_DVFS_MODE_MASK ((0x0)|(0x3<<24))
|
||||
#define PHY_DVFS_CON0_DVFS_MODE_POSITION 24
|
||||
|
||||
#define PHY_DVFS_CON1_SET1_MASK ((0x7<<21)|(0x7<<18)|(0x7<<15)|(0x7<<12)|(0x7<<9)|(0x7<<6)|(0x7<<3)|(0x7<<0))
|
||||
#define PHY_DVFS_CON1_SET0_MASK ((0x0))
|
||||
#define PHY_DVFS_CON2_SET1_MASK ((0x0)|(0x1<<31)|(0x1F<<24)|(0xF<<12)|(0xF<<8))
|
||||
#define PHY_DVFS_CON2_SET0_MASK ((0x0)|(0x1<<30)|(0x1F<<16)|(0xF<<7)|(0xF<<0))
|
||||
#define PHY_DVFS_CON3_SET1_MASK ((0x0)|(0x1<<30)|(0x1<<29)|(0x7<<23)|(0x1<<17)|(0xf<<12)|(0xf<<8))
|
||||
#define PHY_DVFS_CON3_SET0_MASK ((0x0)|(0x1<<31)|(0x1<<28)|(0x7<<20)|(0x1<<16)|(0xf<<4)|(0xf<<0))
|
||||
#define PHY_DVFS_CON4_SET1_MASK ((0x0)|(0x3F<<18)|(0x3F<<12))
|
||||
#define PHY_DVFS_CON4_SET0_MASK ((0x0)|(0x3F<<6)|(0x3F<<0))
|
||||
#define PHY_DVFS_CON5_SET1_MASK ((0x0)|(0x7<<24)|(0x7<<16)|(0x7<<8)|(0x7<<0))
|
||||
#define PHY_DVFS_CON5_SET0_MASK ((0x0))
|
||||
#define PHY_DVFS_CON6_SET1_MASK ((0x0))
|
||||
#define PHY_DVFS_CON6_SET0_MASK ((0x0)|(0x7<<24)|(0x7<<16)|(0x7<<8)|(0x7<<0))
|
||||
|
||||
#define DREX0_DIRECTCMD ((void *)(DREX0_BASE + 0x001C))
|
||||
|
||||
|
||||
#define DREX0_timing_set_sw_con 0 /* Pause triggered from CMU */
|
||||
|
||||
#define DQS_OSC_UPDATE_EN 0
|
||||
#define PERIODIC_WR_TRAIN 0
|
||||
|
||||
#if DQS_OSC_UPDATE_EN
|
||||
#define dvfs_dqs_osc_en 1
|
||||
#else
|
||||
#define dvfs_dqs_osc_en 0
|
||||
#endif
|
||||
|
||||
#if PERIODIC_WR_TRAIN
|
||||
#define dvfs_offset 16
|
||||
#else
|
||||
#define dvfs_offset 0
|
||||
#endif
|
||||
|
||||
|
||||
enum dmc_dvfs_mif_level_idx {
|
||||
DMC_DVFS_MIF_L0,
|
||||
DMC_DVFS_MIF_L1,
|
||||
DMC_DVFS_MIF_L2,
|
||||
DMC_DVFS_MIF_L3,
|
||||
DMC_DVFS_MIF_L4,
|
||||
DMC_DVFS_MIF_L5,
|
||||
DMC_DVFS_MIF_L6,
|
||||
DMC_DVFS_MIF_L7,
|
||||
DMC_DVFS_MIF_L8,
|
||||
COUNT_OF_CMU_DVFS_MIF_LEVEL,
|
||||
CMU_DVFS_MIF_INVALID = 0xFF,
|
||||
};
|
||||
|
||||
enum dmc_timing_set_idx {
|
||||
DMC_TIMING_SET_0 = 0,
|
||||
DMC_TIMING_SET_1
|
||||
};
|
||||
|
||||
enum phy_timing_set_idx {
|
||||
PHY_Normal_mode = 0 ,
|
||||
PHY_DVFS0_mode,
|
||||
PHY_DVFS1_mode
|
||||
};
|
||||
|
||||
enum timing_parameter_column {
|
||||
drex_Tick_Granularity,
|
||||
drex_mr4_sensing_cyc,
|
||||
drex_dqs_osc_start_cyc,
|
||||
drex_Termination_Control,
|
||||
drex_Winconfig_Write_Odt,
|
||||
drex_Timing_Row0,
|
||||
drex_Timing_Row1,
|
||||
drex_Timing_Data_Aclk,
|
||||
drex_Timing_Data_Mclk,
|
||||
drex_Timing_Power0,
|
||||
drex_Timing_Power1,
|
||||
drex_Etcl,
|
||||
drex_Puase_MRS0,
|
||||
drex_Puase_MRS1,
|
||||
drex_Puase_MRS2,
|
||||
drex_Puase_MRS3,
|
||||
drex_Puase_MRS4,
|
||||
phy_Dvfs_Con0_set1,
|
||||
phy_Dvfs_Con0_set0,
|
||||
phy_Dvfs_Con0_set1_mask,
|
||||
phy_Dvfs_Con0_set0_mask,
|
||||
phy_Dvfs_Con1_set1,
|
||||
phy_Dvfs_Con1_set0,
|
||||
phy_Dvfs_Con1_set1_mask,
|
||||
phy_Dvfs_Con1_set0_mask,
|
||||
phy_Dvfs_Con2_set1,
|
||||
phy_Dvfs_Con2_set0,
|
||||
phy_Dvfs_Con2_set1_mask,
|
||||
phy_Dvfs_Con2_set0_mask,
|
||||
phy_Dvfs_Con3_set1,
|
||||
phy_Dvfs_Con3_set0,
|
||||
phy_Dvfs_Con3_set1_mask,
|
||||
phy_Dvfs_Con3_set0_mask,
|
||||
num_of_g_dmc_drex_dfs_mif_table_column = drex_Etcl - drex_Tick_Granularity + 1,
|
||||
num_of_g_dmc_directcmd_dfs_mif_table_column = drex_Puase_MRS4 - drex_Puase_MRS0 + 1,
|
||||
num_of_g_dmc_phy_dfs_mif_table_column = phy_Dvfs_Con3_set0_mask - phy_Dvfs_Con0_set1 + 1,
|
||||
num_of_dram_parameter = num_of_g_dmc_drex_dfs_mif_table_column + num_of_g_dmc_directcmd_dfs_mif_table_column + num_of_g_dmc_phy_dfs_mif_table_column,
|
||||
};
|
||||
|
||||
struct dmc_drex_dfs_mif_table {
|
||||
unsigned int drex_Tick_Granularity;
|
||||
unsigned int drex_mr4_sensing_cyc;
|
||||
unsigned int drex_dqs_osc_start_cyc;
|
||||
unsigned int drex_Termination_Control;
|
||||
unsigned int drex_Winconfig_Write_Odt;
|
||||
unsigned int drex_Timing_Row0;
|
||||
unsigned int drex_Timing_Row1;
|
||||
unsigned int drex_Timing_Data_Aclk;
|
||||
unsigned int drex_Timing_Data_Mclk;
|
||||
unsigned int drex_Timing_Power0;
|
||||
unsigned int drex_Timing_Power1;
|
||||
unsigned int drex_Etcl;
|
||||
};
|
||||
|
||||
|
||||
struct dmc_directcmd_dfs_mif_table {
|
||||
unsigned int drex_Puase_MRS0;
|
||||
unsigned int drex_Puase_MRS1;
|
||||
unsigned int drex_Puase_MRS2;
|
||||
unsigned int drex_Puase_MRS3;
|
||||
unsigned int drex_Puase_MRS4;
|
||||
};
|
||||
|
||||
struct dmc_phy_dfs_mif_table {
|
||||
unsigned int phy_Dvfs_Con0_set1;
|
||||
unsigned int phy_Dvfs_Con0_set0;
|
||||
unsigned int phy_Dvfs_Con0_set1_mask;
|
||||
unsigned int phy_Dvfs_Con0_set0_mask;
|
||||
unsigned int phy_Dvfs_Con1_set1;
|
||||
unsigned int phy_Dvfs_Con1_set0;
|
||||
unsigned int phy_Dvfs_Con1_set1_mask;
|
||||
unsigned int phy_Dvfs_Con1_set0_mask;
|
||||
unsigned int phy_Dvfs_Con2_set1;
|
||||
unsigned int phy_Dvfs_Con2_set0;
|
||||
unsigned int phy_Dvfs_Con2_set1_mask;
|
||||
unsigned int phy_Dvfs_Con2_set0_mask;
|
||||
unsigned int phy_Dvfs_Con3_set1;
|
||||
unsigned int phy_Dvfs_Con3_set0;
|
||||
unsigned int phy_Dvfs_Con3_set1_mask;
|
||||
unsigned int phy_Dvfs_Con3_set0_mask;
|
||||
unsigned int phy_Dvfs_Con4_set1;
|
||||
unsigned int phy_Dvfs_Con4_set0;
|
||||
unsigned int phy_Dvfs_Con4_set1_mask;
|
||||
unsigned int phy_Dvfs_Con4_set0_mask;
|
||||
unsigned int phy_Dvfs_Con5_set1;
|
||||
unsigned int phy_Dvfs_Con5_set0;
|
||||
unsigned int phy_Dvfs_Con5_set1_mask;
|
||||
unsigned int phy_Dvfs_Con5_set0_mask;
|
||||
unsigned int phy_Dvfs_Con6_set1;
|
||||
unsigned int phy_Dvfs_Con6_set0;
|
||||
unsigned int phy_Dvfs_Con6_set1_mask;
|
||||
unsigned int phy_Dvfs_Con6_set0_mask;
|
||||
};
|
||||
|
||||
enum dmc_dvfs_mif_switching_level_idx {
|
||||
DMC_DVFS_MIF__switching_L0,
|
||||
DMC_DVFS_MIF__switching_L1,
|
||||
};
|
||||
|
||||
#define LP4_RL 12
|
||||
#define LP4_WL 6
|
||||
#define LP4_RL_L10 6
|
||||
#define LP4_WL_L10 4
|
||||
#define DRAM_RLWL 0x09
|
||||
#define DRAM_RLWL_L10 0x00
|
||||
|
||||
static struct dmc_drex_dfs_mif_table *pwrcal_dfs_drex_mif_table;
|
||||
static struct dmc_directcmd_dfs_mif_table *pwrcal_pause_directcmd_dfs_mif_table;
|
||||
static struct dmc_phy_dfs_mif_table *pwrcal_dfs_phy_mif_table;
|
||||
|
||||
|
||||
static unsigned long long *mif_freq_to_level;
|
||||
static int num_mif_freq_to_level;
|
||||
|
||||
|
||||
static unsigned int convert_to_level(unsigned long long freq)
|
||||
{
|
||||
int idx;
|
||||
int tablesize = num_mif_freq_to_level;
|
||||
|
||||
for (idx = tablesize - 1; idx >= 0; idx--)
|
||||
if (freq <= mif_freq_to_level[idx])
|
||||
return (unsigned int)idx;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
void pwrcal_dmc_set_dvfs(unsigned long long target_mif_freq, unsigned int timing_set_idx)
|
||||
{
|
||||
unsigned int uReg;
|
||||
// unsigned int soc_vref[4];
|
||||
unsigned int target_mif_level_idx, target_mif_level_switch_idx;
|
||||
unsigned int offset;
|
||||
|
||||
|
||||
target_mif_level_idx = convert_to_level(target_mif_freq);
|
||||
target_mif_level_switch_idx = convert_to_level(target_mif_freq);
|
||||
|
||||
if (timing_set_idx == DMC_TIMING_SET_0) {
|
||||
for (offset = 0; offset < 0x100000; offset += 0x100000) {
|
||||
|
||||
/* Phy & DREX Mode setting */
|
||||
if (target_mif_level_idx != 0) {
|
||||
uReg = pwrcal_readl(offset + PHY0_DVFS_CON0);
|
||||
uReg &= ~(PHY_DVFS_CON0_DVFS_MODE_MASK);
|
||||
uReg |= (PHY_DVFS0_mode<<PHY_DVFS_CON0_DVFS_MODE_POSITION);
|
||||
pwrcal_writel(offset + PHY0_DVFS_CON0, uReg);
|
||||
} else {
|
||||
uReg = pwrcal_readl(offset + PHY0_DVFS_CON0);
|
||||
uReg &= ~(PHY_DVFS_CON0_DVFS_MODE_MASK);
|
||||
uReg |= (PHY_Normal_mode<<PHY_DVFS_CON0_DVFS_MODE_POSITION);
|
||||
pwrcal_writel(offset + PHY0_DVFS_CON0, uReg);
|
||||
}
|
||||
|
||||
pwrcal_writel(offset + DREX0_TIMING_SET_SW, DREX0_timing_set_sw_con);
|
||||
pwrcal_writel((void *)CMU_MIF_BASE + 0x1004, DMC_TIMING_SET_0); /*cmu pause setting */
|
||||
|
||||
#define PHY_DVFS_CON0_DVFS_MODE_MASK ((0x0)|(0x3<<24))
|
||||
#define PHY_DVFS_CON0_DVFS_MODE_POSITION 24
|
||||
|
||||
pwrcal_writel(offset + DREX0_TICK_GRANULARITY_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Tick_Granularity);
|
||||
pwrcal_writel(offset + DREX0_PORT_TICK_GRANULARITY_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Tick_Granularity);
|
||||
pwrcal_writel(offset + DREX0_TEMP_SENSING_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_mr4_sensing_cyc);
|
||||
pwrcal_writel(offset + DREX0_DQS_OSC_CON1_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_dqs_osc_start_cyc);
|
||||
pwrcal_writel(offset + DREX0_TERMINATION_CONTROL_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Termination_Control);
|
||||
pwrcal_writel(offset + DREX0_WINCONFIG_WRITE_ODT_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Winconfig_Write_Odt);
|
||||
pwrcal_writel(offset + DREX0_TIMING_ROW0_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Timing_Row0);
|
||||
pwrcal_writel(offset + DREX0_TIMING_ROW1_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Timing_Row1);
|
||||
pwrcal_writel(offset + DREX0_TIMING_DATA_ACLK_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Timing_Data_Aclk);
|
||||
pwrcal_writel(offset + DREX0_TIMING_DATA_MCLK_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Timing_Data_Mclk);
|
||||
pwrcal_writel(offset + DREX0_TIMING_POWER0_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Timing_Power0);
|
||||
pwrcal_writel(offset + DREX0_TIMING_POWER1_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Timing_Power1);
|
||||
pwrcal_writel(offset + DREX0_TIMING_ETC1_S0, pwrcal_dfs_drex_mif_table[target_mif_level_idx].drex_Etcl);
|
||||
|
||||
uReg = pwrcal_readl(offset + PHY0_DVFS_CON0);
|
||||
uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con0_set0_mask);
|
||||
uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con0_set0;
|
||||
pwrcal_writel(offset + PHY0_DVFS_CON0, uReg);
|
||||
|
||||
uReg = pwrcal_readl(offset + PHY0_DVFS_CON1);
|
||||
uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con1_set0_mask);
|
||||
uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con1_set0;
|
||||
pwrcal_writel(offset + PHY0_DVFS_CON1, uReg);
|
||||
|
||||
uReg = pwrcal_readl(offset + PHY0_DVFS_CON2);
|
||||
uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con2_set0_mask);
|
||||
uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con2_set0;
|
||||
pwrcal_writel(offset + PHY0_DVFS_CON2, uReg);
|
||||
|
||||
uReg = pwrcal_readl(offset + PHY0_DVFS_CON3);
|
||||
uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con3_set0_mask);
|
||||
uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_idx].phy_Dvfs_Con3_set0;
|
||||
pwrcal_writel(offset + PHY0_DVFS_CON3, uReg);
|
||||
|
||||
pwrcal_writel(offset + DREX0_PAUSE_MRS0, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_idx].drex_Puase_MRS0);
|
||||
pwrcal_writel(offset + DREX0_PAUSE_MRS1, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_idx].drex_Puase_MRS1);
|
||||
pwrcal_writel(offset + DREX0_PAUSE_MRS2, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_idx].drex_Puase_MRS2);
|
||||
pwrcal_writel(offset + DREX0_PAUSE_MRS3, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_idx].drex_Puase_MRS3);
|
||||
pwrcal_writel(offset + DREX0_PAUSE_MRS4, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_idx].drex_Puase_MRS4);
|
||||
}
|
||||
|
||||
} else if (timing_set_idx == DMC_TIMING_SET_1) {
|
||||
for (offset = 0; offset < 0x100000; offset += 0x100000) {
|
||||
|
||||
/* Phy & DREX Mode setting */
|
||||
uReg = pwrcal_readl(offset + PHY0_DVFS_CON0);
|
||||
uReg &= ~(PHY_DVFS_CON0_DVFS_MODE_MASK);
|
||||
uReg |= (PHY_DVFS1_mode<<PHY_DVFS_CON0_DVFS_MODE_POSITION);
|
||||
pwrcal_writel(offset + PHY0_DVFS_CON0, uReg);
|
||||
|
||||
pwrcal_writel(offset + DREX0_TIMING_SET_SW, DREX0_timing_set_sw_con);
|
||||
pwrcal_writel((void *)CMU_MIF_BASE + 0x1004, DMC_TIMING_SET_1); /*cmu pause setting */
|
||||
|
||||
pwrcal_writel(offset + DREX0_TICK_GRANULARITY_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Tick_Granularity);
|
||||
pwrcal_writel(offset + DREX0_PORT_TICK_GRANULARITY_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Tick_Granularity);
|
||||
pwrcal_writel(offset + DREX0_TEMP_SENSING_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_mr4_sensing_cyc);
|
||||
pwrcal_writel(offset + DREX0_DQS_OSC_CON1_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_dqs_osc_start_cyc);
|
||||
pwrcal_writel(offset + DREX0_TERMINATION_CONTROL_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Termination_Control);
|
||||
pwrcal_writel(offset + DREX0_WINCONFIG_WRITE_ODT_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Winconfig_Write_Odt);
|
||||
pwrcal_writel(offset + DREX0_TIMING_ROW0_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Timing_Row0);
|
||||
pwrcal_writel(offset + DREX0_TIMING_ROW1_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Timing_Row1);
|
||||
pwrcal_writel(offset + DREX0_TIMING_DATA_ACLK_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Timing_Data_Aclk);
|
||||
pwrcal_writel(offset + DREX0_TIMING_DATA_MCLK_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Timing_Data_Mclk);
|
||||
pwrcal_writel(offset + DREX0_TIMING_POWER0_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Timing_Power0);
|
||||
pwrcal_writel(offset + DREX0_TIMING_POWER1_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Timing_Power1);
|
||||
pwrcal_writel(offset + DREX0_TIMING_ETC1_S1, pwrcal_dfs_drex_mif_table[target_mif_level_switch_idx].drex_Etcl);
|
||||
|
||||
uReg = pwrcal_readl(offset + PHY0_DVFS_CON0);
|
||||
uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con0_set1_mask);
|
||||
uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con0_set1;
|
||||
pwrcal_writel(offset + PHY0_DVFS_CON0, uReg);
|
||||
|
||||
uReg = pwrcal_readl(offset + PHY0_DVFS_CON1);
|
||||
uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con1_set1_mask);
|
||||
uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con1_set1;
|
||||
pwrcal_writel(offset + PHY0_DVFS_CON1, uReg);
|
||||
|
||||
uReg = pwrcal_readl(offset + PHY0_DVFS_CON2);
|
||||
uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con2_set1_mask);
|
||||
uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con2_set1;
|
||||
pwrcal_writel(offset + PHY0_DVFS_CON2, uReg);
|
||||
|
||||
uReg = pwrcal_readl(offset + PHY0_DVFS_CON3);
|
||||
uReg &= ~(pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con3_set1_mask);
|
||||
uReg |= pwrcal_dfs_phy_mif_table[target_mif_level_switch_idx].phy_Dvfs_Con3_set1;
|
||||
pwrcal_writel(offset + PHY0_DVFS_CON3, uReg);
|
||||
|
||||
pwrcal_writel(offset + DREX0_PAUSE_MRS0, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_switch_idx].drex_Puase_MRS0);
|
||||
pwrcal_writel(offset + DREX0_PAUSE_MRS1, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_switch_idx].drex_Puase_MRS1);
|
||||
pwrcal_writel(offset + DREX0_PAUSE_MRS2, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_switch_idx].drex_Puase_MRS2);
|
||||
pwrcal_writel(offset + DREX0_PAUSE_MRS3, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_switch_idx].drex_Puase_MRS3);
|
||||
pwrcal_writel(offset + DREX0_PAUSE_MRS4, pwrcal_pause_directcmd_dfs_mif_table[target_mif_level_switch_idx].drex_Puase_MRS4);
|
||||
}
|
||||
} else {
|
||||
pr_err("wrong DMC timing set selection on DVFS\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
//static unsigned int per_mrs_en;
|
||||
|
||||
void pwrcal_dmc_set_pre_dvfs(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void pwrcal_dmc_set_post_dvfs(unsigned long long target_freq)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
void pwrcal_dmc_set_refresh_method_pre_dvfs(unsigned long long current_rate, unsigned long long target_rate)
|
||||
{
|
||||
/* target_rate is MIF clock rate */
|
||||
unsigned int uReg;
|
||||
uReg = pwrcal_readl(DREX0_CG_CONTROL);
|
||||
uReg = ((uReg & ~(1 << 24)) | (0 << 24));
|
||||
pwrcal_writel(DREX0_CG_CONTROL, uReg); //External Clock Gating - PHY Clock Gating disable
|
||||
}
|
||||
|
||||
void pwrcal_dmc_set_refresh_method_post_dvfs(unsigned long long current_rate, unsigned long long target_rate)
|
||||
{
|
||||
/* target_rate is MIF clock rate */
|
||||
unsigned int uReg;
|
||||
uReg = pwrcal_readl(DREX0_CG_CONTROL);
|
||||
uReg = ((uReg & ~(1 << 24)) | (1 << 24));
|
||||
pwrcal_writel(DREX0_CG_CONTROL, uReg); //External Clock Gating - PHY Clock Gating enable
|
||||
}
|
||||
|
||||
void pwrcal_dmc_set_dsref_cycle(unsigned long long target_rate)
|
||||
{
|
||||
unsigned int uReg, cycle;
|
||||
|
||||
/* target_rate is MIF clock rate */
|
||||
if (target_rate > 800 * MHZ)
|
||||
cycle = 0x3ff;
|
||||
else if (target_rate > 400 * MHZ)
|
||||
cycle = 0x1ff;
|
||||
else if (target_rate > 200 * MHZ)
|
||||
cycle = 0x90;
|
||||
else
|
||||
cycle = 0x90;
|
||||
|
||||
|
||||
/* dsref disable */
|
||||
uReg = pwrcal_readl(DREX0_MEMORY_CONTROL0);
|
||||
uReg &= ~(1 << 4);
|
||||
pwrcal_writel(DREX0_MEMORY_CONTROL0, uReg);
|
||||
|
||||
uReg = pwrcal_readl(DREX0_POWER_DOWN_CONFIG);
|
||||
uReg = ((uReg & ~(0xffff << 16)) | (cycle << 16));
|
||||
pwrcal_writel(DREX0_POWER_DOWN_CONFIG, uReg);
|
||||
|
||||
/* dsref enable */
|
||||
uReg = pwrcal_readl(DREX0_MEMORY_CONTROL0);
|
||||
uReg |= (1 << 4);
|
||||
pwrcal_writel(DREX0_MEMORY_CONTROL0, uReg);
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
void dfs_dram_param_init(void)
|
||||
{
|
||||
int i;
|
||||
void *dram_block;
|
||||
u32 uMem_type;
|
||||
// int memory_size = 2; // means 3GB
|
||||
struct ect_timing_param_size *size;
|
||||
|
||||
uMem_type = (pwrcal_readl(PMU_DREX_CALIBRATION2) & 0xFFFF);
|
||||
|
||||
dram_block = ect_get_block(BLOCK_TIMING_PARAM);
|
||||
if (dram_block == NULL)
|
||||
return;
|
||||
|
||||
size = ect_timing_param_get_size(dram_block, uMem_type);
|
||||
if (size == NULL)
|
||||
return;
|
||||
|
||||
if (num_of_dram_parameter != size->num_of_timing_param)
|
||||
return;
|
||||
|
||||
pwrcal_dfs_drex_mif_table = kzalloc(sizeof(struct dmc_drex_dfs_mif_table) * num_of_g_dmc_drex_dfs_mif_table_column * size->num_of_level, GFP_KERNEL);
|
||||
if (pwrcal_dfs_drex_mif_table == NULL)
|
||||
return;
|
||||
|
||||
pwrcal_pause_directcmd_dfs_mif_table = kzalloc(sizeof(struct dmc_directcmd_dfs_mif_table) * num_of_g_dmc_directcmd_dfs_mif_table_column * size->num_of_level, GFP_KERNEL);
|
||||
if (pwrcal_pause_directcmd_dfs_mif_table == NULL)
|
||||
return;
|
||||
|
||||
pwrcal_dfs_phy_mif_table = kzalloc(sizeof(struct dmc_phy_dfs_mif_table) * num_of_g_dmc_phy_dfs_mif_table_column * size->num_of_level, GFP_KERNEL);
|
||||
if (pwrcal_dfs_phy_mif_table == NULL)
|
||||
return;
|
||||
|
||||
for (i = 0; i < size->num_of_level; ++i) {
|
||||
pwrcal_dfs_drex_mif_table[i].drex_Tick_Granularity = size->timing_parameter[i * num_of_dram_parameter + drex_Tick_Granularity];
|
||||
pwrcal_dfs_drex_mif_table[i].drex_mr4_sensing_cyc = size->timing_parameter[i * num_of_dram_parameter + drex_mr4_sensing_cyc];
|
||||
pwrcal_dfs_drex_mif_table[i].drex_dqs_osc_start_cyc = size->timing_parameter[i * num_of_dram_parameter + drex_dqs_osc_start_cyc];
|
||||
pwrcal_dfs_drex_mif_table[i].drex_Termination_Control = size->timing_parameter[i * num_of_dram_parameter + drex_Termination_Control];
|
||||
pwrcal_dfs_drex_mif_table[i].drex_Winconfig_Write_Odt = size->timing_parameter[i * num_of_dram_parameter + drex_Winconfig_Write_Odt];
|
||||
pwrcal_dfs_drex_mif_table[i].drex_Timing_Row0 = size->timing_parameter[i * num_of_dram_parameter + drex_Timing_Row0];
|
||||
pwrcal_dfs_drex_mif_table[i].drex_Timing_Row1 = size->timing_parameter[i * num_of_dram_parameter + drex_Timing_Row1];
|
||||
pwrcal_dfs_drex_mif_table[i].drex_Timing_Data_Aclk = size->timing_parameter[i * num_of_dram_parameter + drex_Timing_Data_Aclk];
|
||||
pwrcal_dfs_drex_mif_table[i].drex_Timing_Data_Mclk = size->timing_parameter[i * num_of_dram_parameter + drex_Timing_Data_Mclk];
|
||||
pwrcal_dfs_drex_mif_table[i].drex_Timing_Power0 = size->timing_parameter[i * num_of_dram_parameter + drex_Timing_Power0];
|
||||
pwrcal_dfs_drex_mif_table[i].drex_Timing_Power1 = size->timing_parameter[i * num_of_dram_parameter + drex_Timing_Power1];
|
||||
pwrcal_dfs_drex_mif_table[i].drex_Etcl = size->timing_parameter[i * num_of_dram_parameter + drex_Etcl];
|
||||
|
||||
pwrcal_pause_directcmd_dfs_mif_table[i].drex_Puase_MRS0 = size->timing_parameter[i * num_of_dram_parameter + drex_Puase_MRS0];
|
||||
pwrcal_pause_directcmd_dfs_mif_table[i].drex_Puase_MRS1 = size->timing_parameter[i * num_of_dram_parameter + drex_Puase_MRS1];
|
||||
pwrcal_pause_directcmd_dfs_mif_table[i].drex_Puase_MRS2 = size->timing_parameter[i * num_of_dram_parameter + drex_Puase_MRS2];
|
||||
pwrcal_pause_directcmd_dfs_mif_table[i].drex_Puase_MRS3 = size->timing_parameter[i * num_of_dram_parameter + drex_Puase_MRS3];
|
||||
pwrcal_pause_directcmd_dfs_mif_table[i].drex_Puase_MRS4 = size->timing_parameter[i * num_of_dram_parameter + drex_Puase_MRS4];
|
||||
|
||||
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con0_set1 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con0_set1];
|
||||
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con0_set0 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con0_set0];
|
||||
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con0_set1_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con0_set1_mask];
|
||||
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con0_set0_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con0_set0_mask];
|
||||
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con1_set1 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con1_set1];
|
||||
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con1_set0 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con1_set0];
|
||||
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con1_set1_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con1_set1_mask];
|
||||
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con1_set0_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con1_set0_mask];
|
||||
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con2_set1 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con2_set1];
|
||||
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con2_set0 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con2_set0];
|
||||
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con2_set1_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con2_set1_mask];
|
||||
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con2_set0_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con2_set0_mask];
|
||||
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con3_set1 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con3_set1];
|
||||
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con3_set0 = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con3_set0];
|
||||
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con3_set1_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con3_set1_mask];
|
||||
pwrcal_dfs_phy_mif_table[i].phy_Dvfs_Con3_set0_mask = size->timing_parameter[i * num_of_dram_parameter + phy_Dvfs_Con3_set0_mask];
|
||||
}
|
||||
}
|
||||
|
||||
void dfs_mif_level_init(void)
|
||||
{
|
||||
int i;
|
||||
void *dvfs_block;
|
||||
struct ect_dvfs_domain *domain;
|
||||
|
||||
dvfs_block = ect_get_block(BLOCK_DVFS);
|
||||
if (dvfs_block == NULL)
|
||||
return;
|
||||
|
||||
domain = ect_dvfs_get_domain(dvfs_block, vclk_dvfs_mif.vclk.name);
|
||||
if (domain == NULL)
|
||||
return;
|
||||
|
||||
mif_freq_to_level = kzalloc(sizeof(unsigned long long) * domain->num_of_level, GFP_KERNEL);
|
||||
if (mif_freq_to_level == NULL)
|
||||
return;
|
||||
|
||||
num_mif_freq_to_level = domain->num_of_level;
|
||||
|
||||
for (i = 0; i < domain->num_of_level; ++i)
|
||||
mif_freq_to_level[i] = (unsigned long long) domain->list_level[i].level * KHZ;
|
||||
}
|
||||
|
||||
void dfs_dram_init(void)
|
||||
{
|
||||
dfs_dram_param_init();
|
||||
dfs_mif_level_init();
|
||||
}
|
||||
|
||||
|
||||
#endif
|
||||
537
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-pll.c
Normal file
537
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-pll.c
Normal file
|
|
@ -0,0 +1,537 @@
|
|||
#include "../pwrcal.h"
|
||||
#include "../pwrcal-clk.h"
|
||||
#include "../pwrcal-env.h"
|
||||
#include "../pwrcal-rae.h"
|
||||
#include "../pwrcal-pmu.h"
|
||||
#include "S5E7870-cmusfr.h"
|
||||
#include "S5E7870-pmusfr.h"
|
||||
#include "S5E7870-cmu.h"
|
||||
|
||||
|
||||
/*
|
||||
PLLs
|
||||
*/
|
||||
/* PLL141XX Clock Type */
|
||||
#define PLL141XX_MDIV_SHIFT 16
|
||||
#define PLL141XX_PDIV_SHIFT 8
|
||||
#define PLL141XX_SDIV_SHIFT 0
|
||||
#define PLL141XX_MDIV_MASK 0x3FF
|
||||
#define PLL141XX_PDIV_MASK 0x3F
|
||||
#define PLL141XX_SDIV_MASK 0x7
|
||||
#define PLL141XX_ENABLE 31
|
||||
#define PLL141XX_LOCKED 29
|
||||
#define PLL141XX_BYPASS 22
|
||||
|
||||
/* PLL1431X Clock Type */
|
||||
#define PLL1431X_MDIV_SHIFT 16
|
||||
#define PLL1431X_PDIV_SHIFT 8
|
||||
#define PLL1431X_SDIV_SHIFT 0
|
||||
#define PLL1431X_K_SHIFT 0
|
||||
#define PLL1431X_MDIV_MASK 0x3FF
|
||||
#define PLL1431X_PDIV_MASK 0x3F
|
||||
#define PLL1431X_SDIV_MASK 0x7
|
||||
#define PLL1431X_K_MASK 0xFFFF
|
||||
#define PLL1431X_ENABLE 31
|
||||
#define PLL1431X_LOCKED 29
|
||||
#define PLL1431X_BYPASS 4
|
||||
|
||||
#define FIN_HZ_26M (26*MHZ)
|
||||
|
||||
static const struct pwrcal_pll_rate_table *_clk_get_pll_settings(
|
||||
struct pwrcal_pll *pll_clk,
|
||||
unsigned long long rate)
|
||||
{
|
||||
int i;
|
||||
const struct pwrcal_pll_rate_table *prate_table = pll_clk->rate_table;
|
||||
|
||||
for (i = 0; i < pll_clk->rate_count; i++) {
|
||||
if (rate == prate_table[i].rate)
|
||||
return &prate_table[i];
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int _clk_pll141xx_find_pms(struct pll_spec *pll_spec,
|
||||
struct pwrcal_pll_rate_table *rate_table,
|
||||
unsigned long long rate)
|
||||
{
|
||||
unsigned int p, m, s;
|
||||
unsigned long long fref, fvco, fout;
|
||||
unsigned long long tmprate, tmpfout;
|
||||
unsigned long long mindiffrate = 0xFFFFFFFFFFFFFFFF;
|
||||
unsigned int min_p, min_m, min_s, min_fout;
|
||||
|
||||
for (p = pll_spec->pdiv_min; p <= pll_spec->pdiv_max; p++) {
|
||||
fref = FIN_HZ_26M / p;
|
||||
if ((fref < pll_spec->fref_min) || (fref > pll_spec->fref_max))
|
||||
continue;
|
||||
|
||||
for (s = pll_spec->sdiv_min; s <= pll_spec->sdiv_max; s++) {
|
||||
tmprate = rate;
|
||||
do_div(tmprate, MHZ);
|
||||
tmprate = tmprate * p * (1 << s);
|
||||
do_div(tmprate, (FIN_HZ_26M / MHZ));
|
||||
m = (unsigned int)tmprate;
|
||||
|
||||
if ((m < pll_spec->mdiv_min)
|
||||
|| (m > pll_spec->mdiv_max))
|
||||
continue;
|
||||
|
||||
fvco = ((unsigned long long)FIN_HZ_26M) * m;
|
||||
do_div(fvco, p);
|
||||
if ((fvco < pll_spec->fvco_min)
|
||||
|| (fvco > pll_spec->fvco_max))
|
||||
continue;
|
||||
|
||||
fout = fvco >> s;
|
||||
if ((fout >= pll_spec->fout_min)
|
||||
&& (fout <= pll_spec->fout_max)) {
|
||||
tmprate = rate;
|
||||
do_div(tmprate, KHZ);
|
||||
tmpfout = fout;
|
||||
do_div(tmpfout, KHZ);
|
||||
if (tmprate == tmpfout) {
|
||||
rate_table->rate = fout;
|
||||
rate_table->pdiv = p;
|
||||
rate_table->mdiv = m;
|
||||
rate_table->sdiv = s;
|
||||
rate_table->kdiv = 0;
|
||||
return 0;
|
||||
}
|
||||
if (tmpfout < tmprate && mindiffrate > tmprate - tmpfout) {
|
||||
mindiffrate = tmprate - tmpfout;
|
||||
min_fout = fout;
|
||||
min_p = p;
|
||||
min_m = m;
|
||||
min_s = s;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (mindiffrate != 0xFFFFFFFFFFFFFFFF) {
|
||||
rate_table->rate = min_fout;
|
||||
rate_table->pdiv = min_p;
|
||||
rate_table->mdiv = min_m;
|
||||
rate_table->sdiv = min_s;
|
||||
rate_table->kdiv = 0;
|
||||
return 0;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int _clk_pll141xx_is_enabled(struct pwrcal_clk *clk)
|
||||
{
|
||||
return (int)(pwrcal_getbit(clk->offset, PLL141XX_ENABLE));
|
||||
}
|
||||
|
||||
static int _clk_pll141xx_enable(struct pwrcal_clk *clk)
|
||||
{
|
||||
int timeout;
|
||||
|
||||
pwrcal_setbit(clk->offset, PLL141XX_ENABLE, 1);
|
||||
|
||||
for (timeout = 0;; timeout++) {
|
||||
if (pwrcal_getbit(clk->offset, PLL141XX_LOCKED))
|
||||
break;
|
||||
if (timeout > CLK_WAIT_CNT)
|
||||
return -1;
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int _clk_pll141xx_disable(struct pwrcal_clk *clk)
|
||||
{
|
||||
pwrcal_setbit(clk->offset, PLL141XX_ENABLE, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int _clk_pll141xx_is_disabled_bypass(struct pwrcal_clk *clk)
|
||||
{
|
||||
if (pwrcal_getbit(clk->offset + 1, PLL141XX_BYPASS))
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
int _clk_pll141xx_set_bypass(struct pwrcal_clk *clk, int bypass_disable)
|
||||
{
|
||||
if (bypass_disable == 0)
|
||||
pwrcal_setbit(clk + 1, PLL141XX_BYPASS, 1);
|
||||
else
|
||||
pwrcal_setbit(clk + 1, PLL141XX_BYPASS, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _clk_pll141xx_set_pms(struct pwrcal_clk *clk,
|
||||
const struct pwrcal_pll_rate_table *rate_table)
|
||||
{
|
||||
unsigned int mdiv, pdiv, sdiv, pll_con0;
|
||||
|
||||
int timeout;
|
||||
|
||||
pdiv = rate_table->pdiv;
|
||||
mdiv = rate_table->mdiv;
|
||||
sdiv = rate_table->sdiv;
|
||||
|
||||
pll_con0 = pwrcal_readl(clk->offset);
|
||||
pll_con0 &= ~((PLL141XX_MDIV_MASK << PLL141XX_MDIV_SHIFT)
|
||||
| (PLL141XX_PDIV_MASK << PLL141XX_PDIV_SHIFT)
|
||||
| (PLL141XX_SDIV_MASK << PLL141XX_SDIV_SHIFT));
|
||||
pll_con0 |= (mdiv << PLL141XX_MDIV_SHIFT)
|
||||
| (pdiv << PLL141XX_PDIV_SHIFT)
|
||||
| (sdiv << PLL141XX_SDIV_SHIFT);
|
||||
pll_con0 &= ~(1 << 26);
|
||||
pll_con0 |= (1 << 5);
|
||||
|
||||
pwrcal_writel(clk->status, pdiv * 150);
|
||||
pwrcal_writel(clk->offset, pll_con0);
|
||||
|
||||
if (pll_con0 & (1 << PLL141XX_ENABLE)) {
|
||||
for (timeout = 0;; timeout++) {
|
||||
if (pwrcal_getbit(clk->offset, PLL141XX_LOCKED))
|
||||
break;
|
||||
if (timeout > CLK_WAIT_CNT)
|
||||
return -1;
|
||||
cpu_relax();
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
|
||||
static int _clk_pll141xx_set_rate(struct pwrcal_clk *clk,
|
||||
unsigned long long rate)
|
||||
{
|
||||
struct pwrcal_pll *pll = to_pll(clk);
|
||||
struct pll_spec *pll_spec;
|
||||
struct pwrcal_pll_rate_table tmp_rate_table;
|
||||
const struct pwrcal_pll_rate_table *rate_table;
|
||||
|
||||
if (rate == 0) {
|
||||
if (_clk_pll141xx_is_enabled(clk) != 0)
|
||||
if (_clk_pll141xx_disable(clk))
|
||||
goto errorout;
|
||||
return 0;
|
||||
}
|
||||
|
||||
rate_table = _clk_get_pll_settings(pll, rate);
|
||||
if (rate_table == NULL) {
|
||||
pll_spec = clk_pll_get_spec(clk);
|
||||
if (pll_spec == NULL)
|
||||
goto errorout;
|
||||
|
||||
if (_clk_pll141xx_find_pms(pll_spec, &tmp_rate_table, rate)) {
|
||||
pr_err("can't find pms value for rate(%lldHz) of \'%s\'",
|
||||
rate,
|
||||
clk->name);
|
||||
goto errorout;
|
||||
}
|
||||
|
||||
rate_table = &tmp_rate_table;
|
||||
|
||||
pr_warn("not exist in rate table, p(%d), m(%d), s(%d), fout(%lldHz) %s",
|
||||
rate_table->pdiv,
|
||||
rate_table->mdiv,
|
||||
rate_table->sdiv,
|
||||
rate,
|
||||
clk->name);
|
||||
}
|
||||
|
||||
if (_clk_pll141xx_set_pms(clk, rate_table))
|
||||
goto errorout;
|
||||
|
||||
if (rate != 0) {
|
||||
if (_clk_pll141xx_is_enabled(clk) == 0)
|
||||
_clk_pll141xx_enable(clk);
|
||||
}
|
||||
return 0;
|
||||
|
||||
errorout:
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
static unsigned long long _clk_pll141xx_get_rate(struct pwrcal_clk *clk)
|
||||
{
|
||||
unsigned int mdiv, pdiv, sdiv, pll_con0;
|
||||
unsigned long long fout;
|
||||
|
||||
if (_clk_pll141xx_is_enabled(clk) == 0)
|
||||
return 0;
|
||||
pll_con0 = pwrcal_readl(clk->offset);
|
||||
mdiv = (pll_con0 >> PLL141XX_MDIV_SHIFT) & PLL141XX_MDIV_MASK;
|
||||
pdiv = (pll_con0 >> PLL141XX_PDIV_SHIFT) & PLL141XX_PDIV_MASK;
|
||||
sdiv = (pll_con0 >> PLL141XX_SDIV_SHIFT) & PLL141XX_SDIV_MASK;
|
||||
|
||||
if (pdiv == 0) {
|
||||
pr_err("pdiv is 0, id(%s)", clk->name);
|
||||
return 0;
|
||||
}
|
||||
fout = FIN_HZ_26M * mdiv;
|
||||
do_div(fout, (pdiv << sdiv));
|
||||
return (unsigned long long)fout;
|
||||
}
|
||||
|
||||
static int _clk_pll1431x_find_pms(struct pll_spec *pll_spec,
|
||||
struct pwrcal_pll_rate_table *rate_table,
|
||||
unsigned long long rate)
|
||||
{
|
||||
unsigned int p, m, s;
|
||||
signed short k;
|
||||
unsigned long long fref, fvco, fout;
|
||||
unsigned long long tmprate, tmpfout;
|
||||
|
||||
for (p = pll_spec->pdiv_min; p <= pll_spec->pdiv_max; p++) {
|
||||
fref = FIN_HZ_26M / p;
|
||||
if ((fref < pll_spec->fref_min) || (fref > pll_spec->fref_max))
|
||||
continue;
|
||||
|
||||
for (s = pll_spec->sdiv_min; s <= pll_spec->sdiv_max; s++) {
|
||||
tmprate = rate;
|
||||
do_div(tmprate, MHZ);
|
||||
tmprate = tmprate * p * (1 << s);
|
||||
do_div(tmprate, (FIN_HZ_26M / MHZ));
|
||||
m = (unsigned int)tmprate;
|
||||
|
||||
if ((m < pll_spec->mdiv_min)
|
||||
|| (m > pll_spec->mdiv_max))
|
||||
continue;
|
||||
|
||||
tmprate = rate;
|
||||
do_div(tmprate, MHZ);
|
||||
tmprate = tmprate * p * (1 << s);
|
||||
do_div(tmprate, (FIN_HZ_26M / MHZ));
|
||||
tmprate = (tmprate - m) * 65536;
|
||||
k = (unsigned int)tmprate;
|
||||
if ((k < pll_spec->kdiv_min)
|
||||
|| (k > pll_spec->kdiv_max))
|
||||
continue;
|
||||
|
||||
fvco = FIN_HZ_26M * ((m << 16) + k);
|
||||
do_div(fvco, p);
|
||||
fvco >>= 16;
|
||||
if ((fvco < pll_spec->fvco_min)
|
||||
|| (fvco > pll_spec->fvco_max))
|
||||
continue;
|
||||
|
||||
fout = fvco >> s;
|
||||
if ((fout >= pll_spec->fout_min)
|
||||
&& (fout <= pll_spec->fout_max)) {
|
||||
tmprate = rate;
|
||||
do_div(tmprate, KHZ);
|
||||
tmpfout = fout;
|
||||
do_div(tmpfout, KHZ);
|
||||
if (tmprate == tmpfout) {
|
||||
rate_table->rate = fout;
|
||||
rate_table->pdiv = p;
|
||||
rate_table->mdiv = m;
|
||||
rate_table->sdiv = s;
|
||||
rate_table->kdiv = k;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int _clk_pll1431x_is_enabled(struct pwrcal_clk *clk)
|
||||
{
|
||||
return (int)(pwrcal_getbit(clk->offset, PLL1431X_ENABLE));
|
||||
}
|
||||
|
||||
static int _clk_pll1431x_enable(struct pwrcal_clk *clk)
|
||||
{
|
||||
int timeout;
|
||||
|
||||
pwrcal_setbit(clk->offset, PLL1431X_ENABLE, 1);
|
||||
|
||||
for (timeout = 0;; timeout++) {
|
||||
if (pwrcal_getbit(clk->offset, PLL1431X_LOCKED))
|
||||
break;
|
||||
if (timeout > CLK_WAIT_CNT)
|
||||
return -1;
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _clk_pll1431x_disable(struct pwrcal_clk *clk)
|
||||
{
|
||||
pwrcal_setbit(clk->offset, PLL1431X_ENABLE, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int _clk_pll1431x_is_disabled_bypass(struct pwrcal_clk *clk)
|
||||
{
|
||||
if (pwrcal_getbit(clk->offset + 2, PLL1431X_BYPASS))
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int _clk_pll1431x_set_bypass(struct pwrcal_clk *clk, int bypass_disable)
|
||||
{
|
||||
if (bypass_disable == 0)
|
||||
pwrcal_setbit(clk->offset + 2, PLL1431X_BYPASS, 1);
|
||||
else
|
||||
pwrcal_setbit(clk->offset + 2, PLL1431X_BYPASS, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _clk_pll1431x_set_pms(struct pwrcal_clk *clk,
|
||||
const struct pwrcal_pll_rate_table *rate_table)
|
||||
{
|
||||
unsigned int mdiv, pdiv, sdiv, pll_con0, pll_con1;
|
||||
signed short kdiv;
|
||||
int timeout;
|
||||
|
||||
pdiv = rate_table->pdiv;
|
||||
mdiv = rate_table->mdiv;
|
||||
sdiv = rate_table->sdiv;
|
||||
kdiv = rate_table->kdiv;
|
||||
|
||||
pll_con0 = pwrcal_readl(clk->offset);
|
||||
pll_con1 = pwrcal_readl(clk->offset + 1);
|
||||
pll_con0 &= ~((PLL1431X_MDIV_MASK << PLL1431X_MDIV_SHIFT)
|
||||
| (PLL1431X_PDIV_MASK << PLL1431X_PDIV_SHIFT)
|
||||
| (PLL1431X_SDIV_MASK << PLL1431X_SDIV_SHIFT));
|
||||
pll_con0 |= (mdiv << PLL1431X_MDIV_SHIFT)
|
||||
| (pdiv << PLL1431X_PDIV_SHIFT)
|
||||
| (sdiv << PLL1431X_SDIV_SHIFT);
|
||||
pll_con0 &= ~(1 << 26);
|
||||
pll_con0 |= (1 << 5);
|
||||
|
||||
pll_con1 &= ~(PLL1431X_K_MASK << PLL1431X_K_SHIFT);
|
||||
pll_con1 |= (kdiv << PLL1431X_K_SHIFT);
|
||||
|
||||
if (kdiv == 0)
|
||||
pwrcal_writel(clk->status, pdiv * 3000);
|
||||
else
|
||||
pwrcal_writel(clk->status, pdiv * 3000);
|
||||
pwrcal_writel(clk->offset, pll_con0);
|
||||
pwrcal_writel(clk->offset + 1, pll_con1);
|
||||
|
||||
if (pll_con0 & (1 << PLL1431X_ENABLE)) {
|
||||
for (timeout = 0;; timeout++) {
|
||||
if (pwrcal_getbit(clk->offset, PLL1431X_LOCKED))
|
||||
break;
|
||||
if (timeout > CLK_WAIT_CNT)
|
||||
return -1;
|
||||
cpu_relax();
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _clk_pll1431x_set_rate(struct pwrcal_clk *clk,
|
||||
unsigned long long rate)
|
||||
{
|
||||
struct pwrcal_pll *pll = to_pll(clk);
|
||||
struct pwrcal_pll_rate_table tmp_rate_table;
|
||||
const struct pwrcal_pll_rate_table *rate_table;
|
||||
struct pll_spec *pll_spec;
|
||||
|
||||
if (rate == 0) {
|
||||
if (_clk_pll1431x_is_enabled(clk) != 0)
|
||||
if (_clk_pll1431x_disable(clk))
|
||||
goto errorout;
|
||||
return 0;
|
||||
}
|
||||
|
||||
rate_table = _clk_get_pll_settings(pll, rate);
|
||||
if (rate_table == NULL) {
|
||||
pll_spec = clk_pll_get_spec(clk);
|
||||
if (pll_spec == NULL)
|
||||
goto errorout;
|
||||
|
||||
if (_clk_pll1431x_find_pms(pll_spec, &tmp_rate_table, rate) < 0) {
|
||||
pr_err("can't find pms value for rate(%lldHz) of %s",
|
||||
rate,
|
||||
clk->name);
|
||||
goto errorout;
|
||||
}
|
||||
|
||||
rate_table = &tmp_rate_table;
|
||||
pr_warn("not exist in rate table, p(%d) m(%d) s(%d) k(%d) fout(%lld Hz) of %s",
|
||||
rate_table->pdiv,
|
||||
rate_table->mdiv,
|
||||
rate_table->sdiv,
|
||||
rate_table->kdiv,
|
||||
rate,
|
||||
clk->name);
|
||||
}
|
||||
|
||||
if (_clk_pll1431x_set_pms(clk, rate_table))
|
||||
goto errorout;
|
||||
|
||||
if (rate != 0) {
|
||||
if (_clk_pll1431x_is_enabled(clk) == 0)
|
||||
_clk_pll1431x_enable(clk);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
errorout:
|
||||
return -1;
|
||||
}
|
||||
|
||||
static unsigned long long _clk_pll1431x_get_rate(struct pwrcal_clk *clk)
|
||||
{
|
||||
unsigned int mdiv, pdiv, sdiv, pll_con0, pll_con1;
|
||||
signed short kdiv;
|
||||
unsigned long long fout;
|
||||
|
||||
if (_clk_pll1431x_is_enabled(clk) == 0)
|
||||
return 0;
|
||||
|
||||
pll_con0 = pwrcal_readl(clk->offset);
|
||||
pll_con1 = pwrcal_readl(clk->offset + 1);
|
||||
mdiv = (pll_con0 >> PLL1431X_MDIV_SHIFT) & PLL1431X_MDIV_MASK;
|
||||
pdiv = (pll_con0 >> PLL1431X_PDIV_SHIFT) & PLL1431X_PDIV_MASK;
|
||||
sdiv = (pll_con0 >> PLL1431X_SDIV_SHIFT) & PLL1431X_SDIV_MASK;
|
||||
|
||||
kdiv = (short)(pll_con1 >> PLL1431X_K_SHIFT) & PLL1431X_K_MASK;
|
||||
|
||||
if (pdiv == 0) {
|
||||
pr_err("pdiv is 0, id(%s)", clk->name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
fout = FIN_HZ_26M * ((mdiv << 16) + kdiv);
|
||||
do_div(fout, (pdiv << sdiv));
|
||||
fout >>= 16;
|
||||
|
||||
return (unsigned long long)fout;
|
||||
}
|
||||
|
||||
struct pwrcal_pll_ops pll141xx_ops = {
|
||||
.is_enabled = _clk_pll141xx_is_enabled,
|
||||
.enable = _clk_pll141xx_enable,
|
||||
.disable = _clk_pll141xx_disable,
|
||||
.set_rate = _clk_pll141xx_set_rate,
|
||||
.get_rate = _clk_pll141xx_get_rate,
|
||||
};
|
||||
|
||||
struct pwrcal_pll_ops pll1431x_ops = {
|
||||
.is_enabled = _clk_pll1431x_is_enabled,
|
||||
.enable = _clk_pll1431x_enable,
|
||||
.disable = _clk_pll1431x_disable,
|
||||
.set_rate = _clk_pll1431x_set_rate,
|
||||
.get_rate = _clk_pll1431x_get_rate,
|
||||
};
|
||||
198
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-pmu.c
Normal file
198
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-pmu.c
Normal file
|
|
@ -0,0 +1,198 @@
|
|||
#include "../pwrcal.h"
|
||||
#include "../pwrcal-env.h"
|
||||
#include "../pwrcal-rae.h"
|
||||
#include "../pwrcal-pmu.h"
|
||||
#include "S5E7870-cmusfr.h"
|
||||
#include "S5E7870-pmusfr.h"
|
||||
#include "S5E7870-cmu.h"
|
||||
|
||||
|
||||
static void dispaud_prev(int enable)
|
||||
{
|
||||
if (enable == 0) {
|
||||
pwrcal_setf(CLK_ENABLE_CLK_DISPAUD_BUS, 0, 0x7, 0x7);
|
||||
pwrcal_setf(CLK_ENABLE_CLK_DISPAUD_APB, 0, 0x1, 0x1);
|
||||
pwrcal_setbit(CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER, 12, 0);
|
||||
pwrcal_setbit(CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER, 12, 0);
|
||||
pwrcal_setbit(CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER, 27, 1);
|
||||
pwrcal_setbit(CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER, 27, 1);
|
||||
}
|
||||
|
||||
pwrcal_setf(PMU_CLKRUN_CMU_DISPAUD_SYS_PWR_REG, 0, 0x1, 0x0);
|
||||
pwrcal_setf(PMU_CLKSTOP_CMU_DISPAUD_SYS_PWR_REG, 0, 0x1, 0x0);
|
||||
pwrcal_setf(PMU_DISABLE_PLL_CMU_DISPAUD_SYS_PWR_REG, 0, 0x1, 0x0);
|
||||
pwrcal_setf(PMU_RESET_LOGIC_DISPAUD_SYS_PWR_REG, 0, 0x1, 0x0);
|
||||
pwrcal_setf(PMU_RESET_CMU_DISPAUD_SYS_PWR_REG, 0, 0x1, 0x0);
|
||||
}
|
||||
|
||||
static void g3d_prev(int enable)
|
||||
{
|
||||
if (enable == 0) {
|
||||
pwrcal_setf(CLK_ENABLE_CLK_G3D_BUS, 1, 0x3, 0x3);
|
||||
pwrcal_setf(CLK_ENABLE_CLK_G3D_APB, 1, 0x1, 0x1);
|
||||
}
|
||||
|
||||
pwrcal_setf(PMU_CLKRUN_CMU_G3D_SYS_PWR_REG, 0, 0x1, 0x0);
|
||||
pwrcal_setf(PMU_CLKSTOP_CMU_G3D_SYS_PWR_REG, 0, 0x1, 0x0);
|
||||
pwrcal_setf(PMU_DISABLE_PLL_CMU_G3D_SYS_PWR_REG, 0, 0x1, 0x0);
|
||||
pwrcal_setf(PMU_RESET_LOGIC_G3D_SYS_PWR_REG, 0, 0x1, 0x0);
|
||||
pwrcal_setf(PMU_RESET_CMU_G3D_SYS_PWR_REG, 0, 0x1, 0x0);
|
||||
|
||||
}
|
||||
|
||||
static void isp_prev(int enable)
|
||||
{
|
||||
if (enable == 0) {
|
||||
pwrcal_setf(CLK_ENABLE_CLK_ISP_VRA, 0, 0x1, 0x1);
|
||||
pwrcal_setf(CLK_ENABLE_CLK_ISP_APB, 0, 0x1, 0x1);
|
||||
pwrcal_setf(CLK_ENABLE_CLK_ISP_ISPD, 0, 0x1, 0x1);
|
||||
pwrcal_setf(CLK_ENABLE_CLK_ISP_CAM, 0, 0x1, 0x1);
|
||||
pwrcal_setf(CLK_ENABLE_CLK_ISP_ISP, 0, 0x1, 0x1);
|
||||
pwrcal_setbit(CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER, 12, 0);
|
||||
pwrcal_setbit(CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER, 12, 0);
|
||||
pwrcal_setbit(CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER, 27, 1);
|
||||
pwrcal_setbit(CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER, 27, 1);
|
||||
|
||||
#if 0 // plz, check the sfr name first
|
||||
while (pwrcal_getf((void *)0x14403020, 0, 0x1) != 0x0);
|
||||
while (pwrcal_getf((void *)0x14443010, 0, 0x1) != 0x0);
|
||||
while (pwrcal_getf((void *)0x1444B010, 0, 0x1) != 0x0);
|
||||
#endif
|
||||
}
|
||||
|
||||
pwrcal_setf(PMU_CLKRUN_CMU_ISP_SYS_PWR_REG, 0, 0x1, 0x0);
|
||||
pwrcal_setf(PMU_CLKSTOP_CMU_ISP_SYS_PWR_REG, 0, 0x1, 0x0);
|
||||
pwrcal_setf(PMU_DISABLE_PLL_CMU_ISP_SYS_PWR_REG, 0, 0x1, 0x0);
|
||||
pwrcal_setf(PMU_RESET_LOGIC_ISP_SYS_PWR_REG, 0, 0x1, 0x0);
|
||||
pwrcal_setf(PMU_RESET_CMU_ISP_SYS_PWR_REG, 0, 0x1, 0x0);
|
||||
}
|
||||
|
||||
static void mfcmscl_prev(int enable)
|
||||
{
|
||||
if (enable == 0) {
|
||||
pwrcal_setf(CLK_ENABLE_CLK_MFCMSCL_MSCL, 0, 0x1D, 0x1D);
|
||||
pwrcal_setf(CLK_ENABLE_CLK_MFCMSCL_APB, 0, 0x1, 0x1);
|
||||
pwrcal_setf(CLK_ENABLE_CLK_MFCMSCL_MFC, 0, 0x1, 0x1);
|
||||
}
|
||||
|
||||
pwrcal_setf(PMU_CLKRUN_CMU_MFCMSCL_SYS_PWR_REG, 0, 0x1, 0x0);
|
||||
pwrcal_setf(PMU_CLKSTOP_CMU_MFCMSCL_SYS_PWR_REG, 0, 0x1, 0x0);
|
||||
pwrcal_setf(PMU_DISABLE_PLL_CMU_MFCMSCL_SYS_PWR_REG, 0, 0x1, 0x0);
|
||||
pwrcal_setf(PMU_RESET_LOGIC_MFCMSCL_SYS_PWR_REG, 0, 0x1, 0x0);
|
||||
pwrcal_setf(PMU_RESET_CMU_MFCMSCL_SYS_PWR_REG, 0, 0x1, 0x0);
|
||||
|
||||
}
|
||||
|
||||
static void dispaud_post(int enable)
|
||||
{
|
||||
if (enable == 1) {
|
||||
pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_PPMU));
|
||||
pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_DISP));
|
||||
pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS));
|
||||
pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_DISP));
|
||||
pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_EXT2AUD_BCK_gpio_I2S));
|
||||
pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_AUD_I2S_BCLK_BT_IN));
|
||||
pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_CP2AUD_BCK));
|
||||
pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_AUD_I2S_BCLK_FM_IN));
|
||||
pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_VCLK));
|
||||
pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_ECLK));
|
||||
pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_MIXER_AUD_IPCLKPORT_SYSCLK));
|
||||
pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD));
|
||||
pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AUD_IPCLKPORT_I2SCODCLKI));
|
||||
pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD_AMP));
|
||||
pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AMP_IPCLKPORT_I2SCODCLKI));
|
||||
|
||||
/*non used disable*/
|
||||
pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_VPP));
|
||||
pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_DSIM1_IPCLKPORT_I_TXBYTECLKHS));
|
||||
pwrcal_gate_disable(CLK(DISPAUD_GATE_CLK_DISPAUD_UID_DSIM1_IPCLKPORT_I_RXCLKESC0));
|
||||
}
|
||||
}
|
||||
|
||||
static void g3d_post(int enable)
|
||||
{
|
||||
if (enable == 1) {
|
||||
pwrcal_gate_disable(CLK(G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_ACLK));
|
||||
pwrcal_gate_disable(CLK(G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_PCLK));
|
||||
pwrcal_gate_disable(CLK(G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_ACLK));
|
||||
pwrcal_gate_disable(CLK(G3D_GATE_CLK_G3D_UID_G3D_IPCLKPORT_CLK));
|
||||
pwrcal_gate_disable(CLK(G3D_GATE_CLK_G3D_UID_ASYNCS_D0_G3D_IPCLKPORT_I_CLK));
|
||||
pwrcal_gate_disable(CLK(G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKM));
|
||||
pwrcal_gate_disable(CLK(G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK));
|
||||
pwrcal_gate_disable(CLK(G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_PCLK));
|
||||
}
|
||||
}
|
||||
|
||||
static void isp_post(int enable)
|
||||
{
|
||||
if (enable == 1) {
|
||||
pwrcal_gate_disable(CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_ISPD_PPMU));
|
||||
pwrcal_gate_disable(CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_ISPD));
|
||||
pwrcal_gate_disable(CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_CAM));
|
||||
pwrcal_gate_disable(CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_CAM_HALF));
|
||||
pwrcal_gate_disable(CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_VRA));
|
||||
|
||||
/*non used disable*/
|
||||
pwrcal_gate_disable(CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_ISP));
|
||||
}
|
||||
}
|
||||
|
||||
static void mfcmscl_post(int enable)
|
||||
{
|
||||
if (enable == 1) {
|
||||
pwrcal_gate_disable(CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_PPMU));
|
||||
pwrcal_gate_disable(CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_D));
|
||||
pwrcal_gate_disable(CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL));
|
||||
pwrcal_gate_disable(CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_BI));
|
||||
pwrcal_gate_disable(CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_POLY));
|
||||
pwrcal_gate_disable(CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_JPEG));
|
||||
pwrcal_gate_disable(CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC));
|
||||
}
|
||||
}
|
||||
|
||||
static void dispaud_config(int enable)
|
||||
{
|
||||
pwrcal_setf(PMU_DISPAUD_OPTION, 0, 0x3, 0x2);
|
||||
pwrcal_setf(PMU_PAD_RETENTION_AUD_OPTION, 0, 0xFFFFFFFF, 0x10000000);
|
||||
}
|
||||
|
||||
static void g3d_config(int enable)
|
||||
{
|
||||
pwrcal_setf(PMU_G3D_OPTION, 0, 0x1, 0x1);
|
||||
pwrcal_setf(PMU_G3D_DURATION0, 4, 0xFF, 0x0);
|
||||
}
|
||||
|
||||
static void isp_config(int enable)
|
||||
{
|
||||
pwrcal_setf(PMU_ISP_OPTION, 0, 0x3, 0x2);
|
||||
}
|
||||
|
||||
static void mfcmscl_config(int enable)
|
||||
{
|
||||
pwrcal_setf(PMU_MFCMSCL_OPTION, 0, 0x3, 0x2);
|
||||
}
|
||||
|
||||
BLKPWR(blkpwr_dispaud, PMU_DISPAUD_CONFIGURATION, 0, 0xF, PMU_DISPAUD_STATUS, 0, 0xF, dispaud_config, dispaud_prev, dispaud_post);
|
||||
BLKPWR(blkpwr_g3d, PMU_G3D_CONFIGURATION, 0, 0xF, PMU_G3D_STATUS, 0, 0xF, g3d_config, g3d_prev, g3d_post);
|
||||
BLKPWR(blkpwr_isp, PMU_ISP_CONFIGURATION, 0, 0xF, PMU_ISP_STATUS, 0, 0xF, isp_config, isp_prev, isp_post);
|
||||
BLKPWR(blkpwr_mfcmscl, PMU_MFCMSCL_CONFIGURATION, 0, 0xF, PMU_MFCMSCL_STATUS, 0, 0xF, mfcmscl_config, mfcmscl_prev, mfcmscl_post);
|
||||
|
||||
|
||||
struct cal_pd *pwrcal_blkpwr_list[4];
|
||||
unsigned int pwrcal_blkpwr_size = 4;
|
||||
|
||||
static int blkpwr_init(void)
|
||||
{
|
||||
pwrcal_blkpwr_list[0] = &blkpwr_blkpwr_dispaud;
|
||||
pwrcal_blkpwr_list[1] = &blkpwr_blkpwr_g3d;
|
||||
pwrcal_blkpwr_list[2] = &blkpwr_blkpwr_isp;
|
||||
pwrcal_blkpwr_list[3] = &blkpwr_blkpwr_mfcmscl;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct cal_pd_ops cal_pd_ops = {
|
||||
.pd_control = blkpwr_control,
|
||||
.pd_status = blkpwr_status,
|
||||
.pd_init = blkpwr_init,
|
||||
};
|
||||
1429
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-pmusfr.h
Normal file
1429
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-pmusfr.h
Normal file
File diff suppressed because it is too large
Load diff
40
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-rae.c
Normal file
40
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-rae.c
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
#include "../pwrcal-rae.h"
|
||||
#include "S5E7870-sfrbase.h"
|
||||
|
||||
#ifdef PWRCAL_TARGET_LINUX
|
||||
|
||||
struct v2p_sfr v2psfrmap[] = {
|
||||
DEFINE_V2P(CMU_CPUCL0_BASE, 0x10900000),
|
||||
DEFINE_V2P(CMU_CPUCL1_BASE, 0x10800000),
|
||||
DEFINE_V2P(CMU_FSYS_BASE, 0x13730000),
|
||||
DEFINE_V2P(CMU_G3D_BASE, 0x11460000),
|
||||
DEFINE_V2P(CMU_ISP_BASE, 0x144D0000),
|
||||
DEFINE_V2P(CMU_MFCMSCL_BASE, 0x12CB0000),
|
||||
DEFINE_V2P(CMU_MIF_BASE, 0x10460000),
|
||||
DEFINE_V2P(CMU_PERI_BASE, 0x101F0000),
|
||||
DEFINE_V2P(CMU_DISPAUD_BASE, 0x148D0000),
|
||||
|
||||
DEFINE_V2P(PMU_CPUCL0_BASE, 0x10920000),
|
||||
DEFINE_V2P(PMU_CPUCL1_BASE, 0x10820000),
|
||||
DEFINE_V2P(PMU_FSYS_BASE, 0x13740000),
|
||||
DEFINE_V2P(PMU_G3D_BASE, 0x11470000),
|
||||
DEFINE_V2P(PMU_ISP_BASE, 0x144E0000),
|
||||
DEFINE_V2P(PMU_MFCMSCL_BASE, 0x12CC0000),
|
||||
DEFINE_V2P(PMU_MIF_BASE, 0x10470000),
|
||||
DEFINE_V2P(PMU_PERI_BASE, 0x101E0000),
|
||||
DEFINE_V2P(PMU_ALIVE_BASE, 0x10480000),
|
||||
|
||||
DEFINE_V2P(DREX0_BASE, 0x10400000),
|
||||
DEFINE_V2P(DREX0_PF_BASE, 0x10410000),
|
||||
DEFINE_V2P(DREX0_SECURE_BASE, 0x10420000),
|
||||
DEFINE_V2P(DREX0_PF_SECURE_BASE, 0x10430000),
|
||||
DEFINE_V2P(DREXPHY0_BASE, 0x10440000),
|
||||
|
||||
DEFINE_V2P(SYSREG_CPUCL0_BASE, 0x10910000),
|
||||
DEFINE_V2P(SYSREG_CPUCL1_BASE, 0x10810000),
|
||||
DEFINE_V2P(SYSREG_G3D_BASE, 0x11450000),
|
||||
};
|
||||
|
||||
int num_of_v2psfrmap = sizeof(v2psfrmap) / sizeof(v2psfrmap[0]);
|
||||
void *spinlock_enable_offset = (void *)PMU_CPUCL0_BASE;
|
||||
#endif
|
||||
75
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-sfrbase.h
Normal file
75
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-sfrbase.h
Normal file
|
|
@ -0,0 +1,75 @@
|
|||
#ifndef __EXYNOS7870_SFRBASE_H__
|
||||
#define __EXYNOS7870_SFRBASE_H__
|
||||
|
||||
#include "../pwrcal-env.h"
|
||||
|
||||
#ifdef PWRCAL_TARGET_FW
|
||||
|
||||
#define CMU_CPUCL0_BASE 0x10900000
|
||||
#define CMU_CPUCL1_BASE 0x10800000
|
||||
#define CMU_FSYS_BASE 0x13730000
|
||||
#define CMU_G3D_BASE 0x11460000
|
||||
#define CMU_ISP_BASE 0x144D0000
|
||||
#define CMU_MFCMSCL_BASE 0x12CB0000
|
||||
#define CMU_MIF_BASE 0x10460000
|
||||
#define CMU_PERI_BASE 0x101F0000
|
||||
#define CMU_DISPAUD_BASE 0x148D0000
|
||||
|
||||
#define PMU_CPUCL0_BASE 0x10920000
|
||||
#define PMU_CPUCL1_BASE 0x10820000
|
||||
#define PMU_FSYS_BASE 0x13740000
|
||||
#define PMU_G3D_BASE 0x11470000
|
||||
#define PMU_ISP_BASE 0x144E0000
|
||||
#define PMU_MFCMSCL_BASE 0x12CC0000
|
||||
#define PMU_MIF_BASE 0x10470000
|
||||
#define PMU_PERI_BASE 0x101E0000
|
||||
#define PMU_ALIVE_BASE 0x10480000
|
||||
|
||||
#define DREX0_BASE 0x10400000
|
||||
#define DREX0_PF_BASE 0x10410000
|
||||
#define DREX0_SECURE_BASE 0x10420000
|
||||
#define DREX0_PF_SECURE_BASE 0x10430000
|
||||
#define DREXPHY0_BASE 0x10440000
|
||||
|
||||
#define SYSREG_CPUCL0_BASE 0x10910000
|
||||
#define SYSREG_CPUCL1_BASE 0x10810000
|
||||
#define SYSREG_G3D_BASE 0x11450000
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef PWRCAL_TARGET_LINUX
|
||||
|
||||
#define CMU_CPUCL0_BASE 0x00010000
|
||||
#define CMU_CPUCL1_BASE 0x00020000
|
||||
#define CMU_FSYS_BASE 0x00030000
|
||||
#define CMU_G3D_BASE 0x00040000
|
||||
#define CMU_ISP_BASE 0x00050000
|
||||
#define CMU_MFCMSCL_BASE 0x00060000
|
||||
#define CMU_MIF_BASE 0x00070000
|
||||
#define CMU_PERI_BASE 0x00080000
|
||||
#define CMU_DISPAUD_BASE 0x00090000
|
||||
|
||||
#define PMU_CPUCL0_BASE 0x00100000
|
||||
#define PMU_CPUCL1_BASE 0x00110000
|
||||
#define PMU_FSYS_BASE 0x00120000
|
||||
#define PMU_G3D_BASE 0x00130000
|
||||
#define PMU_ISP_BASE 0x00140000
|
||||
#define PMU_MFCMSCL_BASE 0x00150000
|
||||
#define PMU_MIF_BASE 0x00160000
|
||||
#define PMU_PERI_BASE 0x00170000
|
||||
#define PMU_ALIVE_BASE 0x00180000
|
||||
|
||||
#define DREX0_BASE 0x00190000
|
||||
#define DREX0_PF_BASE 0x00200000
|
||||
#define DREX0_SECURE_BASE 0x00210000
|
||||
#define DREX0_PF_SECURE_BASE 0x00220000
|
||||
#define DREXPHY0_BASE 0x00230000
|
||||
|
||||
#define SYSREG_CPUCL0_BASE 0x00240000
|
||||
#define SYSREG_CPUCL1_BASE 0x00250000
|
||||
#define SYSREG_G3D_BASE 0X00260000
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
1074
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-syspwr.c
Normal file
1074
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-syspwr.c
Normal file
File diff suppressed because it is too large
Load diff
13
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-sysreg.h
Normal file
13
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-sysreg.h
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
#ifndef __EXYNOS7870_H__
|
||||
#define __EXYNOS7870_H__
|
||||
|
||||
#include "S5E7870-sfrbase.h"
|
||||
|
||||
#define CPUCL0_EMA_CON ((void *)(SYSREG_CPUCL0_BASE + 0x0330))
|
||||
#define CPUCL0_EMA_REG1 ((void *)(SYSREG_CPUCL0_BASE + 0x0004))
|
||||
#define CPUCL1_EMA_CON ((void *)(SYSREG_CPUCL1_BASE + 0x0330))
|
||||
#define CPUCL1_EMA_REG1 ((void *)(SYSREG_CPUCL1_BASE + 0x0004))
|
||||
#define GPU_EMA_RF2_UHD_CON ((void *)(SYSREG_G3D_BASE + 0x0318))
|
||||
#define CAM_EMA_RF2_UHD_CON ((void *)(SYSREG_ISP_BASE + 0x0318))
|
||||
#define CAM_EMA_RF2_HS_CON ((void *)(SYSREG_ISP_BASE + 0x2718))
|
||||
#endif
|
||||
168
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-vclk-internal.h
Normal file
168
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-vclk-internal.h
Normal file
|
|
@ -0,0 +1,168 @@
|
|||
#ifndef __EXYNOS7870_VCLKS_H__
|
||||
#define __EXYNOS7870_VCLKS_H__
|
||||
|
||||
#include "../pwrcal-vclk.h"
|
||||
#include "../pwrcal-pmu.h"
|
||||
#include "S5E7870-vclk.h"
|
||||
|
||||
M1D1G1_EXTERN(sclk_decon_vclk)
|
||||
M1D1G1_EXTERN(sclk_decon_vclk_local)
|
||||
M1D1G1_EXTERN(sclk_decon_eclk)
|
||||
M1D1G1_EXTERN(sclk_decon_eclk_local)
|
||||
M1D1G1_EXTERN(sclk_mmc0)
|
||||
M1D1G1_EXTERN(sclk_mmc1)
|
||||
M1D1G1_EXTERN(sclk_mmc2)
|
||||
M1D1G1_EXTERN(sclk_ufsunipro)
|
||||
M1D1G1_EXTERN(sclk_ufsunipro_cfg)
|
||||
M1D1G1_EXTERN(sclk_usb20drd)
|
||||
M1D1G1_EXTERN(sclk_uart_sensor)
|
||||
M1D1G1_EXTERN(sclk_uart_btwififm)
|
||||
M1D1G1_EXTERN(sclk_uart_debug)
|
||||
M1D1G1_EXTERN(sclk_spi_frontfrom)
|
||||
M1D1G1_EXTERN(sclk_spi_rearfrom)
|
||||
M1D1G1_EXTERN(sclk_spi_ese)
|
||||
M1D1G1_EXTERN(sclk_spi_voiceprocessor)
|
||||
M1D1G1_EXTERN(sclk_spi_sensorhub)
|
||||
M1D1G1_EXTERN(sclk_isp_sensor0)
|
||||
M1D1G1_EXTERN(sclk_isp_sensor1)
|
||||
M1D1G1_EXTERN(sclk_isp_sensor2)
|
||||
|
||||
PXMXDX_EXTERN(pxmxdx_top)
|
||||
PXMXDX_EXTERN(pxmxdx_disp)
|
||||
PXMXDX_EXTERN(pxmxdx_mfcmscl)
|
||||
PXMXDX_EXTERN(pxmxdx_isp_vra)
|
||||
PXMXDX_EXTERN(pxmxdx_isp_cam)
|
||||
PXMXDX_EXTERN(pxmxdx_isp_isp)
|
||||
|
||||
P1_EXTERN(p1_disp_pll)
|
||||
P1_EXTERN(p1_aud_pll)
|
||||
P1_EXTERN(p1_usb_pll)
|
||||
P1_EXTERN(p1_isp_pll)
|
||||
|
||||
M1_EXTERN(m1_dummy)
|
||||
|
||||
D1_EXTERN(d1_dispaud_mi2s)
|
||||
D1_EXTERN(d1_dispaud_mixer)
|
||||
|
||||
GRPGATE_EXTERN(gate_cpucl0_ppmu)
|
||||
GRPGATE_EXTERN(gate_cpucl0_bts)
|
||||
GRPGATE_EXTERN(gate_cpucll_ppmu)
|
||||
GRPGATE_EXTERN(gate_cpucll_bts)
|
||||
GRPGATE_EXTERN(gate_mfcmscl_sysmmu_mscl)
|
||||
GRPGATE_EXTERN(gate_mfcmscl_sysmmu_mfc)
|
||||
GRPGATE_EXTERN(gate_mfcmscl_ppmu)
|
||||
GRPGATE_EXTERN(gate_mfcmscl_bts)
|
||||
GRPGATE_EXTERN(gate_mfcmscl_common)
|
||||
GRPGATE_EXTERN(gate_mfcmscl_common_mscl)
|
||||
GRPGATE_EXTERN(gate_mfcmscl_mscl_bi)
|
||||
GRPGATE_EXTERN(gate_mfcmscl_mscl_poly)
|
||||
GRPGATE_EXTERN(gate_mfcmscl_jpeg)
|
||||
GRPGATE_EXTERN(gate_mfcmscl_mfc)
|
||||
GRPGATE_EXTERN(gate_g3d_common)
|
||||
GRPGATE_EXTERN(gate_g3d_sysmmu)
|
||||
GRPGATE_EXTERN(gate_g3d_ppmu)
|
||||
GRPGATE_EXTERN(gate_g3d_bts)
|
||||
GRPGATE_EXTERN(gate_g3d_g3d)
|
||||
GRPGATE_EXTERN(gate_peri_peris0)
|
||||
GRPGATE_EXTERN(gate_peri_peric0)
|
||||
GRPGATE_EXTERN(gate_peri_peric1)
|
||||
GRPGATE_EXTERN(gate_peri_pwm_motor)
|
||||
GRPGATE_EXTERN(gate_peri_sclk_pwm_motor)
|
||||
GRPGATE_EXTERN(gate_peri_mct)
|
||||
GRPGATE_EXTERN(gate_peri_i2c_sensor2)
|
||||
GRPGATE_EXTERN(gate_peri_i2c_sensor1)
|
||||
GRPGATE_EXTERN(gate_peri_i2c_tsp)
|
||||
GRPGATE_EXTERN(gate_peri_i2c_touchkey)
|
||||
GRPGATE_EXTERN(gate_peri_i2c_fuelgauge)
|
||||
GRPGATE_EXTERN(gate_peri_i2c_spkamp)
|
||||
GRPGATE_EXTERN(gate_peri_i2c_nfc)
|
||||
GRPGATE_EXTERN(gate_peri_i2c_muic)
|
||||
GRPGATE_EXTERN(gate_peri_i2c_ifpmic)
|
||||
GRPGATE_EXTERN(gate_peri_hsi2c_frontcam)
|
||||
GRPGATE_EXTERN(gate_peri_hsi2c_maincam)
|
||||
GRPGATE_EXTERN(gate_peri_hsi2c_depthcam)
|
||||
GRPGATE_EXTERN(gate_peri_hsi2c_frontsensor)
|
||||
GRPGATE_EXTERN(gate_peri_hsi2c_rearaf)
|
||||
GRPGATE_EXTERN(gate_peri_hsi2c_rearsensor)
|
||||
GRPGATE_EXTERN(gate_peri_gpio_touch)
|
||||
GRPGATE_EXTERN(gate_peri_gpio_top)
|
||||
GRPGATE_EXTERN(gate_peri_gpio_nfc)
|
||||
GRPGATE_EXTERN(gate_peri_gpio_ese)
|
||||
GRPGATE_EXTERN(gate_peri_wdt_cpucl1)
|
||||
GRPGATE_EXTERN(gate_peri_wdt_cpucl0)
|
||||
GRPGATE_EXTERN(gate_peri_uart_debug)
|
||||
GRPGATE_EXTERN(gate_peri_uart_btwififm)
|
||||
GRPGATE_EXTERN(gate_peri_uart_sensor)
|
||||
GRPGATE_EXTERN(gate_peri_tmu_g3d)
|
||||
GRPGATE_EXTERN(gate_peri_tmu_cpucl1)
|
||||
GRPGATE_EXTERN(gate_peri_tmu_cpucl0)
|
||||
GRPGATE_EXTERN(gate_peri_spi_sensorhub)
|
||||
GRPGATE_EXTERN(gate_peri_spi_voiceprocessor)
|
||||
GRPGATE_EXTERN(gate_peri_spi_ese)
|
||||
GRPGATE_EXTERN(gate_peri_spi_rearfrom)
|
||||
GRPGATE_EXTERN(gate_peri_spi_frontfrom)
|
||||
GRPGATE_EXTERN(gate_peri_gpio_alive)
|
||||
GRPGATE_EXTERN(gate_peri_chipid)
|
||||
GRPGATE_EXTERN(gate_peri_otp_con_top)
|
||||
GRPGATE_EXTERN(gate_peri_rtc_alive)
|
||||
GRPGATE_EXTERN(gate_peri_rtc_top)
|
||||
GRPGATE_EXTERN(gate_fsys_common)
|
||||
GRPGATE_EXTERN(gate_fsys_common_sub1)
|
||||
GRPGATE_EXTERN(gate_fsys_common_sub2)
|
||||
GRPGATE_EXTERN(gate_fsys_sysmmu)
|
||||
GRPGATE_EXTERN(gate_fsys_ppmu)
|
||||
GRPGATE_EXTERN(gate_fsys_bts)
|
||||
GRPGATE_EXTERN(gate_fsys_usb20drd)
|
||||
GRPGATE_EXTERN(gate_fsys_mmc0)
|
||||
GRPGATE_EXTERN(gate_fsys_sclk_mmc0)
|
||||
GRPGATE_EXTERN(gate_fsys_mmc1)
|
||||
GRPGATE_EXTERN(gate_fsys_sclk_mmc1)
|
||||
GRPGATE_EXTERN(gate_fsys_mmc2)
|
||||
GRPGATE_EXTERN(gate_fsys_sclk_mmc2)
|
||||
GRPGATE_EXTERN(gate_fsys_sss)
|
||||
GRPGATE_EXTERN(gate_fsys_rtic)
|
||||
GRPGATE_EXTERN(gate_fsys_pdma0)
|
||||
GRPGATE_EXTERN(gate_fsys_pdma1)
|
||||
GRPGATE_EXTERN(gate_fsys_sromc)
|
||||
GRPGATE_EXTERN(gate_dispaud_disp)
|
||||
GRPGATE_EXTERN(gate_dispaud_aud)
|
||||
GRPGATE_EXTERN(gate_dispaud_sysmmu)
|
||||
GRPGATE_EXTERN(gate_dispaud_ppmu)
|
||||
GRPGATE_EXTERN(gate_dispaud_bts)
|
||||
GRPGATE_EXTERN(gate_dispaud_decon)
|
||||
GRPGATE_EXTERN(gate_dispaud_dsim0)
|
||||
GRPGATE_EXTERN(gate_dispaud_mixer)
|
||||
GRPGATE_EXTERN(gate_dispaud_mi2s_aud)
|
||||
GRPGATE_EXTERN(gate_dispaud_mi2s_amp)
|
||||
GRPGATE_EXTERN(gate_isp_common)
|
||||
GRPGATE_EXTERN(gate_isp_sysmmu)
|
||||
GRPGATE_EXTERN(gate_isp_ppmu)
|
||||
GRPGATE_EXTERN(gate_isp_bts)
|
||||
GRPGATE_EXTERN(gate_isp_cam)
|
||||
GRPGATE_EXTERN(gate_isp_isp)
|
||||
GRPGATE_EXTERN(gate_isp_vra)
|
||||
GRPGATE_EXTERN(gate_mif_adcif)
|
||||
GRPGATE_EXTERN(gate_mif_hsi2c_mif)
|
||||
GRPGATE_EXTERN(sclk_uart0)
|
||||
|
||||
|
||||
|
||||
UMUX_EXTERN(umux_dispaud_clkphy_dispaud_mipiphy_txbyteclkhs_user)
|
||||
UMUX_EXTERN(umux_dispaud_clkphy_dispaud_mipiphy_rxclkesc0_user)
|
||||
UMUX_EXTERN(umux_fsys_clkphy_fsys_usb20drd_phyclock_user)
|
||||
UMUX_EXTERN(umux_fsys_clkphy_fsys_ufs_tx0_symbol_user)
|
||||
UMUX_EXTERN(umux_fsys_clkphy_fsys_ufs_rx0_symbol_user)
|
||||
UMUX_EXTERN(umux_isp_clkphy_isp_s_rxbyteclkhs0_s4_user)
|
||||
UMUX_EXTERN(umux_isp_clkphy_isp_s_rxbyteclkhs0_s4s_user)
|
||||
|
||||
|
||||
DFS_EXTERN(dvfs_cpucl0)
|
||||
DFS_EXTERN(dvfs_cpucl1)
|
||||
DFS_EXTERN(dvfs_g3d)
|
||||
DFS_EXTERN(dvfs_mif)
|
||||
DFS_EXTERN(dvfs_int)
|
||||
DFS_EXTERN(dvfs_disp)
|
||||
DFS_EXTERN(dvfs_cam)
|
||||
|
||||
|
||||
#endif
|
||||
970
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-vclk.c
Normal file
970
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-vclk.c
Normal file
|
|
@ -0,0 +1,970 @@
|
|||
#include "../pwrcal-pmu.h"
|
||||
#include "../pwrcal-clk.h"
|
||||
#include "../pwrcal-rae.h"
|
||||
#include "S5E7870-cmu.h"
|
||||
#include "S5E7870-cmusfr.h"
|
||||
#include "S5E7870-vclk.h"
|
||||
#include "S5E7870-vclk-internal.h"
|
||||
|
||||
struct pwrcal_vclk_grpgate *vclk_grpgate_list[num_of_grpgate];
|
||||
struct pwrcal_vclk_m1d1g1 *vclk_m1d1g1_list[num_of_m1d1g1];
|
||||
struct pwrcal_vclk_p1 *vclk_p1_list[num_of_p1];
|
||||
struct pwrcal_vclk_m1 *vclk_m1_list[num_of_m1];
|
||||
struct pwrcal_vclk_d1 *vclk_d1_list[num_of_d1];
|
||||
struct pwrcal_vclk_pxmxdx *vclk_pxmxdx_list[num_of_pxmxdx];
|
||||
struct pwrcal_vclk_umux *vclk_umux_list[num_of_umux];
|
||||
struct pwrcal_vclk_dfs *vclk_dfs_list[num_of_dfs];
|
||||
unsigned int vclk_grpgate_list_size = num_of_grpgate;
|
||||
unsigned int vclk_m1d1g1_list_size = num_of_m1d1g1;
|
||||
unsigned int vclk_p1_list_size = num_of_p1;
|
||||
unsigned int vclk_m1_list_size = num_of_m1;
|
||||
unsigned int vclk_d1_list_size = num_of_d1;
|
||||
unsigned int vclk_pxmxdx_list_size = num_of_pxmxdx;
|
||||
unsigned int vclk_umux_list_size = num_of_umux;
|
||||
unsigned int vclk_dfs_list_size = num_of_dfs;
|
||||
|
||||
|
||||
#define ADD_LIST(to, x) to[x & 0xFFFF] = &(vclk_##x)
|
||||
|
||||
static struct pwrcal_clk_set pxmxdx_top_grp[] = {
|
||||
{CLK_NONE, 0, 0},
|
||||
};
|
||||
static struct pwrcal_clk_set pxmxdx_disp_grp[] = {
|
||||
{CLK(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER), 1, 0},
|
||||
{CLK(DISPAUD_DIV_CLK_DISPAUD_APB), 1, -1},
|
||||
{CLK(MIF_MUXGATE_CLKCMU_DISPAUD_BUS), 1, 0},
|
||||
{CLK_NONE, 0, 0},
|
||||
};
|
||||
static struct pwrcal_clk_set pxmxdx_mfcmscl_grp[] = {
|
||||
{CLK(MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER), 1, 0},
|
||||
{CLK(MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER), 1, 0},
|
||||
{CLK(MFCMSCL_DIV_CLK_MFCMSCL_APB), 2, -1},
|
||||
{CLK(MIF_MUXGATE_CLKCMU_MFCMSCL_MSCL), 1, 0},
|
||||
{CLK(MIF_MUXGATE_CLKCMU_MFCMSCL_MFC), 1, 0},
|
||||
{CLK_NONE, 0, 0},
|
||||
};
|
||||
static struct pwrcal_clk_set pxmxdx_isp_vra_grp[] = {
|
||||
{CLK(ISP_MUX_CLKCMU_ISP_VRA_USER), 1, 0},
|
||||
{CLK(ISP_DIV_CLK_ISP_APB), 3, -1},
|
||||
{CLK(MIF_MUXGATE_CLKCMU_ISP_VRA), 1, 0},
|
||||
{CLK_NONE, 0, 0},
|
||||
};
|
||||
static struct pwrcal_clk_set pxmxdx_isp_cam_grp[] = {
|
||||
{CLK(ISP_MUX_CLKCMU_ISP_CAM_USER), 1, 0},
|
||||
{CLK(ISP_DIV_CLK_ISP_CAM_HALF), 1, -1},
|
||||
{CLK(MIF_MUXGATE_CLKCMU_ISP_CAM), 1, 0},
|
||||
{CLK_NONE, 0, 0},
|
||||
};
|
||||
static struct pwrcal_clk_set pxmxdx_isp_isp_grp[] = {
|
||||
{CLK(ISP_MUX_CLKCMU_ISP_ISP_USER), 1, 0},
|
||||
{CLK(MIF_MUXGATE_CLKCMU_ISP_ISP), 1, 0},
|
||||
{CLK_NONE, 0, 0},
|
||||
};
|
||||
|
||||
PXMXDX(pxmxdx_top, 0, pxmxdx_top_grp);
|
||||
PXMXDX(pxmxdx_disp, dvfs_disp, pxmxdx_disp_grp);
|
||||
PXMXDX(pxmxdx_mfcmscl, 0, pxmxdx_mfcmscl_grp);
|
||||
PXMXDX(pxmxdx_isp_vra, 0, pxmxdx_isp_vra_grp);
|
||||
PXMXDX(pxmxdx_isp_cam, 0, pxmxdx_isp_cam_grp);
|
||||
PXMXDX(pxmxdx_isp_isp, 0, pxmxdx_isp_isp_grp);
|
||||
|
||||
P1(p1_disp_pll, 0, DISP_PLL);
|
||||
P1(p1_aud_pll, 0, AUD_PLL);
|
||||
P1(p1_usb_pll, 0, USB_PLL);
|
||||
P1(p1_isp_pll, 0, ISP_PLL);
|
||||
|
||||
M1(m1_dummy, 0, 0);
|
||||
|
||||
D1(d1_dispaud_mi2s, 0, DISPAUD_DIV_CLK_DISPAUD_MI2S);
|
||||
D1(d1_dispaud_mixer, 0, DISPAUD_DIV_CLK_DISPAUD_MIXER);
|
||||
|
||||
|
||||
M1D1G1(sclk_decon_vclk, 0, MIF_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK, MIF_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK, MIF_GATE_CLKCMU_DISPAUD_DECON_INT_VCLK, DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER);
|
||||
M1D1G1(sclk_decon_vclk_local, 0, DISPAUD_MUX_CLK_DISPAUD_DECON_INT_VCLK, DISPAUD_DIV_CLK_DISPAUD_DECON_INT_VCLK, DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_VCLK, 0);
|
||||
M1D1G1(sclk_decon_eclk, 0, MIF_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK, MIF_DIV_CLKCMU_DISPAUD_DECON_INT_ECLK, MIF_GATE_CLKCMU_DISPAUD_DECON_INT_ECLK, DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER);
|
||||
M1D1G1(sclk_decon_eclk_local, 0, DISPAUD_MUX_CLK_DISPAUD_DECON_INT_ECLK, DISPAUD_DIV_CLK_DISPAUD_DECON_INT_ECLK, DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_ECLK, 0);
|
||||
M1D1G1(sclk_mmc0, 0, MIF_MUX_CLKCMU_FSYS_MMC0, MIF_DIV_CLKCMU_FSYS_MMC0, MIF_GATE_CLKCMU_FSYS_MMC0, 0);
|
||||
M1D1G1(sclk_mmc1, 0, MIF_MUX_CLKCMU_FSYS_MMC1, MIF_DIV_CLKCMU_FSYS_MMC1, MIF_GATE_CLKCMU_FSYS_MMC1, 0);
|
||||
M1D1G1(sclk_mmc2, 0, MIF_MUX_CLKCMU_FSYS_MMC2, MIF_DIV_CLKCMU_FSYS_MMC2, MIF_GATE_CLKCMU_FSYS_MMC2, 0);
|
||||
M1D1G1(sclk_ufsunipro, 0, MIF_MUX_CLKCMU_FSYS_UFSUNIPRO, MIF_DIV_CLKCMU_FSYS_UFSUNIPRO, MIF_GATE_CLKCMU_FSYS_UFSUNIPRO, 0);
|
||||
M1D1G1(sclk_ufsunipro_cfg, 0, MIF_MUX_CLKCMU_FSYS_UFSUNIPRO_CFG, MIF_DIV_CLKCMU_FSYS_UFSUNIPRO_CFG, MIF_GATE_CLKCMU_FSYS_UFSUNIPRO_CFG, 0);
|
||||
M1D1G1(sclk_usb20drd, 0, MIF_MUX_CLKCMU_FSYS_USB20DRD_REFCLK, MIF_DIV_CLKCMU_FSYS_USB20DRD_REFCLK, MIF_GATE_CLKCMU_FSYS_USB20DRD_REFCLK, 0);
|
||||
M1D1G1(sclk_uart_sensor, gate_peri_peric0, MIF_MUX_CLKCMU_PERI_UART_SENSOR, MIF_DIV_CLKCMU_PERI_UART_SENSOR, MIF_GATE_CLKCMU_PERI_UART_SENSOR, 0);
|
||||
M1D1G1(sclk_uart_btwififm, gate_peri_peric0, MIF_MUX_CLKCMU_PERI_UART_BTWIFIFM, MIF_DIV_CLKCMU_PERI_UART_BTWIFIFM, MIF_GATE_CLKCMU_PERI_UART_BTWIFIFM, 0);
|
||||
M1D1G1(sclk_uart_debug, gate_peri_peric0, MIF_MUX_CLKCMU_PERI_UART_DEBUG, MIF_DIV_CLKCMU_PERI_UART_DEBUG, MIF_GATE_CLKCMU_PERI_UART_DEBUG, 0);
|
||||
M1D1G1(sclk_spi_frontfrom, gate_peri_peric1, MIF_MUX_CLKCMU_PERI_SPI_FRONTFROM, MIF_DIV_CLKCMU_PERI_SPI_FRONTFROM, MIF_GATE_CLKCMU_PERI_SPI_FRONTFROM, 0);
|
||||
M1D1G1(sclk_spi_rearfrom, gate_peri_peric1, MIF_MUX_CLKCMU_PERI_SPI_REARFROM, MIF_DIV_CLKCMU_PERI_SPI_REARFROM, MIF_GATE_CLKCMU_PERI_SPI_REARFROM, 0);
|
||||
M1D1G1(sclk_spi_ese, gate_peri_peris0, MIF_MUX_CLKCMU_PERI_SPI_ESE, MIF_DIV_CLKCMU_PERI_SPI_ESE, MIF_GATE_CLKCMU_PERI_SPI_ESE, 0);
|
||||
M1D1G1(sclk_spi_voiceprocessor, gate_peri_peric1, MIF_MUX_CLKCMU_PERI_SPI_VOICEPROCESSOR, MIF_DIV_CLKCMU_PERI_SPI_VOICEPROCESSOR, MIF_GATE_CLKCMU_PERI_SPI_VOICEPROCESSOR, 0);
|
||||
M1D1G1(sclk_spi_sensorhub, gate_peri_peric1, MIF_MUX_CLKCMU_PERI_SPI_SENSORHUB, MIF_DIV_CLKCMU_PERI_SPI_SENSORHUB, MIF_GATE_CLKCMU_PERI_SPI_SENSORHUB, 0);
|
||||
M1D1G1(sclk_isp_sensor0, 0, MIF_MUX_CLKCMU_ISP_SENSOR0, MIF_DIV_CLKCMU_ISP_SENSOR0, MIF_GATE_CLKCMU_ISP_SENSOR0, 0);
|
||||
M1D1G1(sclk_isp_sensor1, 0, MIF_MUX_CLKCMU_ISP_SENSOR1, MIF_DIV_CLKCMU_ISP_SENSOR1, MIF_GATE_CLKCMU_ISP_SENSOR1, 0);
|
||||
M1D1G1(sclk_isp_sensor2, 0, MIF_MUX_CLKCMU_ISP_SENSOR2, MIF_DIV_CLKCMU_ISP_SENSOR2, MIF_GATE_CLKCMU_ISP_SENSOR2, 0);
|
||||
|
||||
|
||||
|
||||
|
||||
static struct pwrcal_clk *gategrp_cpucl0_ppmu[] = {
|
||||
CLK(CPUCL0_DIV_CLK_CPUCL0_ACLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_cpucl0_bts[] = {
|
||||
CLK(CPUCL0_DIV_CLK_CPUCL0_ACLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_cpucl1_ppmu[] = {
|
||||
CLK(CPUCL1_DIV_CLK_CPUCL1_ACLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_cpucl1_bts[] = {
|
||||
CLK(CPUCL1_DIV_CLK_CPUCL1_ACLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_mfcmscl_sysmmu_mscl[] = {
|
||||
CLK(MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_mfcmscl_sysmmu_mfc[] = {
|
||||
CLK(MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_mfcmscl_ppmu[] = {
|
||||
CLK(MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_mfcmscl_bts[] = {
|
||||
CLK(MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_mfcmscl_common[] = {
|
||||
CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_PPMU),
|
||||
CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_mfcmscl_common_mscl[] = {
|
||||
CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_D),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_mfcmscl_mscl_bi[] = {
|
||||
CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_BI),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_mfcmscl_mscl_poly[] = {
|
||||
CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_POLY),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_mfcmscl_jpeg[] = {
|
||||
CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_JPEG),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_mfcmscl_mfc[] = {
|
||||
CLK(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_g3d_common[] = {
|
||||
CLK(G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_ACLK),
|
||||
CLK(G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_PCLK),
|
||||
CLK(G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_ACLK),
|
||||
CLK(G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_PCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_g3d_sysmmu[] = {
|
||||
CLK(G3D_DIV_CLK_G3D_BUS),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_g3d_ppmu[] = {
|
||||
CLK(G3D_DIV_CLK_G3D_BUS),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_g3d_bts[] = {
|
||||
CLK(G3D_DIV_CLK_G3D_BUS),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_g3d_g3d[] = {
|
||||
CLK(G3D_GATE_CLK_G3D_UID_G3D_IPCLKPORT_CLK),
|
||||
CLK(G3D_GATE_CLK_G3D_UID_ASYNCS_D0_G3D_IPCLKPORT_I_CLK),
|
||||
CLK(G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKM),
|
||||
CLK(G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_peris0[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_peric0[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_BUSP1_PERIC0_IPCLKPORT_HCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_peric1[] = {
|
||||
/* CLK(PERI_GATE_CLK_PERI_UID_BUSP1_PERIC1_IPCLKPORT_HCLK),*/
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_pwm_motor[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_PCLK_S0),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_sclk_pwm_motor[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_OSCCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_mct[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_MCT_IPCLKPORT_PCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_i2c_sensor2[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_I2C_SENSOR2_IPCLKPORT_PCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_i2c_sensor1[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_I2C_SENSOR1_IPCLKPORT_PCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_i2c_tsp[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_I2C_TSP_IPCLKPORT_PCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_i2c_touchkey[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_I2C_TOUCHKEY_IPCLKPORT_PCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_i2c_fuelgauge[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_I2C_FUELGAUGE_IPCLKPORT_PCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_i2c_spkamp[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_I2C_SPKAMP_IPCLKPORT_PCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_i2c_nfc[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_I2C_NFC_IPCLKPORT_PCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_i2c_muic[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_I2C_MUIC_IPCLKPORT_PCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_i2c_ifpmic[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_I2C_IFPMIC_IPCLKPORT_PCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_hsi2c_frontcam[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_HSI2C_FRONTCAM_IPCLKPORT_iPCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_hsi2c_maincam[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_HSI2C_MAINCAM_IPCLKPORT_iPCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_hsi2c_depthcam[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_HSI2C_DEPTHCAM_IPCLKPORT_iPCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_hsi2c_frontsensor[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_HSI2C_FRONTSENSOR_IPCLKPORT_iPCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_hsi2c_rearaf[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_HSI2C_REARAF_IPCLKPORT_iPCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_hsi2c_rearsensor[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_HSI2C_REARSENSOR_IPCLKPORT_iPCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_gpio_touch[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_GPIO_TOUCH_IPCLKPORT_PCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_gpio_top[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_GPIO_TOP_IPCLKPORT_PCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_gpio_nfc[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_GPIO_NFC_IPCLKPORT_PCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_gpio_ese[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_GPIO_ESE_IPCLKPORT_PCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_wdt_cpucl1[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_WDT_CPUCL1_IPCLKPORT_PCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_wdt_cpucl0[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_WDT_CPUCL0_IPCLKPORT_PCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_uart_debug[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_PCLK),
|
||||
CLK(PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_EXT_UCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_uart_btwififm[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_UART_BTWIFIFM_IPCLKPORT_PCLK),
|
||||
CLK(PERI_GATE_CLK_PERI_UID_UART_BTWIFIFM_IPCLKPORT_EXT_UCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_uart_sensor[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_PCLK),
|
||||
CLK(PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_EXT_UCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_tmu_g3d[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_SFRIF_TMU_G3D_IPCLKPORT_PCLK),
|
||||
CLK(PERI_GATE_CLK_PERI_UID_TMU_G3D_IPCLKPORT_I_CLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_tmu_cpucl1[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_SFRIF_TMU_CPUCL1_IPCLKPORT_PCLK),
|
||||
CLK(PERI_GATE_CLK_PERI_UID_TMU_CPUCL1_IPCLKPORT_I_CLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_tmu_cpucl0[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_SFRIF_TMU_CPUCL0_IPCLKPORT_PCLK),
|
||||
CLK(PERI_GATE_CLK_PERI_UID_TMU_CPUCL0_IPCLKPORT_I_CLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_spi_sensorhub[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_SPI_SENSORHUB_IPCLKPORT_PCLK),
|
||||
CLK(PERI_GATE_CLK_PERI_UID_SPI_SENSORHUB_IPCLKPORT_SPI_EXT_CLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_spi_voiceprocessor[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_SPI_VOICEPROCESSOR_IPCLKPORT_PCLK),
|
||||
CLK(PERI_GATE_CLK_PERI_UID_SPI_VOICEPROCESSOR_IPCLKPORT_SPI_EXT_CLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_spi_ese[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_PCLK),
|
||||
CLK(PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_SPI_EXT_CLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_spi_rearfrom[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_PCLK),
|
||||
CLK(PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_SPI_EXT_CLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_spi_frontfrom[] = {
|
||||
CLK(PERI_GATE_CLK_PERI_UID_SPI_FRONTFROM_IPCLKPORT_PCLK),
|
||||
CLK(PERI_GATE_CLK_PERI_UID_SPI_FRONTFROM_IPCLKPORT_SPI_EXT_CLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_gpio_alive[] = {
|
||||
CLK(MIF_DIV_CLKCMU_PERI_BUS),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_chipid[] = {
|
||||
CLK(MIF_DIV_CLKCMU_PERI_BUS),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_otp_con_top[] = {
|
||||
CLK(MIF_DIV_CLKCMU_PERI_BUS),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_rtc_alive[] = {
|
||||
CLK(MIF_DIV_CLKCMU_PERI_BUS),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_peri_rtc_top[] = {
|
||||
CLK(MIF_DIV_CLKCMU_PERI_BUS),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_fsys_common[] = {
|
||||
CLK(FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK),
|
||||
CLK(FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_fsys_common_sub1[] = {
|
||||
CLK(FSYS_GATE_CLK_FSYS_UID_UPSIZER_BUS1_FSYS_IPCLKPORT_aclk),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_fsys_common_sub2[] = {
|
||||
CLK(FSYS_GATE_CLK_FSYS_UID_BUSP3_FSYS_IPCLKPORT_HCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_fsys_sysmmu[] = {
|
||||
CLK(MIF_DIV_CLKCMU_FSYS_BUS),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_fsys_ppmu[] = {
|
||||
CLK(MIF_DIV_CLKCMU_FSYS_BUS),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_fsys_bts[] = {
|
||||
CLK(MIF_DIV_CLKCMU_FSYS_BUS),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_fsys_usb20drd[] = {
|
||||
CLK(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HCLK_USB20_CTRL),
|
||||
CLK(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_HSDRD),
|
||||
CLK(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_ref_clk),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_fsys_mmc0[] = {
|
||||
CLK(FSYS_GATE_CLK_FSYS_UID_MMC0_IPCLKPORT_I_ACLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_fsys_sclk_mmc0[] = {
|
||||
CLK(MIF_DIV_CLKCMU_FSYS_MMC0),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_fsys_mmc1[] = {
|
||||
CLK(FSYS_GATE_CLK_FSYS_UID_MMC1_IPCLKPORT_I_ACLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_fsys_sclk_mmc1[] = {
|
||||
CLK(MIF_DIV_CLKCMU_FSYS_MMC1),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_fsys_mmc2[] = {
|
||||
CLK(FSYS_GATE_CLK_FSYS_UID_MMC2_IPCLKPORT_I_ACLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_fsys_sclk_mmc2[] = {
|
||||
CLK(MIF_DIV_CLKCMU_FSYS_MMC2),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_fsys_sss[] = {
|
||||
CLK(MIF_DIV_CLKCMU_FSYS_BUS),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_fsys_rtic[] = {
|
||||
CLK(MIF_DIV_CLKCMU_FSYS_BUS),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_fsys_pdma0[] = {
|
||||
CLK(FSYS_GATE_CLK_FSYS_UID_PDMA0_IPCLKPORT_ACLK_PDMA0),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_fsys_pdma1[] = {
|
||||
CLK(MIF_DIV_CLKCMU_FSYS_BUS),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_fsys_sromc[] = {
|
||||
CLK(FSYS_GATE_CLK_FSYS_UID_SROMC_IPCLKPORT_HCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_dispaud_disp[] = {
|
||||
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_PPMU),
|
||||
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_DISP),
|
||||
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS),
|
||||
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_DISP),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_dispaud_aud[] = {
|
||||
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_EXT2AUD_BCK_gpio_I2S),
|
||||
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_AUD_I2S_BCLK_BT_IN),
|
||||
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_CP2AUD_BCK),
|
||||
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_AUD_I2S_BCLK_FM_IN),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_dispaud_sysmmu[] = {
|
||||
CLK(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_dispaud_ppmu[] = {
|
||||
CLK(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_dispaud_bts[] = {
|
||||
CLK(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_dispaud_decon[] = {
|
||||
CLK(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER),
|
||||
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_VCLK),
|
||||
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_ECLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_dispaud_dsim0[] = {
|
||||
CLK(DISPAUD_DIV_CLK_DISPAUD_APB),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_dispaud_mixer[] = {
|
||||
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_MIXER_AUD_IPCLKPORT_SYSCLK),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_dispaud_mi2s_aud[] = {
|
||||
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD),
|
||||
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AUD_IPCLKPORT_I2SCODCLKI),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_dispaud_mi2s_amp[] = {
|
||||
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD_AMP),
|
||||
CLK(DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AMP_IPCLKPORT_I2SCODCLKI),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_isp_common[] = {
|
||||
CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_ISPD_PPMU),
|
||||
CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_ISPD),
|
||||
CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_CAM),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_isp_sysmmu[] = {
|
||||
CLK(ISP_MUX_CLK_ISP_ISPD),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_isp_ppmu[] = {
|
||||
CLK(ISP_MUX_CLK_ISP_ISPD),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_isp_bts[] = {
|
||||
CLK(ISP_MUX_CLK_ISP_ISPD),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_isp_cam[] = {
|
||||
CLK(ISP_MUX_CLK_ISP_CAM),
|
||||
CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_CAM_HALF),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_isp_isp[] = {
|
||||
CLK(ISP_MUX_CLK_ISP_ISP),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_isp_vra[] = {
|
||||
CLK(ISP_GATE_CLK_ISP_UID_CLK_ISP_VRA),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_mif_adcif[] = {
|
||||
CLK(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_I_OSC_SYS),
|
||||
CLK(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1),
|
||||
CLK(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_mif_hsi2c_mif[] = {
|
||||
CLK(MIF_GATE_CLK_MIF_UID_ASYNCAPB_HSI2C_CP_IPCLKPORT_PCLKS),
|
||||
CLK(MIF_GATE_CLK_MIF_UID_ASYNCAPB_HSI2C_AP_IPCLKPORT_PCLKS),
|
||||
CLK(MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_HSI2C),
|
||||
CLK(MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_HSI2C_BAT_1),
|
||||
CLK(MIF_GATE_CLK_MIF_UID_MODAPIF_V1P5_MIF_CP_IPCLKPORT_PCLK_HSI2C_BAT_0),
|
||||
CLK(MIF_GATE_CLK_MIF_UID_HSI2C_MIF_IPCLKPORT_iTCLK),
|
||||
CLK(MIF_GATE_CLK_MIF_UID_HSI2C_MIF_IPCLKPORT_iPCLK),
|
||||
CLK(MIF_GATE_CLK_MIF_UID_ASYNCAPB_HSI2C_CP_IPCLKPORT_PCLKM),
|
||||
CLK(MIF_GATE_CLK_MIF_UID_ASYNCAPB_HSI2C_AP_IPCLKPORT_PCLKM),
|
||||
CLK_NONE,
|
||||
};
|
||||
static struct pwrcal_clk *gategrp_sclk_uart0[] = {
|
||||
CLK(FIN_TEMP),
|
||||
CLK_NONE,
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
GRPGATE(gate_cpucl0_ppmu, 0, gategrp_cpucl0_ppmu);
|
||||
GRPGATE(gate_cpucl0_bts, 0, gategrp_cpucl0_bts);
|
||||
GRPGATE(gate_cpucll_ppmu, 0, gategrp_cpucl1_ppmu);
|
||||
GRPGATE(gate_cpucll_bts, 0, gategrp_cpucl1_bts);
|
||||
|
||||
GRPGATE(gate_mfcmscl_common, pxmxdx_mfcmscl, gategrp_mfcmscl_common);
|
||||
GRPGATE(gate_mfcmscl_common_mscl, gate_mfcmscl_common, gategrp_mfcmscl_common_mscl);
|
||||
GRPGATE(gate_mfcmscl_sysmmu_mfc, gate_mfcmscl_mfc, gategrp_mfcmscl_sysmmu_mfc);
|
||||
GRPGATE(gate_mfcmscl_sysmmu_mscl, gate_mfcmscl_common_mscl, gategrp_mfcmscl_sysmmu_mscl);
|
||||
GRPGATE(gate_mfcmscl_ppmu, gate_mfcmscl_common, gategrp_mfcmscl_ppmu);
|
||||
GRPGATE(gate_mfcmscl_bts, gate_mfcmscl_common, gategrp_mfcmscl_bts);
|
||||
GRPGATE(gate_mfcmscl_mscl_bi, gate_mfcmscl_common_mscl, gategrp_mfcmscl_mscl_bi);
|
||||
GRPGATE(gate_mfcmscl_mscl_poly, gate_mfcmscl_common_mscl, gategrp_mfcmscl_mscl_poly);
|
||||
GRPGATE(gate_mfcmscl_jpeg, gate_mfcmscl_common_mscl, gategrp_mfcmscl_jpeg);
|
||||
GRPGATE(gate_mfcmscl_mfc, gate_mfcmscl_common, gategrp_mfcmscl_mfc);
|
||||
|
||||
GRPGATE(gate_g3d_common, dvfs_g3d, gategrp_g3d_common);
|
||||
GRPGATE(gate_g3d_sysmmu, gate_g3d_common, gategrp_g3d_sysmmu);
|
||||
GRPGATE(gate_g3d_ppmu, gate_g3d_common, gategrp_g3d_ppmu);
|
||||
GRPGATE(gate_g3d_bts, gate_g3d_common, gategrp_g3d_bts);
|
||||
GRPGATE(gate_g3d_g3d, gate_g3d_common, gategrp_g3d_g3d);
|
||||
|
||||
GRPGATE(gate_peri_peris0, 0, gategrp_peri_peris0);
|
||||
GRPGATE(gate_peri_peric0, 0, gategrp_peri_peric0);
|
||||
GRPGATE(gate_peri_peric1, 0, gategrp_peri_peric1);
|
||||
GRPGATE(gate_peri_pwm_motor, gate_peri_peric1, gategrp_peri_pwm_motor);
|
||||
GRPGATE(gate_peri_sclk_pwm_motor, 0, gategrp_peri_sclk_pwm_motor);
|
||||
GRPGATE(gate_peri_mct, 0, gategrp_peri_mct);
|
||||
GRPGATE(gate_peri_i2c_sensor2, gate_peri_peric0, gategrp_peri_i2c_sensor2);
|
||||
GRPGATE(gate_peri_i2c_sensor1, gate_peri_peric0, gategrp_peri_i2c_sensor1);
|
||||
GRPGATE(gate_peri_i2c_tsp, gate_peri_peric0, gategrp_peri_i2c_tsp);
|
||||
GRPGATE(gate_peri_i2c_touchkey, gate_peri_peric0, gategrp_peri_i2c_touchkey);
|
||||
GRPGATE(gate_peri_i2c_fuelgauge, gate_peri_peric0, gategrp_peri_i2c_fuelgauge);
|
||||
GRPGATE(gate_peri_i2c_spkamp, gate_peri_peric0, gategrp_peri_i2c_spkamp);
|
||||
GRPGATE(gate_peri_i2c_nfc, gate_peri_peric0, gategrp_peri_i2c_nfc);
|
||||
GRPGATE(gate_peri_i2c_muic, gate_peri_peric0, gategrp_peri_i2c_muic);
|
||||
GRPGATE(gate_peri_i2c_ifpmic, gate_peri_peric0, gategrp_peri_i2c_ifpmic);
|
||||
GRPGATE(gate_peri_hsi2c_frontcam, gate_peri_peric1, gategrp_peri_hsi2c_frontcam);
|
||||
GRPGATE(gate_peri_hsi2c_maincam, gate_peri_peric1, gategrp_peri_hsi2c_maincam);
|
||||
GRPGATE(gate_peri_hsi2c_depthcam, gate_peri_peric0, gategrp_peri_hsi2c_depthcam);
|
||||
GRPGATE(gate_peri_hsi2c_frontsensor, gate_peri_peric0, gategrp_peri_hsi2c_frontsensor);
|
||||
GRPGATE(gate_peri_hsi2c_rearaf, gate_peri_peric0, gategrp_peri_hsi2c_rearaf);
|
||||
GRPGATE(gate_peri_hsi2c_rearsensor, gate_peri_peric0, gategrp_peri_hsi2c_rearsensor);
|
||||
GRPGATE(gate_peri_gpio_touch, gate_peri_peric1, gategrp_peri_gpio_touch);
|
||||
GRPGATE(gate_peri_gpio_top, gate_peri_peric1, gategrp_peri_gpio_top);
|
||||
GRPGATE(gate_peri_gpio_nfc, gate_peri_peric1, gategrp_peri_gpio_nfc);
|
||||
GRPGATE(gate_peri_gpio_ese, gate_peri_peric1, gategrp_peri_gpio_ese);
|
||||
GRPGATE(gate_peri_wdt_cpucl1, 0, gategrp_peri_wdt_cpucl1);
|
||||
GRPGATE(gate_peri_wdt_cpucl0, 0, gategrp_peri_wdt_cpucl0);
|
||||
GRPGATE(gate_peri_uart_debug, sclk_uart_debug, gategrp_peri_uart_debug);
|
||||
GRPGATE(gate_peri_uart_btwififm, sclk_uart_btwififm, gategrp_peri_uart_btwififm);
|
||||
GRPGATE(gate_peri_uart_sensor, sclk_uart_sensor, gategrp_peri_uart_sensor);
|
||||
GRPGATE(gate_peri_tmu_g3d, 0, gategrp_peri_tmu_g3d);
|
||||
GRPGATE(gate_peri_tmu_cpucl1, 0, gategrp_peri_tmu_cpucl1);
|
||||
GRPGATE(gate_peri_tmu_cpucl0, 0, gategrp_peri_tmu_cpucl0);
|
||||
GRPGATE(gate_peri_spi_sensorhub, sclk_spi_sensorhub, gategrp_peri_spi_sensorhub);
|
||||
GRPGATE(gate_peri_spi_voiceprocessor, sclk_spi_voiceprocessor, gategrp_peri_spi_voiceprocessor);
|
||||
GRPGATE(gate_peri_spi_ese, sclk_spi_ese, gategrp_peri_spi_ese);
|
||||
GRPGATE(gate_peri_spi_rearfrom, sclk_spi_rearfrom, gategrp_peri_spi_rearfrom);
|
||||
GRPGATE(gate_peri_spi_frontfrom, sclk_spi_frontfrom, gategrp_peri_spi_frontfrom);
|
||||
GRPGATE(gate_peri_gpio_alive, gate_peri_peric1, gategrp_peri_gpio_alive);
|
||||
GRPGATE(gate_peri_chipid, 0, gategrp_peri_chipid);
|
||||
GRPGATE(gate_peri_otp_con_top, gate_peri_peris0, gategrp_peri_otp_con_top);
|
||||
GRPGATE(gate_peri_rtc_alive, 0, gategrp_peri_rtc_alive);
|
||||
GRPGATE(gate_peri_rtc_top, 0, gategrp_peri_rtc_top);
|
||||
|
||||
GRPGATE(gate_fsys_common, 0, gategrp_fsys_common);
|
||||
GRPGATE(gate_fsys_common_sub1, gate_fsys_common, gategrp_fsys_common_sub1);
|
||||
GRPGATE(gate_fsys_common_sub2, gate_fsys_common, gategrp_fsys_common_sub2);
|
||||
GRPGATE(gate_fsys_sysmmu, gate_fsys_common, gategrp_fsys_sysmmu);
|
||||
GRPGATE(gate_fsys_ppmu, gate_fsys_common, gategrp_fsys_ppmu);
|
||||
GRPGATE(gate_fsys_bts, gate_fsys_common, gategrp_fsys_bts);
|
||||
GRPGATE(gate_fsys_usb20drd, gate_fsys_common_sub2, gategrp_fsys_usb20drd);
|
||||
GRPGATE(gate_fsys_mmc0, gate_fsys_common_sub2, gategrp_fsys_mmc0);
|
||||
GRPGATE(gate_fsys_sclk_mmc0, sclk_mmc0, gategrp_fsys_sclk_mmc0);
|
||||
GRPGATE(gate_fsys_mmc1, gate_fsys_common_sub2, gategrp_fsys_mmc1);
|
||||
GRPGATE(gate_fsys_sclk_mmc1, sclk_mmc1, gategrp_fsys_sclk_mmc1);
|
||||
GRPGATE(gate_fsys_mmc2, gate_fsys_common_sub2, gategrp_fsys_mmc2);
|
||||
GRPGATE(gate_fsys_sclk_mmc2, sclk_mmc2, gategrp_fsys_sclk_mmc2);
|
||||
GRPGATE(gate_fsys_sss, gate_fsys_common_sub1, gategrp_fsys_sss);
|
||||
GRPGATE(gate_fsys_rtic, gate_fsys_common_sub1, gategrp_fsys_rtic);
|
||||
GRPGATE(gate_fsys_pdma0, gate_fsys_common_sub1, gategrp_fsys_pdma0);
|
||||
GRPGATE(gate_fsys_pdma1, gate_fsys_common_sub1, gategrp_fsys_pdma1);
|
||||
GRPGATE(gate_fsys_sromc, gate_fsys_common_sub2, gategrp_fsys_sromc);
|
||||
|
||||
GRPGATE(gate_dispaud_disp, pxmxdx_disp, gategrp_dispaud_disp);
|
||||
GRPGATE(gate_dispaud_aud, pxmxdx_disp, gategrp_dispaud_aud);
|
||||
GRPGATE(gate_dispaud_sysmmu, gate_dispaud_disp, gategrp_dispaud_sysmmu);
|
||||
GRPGATE(gate_dispaud_ppmu, gate_dispaud_disp, gategrp_dispaud_ppmu);
|
||||
GRPGATE(gate_dispaud_bts, gate_dispaud_disp, gategrp_dispaud_bts);
|
||||
GRPGATE(gate_dispaud_decon, gate_dispaud_disp, gategrp_dispaud_decon);
|
||||
GRPGATE(gate_dispaud_dsim0, gate_dispaud_disp, gategrp_dispaud_dsim0);
|
||||
GRPGATE(gate_dispaud_mixer, gate_dispaud_aud, gategrp_dispaud_mixer);
|
||||
GRPGATE(gate_dispaud_mi2s_aud, gate_dispaud_aud, gategrp_dispaud_mi2s_aud);
|
||||
GRPGATE(gate_dispaud_mi2s_amp, gate_dispaud_aud, gategrp_dispaud_mi2s_amp);
|
||||
|
||||
GRPGATE(gate_isp_common, dvfs_cam, gategrp_isp_common);
|
||||
GRPGATE(gate_isp_sysmmu, gate_isp_common, gategrp_isp_sysmmu);
|
||||
GRPGATE(gate_isp_ppmu, gate_isp_common, gategrp_isp_ppmu);
|
||||
GRPGATE(gate_isp_bts, gate_isp_common, gategrp_isp_bts);
|
||||
GRPGATE(gate_isp_cam, gate_isp_common, gategrp_isp_cam);
|
||||
GRPGATE(gate_isp_isp, gate_isp_common, gategrp_isp_isp);
|
||||
GRPGATE(gate_isp_vra, gate_isp_common, gategrp_isp_vra);
|
||||
|
||||
GRPGATE(gate_mif_adcif, 0, gategrp_mif_adcif);
|
||||
GRPGATE(gate_mif_hsi2c_mif, 0, gategrp_mif_hsi2c_mif);
|
||||
|
||||
GRPGATE(sclk_uart0, 0, gategrp_sclk_uart0);
|
||||
|
||||
|
||||
UMUX(umux_dispaud_clkphy_dispaud_mipiphy_txbyteclkhs_user, 0, DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER);
|
||||
UMUX(umux_dispaud_clkphy_dispaud_mipiphy_rxclkesc0_user, 0, DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER);
|
||||
UMUX(umux_fsys_clkphy_fsys_usb20drd_phyclock_user, 0, FSYS_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER);
|
||||
UMUX(umux_fsys_clkphy_fsys_ufs_tx0_symbol_user, 0, FSYS_MUX_CLKPHY_FSYS_UFS_TX0_SYMBOL_USER);
|
||||
UMUX(umux_fsys_clkphy_fsys_ufs_rx0_symbol_user, 0, FSYS_MUX_CLKPHY_FSYS_UFS_RX0_SYMBOL_USER);
|
||||
UMUX(umux_isp_clkphy_isp_s_rxbyteclkhs0_s4_user, 0, ISP_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER);
|
||||
UMUX(umux_isp_clkphy_isp_s_rxbyteclkhs0_s4s_user, 0, ISP_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER);
|
||||
|
||||
|
||||
void vclk_unused_disable(void)
|
||||
{
|
||||
vclk_disable(VCLK(gate_cpucl0_ppmu));
|
||||
vclk_disable(VCLK(gate_cpucl0_bts));
|
||||
vclk_disable(VCLK(gate_cpucll_ppmu));
|
||||
vclk_disable(VCLK(gate_cpucll_bts));
|
||||
vclk_disable(VCLK(gate_mfcmscl_sysmmu_mscl));
|
||||
vclk_disable(VCLK(gate_mfcmscl_sysmmu_mfc));
|
||||
vclk_disable(VCLK(gate_mfcmscl_ppmu));
|
||||
vclk_disable(VCLK(gate_mfcmscl_bts));
|
||||
vclk_disable(VCLK(gate_mfcmscl_common));
|
||||
vclk_disable(VCLK(gate_mfcmscl_mscl_bi));
|
||||
vclk_disable(VCLK(gate_mfcmscl_mscl_poly));
|
||||
vclk_disable(VCLK(gate_mfcmscl_jpeg));
|
||||
vclk_disable(VCLK(gate_mfcmscl_mfc));
|
||||
vclk_disable(VCLK(gate_g3d_common));
|
||||
vclk_disable(VCLK(gate_g3d_sysmmu));
|
||||
vclk_disable(VCLK(gate_g3d_ppmu));
|
||||
vclk_disable(VCLK(gate_g3d_bts));
|
||||
vclk_disable(VCLK(gate_g3d_g3d));
|
||||
// vclk_disable(VCLK(gate_peri_pwm_motor));
|
||||
// vclk_disable(VCLK(gate_peri_sclk_pwm_motor));
|
||||
vclk_disable(VCLK(gate_peri_i2c_sensor2));
|
||||
vclk_disable(VCLK(gate_peri_i2c_sensor1));
|
||||
vclk_disable(VCLK(gate_peri_i2c_tsp));
|
||||
vclk_disable(VCLK(gate_peri_i2c_touchkey));
|
||||
vclk_disable(VCLK(gate_peri_i2c_fuelgauge));
|
||||
vclk_disable(VCLK(gate_peri_i2c_spkamp));
|
||||
vclk_disable(VCLK(gate_peri_i2c_nfc));
|
||||
vclk_disable(VCLK(gate_peri_i2c_muic));
|
||||
vclk_disable(VCLK(gate_peri_i2c_ifpmic));
|
||||
vclk_disable(VCLK(gate_peri_hsi2c_frontcam));
|
||||
vclk_disable(VCLK(gate_peri_hsi2c_maincam));
|
||||
vclk_disable(VCLK(gate_peri_hsi2c_depthcam));
|
||||
vclk_disable(VCLK(gate_peri_hsi2c_frontsensor));
|
||||
vclk_disable(VCLK(gate_peri_hsi2c_rearaf));
|
||||
vclk_disable(VCLK(gate_peri_hsi2c_rearsensor));
|
||||
// vclk_disable(VCLK(gate_peri_uart_debug));
|
||||
// vclk_disable(VCLK(gate_peri_uart_btwififm));
|
||||
// vclk_disable(VCLK(gate_peri_uart_sensor));
|
||||
// vclk_disable(VCLK(gate_peri_tmu_g3d));
|
||||
// vclk_disable(VCLK(gate_peri_tmu_cpucl1));
|
||||
// vclk_disable(VCLK(gate_peri_tmu_cpucl0));
|
||||
vclk_disable(VCLK(gate_peri_spi_sensorhub));
|
||||
vclk_disable(VCLK(gate_peri_spi_voiceprocessor));
|
||||
vclk_disable(VCLK(gate_peri_spi_ese));
|
||||
vclk_disable(VCLK(gate_peri_spi_rearfrom));
|
||||
vclk_disable(VCLK(gate_peri_spi_frontfrom));
|
||||
vclk_disable(VCLK(gate_peri_chipid));
|
||||
vclk_disable(VCLK(gate_peri_otp_con_top));
|
||||
vclk_disable(VCLK(gate_peri_rtc_alive));
|
||||
vclk_disable(VCLK(gate_peri_rtc_top));
|
||||
|
||||
vclk_disable(VCLK(gate_fsys_sysmmu));
|
||||
vclk_disable(VCLK(gate_fsys_ppmu));
|
||||
vclk_disable(VCLK(gate_fsys_bts));
|
||||
vclk_disable(VCLK(gate_fsys_usb20drd));
|
||||
vclk_disable(VCLK(gate_fsys_mmc0));
|
||||
vclk_disable(VCLK(gate_fsys_mmc1));
|
||||
vclk_disable(VCLK(gate_fsys_mmc2));
|
||||
vclk_disable(VCLK(gate_fsys_sss));
|
||||
vclk_disable(VCLK(gate_fsys_rtic));
|
||||
vclk_disable(VCLK(gate_fsys_pdma0));
|
||||
vclk_disable(VCLK(gate_fsys_pdma1));
|
||||
vclk_disable(VCLK(gate_fsys_sromc));
|
||||
vclk_disable(VCLK(gate_dispaud_sysmmu));
|
||||
vclk_disable(VCLK(gate_dispaud_ppmu));
|
||||
vclk_disable(VCLK(gate_dispaud_bts));
|
||||
vclk_disable(VCLK(gate_dispaud_decon));
|
||||
vclk_disable(VCLK(gate_dispaud_dsim0));
|
||||
vclk_disable(VCLK(gate_dispaud_mixer));
|
||||
vclk_disable(VCLK(gate_dispaud_mi2s_aud));
|
||||
vclk_disable(VCLK(gate_dispaud_mi2s_amp));
|
||||
vclk_disable(VCLK(gate_dispaud_disp));
|
||||
vclk_disable(VCLK(gate_dispaud_aud));
|
||||
vclk_disable(VCLK(gate_isp_sysmmu));
|
||||
vclk_disable(VCLK(gate_isp_ppmu));
|
||||
vclk_disable(VCLK(gate_isp_bts));
|
||||
vclk_disable(VCLK(gate_isp_cam));
|
||||
vclk_disable(VCLK(gate_isp_isp));
|
||||
vclk_disable(VCLK(gate_isp_vra));
|
||||
vclk_disable(VCLK(gate_mif_adcif));
|
||||
vclk_disable(VCLK(gate_mif_hsi2c_mif));
|
||||
|
||||
|
||||
vclk_disable(VCLK(sclk_decon_vclk));
|
||||
vclk_disable(VCLK(sclk_decon_vclk_local));
|
||||
vclk_disable(VCLK(sclk_decon_eclk));
|
||||
vclk_disable(VCLK(sclk_decon_eclk_local));
|
||||
vclk_disable(VCLK(sclk_mmc0));
|
||||
vclk_disable(VCLK(sclk_mmc1));
|
||||
vclk_disable(VCLK(sclk_mmc2));
|
||||
vclk_disable(VCLK(sclk_ufsunipro));
|
||||
vclk_disable(VCLK(sclk_ufsunipro_cfg));
|
||||
vclk_disable(VCLK(sclk_usb20drd));
|
||||
// vclk_disable(VCLK(sclk_uart_sensor));
|
||||
// vclk_disable(VCLK(sclk_uart_btwififm));
|
||||
// vclk_disable(VCLK(sclk_uart_debug));
|
||||
vclk_disable(VCLK(sclk_spi_frontfrom));
|
||||
vclk_disable(VCLK(sclk_spi_rearfrom));
|
||||
vclk_disable(VCLK(sclk_spi_ese));
|
||||
vclk_disable(VCLK(sclk_spi_voiceprocessor));
|
||||
vclk_disable(VCLK(sclk_spi_sensorhub));
|
||||
vclk_disable(VCLK(sclk_isp_sensor0));
|
||||
vclk_disable(VCLK(sclk_isp_sensor1));
|
||||
vclk_disable(VCLK(sclk_isp_sensor2));
|
||||
|
||||
vclk_disable(VCLK(p1_disp_pll));
|
||||
vclk_disable(VCLK(p1_aud_pll));
|
||||
vclk_disable(VCLK(p1_usb_pll));
|
||||
vclk_disable(VCLK(p1_isp_pll));
|
||||
|
||||
vclk_disable(VCLK(pxmxdx_top));
|
||||
vclk_disable(VCLK(pxmxdx_disp));
|
||||
vclk_disable(VCLK(pxmxdx_mfcmscl));
|
||||
vclk_disable(VCLK(pxmxdx_isp_vra));
|
||||
vclk_disable(VCLK(pxmxdx_isp_cam));
|
||||
vclk_disable(VCLK(pxmxdx_isp_isp));
|
||||
|
||||
vclk_disable(VCLK(umux_dispaud_clkphy_dispaud_mipiphy_txbyteclkhs_user));
|
||||
vclk_disable(VCLK(umux_dispaud_clkphy_dispaud_mipiphy_rxclkesc0_user));
|
||||
vclk_disable(VCLK(umux_fsys_clkphy_fsys_usb20drd_phyclock_user));
|
||||
vclk_disable(VCLK(umux_fsys_clkphy_fsys_ufs_tx0_symbol_user));
|
||||
vclk_disable(VCLK(umux_fsys_clkphy_fsys_ufs_rx0_symbol_user));
|
||||
vclk_disable(VCLK(umux_isp_clkphy_isp_s_rxbyteclkhs0_s4_user));
|
||||
vclk_disable(VCLK(umux_isp_clkphy_isp_s_rxbyteclkhs0_s4s_user));
|
||||
|
||||
}
|
||||
|
||||
void vclk_init(void)
|
||||
{
|
||||
ADD_LIST(vclk_pxmxdx_list, pxmxdx_top);
|
||||
ADD_LIST(vclk_pxmxdx_list, pxmxdx_disp);
|
||||
ADD_LIST(vclk_pxmxdx_list, pxmxdx_mfcmscl);
|
||||
ADD_LIST(vclk_pxmxdx_list, pxmxdx_isp_vra);
|
||||
ADD_LIST(vclk_pxmxdx_list, pxmxdx_isp_cam);
|
||||
ADD_LIST(vclk_pxmxdx_list, pxmxdx_isp_isp);
|
||||
|
||||
ADD_LIST(vclk_p1_list, p1_disp_pll);
|
||||
ADD_LIST(vclk_p1_list, p1_aud_pll);
|
||||
ADD_LIST(vclk_p1_list, p1_usb_pll);
|
||||
ADD_LIST(vclk_p1_list, p1_isp_pll);
|
||||
|
||||
ADD_LIST(vclk_m1_list, m1_dummy);
|
||||
|
||||
ADD_LIST(vclk_d1_list, d1_dispaud_mi2s);
|
||||
ADD_LIST(vclk_d1_list, d1_dispaud_mixer);
|
||||
|
||||
|
||||
ADD_LIST(vclk_m1d1g1_list, sclk_decon_vclk);
|
||||
ADD_LIST(vclk_m1d1g1_list, sclk_decon_vclk_local);
|
||||
ADD_LIST(vclk_m1d1g1_list, sclk_decon_eclk);
|
||||
ADD_LIST(vclk_m1d1g1_list, sclk_decon_eclk_local);
|
||||
ADD_LIST(vclk_m1d1g1_list, sclk_mmc0);
|
||||
ADD_LIST(vclk_m1d1g1_list, sclk_mmc1);
|
||||
ADD_LIST(vclk_m1d1g1_list, sclk_mmc2);
|
||||
ADD_LIST(vclk_m1d1g1_list, sclk_ufsunipro);
|
||||
ADD_LIST(vclk_m1d1g1_list, sclk_ufsunipro_cfg);
|
||||
ADD_LIST(vclk_m1d1g1_list, sclk_usb20drd);
|
||||
ADD_LIST(vclk_m1d1g1_list, sclk_uart_sensor);
|
||||
ADD_LIST(vclk_m1d1g1_list, sclk_uart_btwififm);
|
||||
ADD_LIST(vclk_m1d1g1_list, sclk_uart_debug);
|
||||
ADD_LIST(vclk_m1d1g1_list, sclk_spi_frontfrom);
|
||||
ADD_LIST(vclk_m1d1g1_list, sclk_spi_rearfrom);
|
||||
ADD_LIST(vclk_m1d1g1_list, sclk_spi_ese);
|
||||
ADD_LIST(vclk_m1d1g1_list, sclk_spi_voiceprocessor);
|
||||
ADD_LIST(vclk_m1d1g1_list, sclk_spi_sensorhub);
|
||||
ADD_LIST(vclk_m1d1g1_list, sclk_isp_sensor0);
|
||||
ADD_LIST(vclk_m1d1g1_list, sclk_isp_sensor1);
|
||||
ADD_LIST(vclk_m1d1g1_list, sclk_isp_sensor2);
|
||||
|
||||
|
||||
ADD_LIST(vclk_grpgate_list, gate_cpucl0_ppmu);
|
||||
ADD_LIST(vclk_grpgate_list, gate_cpucl0_bts);
|
||||
ADD_LIST(vclk_grpgate_list, gate_cpucll_ppmu);
|
||||
ADD_LIST(vclk_grpgate_list, gate_cpucll_bts);
|
||||
|
||||
ADD_LIST(vclk_grpgate_list, gate_mfcmscl_common);
|
||||
ADD_LIST(vclk_grpgate_list, gate_mfcmscl_common_mscl);
|
||||
ADD_LIST(vclk_grpgate_list, gate_mfcmscl_sysmmu_mscl);
|
||||
ADD_LIST(vclk_grpgate_list, gate_mfcmscl_sysmmu_mfc);
|
||||
ADD_LIST(vclk_grpgate_list, gate_mfcmscl_ppmu);
|
||||
ADD_LIST(vclk_grpgate_list, gate_mfcmscl_bts);
|
||||
ADD_LIST(vclk_grpgate_list, gate_mfcmscl_mscl_bi);
|
||||
ADD_LIST(vclk_grpgate_list, gate_mfcmscl_mscl_poly);
|
||||
ADD_LIST(vclk_grpgate_list, gate_mfcmscl_jpeg);
|
||||
ADD_LIST(vclk_grpgate_list, gate_mfcmscl_mfc);
|
||||
|
||||
ADD_LIST(vclk_grpgate_list, gate_g3d_common);
|
||||
ADD_LIST(vclk_grpgate_list, gate_g3d_sysmmu);
|
||||
ADD_LIST(vclk_grpgate_list, gate_g3d_ppmu);
|
||||
ADD_LIST(vclk_grpgate_list, gate_g3d_bts);
|
||||
ADD_LIST(vclk_grpgate_list, gate_g3d_g3d);
|
||||
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_peris0);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_peric0);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_peric1);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_pwm_motor);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_sclk_pwm_motor);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_mct);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_i2c_sensor2);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_i2c_sensor1);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_i2c_tsp);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_i2c_touchkey);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_i2c_fuelgauge);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_i2c_spkamp);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_i2c_nfc);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_i2c_muic);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_i2c_ifpmic);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_hsi2c_frontcam);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_hsi2c_maincam);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_hsi2c_depthcam);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_hsi2c_frontsensor);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_hsi2c_rearaf);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_hsi2c_rearsensor);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_gpio_touch);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_gpio_top);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_gpio_nfc);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_gpio_ese);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_wdt_cpucl1);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_wdt_cpucl0);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_uart_debug);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_uart_btwififm);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_uart_sensor);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_tmu_g3d);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_tmu_cpucl1);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_tmu_cpucl0);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_spi_sensorhub);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_spi_voiceprocessor);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_spi_ese);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_spi_rearfrom);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_spi_frontfrom);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_gpio_alive);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_chipid);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_otp_con_top);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_rtc_alive);
|
||||
ADD_LIST(vclk_grpgate_list, gate_peri_rtc_top);
|
||||
|
||||
ADD_LIST(vclk_grpgate_list, gate_fsys_common);
|
||||
ADD_LIST(vclk_grpgate_list, gate_fsys_common_sub1);
|
||||
ADD_LIST(vclk_grpgate_list, gate_fsys_common_sub2);
|
||||
ADD_LIST(vclk_grpgate_list, gate_fsys_sysmmu);
|
||||
ADD_LIST(vclk_grpgate_list, gate_fsys_ppmu);
|
||||
ADD_LIST(vclk_grpgate_list, gate_fsys_bts);
|
||||
ADD_LIST(vclk_grpgate_list, gate_fsys_usb20drd);
|
||||
ADD_LIST(vclk_grpgate_list, gate_fsys_mmc0);
|
||||
ADD_LIST(vclk_grpgate_list, gate_fsys_sclk_mmc0);
|
||||
ADD_LIST(vclk_grpgate_list, gate_fsys_mmc1);
|
||||
ADD_LIST(vclk_grpgate_list, gate_fsys_sclk_mmc1);
|
||||
ADD_LIST(vclk_grpgate_list, gate_fsys_mmc2);
|
||||
ADD_LIST(vclk_grpgate_list, gate_fsys_sclk_mmc2);
|
||||
ADD_LIST(vclk_grpgate_list, gate_fsys_sss);
|
||||
ADD_LIST(vclk_grpgate_list, gate_fsys_rtic);
|
||||
ADD_LIST(vclk_grpgate_list, gate_fsys_pdma0);
|
||||
ADD_LIST(vclk_grpgate_list, gate_fsys_pdma1);
|
||||
ADD_LIST(vclk_grpgate_list, gate_fsys_sromc);
|
||||
|
||||
ADD_LIST(vclk_grpgate_list, gate_dispaud_disp);
|
||||
ADD_LIST(vclk_grpgate_list, gate_dispaud_aud);
|
||||
ADD_LIST(vclk_grpgate_list, gate_dispaud_sysmmu);
|
||||
ADD_LIST(vclk_grpgate_list, gate_dispaud_ppmu);
|
||||
ADD_LIST(vclk_grpgate_list, gate_dispaud_bts);
|
||||
ADD_LIST(vclk_grpgate_list, gate_dispaud_decon);
|
||||
ADD_LIST(vclk_grpgate_list, gate_dispaud_dsim0);
|
||||
ADD_LIST(vclk_grpgate_list, gate_dispaud_mixer);
|
||||
ADD_LIST(vclk_grpgate_list, gate_dispaud_mi2s_aud);
|
||||
ADD_LIST(vclk_grpgate_list, gate_dispaud_mi2s_amp);
|
||||
|
||||
ADD_LIST(vclk_grpgate_list, gate_isp_common);
|
||||
ADD_LIST(vclk_grpgate_list, gate_isp_sysmmu);
|
||||
ADD_LIST(vclk_grpgate_list, gate_isp_ppmu);
|
||||
ADD_LIST(vclk_grpgate_list, gate_isp_bts);
|
||||
ADD_LIST(vclk_grpgate_list, gate_isp_cam);
|
||||
ADD_LIST(vclk_grpgate_list, gate_isp_isp);
|
||||
ADD_LIST(vclk_grpgate_list, gate_isp_vra);
|
||||
ADD_LIST(vclk_grpgate_list, gate_mif_adcif);
|
||||
ADD_LIST(vclk_grpgate_list, gate_mif_hsi2c_mif);
|
||||
ADD_LIST(vclk_grpgate_list, sclk_uart0);
|
||||
|
||||
ADD_LIST(vclk_umux_list, umux_dispaud_clkphy_dispaud_mipiphy_txbyteclkhs_user);
|
||||
ADD_LIST(vclk_umux_list, umux_dispaud_clkphy_dispaud_mipiphy_rxclkesc0_user);
|
||||
ADD_LIST(vclk_umux_list, umux_fsys_clkphy_fsys_usb20drd_phyclock_user);
|
||||
ADD_LIST(vclk_umux_list, umux_fsys_clkphy_fsys_ufs_tx0_symbol_user);
|
||||
ADD_LIST(vclk_umux_list, umux_fsys_clkphy_fsys_ufs_rx0_symbol_user);
|
||||
ADD_LIST(vclk_umux_list, umux_isp_clkphy_isp_s_rxbyteclkhs0_s4_user);
|
||||
ADD_LIST(vclk_umux_list, umux_isp_clkphy_isp_s_rxbyteclkhs0_s4s_user);
|
||||
|
||||
ADD_LIST(vclk_dfs_list, dvfs_cpucl0);
|
||||
ADD_LIST(vclk_dfs_list, dvfs_cpucl1);
|
||||
ADD_LIST(vclk_dfs_list, dvfs_g3d);
|
||||
ADD_LIST(vclk_dfs_list, dvfs_mif);
|
||||
ADD_LIST(vclk_dfs_list, dvfs_int);
|
||||
ADD_LIST(vclk_dfs_list, dvfs_disp);
|
||||
ADD_LIST(vclk_dfs_list, dvfs_cam);
|
||||
|
||||
return;
|
||||
}
|
||||
182
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-vclk.h
Normal file
182
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-vclk.h
Normal file
|
|
@ -0,0 +1,182 @@
|
|||
#ifndef __EXYNOS7870_VCLK_H__
|
||||
#define __EXYNOS7870_VCLK_H__
|
||||
|
||||
|
||||
enum {
|
||||
|
||||
gate_cpucl0_ppmu = 0x0A000000,
|
||||
gate_cpucl0_bts,
|
||||
gate_cpucll_ppmu,
|
||||
gate_cpucll_bts,
|
||||
gate_mfcmscl_sysmmu_mscl,
|
||||
gate_mfcmscl_sysmmu_mfc,
|
||||
gate_mfcmscl_ppmu,
|
||||
gate_mfcmscl_bts,
|
||||
gate_mfcmscl_common,
|
||||
gate_mfcmscl_common_mscl,
|
||||
gate_mfcmscl_mscl_bi,
|
||||
gate_mfcmscl_mscl_poly,
|
||||
gate_mfcmscl_jpeg,
|
||||
gate_mfcmscl_mfc,
|
||||
gate_g3d_common,
|
||||
gate_g3d_sysmmu,
|
||||
gate_g3d_ppmu,
|
||||
gate_g3d_bts,
|
||||
gate_g3d_g3d,
|
||||
gate_peri_peris0,
|
||||
gate_peri_peric0,
|
||||
gate_peri_peric1,
|
||||
gate_peri_pwm_motor,
|
||||
gate_peri_sclk_pwm_motor,
|
||||
gate_peri_mct,
|
||||
gate_peri_i2c_sensor2,
|
||||
gate_peri_i2c_sensor1,
|
||||
gate_peri_i2c_tsp,
|
||||
gate_peri_i2c_touchkey,
|
||||
gate_peri_i2c_fuelgauge,
|
||||
gate_peri_i2c_spkamp,
|
||||
gate_peri_i2c_nfc,
|
||||
gate_peri_i2c_muic,
|
||||
gate_peri_i2c_ifpmic,
|
||||
gate_peri_hsi2c_frontcam,
|
||||
gate_peri_hsi2c_maincam,
|
||||
gate_peri_hsi2c_depthcam,
|
||||
gate_peri_hsi2c_frontsensor,
|
||||
gate_peri_hsi2c_rearaf,
|
||||
gate_peri_hsi2c_rearsensor,
|
||||
gate_peri_gpio_touch,
|
||||
gate_peri_gpio_top,
|
||||
gate_peri_gpio_nfc,
|
||||
gate_peri_gpio_ese,
|
||||
gate_peri_wdt_cpucl1,
|
||||
gate_peri_wdt_cpucl0,
|
||||
gate_peri_uart_debug,
|
||||
gate_peri_uart_btwififm,
|
||||
gate_peri_uart_sensor,
|
||||
gate_peri_tmu_g3d,
|
||||
gate_peri_tmu_cpucl1,
|
||||
gate_peri_tmu_cpucl0,
|
||||
gate_peri_spi_sensorhub,
|
||||
gate_peri_spi_voiceprocessor,
|
||||
gate_peri_spi_ese,
|
||||
gate_peri_spi_rearfrom,
|
||||
gate_peri_spi_frontfrom,
|
||||
gate_peri_gpio_alive,
|
||||
gate_peri_chipid,
|
||||
gate_peri_otp_con_top,
|
||||
gate_peri_rtc_alive,
|
||||
gate_peri_rtc_top,
|
||||
|
||||
gate_fsys_common,
|
||||
gate_fsys_common_sub1,
|
||||
gate_fsys_common_sub2,
|
||||
gate_fsys_sysmmu,
|
||||
gate_fsys_ppmu,
|
||||
gate_fsys_bts,
|
||||
gate_fsys_usb20drd,
|
||||
gate_fsys_mmc0,
|
||||
gate_fsys_sclk_mmc0,
|
||||
gate_fsys_mmc1,
|
||||
gate_fsys_sclk_mmc1,
|
||||
gate_fsys_mmc2,
|
||||
gate_fsys_sclk_mmc2,
|
||||
gate_fsys_sss,
|
||||
gate_fsys_rtic,
|
||||
gate_fsys_pdma0,
|
||||
gate_fsys_pdma1,
|
||||
gate_fsys_sromc,
|
||||
gate_dispaud_disp,
|
||||
gate_dispaud_aud,
|
||||
gate_dispaud_sysmmu,
|
||||
gate_dispaud_ppmu,
|
||||
gate_dispaud_bts,
|
||||
gate_dispaud_decon,
|
||||
gate_dispaud_dsim0,
|
||||
gate_dispaud_mixer,
|
||||
gate_dispaud_mi2s_aud,
|
||||
gate_dispaud_mi2s_amp,
|
||||
gate_isp_common,
|
||||
gate_isp_sysmmu,
|
||||
gate_isp_ppmu,
|
||||
gate_isp_bts,
|
||||
gate_isp_cam,
|
||||
gate_isp_isp,
|
||||
gate_isp_vra,
|
||||
gate_mif_adcif,
|
||||
gate_mif_hsi2c_mif,
|
||||
sclk_uart0,
|
||||
vclk_group_grpgate_end,
|
||||
num_of_grpgate = vclk_group_grpgate_end - 0x0A000000,
|
||||
|
||||
|
||||
sclk_decon_vclk = 0x0A010000,
|
||||
sclk_decon_vclk_local,
|
||||
sclk_decon_eclk,
|
||||
sclk_decon_eclk_local,
|
||||
sclk_mmc0,
|
||||
sclk_mmc1,
|
||||
sclk_mmc2,
|
||||
sclk_ufsunipro,
|
||||
sclk_ufsunipro_cfg,
|
||||
sclk_usb20drd,
|
||||
sclk_uart_sensor,
|
||||
sclk_uart_btwififm,
|
||||
sclk_uart_debug,
|
||||
sclk_spi_frontfrom,
|
||||
sclk_spi_rearfrom,
|
||||
sclk_spi_ese,
|
||||
sclk_spi_voiceprocessor,
|
||||
sclk_spi_sensorhub,
|
||||
sclk_isp_sensor0,
|
||||
sclk_isp_sensor1,
|
||||
sclk_isp_sensor2,
|
||||
vclk_group_m1d1g1_end,
|
||||
num_of_m1d1g1 = vclk_group_m1d1g1_end - 0x0A010000,
|
||||
|
||||
p1_disp_pll = 0x0A020000,
|
||||
p1_aud_pll,
|
||||
p1_usb_pll,
|
||||
p1_isp_pll,
|
||||
vclk_group_p1_end,
|
||||
num_of_p1 = vclk_group_p1_end - 0x0A020000,
|
||||
|
||||
m1_dummy = 0x0A030000,
|
||||
vclk_group_m1_end,
|
||||
num_of_m1 = vclk_group_m1_end - 0x0A030000,
|
||||
|
||||
d1_dispaud_mi2s = 0x0A040000,
|
||||
d1_dispaud_mixer,
|
||||
vclk_group_d1_end,
|
||||
num_of_d1 = vclk_group_d1_end - 0x0A040000,
|
||||
|
||||
pxmxdx_top = 0x0A050000,
|
||||
pxmxdx_disp,
|
||||
pxmxdx_mfcmscl,
|
||||
pxmxdx_isp_vra,
|
||||
pxmxdx_isp_cam,
|
||||
pxmxdx_isp_isp,
|
||||
vclk_group_pxmxdx_end,
|
||||
num_of_pxmxdx = vclk_group_pxmxdx_end - 0x0A050000,
|
||||
|
||||
umux_dispaud_clkphy_dispaud_mipiphy_txbyteclkhs_user = 0x0A060000,
|
||||
umux_dispaud_clkphy_dispaud_mipiphy_rxclkesc0_user,
|
||||
umux_fsys_clkphy_fsys_usb20drd_phyclock_user,
|
||||
umux_fsys_clkphy_fsys_ufs_tx0_symbol_user,
|
||||
umux_fsys_clkphy_fsys_ufs_rx0_symbol_user,
|
||||
umux_isp_clkphy_isp_s_rxbyteclkhs0_s4_user,
|
||||
umux_isp_clkphy_isp_s_rxbyteclkhs0_s4s_user,
|
||||
vclk_group_umux_end,
|
||||
num_of_umux = vclk_group_umux_end - 0x0A060000,
|
||||
|
||||
dvfs_cpucl0 = 0x0A070000,
|
||||
dvfs_cpucl1,
|
||||
dvfs_g3d,
|
||||
dvfs_mif,
|
||||
dvfs_int,
|
||||
dvfs_disp,
|
||||
dvfs_cam,
|
||||
vclk_group_dfs_end,
|
||||
num_of_dfs = vclk_group_dfs_end - 0x0A070000,
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue