mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-11-02 00:55:37 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
537
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-pll.c
Normal file
537
drivers/soc/samsung/pwrcal/S5E7870/S5E7870-pll.c
Normal file
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@ -0,0 +1,537 @@
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#include "../pwrcal.h"
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#include "../pwrcal-clk.h"
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#include "../pwrcal-env.h"
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#include "../pwrcal-rae.h"
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#include "../pwrcal-pmu.h"
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#include "S5E7870-cmusfr.h"
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#include "S5E7870-pmusfr.h"
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#include "S5E7870-cmu.h"
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/*
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PLLs
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*/
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/* PLL141XX Clock Type */
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#define PLL141XX_MDIV_SHIFT 16
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#define PLL141XX_PDIV_SHIFT 8
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#define PLL141XX_SDIV_SHIFT 0
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#define PLL141XX_MDIV_MASK 0x3FF
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#define PLL141XX_PDIV_MASK 0x3F
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#define PLL141XX_SDIV_MASK 0x7
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#define PLL141XX_ENABLE 31
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#define PLL141XX_LOCKED 29
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#define PLL141XX_BYPASS 22
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/* PLL1431X Clock Type */
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#define PLL1431X_MDIV_SHIFT 16
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#define PLL1431X_PDIV_SHIFT 8
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#define PLL1431X_SDIV_SHIFT 0
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#define PLL1431X_K_SHIFT 0
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#define PLL1431X_MDIV_MASK 0x3FF
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#define PLL1431X_PDIV_MASK 0x3F
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#define PLL1431X_SDIV_MASK 0x7
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#define PLL1431X_K_MASK 0xFFFF
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#define PLL1431X_ENABLE 31
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#define PLL1431X_LOCKED 29
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#define PLL1431X_BYPASS 4
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#define FIN_HZ_26M (26*MHZ)
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static const struct pwrcal_pll_rate_table *_clk_get_pll_settings(
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struct pwrcal_pll *pll_clk,
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unsigned long long rate)
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{
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int i;
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const struct pwrcal_pll_rate_table *prate_table = pll_clk->rate_table;
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for (i = 0; i < pll_clk->rate_count; i++) {
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if (rate == prate_table[i].rate)
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return &prate_table[i];
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}
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return NULL;
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}
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static int _clk_pll141xx_find_pms(struct pll_spec *pll_spec,
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struct pwrcal_pll_rate_table *rate_table,
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unsigned long long rate)
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{
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unsigned int p, m, s;
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unsigned long long fref, fvco, fout;
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unsigned long long tmprate, tmpfout;
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unsigned long long mindiffrate = 0xFFFFFFFFFFFFFFFF;
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unsigned int min_p, min_m, min_s, min_fout;
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for (p = pll_spec->pdiv_min; p <= pll_spec->pdiv_max; p++) {
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fref = FIN_HZ_26M / p;
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if ((fref < pll_spec->fref_min) || (fref > pll_spec->fref_max))
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continue;
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for (s = pll_spec->sdiv_min; s <= pll_spec->sdiv_max; s++) {
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tmprate = rate;
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do_div(tmprate, MHZ);
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tmprate = tmprate * p * (1 << s);
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do_div(tmprate, (FIN_HZ_26M / MHZ));
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m = (unsigned int)tmprate;
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if ((m < pll_spec->mdiv_min)
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|| (m > pll_spec->mdiv_max))
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continue;
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fvco = ((unsigned long long)FIN_HZ_26M) * m;
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do_div(fvco, p);
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if ((fvco < pll_spec->fvco_min)
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|| (fvco > pll_spec->fvco_max))
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continue;
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fout = fvco >> s;
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if ((fout >= pll_spec->fout_min)
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&& (fout <= pll_spec->fout_max)) {
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tmprate = rate;
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do_div(tmprate, KHZ);
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tmpfout = fout;
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do_div(tmpfout, KHZ);
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if (tmprate == tmpfout) {
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rate_table->rate = fout;
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rate_table->pdiv = p;
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rate_table->mdiv = m;
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rate_table->sdiv = s;
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rate_table->kdiv = 0;
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return 0;
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}
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if (tmpfout < tmprate && mindiffrate > tmprate - tmpfout) {
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mindiffrate = tmprate - tmpfout;
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min_fout = fout;
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min_p = p;
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min_m = m;
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min_s = s;
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}
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}
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}
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}
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if (mindiffrate != 0xFFFFFFFFFFFFFFFF) {
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rate_table->rate = min_fout;
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rate_table->pdiv = min_p;
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rate_table->mdiv = min_m;
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rate_table->sdiv = min_s;
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rate_table->kdiv = 0;
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return 0;
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}
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return -1;
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}
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static int _clk_pll141xx_is_enabled(struct pwrcal_clk *clk)
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{
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return (int)(pwrcal_getbit(clk->offset, PLL141XX_ENABLE));
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}
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static int _clk_pll141xx_enable(struct pwrcal_clk *clk)
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{
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int timeout;
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pwrcal_setbit(clk->offset, PLL141XX_ENABLE, 1);
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for (timeout = 0;; timeout++) {
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if (pwrcal_getbit(clk->offset, PLL141XX_LOCKED))
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break;
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if (timeout > CLK_WAIT_CNT)
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return -1;
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cpu_relax();
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}
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return 0;
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}
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static int _clk_pll141xx_disable(struct pwrcal_clk *clk)
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{
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pwrcal_setbit(clk->offset, PLL141XX_ENABLE, 0);
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return 0;
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}
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int _clk_pll141xx_is_disabled_bypass(struct pwrcal_clk *clk)
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{
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if (pwrcal_getbit(clk->offset + 1, PLL141XX_BYPASS))
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return 0;
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return 1;
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}
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int _clk_pll141xx_set_bypass(struct pwrcal_clk *clk, int bypass_disable)
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{
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if (bypass_disable == 0)
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pwrcal_setbit(clk + 1, PLL141XX_BYPASS, 1);
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else
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pwrcal_setbit(clk + 1, PLL141XX_BYPASS, 0);
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return 0;
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}
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static int _clk_pll141xx_set_pms(struct pwrcal_clk *clk,
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const struct pwrcal_pll_rate_table *rate_table)
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{
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unsigned int mdiv, pdiv, sdiv, pll_con0;
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int timeout;
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pdiv = rate_table->pdiv;
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mdiv = rate_table->mdiv;
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sdiv = rate_table->sdiv;
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pll_con0 = pwrcal_readl(clk->offset);
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pll_con0 &= ~((PLL141XX_MDIV_MASK << PLL141XX_MDIV_SHIFT)
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| (PLL141XX_PDIV_MASK << PLL141XX_PDIV_SHIFT)
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| (PLL141XX_SDIV_MASK << PLL141XX_SDIV_SHIFT));
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pll_con0 |= (mdiv << PLL141XX_MDIV_SHIFT)
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| (pdiv << PLL141XX_PDIV_SHIFT)
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| (sdiv << PLL141XX_SDIV_SHIFT);
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pll_con0 &= ~(1 << 26);
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pll_con0 |= (1 << 5);
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pwrcal_writel(clk->status, pdiv * 150);
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pwrcal_writel(clk->offset, pll_con0);
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if (pll_con0 & (1 << PLL141XX_ENABLE)) {
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for (timeout = 0;; timeout++) {
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if (pwrcal_getbit(clk->offset, PLL141XX_LOCKED))
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break;
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if (timeout > CLK_WAIT_CNT)
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return -1;
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cpu_relax();
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}
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}
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return 0;
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}
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static int _clk_pll141xx_set_rate(struct pwrcal_clk *clk,
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unsigned long long rate)
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{
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struct pwrcal_pll *pll = to_pll(clk);
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struct pll_spec *pll_spec;
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struct pwrcal_pll_rate_table tmp_rate_table;
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const struct pwrcal_pll_rate_table *rate_table;
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if (rate == 0) {
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if (_clk_pll141xx_is_enabled(clk) != 0)
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if (_clk_pll141xx_disable(clk))
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goto errorout;
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return 0;
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}
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rate_table = _clk_get_pll_settings(pll, rate);
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if (rate_table == NULL) {
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pll_spec = clk_pll_get_spec(clk);
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if (pll_spec == NULL)
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goto errorout;
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if (_clk_pll141xx_find_pms(pll_spec, &tmp_rate_table, rate)) {
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pr_err("can't find pms value for rate(%lldHz) of \'%s\'",
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rate,
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clk->name);
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goto errorout;
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}
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rate_table = &tmp_rate_table;
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pr_warn("not exist in rate table, p(%d), m(%d), s(%d), fout(%lldHz) %s",
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rate_table->pdiv,
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rate_table->mdiv,
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rate_table->sdiv,
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rate,
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clk->name);
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}
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if (_clk_pll141xx_set_pms(clk, rate_table))
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goto errorout;
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if (rate != 0) {
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if (_clk_pll141xx_is_enabled(clk) == 0)
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_clk_pll141xx_enable(clk);
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}
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return 0;
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errorout:
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return -1;
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}
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static unsigned long long _clk_pll141xx_get_rate(struct pwrcal_clk *clk)
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{
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unsigned int mdiv, pdiv, sdiv, pll_con0;
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unsigned long long fout;
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if (_clk_pll141xx_is_enabled(clk) == 0)
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return 0;
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pll_con0 = pwrcal_readl(clk->offset);
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mdiv = (pll_con0 >> PLL141XX_MDIV_SHIFT) & PLL141XX_MDIV_MASK;
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pdiv = (pll_con0 >> PLL141XX_PDIV_SHIFT) & PLL141XX_PDIV_MASK;
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sdiv = (pll_con0 >> PLL141XX_SDIV_SHIFT) & PLL141XX_SDIV_MASK;
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if (pdiv == 0) {
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pr_err("pdiv is 0, id(%s)", clk->name);
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return 0;
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}
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fout = FIN_HZ_26M * mdiv;
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do_div(fout, (pdiv << sdiv));
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return (unsigned long long)fout;
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}
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static int _clk_pll1431x_find_pms(struct pll_spec *pll_spec,
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struct pwrcal_pll_rate_table *rate_table,
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unsigned long long rate)
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{
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unsigned int p, m, s;
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signed short k;
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unsigned long long fref, fvco, fout;
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unsigned long long tmprate, tmpfout;
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for (p = pll_spec->pdiv_min; p <= pll_spec->pdiv_max; p++) {
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fref = FIN_HZ_26M / p;
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if ((fref < pll_spec->fref_min) || (fref > pll_spec->fref_max))
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continue;
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for (s = pll_spec->sdiv_min; s <= pll_spec->sdiv_max; s++) {
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tmprate = rate;
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do_div(tmprate, MHZ);
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tmprate = tmprate * p * (1 << s);
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do_div(tmprate, (FIN_HZ_26M / MHZ));
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m = (unsigned int)tmprate;
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if ((m < pll_spec->mdiv_min)
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|| (m > pll_spec->mdiv_max))
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continue;
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tmprate = rate;
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do_div(tmprate, MHZ);
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tmprate = tmprate * p * (1 << s);
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do_div(tmprate, (FIN_HZ_26M / MHZ));
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tmprate = (tmprate - m) * 65536;
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k = (unsigned int)tmprate;
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if ((k < pll_spec->kdiv_min)
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|| (k > pll_spec->kdiv_max))
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continue;
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fvco = FIN_HZ_26M * ((m << 16) + k);
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do_div(fvco, p);
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fvco >>= 16;
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if ((fvco < pll_spec->fvco_min)
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|| (fvco > pll_spec->fvco_max))
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continue;
|
||||
|
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fout = fvco >> s;
|
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if ((fout >= pll_spec->fout_min)
|
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&& (fout <= pll_spec->fout_max)) {
|
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tmprate = rate;
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do_div(tmprate, KHZ);
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tmpfout = fout;
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do_div(tmpfout, KHZ);
|
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if (tmprate == tmpfout) {
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rate_table->rate = fout;
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rate_table->pdiv = p;
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rate_table->mdiv = m;
|
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rate_table->sdiv = s;
|
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rate_table->kdiv = k;
|
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return 0;
|
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}
|
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}
|
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}
|
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}
|
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|
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return -1;
|
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}
|
||||
|
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static int _clk_pll1431x_is_enabled(struct pwrcal_clk *clk)
|
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{
|
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return (int)(pwrcal_getbit(clk->offset, PLL1431X_ENABLE));
|
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}
|
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|
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static int _clk_pll1431x_enable(struct pwrcal_clk *clk)
|
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{
|
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int timeout;
|
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|
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pwrcal_setbit(clk->offset, PLL1431X_ENABLE, 1);
|
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|
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for (timeout = 0;; timeout++) {
|
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if (pwrcal_getbit(clk->offset, PLL1431X_LOCKED))
|
||||
break;
|
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if (timeout > CLK_WAIT_CNT)
|
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return -1;
|
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cpu_relax();
|
||||
}
|
||||
|
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return 0;
|
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}
|
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|
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static int _clk_pll1431x_disable(struct pwrcal_clk *clk)
|
||||
{
|
||||
pwrcal_setbit(clk->offset, PLL1431X_ENABLE, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int _clk_pll1431x_is_disabled_bypass(struct pwrcal_clk *clk)
|
||||
{
|
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if (pwrcal_getbit(clk->offset + 2, PLL1431X_BYPASS))
|
||||
return 0;
|
||||
|
||||
return 1;
|
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}
|
||||
|
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int _clk_pll1431x_set_bypass(struct pwrcal_clk *clk, int bypass_disable)
|
||||
{
|
||||
if (bypass_disable == 0)
|
||||
pwrcal_setbit(clk->offset + 2, PLL1431X_BYPASS, 1);
|
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else
|
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pwrcal_setbit(clk->offset + 2, PLL1431X_BYPASS, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _clk_pll1431x_set_pms(struct pwrcal_clk *clk,
|
||||
const struct pwrcal_pll_rate_table *rate_table)
|
||||
{
|
||||
unsigned int mdiv, pdiv, sdiv, pll_con0, pll_con1;
|
||||
signed short kdiv;
|
||||
int timeout;
|
||||
|
||||
pdiv = rate_table->pdiv;
|
||||
mdiv = rate_table->mdiv;
|
||||
sdiv = rate_table->sdiv;
|
||||
kdiv = rate_table->kdiv;
|
||||
|
||||
pll_con0 = pwrcal_readl(clk->offset);
|
||||
pll_con1 = pwrcal_readl(clk->offset + 1);
|
||||
pll_con0 &= ~((PLL1431X_MDIV_MASK << PLL1431X_MDIV_SHIFT)
|
||||
| (PLL1431X_PDIV_MASK << PLL1431X_PDIV_SHIFT)
|
||||
| (PLL1431X_SDIV_MASK << PLL1431X_SDIV_SHIFT));
|
||||
pll_con0 |= (mdiv << PLL1431X_MDIV_SHIFT)
|
||||
| (pdiv << PLL1431X_PDIV_SHIFT)
|
||||
| (sdiv << PLL1431X_SDIV_SHIFT);
|
||||
pll_con0 &= ~(1 << 26);
|
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pll_con0 |= (1 << 5);
|
||||
|
||||
pll_con1 &= ~(PLL1431X_K_MASK << PLL1431X_K_SHIFT);
|
||||
pll_con1 |= (kdiv << PLL1431X_K_SHIFT);
|
||||
|
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if (kdiv == 0)
|
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pwrcal_writel(clk->status, pdiv * 3000);
|
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else
|
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pwrcal_writel(clk->status, pdiv * 3000);
|
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pwrcal_writel(clk->offset, pll_con0);
|
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pwrcal_writel(clk->offset + 1, pll_con1);
|
||||
|
||||
if (pll_con0 & (1 << PLL1431X_ENABLE)) {
|
||||
for (timeout = 0;; timeout++) {
|
||||
if (pwrcal_getbit(clk->offset, PLL1431X_LOCKED))
|
||||
break;
|
||||
if (timeout > CLK_WAIT_CNT)
|
||||
return -1;
|
||||
cpu_relax();
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _clk_pll1431x_set_rate(struct pwrcal_clk *clk,
|
||||
unsigned long long rate)
|
||||
{
|
||||
struct pwrcal_pll *pll = to_pll(clk);
|
||||
struct pwrcal_pll_rate_table tmp_rate_table;
|
||||
const struct pwrcal_pll_rate_table *rate_table;
|
||||
struct pll_spec *pll_spec;
|
||||
|
||||
if (rate == 0) {
|
||||
if (_clk_pll1431x_is_enabled(clk) != 0)
|
||||
if (_clk_pll1431x_disable(clk))
|
||||
goto errorout;
|
||||
return 0;
|
||||
}
|
||||
|
||||
rate_table = _clk_get_pll_settings(pll, rate);
|
||||
if (rate_table == NULL) {
|
||||
pll_spec = clk_pll_get_spec(clk);
|
||||
if (pll_spec == NULL)
|
||||
goto errorout;
|
||||
|
||||
if (_clk_pll1431x_find_pms(pll_spec, &tmp_rate_table, rate) < 0) {
|
||||
pr_err("can't find pms value for rate(%lldHz) of %s",
|
||||
rate,
|
||||
clk->name);
|
||||
goto errorout;
|
||||
}
|
||||
|
||||
rate_table = &tmp_rate_table;
|
||||
pr_warn("not exist in rate table, p(%d) m(%d) s(%d) k(%d) fout(%lld Hz) of %s",
|
||||
rate_table->pdiv,
|
||||
rate_table->mdiv,
|
||||
rate_table->sdiv,
|
||||
rate_table->kdiv,
|
||||
rate,
|
||||
clk->name);
|
||||
}
|
||||
|
||||
if (_clk_pll1431x_set_pms(clk, rate_table))
|
||||
goto errorout;
|
||||
|
||||
if (rate != 0) {
|
||||
if (_clk_pll1431x_is_enabled(clk) == 0)
|
||||
_clk_pll1431x_enable(clk);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
errorout:
|
||||
return -1;
|
||||
}
|
||||
|
||||
static unsigned long long _clk_pll1431x_get_rate(struct pwrcal_clk *clk)
|
||||
{
|
||||
unsigned int mdiv, pdiv, sdiv, pll_con0, pll_con1;
|
||||
signed short kdiv;
|
||||
unsigned long long fout;
|
||||
|
||||
if (_clk_pll1431x_is_enabled(clk) == 0)
|
||||
return 0;
|
||||
|
||||
pll_con0 = pwrcal_readl(clk->offset);
|
||||
pll_con1 = pwrcal_readl(clk->offset + 1);
|
||||
mdiv = (pll_con0 >> PLL1431X_MDIV_SHIFT) & PLL1431X_MDIV_MASK;
|
||||
pdiv = (pll_con0 >> PLL1431X_PDIV_SHIFT) & PLL1431X_PDIV_MASK;
|
||||
sdiv = (pll_con0 >> PLL1431X_SDIV_SHIFT) & PLL1431X_SDIV_MASK;
|
||||
|
||||
kdiv = (short)(pll_con1 >> PLL1431X_K_SHIFT) & PLL1431X_K_MASK;
|
||||
|
||||
if (pdiv == 0) {
|
||||
pr_err("pdiv is 0, id(%s)", clk->name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
fout = FIN_HZ_26M * ((mdiv << 16) + kdiv);
|
||||
do_div(fout, (pdiv << sdiv));
|
||||
fout >>= 16;
|
||||
|
||||
return (unsigned long long)fout;
|
||||
}
|
||||
|
||||
struct pwrcal_pll_ops pll141xx_ops = {
|
||||
.is_enabled = _clk_pll141xx_is_enabled,
|
||||
.enable = _clk_pll141xx_enable,
|
||||
.disable = _clk_pll141xx_disable,
|
||||
.set_rate = _clk_pll141xx_set_rate,
|
||||
.get_rate = _clk_pll141xx_get_rate,
|
||||
};
|
||||
|
||||
struct pwrcal_pll_ops pll1431x_ops = {
|
||||
.is_enabled = _clk_pll1431x_is_enabled,
|
||||
.enable = _clk_pll1431x_enable,
|
||||
.disable = _clk_pll1431x_disable,
|
||||
.set_rate = _clk_pll1431x_set_rate,
|
||||
.get_rate = _clk_pll1431x_get_rate,
|
||||
};
|
||||
Loading…
Add table
Add a link
Reference in a new issue