mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 08:08:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
796
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-asv.c
Normal file
796
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-asv.c
Normal file
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@ -0,0 +1,796 @@
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#include "../pwrcal-env.h"
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#include "../pwrcal-rae.h"
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#include "../pwrcal-asv.h"
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#include "S5E8890-cmusfr.h"
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#include "S5E8890-cmu.h"
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#include "S5E8890-vclk.h"
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#include "S5E8890-vclk-internal.h"
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#include <soc/samsung/ect_parser.h>
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#ifdef PWRCAL_TARGET_LINUX
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#include <linux/io.h>
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#include <asm/map.h>
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#endif
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#ifdef PWRCAL_TARGET_FW
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#define S5P_VA_APM_SRAM ((void *)0x11200000)
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#endif
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#define EXYNOS_MAILBOX_RCC_MIN_MAX(x) (S5P_VA_APM_SRAM + (0x3700) + (x * 0x4))
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#define EXYNOS_MAILBOX_ATLAS_RCC(x) (S5P_VA_APM_SRAM + (0x3730) + (x * 0x4))
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#define EXYNOS_MAILBOX_APOLLO_RCC(x) (S5P_VA_APM_SRAM + (0x3798) + (x * 0x4))
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#define EXYNOS_MAILBOX_G3D_RCC(x) (S5P_VA_APM_SRAM + (0x37EC) + (x * 0x4))
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#define EXYNOS_MAILBOX_MIF_RCC(x) (S5P_VA_APM_SRAM + (0x381C) + (x * 0x4))
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enum dvfs_id {
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cal_asv_dvfs_big,
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cal_asv_dvfs_little,
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cal_asv_dvfs_g3d,
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cal_asv_dvfs_mif,
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cal_asv_dvfs_int,
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cal_asv_dvfs_cam,
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cal_asv_dvfs_disp,
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num_of_dvfs,
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};
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#define MAX_ASV_GROUP 16
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#define NUM_OF_ASVTABLE 1
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#define PWRCAL_ASV_LIST(table) {table, sizeof(table) / sizeof(table[0])}
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struct asv_table_entry {
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unsigned int index;
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unsigned int *voltage;
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};
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struct asv_table_list {
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struct asv_table_entry *table;
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unsigned int table_size;
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unsigned int voltage_count;
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};
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#define FORCE_ASV_MAGIC 0x57E90000
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static unsigned int force_asv_group[num_of_dvfs];
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#define APM_OTP_ADDRESS 0x101E9018
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#define APM_TABLE_BASE 0x11203700
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#define APM_FUSE_TABLE_BASE APM_TABLE_BASE
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#define APM_RCC_TABLE_BASE (APM_TABLE_BASE + 0x0030)
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static void *apm_sram_base;
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struct asv_tbl_info {
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unsigned mngs_asv_group:4;
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int mngs_modified_group:4;
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unsigned mngs_ssa10:2;
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unsigned mngs_ssa11:2;
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unsigned mngs_ssa0:4;
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unsigned apollo_asv_group:4;
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int apollo_modified_group:4;
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unsigned apollo_ssa10:2;
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unsigned apollo_ssa11:2;
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unsigned apollo_ssa0:4;
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unsigned g3d_asv_group:4;
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int g3d_modified_group:4;
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unsigned g3d_ssa10:2;
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unsigned g3d_ssa11:2;
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unsigned g3d_ssa0:4;
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unsigned mif_asv_group:4;
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int mif_modified_group:4;
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unsigned mif_ssa10:2;
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unsigned mif_ssa11:2;
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unsigned mif_ssa0:4;
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unsigned int_asv_group:4;
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int int_modified_group:4;
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unsigned int_ssa10:2;
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unsigned int_ssa11:2;
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unsigned int_ssa0:4;
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unsigned disp_asv_group:4;
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int disp_modified_group:4;
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unsigned disp_ssa10:2;
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unsigned disp_ssa11:2;
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unsigned disp_ssa0:4;
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unsigned asv_table_ver:7;
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unsigned fused_grp:1;
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unsigned reserved_0:12;
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unsigned g3d_mcs0:4;
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unsigned g3d_mcs1:4;
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};
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#define ASV_INFO_ADDR_BASE (0x101E9000)
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#define ASV_INFO_ADDR_CNT (sizeof(struct asv_tbl_info) / 4)
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static struct asv_tbl_info asv_tbl_info;
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static struct asv_table_list *pwrcal_big_asv_table;
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static struct asv_table_list *pwrcal_little_asv_table;
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static struct asv_table_list *pwrcal_g3d_asv_table;
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static struct asv_table_list *pwrcal_mif_asv_table;
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static struct asv_table_list *pwrcal_int_asv_table;
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static struct asv_table_list *pwrcal_cam_asv_table;
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static struct asv_table_list *pwrcal_disp_asv_table;
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static struct asv_table_list *pwrcal_big_rcc_table;
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static struct asv_table_list *pwrcal_little_rcc_table;
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static struct asv_table_list *pwrcal_g3d_rcc_table;
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static struct asv_table_list *pwrcal_mif_rcc_table;
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static struct pwrcal_vclk_dfs *asv_dvfs_big;
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static struct pwrcal_vclk_dfs *asv_dvfs_little;
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static struct pwrcal_vclk_dfs *asv_dvfs_g3d;
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static struct pwrcal_vclk_dfs *asv_dvfs_mif;
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static struct pwrcal_vclk_dfs *asv_dvfs_int;
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static struct pwrcal_vclk_dfs *asv_dvfs_cam;
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static struct pwrcal_vclk_dfs *asv_dvfs_disp;
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static void asv_set_grp(unsigned int id, unsigned int asvgrp)
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{
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force_asv_group[id & 0x0000FFFF] = FORCE_ASV_MAGIC | asvgrp;
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}
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static void asv_set_tablever(unsigned int version)
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{
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asv_tbl_info.asv_table_ver = version;
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return;
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}
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static struct freq_limit {
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unsigned int big_max;
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unsigned int little_max;
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unsigned int g3d_max;
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unsigned int mif_max;
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unsigned int int_max;
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unsigned int cam_max;
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unsigned int disp_max;
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} freq_limit_policy[] = {
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[0] = {
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.big_max = 1872000,
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.little_max = 1378000,
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.g3d_max = 600000,
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.mif_max = 1539000,
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},
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[1] = {
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.big_max = 1872000,
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.little_max = 1378000,
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.g3d_max = 600000,
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.mif_max = 1539000,
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},
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};
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static void asv_set_freq_limit(void)
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{
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if (!asv_tbl_info.fused_grp) {
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asv_dvfs_big->table->max_freq = 728000;
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asv_dvfs_little->table->max_freq = 1274000;
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asv_dvfs_g3d->table->max_freq = 260000;
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asv_dvfs_mif->table->max_freq = 1144000;
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} else {
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if (freq_limit_policy[asv_tbl_info.asv_table_ver].big_max)
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asv_dvfs_big->table->max_freq = freq_limit_policy[asv_tbl_info.asv_table_ver].big_max;
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if (freq_limit_policy[asv_tbl_info.asv_table_ver].little_max)
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asv_dvfs_little->table->max_freq = freq_limit_policy[asv_tbl_info.asv_table_ver].little_max;
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if (freq_limit_policy[asv_tbl_info.asv_table_ver].g3d_max)
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asv_dvfs_g3d->table->max_freq = freq_limit_policy[asv_tbl_info.asv_table_ver].g3d_max;
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if (freq_limit_policy[asv_tbl_info.asv_table_ver].mif_max)
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asv_dvfs_mif->table->max_freq = freq_limit_policy[asv_tbl_info.asv_table_ver].mif_max;
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if (freq_limit_policy[asv_tbl_info.asv_table_ver].int_max)
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asv_dvfs_int->table->max_freq = freq_limit_policy[asv_tbl_info.asv_table_ver].int_max;
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if (freq_limit_policy[asv_tbl_info.asv_table_ver].cam_max)
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asv_dvfs_cam->table->max_freq = freq_limit_policy[asv_tbl_info.asv_table_ver].cam_max;
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if (freq_limit_policy[asv_tbl_info.asv_table_ver].disp_max)
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asv_dvfs_disp->table->max_freq = freq_limit_policy[asv_tbl_info.asv_table_ver].disp_max;
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}
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return;
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}
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static void asv_get_asvinfo(void)
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{
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int i;
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unsigned int *pasv_table;
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unsigned long tmp;
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pasv_table = (unsigned int *)&asv_tbl_info;
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for (i = 0; i < ASV_INFO_ADDR_CNT; i++) {
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#ifdef PWRCAL_TARGET_LINUX
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exynos_smc_readsfr((unsigned long)(ASV_INFO_ADDR_BASE + 0x4 * i), &tmp);
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#else
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#if (CONFIG_STARTUP_EL_MODE == STARTUP_EL3)
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tmp = *((volatile unsigned int *)(unsigned long)(ASV_INFO_ADDR_BASE + 0x4 * i));
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#else
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smc_readsfr((unsigned long)(ASV_INFO_ADDR_BASE + 0x4 * i), &tmp);
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#endif
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#endif
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*(pasv_table + i) = (unsigned int)tmp;
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}
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if (!asv_tbl_info.fused_grp) {
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asv_tbl_info.mngs_asv_group = 0;
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asv_tbl_info.mngs_modified_group = 0;
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asv_tbl_info.mngs_ssa10 = 0;
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asv_tbl_info.mngs_ssa11 = 0;
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asv_tbl_info.mngs_ssa0 = 0;
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asv_tbl_info.apollo_asv_group = 0;
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asv_tbl_info.apollo_modified_group = 0;
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asv_tbl_info.apollo_ssa10 = 0;
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asv_tbl_info.apollo_ssa11 = 0;
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asv_tbl_info.apollo_ssa0 = 0;
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asv_tbl_info.g3d_asv_group = 0;
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asv_tbl_info.g3d_modified_group = 0;
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asv_tbl_info.g3d_ssa10 = 0;
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asv_tbl_info.g3d_ssa11 = 0;
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asv_tbl_info.g3d_ssa0 = 0;
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asv_tbl_info.mif_asv_group = 0;
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asv_tbl_info.mif_modified_group = 0;
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asv_tbl_info.mif_ssa10 = 0;
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asv_tbl_info.mif_ssa11 = 0;
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asv_tbl_info.mif_ssa0 = 0;
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asv_tbl_info.int_asv_group = 0;
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asv_tbl_info.int_modified_group = 0;
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asv_tbl_info.int_ssa10 = 0;
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asv_tbl_info.int_ssa11 = 0;
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asv_tbl_info.int_ssa0 = 0;
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asv_tbl_info.disp_asv_group = 0;
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asv_tbl_info.disp_modified_group = 0;
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asv_tbl_info.disp_ssa10 = 0;
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asv_tbl_info.disp_ssa11 = 0;
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asv_tbl_info.disp_ssa0 = 0;
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asv_tbl_info.asv_table_ver = 0;
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asv_tbl_info.fused_grp = 0;
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asv_tbl_info.reserved_0 = 0;
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asv_tbl_info.g3d_mcs0 = 0;
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asv_tbl_info.g3d_mcs1 = 0;
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}
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if (asv_tbl_info.g3d_mcs0 == 0)
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asv_tbl_info.g3d_mcs0 = 0x5;
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if (asv_tbl_info.g3d_mcs1 == 0)
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asv_tbl_info.g3d_mcs1 = 0xE;
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asv_set_freq_limit();
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}
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static int get_asv_group(enum dvfs_id domain, unsigned int lv)
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{
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int asv = 0;
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int mod = 0;
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switch (domain) {
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case cal_asv_dvfs_big:
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asv = asv_tbl_info.mngs_asv_group;
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mod = asv_tbl_info.mngs_modified_group;
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break;
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case cal_asv_dvfs_little:
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asv = asv_tbl_info.apollo_asv_group;
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mod = asv_tbl_info.apollo_modified_group;
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break;
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case cal_asv_dvfs_g3d:
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asv = asv_tbl_info.g3d_asv_group;
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mod = asv_tbl_info.g3d_modified_group;
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break;
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case cal_asv_dvfs_mif:
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asv = asv_tbl_info.mif_asv_group;
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mod = asv_tbl_info.mif_modified_group;
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break;
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case cal_asv_dvfs_int:
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asv = asv_tbl_info.int_asv_group;
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mod = asv_tbl_info.int_modified_group;
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break;
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case cal_asv_dvfs_cam:
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asv = asv_tbl_info.disp_asv_group;
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mod = asv_tbl_info.disp_modified_group;
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break;
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case cal_asv_dvfs_disp:
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asv = asv_tbl_info.disp_asv_group;
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mod = asv_tbl_info.disp_modified_group;
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break;
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default:
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BUG(); /* Never reach */
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break;
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}
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if ((force_asv_group[domain & 0x0000FFFF] & 0xFFFF0000) != FORCE_ASV_MAGIC) {
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if (mod)
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asv += mod;
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} else {
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asv = force_asv_group[domain & 0x0000FFFF] & 0x0000FFFF;
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}
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if (asv < 0 || asv >= MAX_ASV_GROUP)
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BUG(); /* Never reach */
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return asv;
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}
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static unsigned int get_asv_voltage(enum dvfs_id domain, unsigned int lv)
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{
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int asv;
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unsigned int ssa10, ssa11;
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unsigned int ssa0;
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unsigned int subgrp_index;
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const unsigned int *table;
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unsigned int volt;
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switch (domain) {
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case cal_asv_dvfs_big:
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asv = get_asv_group(cal_asv_dvfs_big, lv);
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ssa10 = asv_tbl_info.mngs_ssa10;
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ssa11 = asv_tbl_info.mngs_ssa11;
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ssa0 = asv_tbl_info.mngs_ssa0;
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subgrp_index = 16;
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table = pwrcal_big_asv_table[asv_tbl_info.asv_table_ver].table[lv].voltage;
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break;
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case cal_asv_dvfs_little:
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asv = get_asv_group(cal_asv_dvfs_little, lv);
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ssa10 = asv_tbl_info.apollo_ssa10;
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ssa11 = asv_tbl_info.apollo_ssa11;
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ssa0 = asv_tbl_info.apollo_ssa0;
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subgrp_index = 10;
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table = pwrcal_little_asv_table[asv_tbl_info.asv_table_ver].table[lv].voltage;
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break;
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case cal_asv_dvfs_g3d:
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asv = get_asv_group(cal_asv_dvfs_g3d, lv);
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ssa10 = asv_tbl_info.g3d_ssa10;
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ssa11 = asv_tbl_info.g3d_ssa11;
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ssa0 = asv_tbl_info.g3d_ssa0;
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subgrp_index = 7;
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table = pwrcal_g3d_asv_table[asv_tbl_info.asv_table_ver].table[lv].voltage;
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break;
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case cal_asv_dvfs_mif:
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asv = get_asv_group(cal_asv_dvfs_mif, lv);
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ssa10 = asv_tbl_info.mif_ssa10;
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ssa11 = asv_tbl_info.mif_ssa11;
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ssa0 = asv_tbl_info.mif_ssa0;
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subgrp_index = 8;
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table = pwrcal_mif_asv_table[asv_tbl_info.asv_table_ver].table[lv].voltage;
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break;
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case cal_asv_dvfs_int:
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asv = get_asv_group(cal_asv_dvfs_int, lv);
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ssa10 = asv_tbl_info.int_ssa10;
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ssa11 = asv_tbl_info.int_ssa11;
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ssa0 = asv_tbl_info.int_ssa0;
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subgrp_index = 15;
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table = pwrcal_int_asv_table[asv_tbl_info.asv_table_ver].table[lv].voltage;
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break;
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case cal_asv_dvfs_cam:
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asv = get_asv_group(cal_asv_dvfs_cam, lv);
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ssa10 = asv_tbl_info.disp_ssa10;
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ssa11 = asv_tbl_info.disp_ssa11;
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ssa0 = asv_tbl_info.disp_ssa0;
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subgrp_index = 5;
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table = pwrcal_cam_asv_table[asv_tbl_info.asv_table_ver].table[lv].voltage;
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break;
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case cal_asv_dvfs_disp:
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asv = get_asv_group(cal_asv_dvfs_disp, lv);
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ssa10 = asv_tbl_info.disp_ssa10;
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ssa11 = asv_tbl_info.disp_ssa11;
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ssa0 = asv_tbl_info.disp_ssa0;
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subgrp_index = 2;
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table = pwrcal_disp_asv_table[asv_tbl_info.asv_table_ver].table[lv].voltage;
|
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break;
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default:
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BUG(); /* Never reach */
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break;
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}
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volt = table[asv];
|
||||
if (lv < subgrp_index) {
|
||||
volt += 12500 * ssa10;
|
||||
if (ssa10 == 3)
|
||||
volt += 12500;
|
||||
} else {
|
||||
volt += 12500 * ssa11;
|
||||
if (ssa11 == 3)
|
||||
volt += 12500;
|
||||
}
|
||||
|
||||
if (volt < 575000 + ssa0 * 25000)
|
||||
volt = 575000 + ssa0 * 25000;
|
||||
|
||||
return volt;
|
||||
}
|
||||
|
||||
static int dvfsbig_get_asv_table(unsigned int *table)
|
||||
{
|
||||
int lv, max_lv;
|
||||
|
||||
max_lv = asv_dvfs_big->table->num_of_lv;
|
||||
|
||||
for (lv = 0; lv < max_lv; lv++)
|
||||
table[lv] = get_asv_voltage(cal_asv_dvfs_big, lv);
|
||||
|
||||
return max_lv;
|
||||
}
|
||||
|
||||
static int dvfslittle_get_asv_table(unsigned int *table)
|
||||
{
|
||||
int lv, max_lv;
|
||||
|
||||
max_lv = asv_dvfs_little->table->num_of_lv;
|
||||
|
||||
for (lv = 0; lv < max_lv; lv++)
|
||||
table[lv] = get_asv_voltage(cal_asv_dvfs_little, lv);
|
||||
|
||||
return max_lv;
|
||||
}
|
||||
|
||||
static int dvfsg3d_get_asv_table(unsigned int *table)
|
||||
{
|
||||
int lv, max_lv;
|
||||
|
||||
max_lv = asv_dvfs_g3d->table->num_of_lv;
|
||||
|
||||
for (lv = 0; lv < max_lv; lv++)
|
||||
table[lv] = get_asv_voltage(cal_asv_dvfs_g3d, lv);
|
||||
|
||||
return max_lv;
|
||||
}
|
||||
|
||||
static int dvfsmif_get_asv_table(unsigned int *table)
|
||||
{
|
||||
int lv, max_lv;
|
||||
|
||||
max_lv = asv_dvfs_mif->table->num_of_lv;
|
||||
|
||||
for (lv = 0; lv < max_lv; lv++)
|
||||
table[lv] = get_asv_voltage(cal_asv_dvfs_mif, lv);
|
||||
|
||||
return max_lv;
|
||||
}
|
||||
|
||||
static int dvfsint_get_asv_table(unsigned int *table)
|
||||
{
|
||||
int lv, max_lv;
|
||||
|
||||
max_lv = asv_dvfs_int->table->num_of_lv;
|
||||
|
||||
for (lv = 0; lv < max_lv; lv++)
|
||||
table[lv] = get_asv_voltage(cal_asv_dvfs_int, lv);
|
||||
|
||||
return max_lv;
|
||||
}
|
||||
|
||||
static int dvfscam_get_asv_table(unsigned int *table)
|
||||
{
|
||||
int lv, max_lv;
|
||||
|
||||
max_lv = asv_dvfs_cam->table->num_of_lv;
|
||||
|
||||
for (lv = 0; lv < max_lv; lv++)
|
||||
table[lv] = get_asv_voltage(cal_asv_dvfs_cam, lv);
|
||||
|
||||
return max_lv;
|
||||
}
|
||||
|
||||
static int dvfsdisp_get_asv_table(unsigned int *table)
|
||||
{
|
||||
int lv, max_lv;
|
||||
|
||||
max_lv = asv_dvfs_disp->table->num_of_lv;
|
||||
|
||||
for (lv = 0; lv < max_lv; lv++)
|
||||
table[lv] = get_asv_voltage(cal_asv_dvfs_disp, lv);
|
||||
|
||||
return max_lv;
|
||||
}
|
||||
|
||||
static int dfsg3d_set_ema(unsigned int volt)
|
||||
{
|
||||
if (volt > 750000)
|
||||
pwrcal_writel(EMA_RF2_UHD_CON, asv_tbl_info.g3d_mcs0);
|
||||
else
|
||||
pwrcal_writel(EMA_RF2_UHD_CON, asv_tbl_info.g3d_mcs1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int asv_rcc_set_table(void)
|
||||
{
|
||||
int i;
|
||||
int lv, max_lv, asv;
|
||||
unsigned int *p;
|
||||
unsigned long tmp;
|
||||
|
||||
if (!apm_sram_base) {
|
||||
#ifdef PWRCAL_TARGET_LINUX
|
||||
apm_sram_base = (void *)ioremap(APM_TABLE_BASE, SZ_4K);
|
||||
#else
|
||||
apm_sram_base = (void *)APM_TABLE_BASE;
|
||||
#endif
|
||||
}
|
||||
|
||||
p = (unsigned int *)(apm_sram_base);
|
||||
for (i = 0; i < 8; i++) {
|
||||
#ifdef PWRCAL_TARGET_LINUX
|
||||
exynos_smc_readsfr((unsigned long)(APM_OTP_ADDRESS + 0x4 * i), &tmp);
|
||||
#else
|
||||
#if (CONFIG_STARTUP_EL_MODE == STARTUP_EL3)
|
||||
tmp = *((volatile unsigned int *)(unsigned long)(APM_OTP_ADDRESS + 0x4 * i));
|
||||
#else
|
||||
smc_readsfr((unsigned long)(APM_OTP_ADDRESS + 0x4 * i), &tmp);
|
||||
#endif
|
||||
#endif
|
||||
*(p + i) = (unsigned int)tmp;
|
||||
}
|
||||
|
||||
p = (unsigned int *)(apm_sram_base + 0x0030);
|
||||
max_lv = asv_dvfs_big->table->num_of_lv;
|
||||
if (max_lv > 25)
|
||||
max_lv = 25;
|
||||
for (lv = 0; lv < max_lv; lv++) {
|
||||
asv = get_asv_group(cal_asv_dvfs_big, lv);
|
||||
*(p + lv) = pwrcal_big_rcc_table[asv_tbl_info.asv_table_ver].table[lv].voltage[asv];
|
||||
}
|
||||
|
||||
p = (unsigned int *)(apm_sram_base + 0x0098);
|
||||
max_lv = asv_dvfs_little->table->num_of_lv;
|
||||
if (max_lv > 20)
|
||||
max_lv = 20;
|
||||
for (lv = 0; lv < max_lv; lv++) {
|
||||
asv = get_asv_group(cal_asv_dvfs_little, lv);
|
||||
*(p + lv) = pwrcal_little_rcc_table[asv_tbl_info.asv_table_ver].table[lv].voltage[asv];
|
||||
}
|
||||
|
||||
p = (unsigned int *)(apm_sram_base + 0x00EC);
|
||||
max_lv = asv_dvfs_g3d->table->num_of_lv;
|
||||
if (max_lv > 11)
|
||||
max_lv = 11;
|
||||
for (lv = 0; lv < max_lv; lv++) {
|
||||
asv = get_asv_group(cal_asv_dvfs_g3d, lv);
|
||||
*(p + lv) = pwrcal_g3d_rcc_table[asv_tbl_info.asv_table_ver].table[lv].voltage[asv];
|
||||
}
|
||||
|
||||
p = (unsigned int *)(apm_sram_base + 0x011C);
|
||||
max_lv = asv_dvfs_mif->table->num_of_lv;
|
||||
if (max_lv > 16)
|
||||
max_lv = 16;
|
||||
for (lv = 0; lv < max_lv; lv++) {
|
||||
asv = get_asv_group(cal_asv_dvfs_mif, lv);
|
||||
*(p + lv) = pwrcal_mif_rcc_table[asv_tbl_info.asv_table_ver].table[lv].voltage[asv];
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void asv_voltage_init_table(struct asv_table_list **asv_table, struct pwrcal_vclk_dfs *dfs)
|
||||
{
|
||||
int i, j, k;
|
||||
void *asv_block, *margin_block;
|
||||
struct ect_voltage_domain *domain;
|
||||
struct ect_voltage_table *table;
|
||||
struct asv_table_entry *asv_entry;
|
||||
struct ect_margin_domain *margin_domain = NULL;
|
||||
|
||||
asv_block = ect_get_block("ASV");
|
||||
if (asv_block == NULL)
|
||||
return;
|
||||
|
||||
margin_block = ect_get_block("MARGIN");
|
||||
|
||||
domain = ect_asv_get_domain(asv_block, dfs->vclk.name);
|
||||
if (domain == NULL)
|
||||
return;
|
||||
|
||||
if (asv_tbl_info.asv_table_ver >= domain->num_of_table)
|
||||
BUG();
|
||||
|
||||
if (margin_block)
|
||||
margin_domain = ect_margin_get_domain(margin_block, dfs->vclk.name);
|
||||
|
||||
*asv_table = kzalloc(sizeof(struct asv_table_list) * domain->num_of_table, GFP_KERNEL);
|
||||
if (*asv_table == NULL)
|
||||
return;
|
||||
|
||||
for (i = 0; i < domain->num_of_table; ++i) {
|
||||
table = &domain->table_list[i];
|
||||
|
||||
(*asv_table)[i].table_size = domain->num_of_table;
|
||||
(*asv_table)[i].table = kzalloc(sizeof(struct asv_table_entry) * domain->num_of_level, GFP_KERNEL);
|
||||
if ((*asv_table)[i].table == NULL)
|
||||
return;
|
||||
|
||||
for (j = 0; j < domain->num_of_level; ++j) {
|
||||
asv_entry = &(*asv_table)[i].table[j];
|
||||
|
||||
asv_entry->index = domain->level_list[j];
|
||||
asv_entry->voltage = kzalloc(sizeof(unsigned int) * domain->num_of_group, GFP_KERNEL);
|
||||
|
||||
for (k = 0; k < domain->num_of_group; ++k) {
|
||||
asv_entry->voltage[k] = table->voltages[j * domain->num_of_group + k];
|
||||
if (margin_domain != NULL)
|
||||
asv_entry->voltage[k] += margin_domain->offset[j * margin_domain->num_of_group + k];
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void asv_rcc_init_table(struct asv_table_list **rcc_table, struct pwrcal_vclk_dfs *dfs)
|
||||
|
||||
{
|
||||
int i, j, k;
|
||||
void *rcc_block;
|
||||
struct ect_rcc_domain *domain;
|
||||
struct ect_rcc_table *table;
|
||||
struct asv_table_entry *rcc_entry;
|
||||
|
||||
rcc_block = ect_get_block("RCC");
|
||||
if (rcc_block == NULL)
|
||||
return;
|
||||
|
||||
domain = ect_rcc_get_domain(rcc_block, dfs->vclk.name);
|
||||
if (domain == NULL)
|
||||
return;
|
||||
|
||||
*rcc_table = kzalloc(sizeof(struct asv_table_list) * domain->num_of_table, GFP_KERNEL);
|
||||
if (*rcc_table == NULL)
|
||||
return;
|
||||
|
||||
for (i = 0; i < domain->num_of_table; ++i) {
|
||||
table = &domain->table_list[i];
|
||||
|
||||
(*rcc_table)[i].table_size = domain->num_of_table;
|
||||
(*rcc_table)[i].table = kzalloc(sizeof(struct asv_table_entry) * domain->num_of_level, GFP_KERNEL);
|
||||
if ((*rcc_table)[i].table == NULL)
|
||||
return;
|
||||
|
||||
for (j = 0; j < domain->num_of_level; ++j) {
|
||||
rcc_entry = &(*rcc_table)[i].table[j];
|
||||
|
||||
rcc_entry->index = domain->level_list[j];
|
||||
rcc_entry->voltage = kzalloc(sizeof(unsigned int) * domain->num_of_group, GFP_KERNEL);
|
||||
|
||||
for (k = 0; k < domain->num_of_group; ++k)
|
||||
rcc_entry->voltage[k] = table->rcc[j * domain->num_of_group + k];
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void asv_voltage_table_init(void)
|
||||
{
|
||||
asv_voltage_init_table(&pwrcal_big_asv_table, asv_dvfs_big);
|
||||
asv_voltage_init_table(&pwrcal_little_asv_table, asv_dvfs_little);
|
||||
asv_voltage_init_table(&pwrcal_g3d_asv_table, asv_dvfs_g3d);
|
||||
asv_voltage_init_table(&pwrcal_mif_asv_table, asv_dvfs_mif);
|
||||
asv_voltage_init_table(&pwrcal_int_asv_table, asv_dvfs_int);
|
||||
asv_voltage_init_table(&pwrcal_cam_asv_table, asv_dvfs_cam);
|
||||
asv_voltage_init_table(&pwrcal_disp_asv_table, asv_dvfs_disp);
|
||||
}
|
||||
|
||||
static void asv_rcc_table_init(void)
|
||||
{
|
||||
asv_rcc_init_table(&pwrcal_big_rcc_table, asv_dvfs_big);
|
||||
asv_rcc_init_table(&pwrcal_little_rcc_table, asv_dvfs_little);
|
||||
asv_rcc_init_table(&pwrcal_g3d_rcc_table, asv_dvfs_g3d);
|
||||
asv_rcc_init_table(&pwrcal_mif_rcc_table, asv_dvfs_mif);
|
||||
}
|
||||
|
||||
static int asv_init(void)
|
||||
{
|
||||
struct vclk *vclk;
|
||||
|
||||
vclk = cal_get_vclk(dvfs_big);
|
||||
asv_dvfs_big = to_dfs(vclk);
|
||||
asv_dvfs_big->dfsops->get_asv_table = dvfsbig_get_asv_table;
|
||||
/* asv_dvfs_big->dfsops->set_ema = dvfsbig_set_ema;
|
||||
*/
|
||||
vclk = cal_get_vclk(dvfs_little);
|
||||
asv_dvfs_little = to_dfs(vclk);
|
||||
asv_dvfs_little->dfsops->get_asv_table = dvfslittle_get_asv_table;
|
||||
/* asv_dvfs_little->dfsops->set_ema = dvfslittle_set_ema;
|
||||
*/
|
||||
vclk = cal_get_vclk(dvfs_g3d);
|
||||
asv_dvfs_g3d = to_dfs(vclk);
|
||||
asv_dvfs_g3d->dfsops->get_asv_table = dvfsg3d_get_asv_table;
|
||||
asv_dvfs_g3d->dfsops->set_ema = dfsg3d_set_ema;
|
||||
|
||||
vclk = cal_get_vclk(dvfs_mif);
|
||||
asv_dvfs_mif = to_dfs(vclk);
|
||||
asv_dvfs_mif->dfsops->get_asv_table = dvfsmif_get_asv_table;
|
||||
|
||||
vclk = cal_get_vclk(dvfs_int);
|
||||
asv_dvfs_int = to_dfs(vclk);
|
||||
asv_dvfs_int->dfsops->get_asv_table = dvfsint_get_asv_table;
|
||||
/* asv_dvfs_int->dfsops->set_ema = dvfsint_set_ema;
|
||||
*/
|
||||
vclk = cal_get_vclk(dvfs_cam);
|
||||
asv_dvfs_cam = to_dfs(vclk);
|
||||
asv_dvfs_cam->dfsops->get_asv_table = dvfscam_get_asv_table;
|
||||
|
||||
vclk = cal_get_vclk(dvfs_disp);
|
||||
asv_dvfs_disp = to_dfs(vclk);
|
||||
asv_dvfs_disp->dfsops->get_asv_table = dvfsdisp_get_asv_table;
|
||||
|
||||
pwrcal_big_asv_table = NULL;
|
||||
pwrcal_little_asv_table = NULL;
|
||||
pwrcal_g3d_asv_table = NULL;
|
||||
pwrcal_mif_asv_table = NULL;
|
||||
pwrcal_int_asv_table = NULL;
|
||||
pwrcal_cam_asv_table = NULL;
|
||||
pwrcal_disp_asv_table = NULL;
|
||||
|
||||
pwrcal_big_rcc_table = NULL;
|
||||
pwrcal_little_rcc_table = NULL;
|
||||
pwrcal_g3d_rcc_table = NULL;
|
||||
pwrcal_mif_rcc_table = NULL;
|
||||
|
||||
asv_get_asvinfo();
|
||||
asv_voltage_table_init();
|
||||
asv_rcc_table_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void asv_print_info(void)
|
||||
{
|
||||
pr_info("asv_table_ver : %d\n", asv_tbl_info.asv_table_ver);
|
||||
pr_info("fused_grp : %d\n", asv_tbl_info.fused_grp);
|
||||
|
||||
pr_info("mngs_asv_group : %d\n", asv_tbl_info.mngs_asv_group);
|
||||
pr_info("mngs_modified_group : %d\n", asv_tbl_info.mngs_modified_group);
|
||||
pr_info("apollo_asv_group : %d\n", asv_tbl_info.apollo_asv_group);
|
||||
pr_info("apollo_modified_group : %d\n", asv_tbl_info.apollo_modified_group);
|
||||
|
||||
pr_info("g3d_asv_group : %d\n", asv_tbl_info.g3d_asv_group);
|
||||
pr_info("g3d_modified_group : %d\n", asv_tbl_info.g3d_modified_group);
|
||||
pr_info("mif_asv_group : %d\n", asv_tbl_info.mif_asv_group);
|
||||
pr_info("mif_modified_group : %d\n", asv_tbl_info.mif_modified_group);
|
||||
|
||||
pr_info("int_asv_group : %d\n", asv_tbl_info.int_asv_group);
|
||||
pr_info("int_modified_group : %d\n", asv_tbl_info.int_modified_group);
|
||||
pr_info("disp_asv_group : %d\n", asv_tbl_info.disp_asv_group);
|
||||
pr_info("disp_modified_group : %d\n", asv_tbl_info.disp_modified_group);
|
||||
|
||||
pr_info("g3d_mcs0 : %d\n", asv_tbl_info.g3d_mcs0);
|
||||
pr_info("g3d_mcs1 : %d\n", asv_tbl_info.g3d_mcs1);
|
||||
}
|
||||
|
||||
static void rcc_print_info(void)
|
||||
{
|
||||
int lv, max_lv, asv;
|
||||
|
||||
pr_info("==== RCC Table ====\n");
|
||||
max_lv = asv_dvfs_big->table->num_of_lv;
|
||||
if (max_lv > 25)
|
||||
max_lv = 25;
|
||||
for (lv = 0; lv < max_lv; lv++) {
|
||||
asv = get_asv_group(cal_asv_dvfs_big, lv);
|
||||
pr_info("big rcc [%d] : %d\n", lv, pwrcal_big_rcc_table[asv_tbl_info.asv_table_ver].table[lv].voltage[asv]);
|
||||
}
|
||||
|
||||
max_lv = asv_dvfs_little->table->num_of_lv;
|
||||
if (max_lv > 20)
|
||||
max_lv = 20;
|
||||
for (lv = 0; lv < max_lv; lv++) {
|
||||
asv = get_asv_group(cal_asv_dvfs_little, lv);
|
||||
pr_info("little rcc [%d] : %d\n", lv, pwrcal_little_rcc_table[asv_tbl_info.asv_table_ver].table[lv].voltage[asv]);
|
||||
}
|
||||
|
||||
max_lv = asv_dvfs_g3d->table->num_of_lv;
|
||||
if (max_lv > 11)
|
||||
max_lv = 11;
|
||||
for (lv = 0; lv < max_lv; lv++) {
|
||||
asv = get_asv_group(cal_asv_dvfs_g3d, lv);
|
||||
pr_info("g3d rcc [%d] : %d\n", lv, pwrcal_g3d_rcc_table[asv_tbl_info.asv_table_ver].table[lv].voltage[asv]);
|
||||
}
|
||||
|
||||
max_lv = asv_dvfs_mif->table->num_of_lv;
|
||||
if (max_lv > 16)
|
||||
max_lv = 16;
|
||||
for (lv = 0; lv < max_lv; lv++) {
|
||||
asv = get_asv_group(cal_asv_dvfs_mif, lv);
|
||||
pr_info("mif rcc [%d] : %d\n", lv, pwrcal_mif_rcc_table[asv_tbl_info.asv_table_ver].table[lv].voltage[asv]);
|
||||
}
|
||||
}
|
||||
|
||||
struct cal_asv_ops cal_asv_ops = {
|
||||
.print_asv_info = asv_print_info,
|
||||
.print_rcc_info = rcc_print_info,
|
||||
.set_grp = asv_set_grp,
|
||||
.set_tablever = asv_set_tablever,
|
||||
.set_rcc_table = asv_rcc_set_table,
|
||||
.asv_init = asv_init,
|
||||
};
|
||||
3617
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-cmu.c
Normal file
3617
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-cmu.c
Normal file
File diff suppressed because it is too large
Load diff
3290
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-cmu.h
Normal file
3290
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-cmu.h
Normal file
File diff suppressed because it is too large
Load diff
1947
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-cmusfr.h
Executable file
1947
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-cmusfr.h
Executable file
File diff suppressed because it is too large
Load diff
1075
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-dfs.c
Executable file
1075
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-dfs.c
Executable file
File diff suppressed because it is too large
Load diff
513
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-drampara.c
Executable file
513
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-drampara.c
Executable file
|
|
@ -0,0 +1,513 @@
|
|||
#include "../pwrcal-env.h"
|
||||
#include "../pwrcal-rae.h"
|
||||
#include "S5E8890-sfrbase.h"
|
||||
#include "S5E8890-vclk-internal.h"
|
||||
|
||||
#include <soc/samsung/ect_parser.h>
|
||||
|
||||
#ifndef MHZ
|
||||
#define MHZ ((unsigned long long)1000000)
|
||||
#endif
|
||||
|
||||
#define __SMC_ALL (DMC_MISC_CCORE_BASE + 0x8000)
|
||||
#define __PHY_ALL (DMC_MISC_CCORE_BASE + 0x4000)
|
||||
#define __DMC_MISC_ALL (DMC_MISC_CCORE_BASE + 0x0000)
|
||||
|
||||
#define ModeRegAddr ((void *)(__SMC_ALL + 0x0000))
|
||||
#define MprMrCtl ((void *)(__SMC_ALL + 0x0004))
|
||||
#define ModeRegWrData ((void *)(__SMC_ALL + 0x0008))
|
||||
|
||||
#define DramTiming0_0 ((void *)(__SMC_ALL + 0x0058))
|
||||
#define DramTiming1_0 ((void *)(__SMC_ALL + 0x005C))
|
||||
#define DramTiming2_0 ((void *)(__SMC_ALL + 0x0060))
|
||||
#define DramTiming3_0 ((void *)(__SMC_ALL + 0x0064))
|
||||
#define DramTiming4_0 ((void *)(__SMC_ALL + 0x0068))
|
||||
#define DramTiming5_0 ((void *)(__SMC_ALL + 0x006C))
|
||||
#define DramTiming6_0 ((void *)(__SMC_ALL + 0x0070))
|
||||
#define DramTiming7_0 ((void *)(__SMC_ALL + 0x0074))
|
||||
#define DramTiming8_0 ((void *)(__SMC_ALL + 0x0078))
|
||||
#define DramTiming9_0 ((void *)(__SMC_ALL + 0x007C))
|
||||
#define DramDerateTiming0_0 ((void *)(__SMC_ALL + 0x0088))
|
||||
#define DramDerateTiming1_0 ((void *)(__SMC_ALL + 0x008C))
|
||||
#define Dimm0AutoRefTiming1_0 ((void *)(__SMC_ALL + 0x009C))
|
||||
#define Dimm1AutoRefTiming1_0 ((void *)(__SMC_ALL + 0x00A4))
|
||||
#define AutoRefTiming2_0 ((void *)(__SMC_ALL + 0x00A8))
|
||||
#define PwrMgmtTiming0_0 ((void *)(__SMC_ALL + 0x00B8))
|
||||
#define PwrMgmtTiming1_0 ((void *)(__SMC_ALL + 0x00BC))
|
||||
#define PwrMgmtTiming2_0 ((void *)(__SMC_ALL + 0x00C0))
|
||||
#define PwrMgmtTiming3_0 ((void *)(__SMC_ALL + 0x00C4))
|
||||
#define TmrTrnInterval_0 ((void *)(__SMC_ALL + 0x00C8))
|
||||
#define DvfsTrnCtl_0 ((void *)(__SMC_ALL + 0x00CC))
|
||||
#define TrnTiming0_0 ((void *)(__SMC_ALL + 0x00D0))
|
||||
#define TrnTiming1_0 ((void *)(__SMC_ALL + 0x00D4))
|
||||
#define TrnTiming2_0 ((void *)(__SMC_ALL + 0x00D8))
|
||||
#define DFIDelay1_0 ((void *)(__SMC_ALL + 0x00E0))
|
||||
#define DFIDelay2_0 ((void *)(__SMC_ALL + 0x00E4))
|
||||
|
||||
#define DramTiming0_1 ((void *)(__SMC_ALL + 0x0108))
|
||||
#define DramTiming1_1 ((void *)(__SMC_ALL + 0x010C))
|
||||
#define DramTiming2_1 ((void *)(__SMC_ALL + 0x0110))
|
||||
#define DramTiming3_1 ((void *)(__SMC_ALL + 0x0114))
|
||||
#define DramTiming4_1 ((void *)(__SMC_ALL + 0x0118))
|
||||
#define DramTiming5_1 ((void *)(__SMC_ALL + 0x011C))
|
||||
#define DramTiming6_1 ((void *)(__SMC_ALL + 0x0120))
|
||||
#define DramTiming7_1 ((void *)(__SMC_ALL + 0x0124))
|
||||
#define DramTiming8_1 ((void *)(__SMC_ALL + 0x0128))
|
||||
#define DramTiming9_1 ((void *)(__SMC_ALL + 0x012C))
|
||||
#define DramDerateTiming0_1 ((void *)(__SMC_ALL + 0x0138))
|
||||
#define DramDerateTiming1_1 ((void *)(__SMC_ALL + 0x013C))
|
||||
#define Dimm0AutoRefTiming1_1 ((void *)(__SMC_ALL + 0x014C))
|
||||
#define Dimm1AutoRefTiming1_1 ((void *)(__SMC_ALL + 0x0154))
|
||||
#define AutoRefTiming2_1 ((void *)(__SMC_ALL + 0x0168))
|
||||
#define PwrMgmtTiming0_1 ((void *)(__SMC_ALL + 0x0168))
|
||||
#define PwrMgmtTiming1_1 ((void *)(__SMC_ALL + 0x016C))
|
||||
#define PwrMgmtTiming2_1 ((void *)(__SMC_ALL + 0x0170))
|
||||
#define PwrMgmtTiming3_1 ((void *)(__SMC_ALL + 0x0174))
|
||||
#define TmrTrnInterval_1 ((void *)(__SMC_ALL + 0x0178))
|
||||
#define DvfsTrnCtl_1 ((void *)(__SMC_ALL + 0x017C))
|
||||
#define TrnTiming0_1 ((void *)(__SMC_ALL + 0x0180))
|
||||
#define TrnTiming1_1 ((void *)(__SMC_ALL + 0x0184))
|
||||
#define TrnTiming2_1 ((void *)(__SMC_ALL + 0x0188))
|
||||
#define DFIDelay1_1 ((void *)(__SMC_ALL + 0x0190))
|
||||
#define DFIDelay2_1 ((void *)(__SMC_ALL + 0x0194))
|
||||
|
||||
#define PHY_DVFS_CON_CH0 ((void *)(LPDDR4_PHY0_BASE + 0x00B8))
|
||||
#define PHY_DVFS_CON ((void *)(__PHY_ALL + 0x00B8))
|
||||
#define PHY_DVFS0_CON0 ((void *)(__PHY_ALL + 0x00BC))
|
||||
#define PHY_DVFS0_CON1 ((void *)(__PHY_ALL + 0x00C4))
|
||||
#define PHY_DVFS0_CON2 ((void *)(__PHY_ALL + 0x00CC))
|
||||
#define PHY_DVFS0_CON3 ((void *)(__PHY_ALL + 0x00D4))
|
||||
#define PHY_DVFS0_CON4 ((void *)(__PHY_ALL + 0x00DC))
|
||||
|
||||
#define PHY_DVFS1_CON0 ((void *)(__PHY_ALL + 0x00C0))
|
||||
#define PHY_DVFS1_CON1 ((void *)(__PHY_ALL + 0x00C8))
|
||||
#define PHY_DVFS1_CON2 ((void *)(__PHY_ALL + 0x00D0))
|
||||
#define PHY_DVFS1_CON3 ((void *)(__PHY_ALL + 0x00D8))
|
||||
#define PHY_DVFS1_CON4 ((void *)(__PHY_ALL + 0x00E0))
|
||||
|
||||
#define DMC_MISC_CON0 ((void *)(__DMC_MISC_ALL + 0x0014))
|
||||
#define DMC_MISC_CON1 ((void *)(__DMC_MISC_ALL + 0x003C))
|
||||
#define MRS_DATA1 ((void *)(__DMC_MISC_ALL + 0x0054))
|
||||
|
||||
enum mif_timing_set_idx {
|
||||
MIF_TIMING_SET_0,
|
||||
MIF_TIMING_SET_1
|
||||
};
|
||||
|
||||
enum smc_dram_mode_register {
|
||||
DRAM_MR0,
|
||||
DRAM_MR1,
|
||||
DRAM_MR2,
|
||||
DRAM_MR3,
|
||||
DRAM_MR4,
|
||||
DRAM_MR5,
|
||||
DRAM_MR6,
|
||||
DRAM_MR7,
|
||||
DRAM_MR8,
|
||||
DRAM_MR9,
|
||||
DRAM_MR10,
|
||||
DRAM_MR11,
|
||||
DRAM_MR12,
|
||||
DRAM_MR13,
|
||||
DRAM_MR14,
|
||||
DRAM_MR15,
|
||||
DRAM_MR16,
|
||||
DRAM_MR17,
|
||||
DRAM_MR18,
|
||||
DRAM_MR19,
|
||||
DRAM_MR20,
|
||||
DRAM_MR21,
|
||||
DRAM_MR22,
|
||||
DRAM_MR23,
|
||||
DRAM_MR24,
|
||||
DRAM_MR25,
|
||||
DRAM_MR32 = 32,
|
||||
DRAM_MR40 = 40,
|
||||
};
|
||||
|
||||
enum timing_parameter_column {
|
||||
DramTiming0,
|
||||
DramTiming1,
|
||||
DramTiming2,
|
||||
DramTiming3,
|
||||
DramTiming4,
|
||||
DramTiming5,
|
||||
DramTiming6,
|
||||
DramTiming7,
|
||||
DramTiming8,
|
||||
DramTiming9,
|
||||
DramDerateTiming0,
|
||||
DramDerateTiming1,
|
||||
Dimm0AutoRefTiming1,
|
||||
Dimm1AutoRefTiming1,
|
||||
AutoRefTiming2,
|
||||
PwrMgmtTiming0,
|
||||
PwrMgmtTiming1,
|
||||
PwrMgmtTiming2,
|
||||
PwrMgmtTiming3,
|
||||
TmrTrnInterval,
|
||||
DFIDelay1,
|
||||
DFIDelay2,
|
||||
DvfsTrnCtl,
|
||||
TrnTiming0,
|
||||
TrnTiming1,
|
||||
TrnTiming2,
|
||||
DVFSn_CON0,
|
||||
DVFSn_CON1,
|
||||
DVFSn_CON2,
|
||||
DVFSn_CON3,
|
||||
DVFSn_CON4,
|
||||
DirectCmd_MR1,
|
||||
DirectCmd_MR2,
|
||||
DirectCmd_MR3,
|
||||
DirectCmd_MR11,
|
||||
DirectCmd_MR12,
|
||||
DirectCmd_MR14,
|
||||
DirectCmd_MR22,
|
||||
|
||||
num_of_g_smc_dfs_table_column = TrnTiming2 - DramTiming0 + 1,
|
||||
num_of_g_phy_dfs_table_column = DVFSn_CON4 - DVFSn_CON0 + 1,
|
||||
num_of_g_dram_dfs_table_column = DirectCmd_MR22 - DirectCmd_MR1 + 1,
|
||||
num_of_dram_parameter = num_of_g_smc_dfs_table_column + num_of_g_phy_dfs_table_column + num_of_g_dram_dfs_table_column,
|
||||
};
|
||||
|
||||
struct smc_dfs_table {
|
||||
unsigned int DramTiming0;
|
||||
unsigned int DramTiming1;
|
||||
unsigned int DramTiming2;
|
||||
unsigned int DramTiming3;
|
||||
unsigned int DramTiming4;
|
||||
unsigned int DramTiming5;
|
||||
unsigned int DramTiming6;
|
||||
unsigned int DramTiming7;
|
||||
unsigned int DramTiming8;
|
||||
unsigned int DramTiming9;
|
||||
unsigned int DramDerateTiming0;
|
||||
unsigned int DramDerateTiming1;
|
||||
unsigned int Dimm0AutoRefTiming1;
|
||||
unsigned int Dimm1AutoRefTiming1;
|
||||
unsigned int AutoRefTiming2;
|
||||
unsigned int PwrMgmtTiming0;
|
||||
unsigned int PwrMgmtTiming1;
|
||||
unsigned int PwrMgmtTiming2;
|
||||
unsigned int PwrMgmtTiming3;
|
||||
unsigned int TmrTrnInterval;
|
||||
unsigned int DFIDelay1;
|
||||
unsigned int DFIDelay2;
|
||||
unsigned int DvfsTrnCtl;
|
||||
unsigned int TrnTiming0;
|
||||
unsigned int TrnTiming1;
|
||||
unsigned int TrnTiming2;
|
||||
};
|
||||
|
||||
struct phy_dfs_table {
|
||||
unsigned int DVFSn_CON0;
|
||||
unsigned int DVFSn_CON1;
|
||||
unsigned int DVFSn_CON2;
|
||||
unsigned int DVFSn_CON3;
|
||||
unsigned int DVFSn_CON4;
|
||||
};
|
||||
|
||||
struct dram_dfs_table {
|
||||
unsigned int DirectCmd_MR1;
|
||||
unsigned int DirectCmd_MR2;
|
||||
unsigned int DirectCmd_MR3;
|
||||
unsigned int DirectCmd_MR11;
|
||||
unsigned int DirectCmd_MR12;
|
||||
unsigned int DirectCmd_MR14;
|
||||
unsigned int DirectCmd_MR22;
|
||||
};
|
||||
|
||||
static struct smc_dfs_table *g_smc_dfs_table;
|
||||
static struct phy_dfs_table *g_phy_dfs_table;
|
||||
static struct dram_dfs_table *g_dram_dfs_table;
|
||||
static unsigned long long *mif_freq_to_level;
|
||||
static int num_mif_freq_to_level;
|
||||
|
||||
static const struct smc_dfs_table g_smc_dfs_table_switch[] = {
|
||||
/* DramTiming0__n, DramTiming1__n, DramTiming2__n, DramTiming3__n, DramTiming4__n, DramTiming5__n, DramTiming6__n, DramTiming7__n, DramTiming8__n, DramTiming9__n, DramDerateTiming0__n, DramDerateTiming1__n, Dimm0AutoRefTiming1__n, Dimm1AutoRefTiming1__n, AutoRefTiming2__n, PwmMgmtTiming0_n, PwmMgmtTiming1__n, PwmMgmtTiming2__n, PwmMgmtTiming3__n, TmrTrnIntvl, DFIDelay1, DFIDelay2, DvfsTrnCtl, TrnTiming0, TrnTiming1, TrnTiming2 */
|
||||
/* BUS3_PLL SW 936 */ { 0x00050a09, 0x09041e14, 0x05000013, 0x00000100, 0x09050500, 0x00110805, 0x00070004, 0x00070004, 0x00001004, 0x0a132811, 0x20150b0a, 0x00000a06, 0x002b0055, 0x002b0055, 0x00000005, 0x04020604, 0x00000404, 0x0000005a, 0x00000492, 0x00000000, 0x00010510, 0x00001004, 0x00000303, 0x25180875, 0x16250f18, 0x00000014 },
|
||||
/* BUS0_PLL SW 468 */ { 0x00030505, 0x05040f0a, 0x0400000a, 0x00000100, 0x05040400, 0x000a0605, 0x00070004, 0x00070004, 0x00000c04, 0x0a101c0a, 0x100b0605, 0x00000504, 0x0016002b, 0x0016002b, 0x00000004, 0x03020403, 0x00000404, 0x0000002e, 0x00000249, 0x00000000, 0x00010309, 0x00000902, 0x00000000, 0x1e18043b, 0x101e0c18, 0x00000014 }
|
||||
};
|
||||
|
||||
static const struct phy_dfs_table g_phy_dfs_table_switch[] = {
|
||||
/* DVFSn_CON0, DVFSn_CON1, DVFSn_CON2, DVFSn_CON3, DVFSn_CON4 */
|
||||
/* BUS3_PLL SW 936 */ { 0x3a859800, 0x80100000, 0x4001a070, 0x7df3ffff, 0x00003f3f },
|
||||
/* BUS0_PLL SW 468 */ { 0x1d430800, 0x80100000, 0x00004051, 0x7df3ffff, 0x00003f3f }
|
||||
};
|
||||
|
||||
static const struct dram_dfs_table g_dram_dfs_table_switch[] = {
|
||||
/* MR1OP, MR2OP, MR3OP, MR11OP, MR12OP, MR14OP, MR22OP */
|
||||
/* BUS3_PLL SW 936 */ { 0x3e, 0x1b, 0xf1, 0x04, 0x5d, 0x17, 0x26 },
|
||||
/* BUS0_PLL SW 468 */ { 0x16, 0x09, 0xf1, 0x04, 0x5d, 0x17, 0x26 }
|
||||
};
|
||||
|
||||
static const unsigned long long mif_freq_to_level_switch[] = {
|
||||
/* BUS3_PLL SW 936 */ 936 * MHZ,
|
||||
/* BUS0_PLL SW 468 */ 468 * MHZ
|
||||
};
|
||||
|
||||
void dmc_misc_direct_dmc_enable(int enable)
|
||||
{
|
||||
pwrcal_writel(DMC_MISC_CON0, (enable<<24)|(0x2<<20));
|
||||
}
|
||||
|
||||
void smc_mode_register_write(int mr, int op)
|
||||
{
|
||||
pwrcal_writel(ModeRegAddr, ((0x3<<28)|(mr<<20)));
|
||||
pwrcal_writel(ModeRegWrData, op);
|
||||
pwrcal_writel(MprMrCtl, 0x10);
|
||||
}
|
||||
|
||||
static unsigned int convert_to_level(unsigned long long freq)
|
||||
{
|
||||
int idx;
|
||||
int tablesize = num_mif_freq_to_level;
|
||||
|
||||
for (idx = tablesize - 1; idx >= 0; idx--)
|
||||
if (freq <= mif_freq_to_level[idx])
|
||||
return (unsigned int)idx;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned int convert_to_level_switch(unsigned long long freq)
|
||||
{
|
||||
int idx;
|
||||
int tablesize = sizeof(mif_freq_to_level_switch) / sizeof(mif_freq_to_level_switch[0]);
|
||||
|
||||
for (idx = tablesize - 1; idx >= 0; idx--)
|
||||
if (freq <= mif_freq_to_level_switch[idx])
|
||||
return (unsigned int)idx;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void pwrcal_dmc_set_dvfs(unsigned long long target_mif_freq, unsigned int timing_set_idx)
|
||||
{
|
||||
unsigned int uReg;
|
||||
unsigned int target_mif_level_idx, target_mif_level_switch_idx;
|
||||
unsigned int mr13;
|
||||
|
||||
target_mif_level_idx = convert_to_level(target_mif_freq);
|
||||
|
||||
target_mif_level_switch_idx = convert_to_level_switch(target_mif_freq);
|
||||
|
||||
/* 1. Configure parameter */
|
||||
if (timing_set_idx == MIF_TIMING_SET_0) {
|
||||
pwrcal_writel(DMC_MISC_CON1, 0x0); //timing_set_sw_r=0x0
|
||||
|
||||
pwrcal_writel(DramTiming0_0, g_smc_dfs_table[target_mif_level_idx].DramTiming0);
|
||||
pwrcal_writel(DramTiming1_0, g_smc_dfs_table[target_mif_level_idx].DramTiming1);
|
||||
pwrcal_writel(DramTiming2_0, g_smc_dfs_table[target_mif_level_idx].DramTiming2);
|
||||
pwrcal_writel(DramTiming3_0, g_smc_dfs_table[target_mif_level_idx].DramTiming3);
|
||||
pwrcal_writel(DramTiming4_0, g_smc_dfs_table[target_mif_level_idx].DramTiming4);
|
||||
pwrcal_writel(DramTiming5_0, g_smc_dfs_table[target_mif_level_idx].DramTiming5);
|
||||
pwrcal_writel(DramTiming6_0, g_smc_dfs_table[target_mif_level_idx].DramTiming6);
|
||||
pwrcal_writel(DramTiming7_0, g_smc_dfs_table[target_mif_level_idx].DramTiming7);
|
||||
pwrcal_writel(DramTiming8_0, g_smc_dfs_table[target_mif_level_idx].DramTiming8);
|
||||
pwrcal_writel(DramTiming9_0, g_smc_dfs_table[target_mif_level_idx].DramTiming9);
|
||||
pwrcal_writel(DramDerateTiming0_0, g_smc_dfs_table[target_mif_level_idx].DramDerateTiming0);
|
||||
pwrcal_writel(DramDerateTiming1_0, g_smc_dfs_table[target_mif_level_idx].DramDerateTiming1);
|
||||
pwrcal_writel(Dimm0AutoRefTiming1_0, g_smc_dfs_table[target_mif_level_idx].Dimm0AutoRefTiming1);
|
||||
pwrcal_writel(Dimm1AutoRefTiming1_0, g_smc_dfs_table[target_mif_level_idx].Dimm1AutoRefTiming1);
|
||||
pwrcal_writel(AutoRefTiming2_0, g_smc_dfs_table[target_mif_level_idx].AutoRefTiming2);
|
||||
pwrcal_writel(PwrMgmtTiming0_0, g_smc_dfs_table[target_mif_level_idx].PwrMgmtTiming0);
|
||||
pwrcal_writel(PwrMgmtTiming1_0, g_smc_dfs_table[target_mif_level_idx].PwrMgmtTiming1);
|
||||
pwrcal_writel(PwrMgmtTiming2_0, g_smc_dfs_table[target_mif_level_idx].PwrMgmtTiming2);
|
||||
pwrcal_writel(PwrMgmtTiming3_0, g_smc_dfs_table[target_mif_level_idx].PwrMgmtTiming3);
|
||||
pwrcal_writel(TmrTrnInterval_0, g_smc_dfs_table[target_mif_level_idx].TmrTrnInterval);
|
||||
pwrcal_writel(DFIDelay1_0, g_smc_dfs_table[target_mif_level_idx].DFIDelay1);
|
||||
pwrcal_writel(DFIDelay2_0, g_smc_dfs_table[target_mif_level_idx].DFIDelay2);
|
||||
pwrcal_writel(DvfsTrnCtl_0, g_smc_dfs_table[target_mif_level_idx].DvfsTrnCtl);
|
||||
pwrcal_writel(TrnTiming0_0, g_smc_dfs_table[target_mif_level_idx].TrnTiming0);
|
||||
pwrcal_writel(TrnTiming1_0, g_smc_dfs_table[target_mif_level_idx].TrnTiming1);
|
||||
pwrcal_writel(TrnTiming2_0, g_smc_dfs_table[target_mif_level_idx].TrnTiming2);
|
||||
|
||||
uReg = pwrcal_readl((void *)PHY_DVFS_CON_CH0);
|
||||
uReg &= ~(0x3<<30);
|
||||
uReg |= (0x1<<30); //0x1 = DVFS 1 mode
|
||||
pwrcal_writel(PHY_DVFS_CON, uReg);
|
||||
|
||||
pwrcal_writel(PHY_DVFS0_CON0, g_phy_dfs_table[target_mif_level_idx].DVFSn_CON0);
|
||||
pwrcal_writel(PHY_DVFS0_CON1, g_phy_dfs_table[target_mif_level_idx].DVFSn_CON1);
|
||||
pwrcal_writel(PHY_DVFS0_CON2, g_phy_dfs_table[target_mif_level_idx].DVFSn_CON2);
|
||||
pwrcal_writel(PHY_DVFS0_CON3, g_phy_dfs_table[target_mif_level_idx].DVFSn_CON3);
|
||||
pwrcal_writel(PHY_DVFS0_CON4, g_phy_dfs_table[target_mif_level_idx].DVFSn_CON4);
|
||||
|
||||
mr13 = (0x1<<7)|(0x0<<6)|(0x0<<5)|(0x1<<3); //FSP-OP=0x1, FSP-WR=0x0, DMD=0x0, VRCG=0x1
|
||||
smc_mode_register_write(DRAM_MR13, mr13);
|
||||
smc_mode_register_write(DRAM_MR1, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR1);
|
||||
smc_mode_register_write(DRAM_MR2, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR2);
|
||||
smc_mode_register_write(DRAM_MR3, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR3);
|
||||
smc_mode_register_write(DRAM_MR11, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR11);
|
||||
smc_mode_register_write(DRAM_MR12, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR12);
|
||||
smc_mode_register_write(DRAM_MR14, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR14);
|
||||
smc_mode_register_write(DRAM_MR22, g_dram_dfs_table[target_mif_level_idx].DirectCmd_MR22);
|
||||
|
||||
mr13 &= ~(0x1<<7); // clear FSP-OP[7]
|
||||
pwrcal_writel(MRS_DATA1, mr13);
|
||||
} else if (timing_set_idx == MIF_TIMING_SET_1) {
|
||||
pwrcal_writel(DMC_MISC_CON1, 0x1); //timing_set_sw_r=0x1
|
||||
|
||||
pwrcal_writel(DramTiming0_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DramTiming0);
|
||||
pwrcal_writel(DramTiming1_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DramTiming1);
|
||||
pwrcal_writel(DramTiming2_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DramTiming2);
|
||||
pwrcal_writel(DramTiming3_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DramTiming3);
|
||||
pwrcal_writel(DramTiming4_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DramTiming4);
|
||||
pwrcal_writel(DramTiming5_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DramTiming5);
|
||||
pwrcal_writel(DramTiming6_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DramTiming6);
|
||||
pwrcal_writel(DramTiming7_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DramTiming7);
|
||||
pwrcal_writel(DramTiming8_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DramTiming8);
|
||||
pwrcal_writel(DramTiming9_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DramTiming9);
|
||||
pwrcal_writel(DramDerateTiming0_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DramDerateTiming0);
|
||||
pwrcal_writel(DramDerateTiming1_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DramDerateTiming1);
|
||||
pwrcal_writel(Dimm0AutoRefTiming1_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].Dimm0AutoRefTiming1);
|
||||
pwrcal_writel(Dimm1AutoRefTiming1_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].Dimm1AutoRefTiming1);
|
||||
pwrcal_writel(AutoRefTiming2_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].AutoRefTiming2);
|
||||
pwrcal_writel(PwrMgmtTiming0_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].PwrMgmtTiming0);
|
||||
pwrcal_writel(PwrMgmtTiming1_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].PwrMgmtTiming1);
|
||||
pwrcal_writel(PwrMgmtTiming2_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].PwrMgmtTiming2);
|
||||
pwrcal_writel(PwrMgmtTiming3_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].PwrMgmtTiming3);
|
||||
pwrcal_writel(TmrTrnInterval_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].TmrTrnInterval);
|
||||
pwrcal_writel(DFIDelay1_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DFIDelay1);
|
||||
pwrcal_writel(DFIDelay2_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DFIDelay2);
|
||||
pwrcal_writel(DvfsTrnCtl_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].DvfsTrnCtl);
|
||||
pwrcal_writel(TrnTiming0_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].TrnTiming0);
|
||||
pwrcal_writel(TrnTiming1_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].TrnTiming1);
|
||||
pwrcal_writel(TrnTiming2_1, g_smc_dfs_table_switch[target_mif_level_switch_idx].TrnTiming2);
|
||||
|
||||
uReg = pwrcal_readl(PHY_DVFS_CON_CH0);
|
||||
uReg &= ~(0x3<<30);
|
||||
uReg |= (0x2<<30); //0x2 = DVFS 2 mode
|
||||
pwrcal_writel(PHY_DVFS_CON, uReg);
|
||||
|
||||
pwrcal_writel(PHY_DVFS1_CON0, g_phy_dfs_table_switch[target_mif_level_switch_idx].DVFSn_CON0);
|
||||
pwrcal_writel(PHY_DVFS1_CON1, g_phy_dfs_table_switch[target_mif_level_switch_idx].DVFSn_CON1);
|
||||
pwrcal_writel(PHY_DVFS1_CON2, g_phy_dfs_table_switch[target_mif_level_switch_idx].DVFSn_CON2);
|
||||
pwrcal_writel(PHY_DVFS1_CON3, g_phy_dfs_table_switch[target_mif_level_switch_idx].DVFSn_CON3);
|
||||
pwrcal_writel(PHY_DVFS1_CON4, g_phy_dfs_table_switch[target_mif_level_switch_idx].DVFSn_CON4);
|
||||
|
||||
mr13 = (0x0<<7)|(0x1<<6)|(0x0<<5)|(0x1<<3); //FSP-OP=0x0, FSP-WR=0x1, DMD=0x0, VRCG=0x1
|
||||
smc_mode_register_write(DRAM_MR13, mr13);
|
||||
smc_mode_register_write(DRAM_MR1, g_dram_dfs_table_switch[target_mif_level_switch_idx].DirectCmd_MR1);
|
||||
smc_mode_register_write(DRAM_MR2, g_dram_dfs_table_switch[target_mif_level_switch_idx].DirectCmd_MR2);
|
||||
smc_mode_register_write(DRAM_MR3, g_dram_dfs_table_switch[target_mif_level_switch_idx].DirectCmd_MR3);
|
||||
smc_mode_register_write(DRAM_MR11, g_dram_dfs_table_switch[target_mif_level_switch_idx].DirectCmd_MR11);
|
||||
smc_mode_register_write(DRAM_MR12, g_dram_dfs_table_switch[target_mif_level_switch_idx].DirectCmd_MR12);
|
||||
smc_mode_register_write(DRAM_MR14, g_dram_dfs_table_switch[target_mif_level_switch_idx].DirectCmd_MR14);
|
||||
smc_mode_register_write(DRAM_MR22, g_dram_dfs_table_switch[target_mif_level_switch_idx].DirectCmd_MR22);
|
||||
|
||||
mr13 &= ~(0x1<<7); // clear FSP-OP[7]
|
||||
mr13 |= (0x1<<7); // set FSP-OP[7]=0x1
|
||||
pwrcal_writel(MRS_DATA1, mr13);
|
||||
} else {
|
||||
pr_err("wrong DMC timing set selection on DVFS\n");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void dfs_dram_param_init(void)
|
||||
{
|
||||
int i;
|
||||
void *dram_block;
|
||||
int memory_size = 3; // means 3GB
|
||||
struct ect_timing_param_size *size;
|
||||
|
||||
dram_block = ect_get_block(BLOCK_TIMING_PARAM);
|
||||
if (dram_block == NULL)
|
||||
return;
|
||||
|
||||
size = ect_timing_param_get_size(dram_block, memory_size);
|
||||
if (size == NULL)
|
||||
return;
|
||||
|
||||
if (num_of_g_smc_dfs_table_column + num_of_g_phy_dfs_table_column + num_of_g_dram_dfs_table_column != size->num_of_timing_param)
|
||||
return;
|
||||
|
||||
g_smc_dfs_table = kzalloc(sizeof(struct smc_dfs_table) * num_of_g_smc_dfs_table_column * size->num_of_level, GFP_KERNEL);
|
||||
if (g_smc_dfs_table == NULL)
|
||||
return;
|
||||
|
||||
g_phy_dfs_table = kzalloc(sizeof(struct phy_dfs_table) * num_of_g_phy_dfs_table_column * size->num_of_level, GFP_KERNEL);
|
||||
if (g_phy_dfs_table == NULL)
|
||||
return;
|
||||
|
||||
g_dram_dfs_table = kzalloc(sizeof(struct dram_dfs_table) * num_of_g_dram_dfs_table_column * size->num_of_level, GFP_KERNEL);
|
||||
if (g_dram_dfs_table == NULL)
|
||||
return;
|
||||
|
||||
for (i = 0; i < size->num_of_level; ++i) {
|
||||
g_smc_dfs_table[i].DramTiming0 = size->timing_parameter[i * num_of_dram_parameter + DramTiming0];
|
||||
g_smc_dfs_table[i].DramTiming1 = size->timing_parameter[i * num_of_dram_parameter + DramTiming1];
|
||||
g_smc_dfs_table[i].DramTiming2 = size->timing_parameter[i * num_of_dram_parameter + DramTiming2];
|
||||
g_smc_dfs_table[i].DramTiming3 = size->timing_parameter[i * num_of_dram_parameter + DramTiming3];
|
||||
g_smc_dfs_table[i].DramTiming4 = size->timing_parameter[i * num_of_dram_parameter + DramTiming4];
|
||||
g_smc_dfs_table[i].DramTiming5 = size->timing_parameter[i * num_of_dram_parameter + DramTiming5];
|
||||
g_smc_dfs_table[i].DramTiming6 = size->timing_parameter[i * num_of_dram_parameter + DramTiming6];
|
||||
g_smc_dfs_table[i].DramTiming7 = size->timing_parameter[i * num_of_dram_parameter + DramTiming7];
|
||||
g_smc_dfs_table[i].DramTiming8 = size->timing_parameter[i * num_of_dram_parameter + DramTiming8];
|
||||
g_smc_dfs_table[i].DramTiming9 = size->timing_parameter[i * num_of_dram_parameter + DramTiming9];
|
||||
g_smc_dfs_table[i].DramDerateTiming0 = size->timing_parameter[i * num_of_dram_parameter + DramDerateTiming0];
|
||||
g_smc_dfs_table[i].DramDerateTiming1 = size->timing_parameter[i * num_of_dram_parameter + DramDerateTiming1];
|
||||
g_smc_dfs_table[i].Dimm0AutoRefTiming1 = size->timing_parameter[i * num_of_dram_parameter + Dimm0AutoRefTiming1];
|
||||
g_smc_dfs_table[i].Dimm1AutoRefTiming1 = size->timing_parameter[i * num_of_dram_parameter + Dimm1AutoRefTiming1];
|
||||
g_smc_dfs_table[i].AutoRefTiming2 = size->timing_parameter[i * num_of_dram_parameter + AutoRefTiming2];
|
||||
g_smc_dfs_table[i].PwrMgmtTiming0 = size->timing_parameter[i * num_of_dram_parameter + PwrMgmtTiming0];
|
||||
g_smc_dfs_table[i].PwrMgmtTiming1 = size->timing_parameter[i * num_of_dram_parameter + PwrMgmtTiming1];
|
||||
g_smc_dfs_table[i].PwrMgmtTiming2 = size->timing_parameter[i * num_of_dram_parameter + PwrMgmtTiming2];
|
||||
g_smc_dfs_table[i].PwrMgmtTiming3 = size->timing_parameter[i * num_of_dram_parameter + PwrMgmtTiming3];
|
||||
g_smc_dfs_table[i].TmrTrnInterval = size->timing_parameter[i * num_of_dram_parameter + TmrTrnInterval];
|
||||
g_smc_dfs_table[i].DFIDelay1 = size->timing_parameter[i * num_of_dram_parameter + DFIDelay1];
|
||||
g_smc_dfs_table[i].DFIDelay2 = size->timing_parameter[i * num_of_dram_parameter + DFIDelay2];
|
||||
g_smc_dfs_table[i].DvfsTrnCtl = size->timing_parameter[i * num_of_dram_parameter + DvfsTrnCtl];
|
||||
g_smc_dfs_table[i].TrnTiming0 = size->timing_parameter[i * num_of_dram_parameter + TrnTiming0];
|
||||
g_smc_dfs_table[i].TrnTiming1 = size->timing_parameter[i * num_of_dram_parameter + TrnTiming1];
|
||||
g_smc_dfs_table[i].TrnTiming2 = size->timing_parameter[i * num_of_dram_parameter + TrnTiming2];
|
||||
|
||||
g_phy_dfs_table[i].DVFSn_CON0 = size->timing_parameter[i * num_of_dram_parameter + DVFSn_CON0];
|
||||
g_phy_dfs_table[i].DVFSn_CON1 = size->timing_parameter[i * num_of_dram_parameter + DVFSn_CON1];
|
||||
g_phy_dfs_table[i].DVFSn_CON2 = size->timing_parameter[i * num_of_dram_parameter + DVFSn_CON2];
|
||||
g_phy_dfs_table[i].DVFSn_CON3 = size->timing_parameter[i * num_of_dram_parameter + DVFSn_CON3];
|
||||
g_phy_dfs_table[i].DVFSn_CON4 = size->timing_parameter[i * num_of_dram_parameter + DVFSn_CON4];
|
||||
|
||||
g_dram_dfs_table[i].DirectCmd_MR1 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR1];
|
||||
g_dram_dfs_table[i].DirectCmd_MR2 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR2];
|
||||
g_dram_dfs_table[i].DirectCmd_MR3 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR3];
|
||||
g_dram_dfs_table[i].DirectCmd_MR11 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR11];
|
||||
g_dram_dfs_table[i].DirectCmd_MR12 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR12];
|
||||
g_dram_dfs_table[i].DirectCmd_MR14 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR14];
|
||||
g_dram_dfs_table[i].DirectCmd_MR22 = size->timing_parameter[i * num_of_dram_parameter + DirectCmd_MR22];
|
||||
}
|
||||
}
|
||||
|
||||
void dfs_mif_level_init(void)
|
||||
{
|
||||
int i;
|
||||
void *dvfs_block;
|
||||
struct ect_dvfs_domain *domain;
|
||||
|
||||
dvfs_block = ect_get_block(BLOCK_DVFS);
|
||||
if (dvfs_block == NULL)
|
||||
return;
|
||||
|
||||
domain = ect_dvfs_get_domain(dvfs_block, vclk_dvfs_mif.vclk.name);
|
||||
if (domain == NULL)
|
||||
return;
|
||||
|
||||
mif_freq_to_level = kzalloc(sizeof(unsigned long long) * domain->num_of_level, GFP_KERNEL);
|
||||
if (mif_freq_to_level == NULL)
|
||||
return;
|
||||
|
||||
num_mif_freq_to_level = domain->num_of_level;
|
||||
|
||||
for (i = 0; i < domain->num_of_level; ++i)
|
||||
mif_freq_to_level[i] = domain->list_level[i].level * KHZ;
|
||||
}
|
||||
|
||||
void dfs_dram_init(void)
|
||||
{
|
||||
dfs_dram_param_init();
|
||||
dfs_mif_level_init();
|
||||
}
|
||||
798
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-pll.c
Normal file
798
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-pll.c
Normal file
|
|
@ -0,0 +1,798 @@
|
|||
#include "../pwrcal.h"
|
||||
#include "../pwrcal-clk.h"
|
||||
#include "../pwrcal-env.h"
|
||||
#include "../pwrcal-rae.h"
|
||||
#include "../pwrcal-pmu.h"
|
||||
#include "S5E8890-cmusfr.h"
|
||||
#include "S5E8890-pmusfr.h"
|
||||
#include "S5E8890-cmu.h"
|
||||
|
||||
|
||||
/*
|
||||
PLLs
|
||||
*/
|
||||
/* PLL141XX Clock Type */
|
||||
#define PLL141XX_MDIV_SHIFT 16
|
||||
#define PLL141XX_PDIV_SHIFT 8
|
||||
#define PLL141XX_SDIV_SHIFT 0
|
||||
#define PLL141XX_MDIV_MASK 0x3FF
|
||||
#define PLL141XX_PDIV_MASK 0x3F
|
||||
#define PLL141XX_SDIV_MASK 0x7
|
||||
#define PLL141XX_ENABLE 31
|
||||
#define PLL141XX_LOCKED 29
|
||||
#define PLL141XX_BYPASS 22
|
||||
|
||||
/* PLL1431X Clock Type */
|
||||
#define PLL1431X_MDIV_SHIFT 16
|
||||
#define PLL1431X_PDIV_SHIFT 8
|
||||
#define PLL1431X_SDIV_SHIFT 0
|
||||
#define PLL1431X_K_SHIFT 0
|
||||
#define PLL1431X_MDIV_MASK 0x3FF
|
||||
#define PLL1431X_PDIV_MASK 0x3F
|
||||
#define PLL1431X_SDIV_MASK 0x7
|
||||
#define PLL1431X_K_MASK 0xFFFF
|
||||
#define PLL1431X_ENABLE 31
|
||||
#define PLL1431X_LOCKED 29
|
||||
#define PLL1431X_BYPASS 4
|
||||
|
||||
#define FIN_HZ_26M (26*MHZ)
|
||||
|
||||
static const struct pwrcal_pll_rate_table *_clk_get_pll_settings(
|
||||
struct pwrcal_pll *pll_clk,
|
||||
unsigned long long rate)
|
||||
{
|
||||
int i;
|
||||
const struct pwrcal_pll_rate_table *prate_table = pll_clk->rate_table;
|
||||
|
||||
for (i = 0; i < pll_clk->rate_count; i++) {
|
||||
if (rate == prate_table[i].rate)
|
||||
return &prate_table[i];
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static int _clk_pll141xx_find_pms(struct pll_spec *pll_spec,
|
||||
struct pwrcal_pll_rate_table *rate_table,
|
||||
unsigned long long rate)
|
||||
{
|
||||
unsigned int p, m, s;
|
||||
unsigned long long fref, fvco, fout;
|
||||
unsigned long long tmprate, tmpfout;
|
||||
unsigned long long mindiffrate = 0xFFFFFFFFFFFFFFFF;
|
||||
unsigned int min_p, min_m, min_s, min_fout;
|
||||
|
||||
for (p = pll_spec->pdiv_min; p <= pll_spec->pdiv_max; p++) {
|
||||
fref = FIN_HZ_26M / p;
|
||||
if ((fref < pll_spec->fref_min) || (fref > pll_spec->fref_max))
|
||||
continue;
|
||||
|
||||
for (s = pll_spec->sdiv_min; s <= pll_spec->sdiv_max; s++) {
|
||||
tmprate = rate;
|
||||
do_div(tmprate, MHZ);
|
||||
tmprate = tmprate * p * (1 << s);
|
||||
do_div(tmprate, (FIN_HZ_26M / MHZ));
|
||||
m = (unsigned int)tmprate;
|
||||
|
||||
if ((m < pll_spec->mdiv_min)
|
||||
|| (m > pll_spec->mdiv_max))
|
||||
continue;
|
||||
|
||||
fvco = ((unsigned long long)FIN_HZ_26M) * m;
|
||||
do_div(fvco, p);
|
||||
if ((fvco < pll_spec->fvco_min)
|
||||
|| (fvco > pll_spec->fvco_max))
|
||||
continue;
|
||||
|
||||
fout = fvco >> s;
|
||||
if ((fout >= pll_spec->fout_min)
|
||||
&& (fout <= pll_spec->fout_max)) {
|
||||
tmprate = rate;
|
||||
do_div(tmprate, KHZ);
|
||||
tmpfout = fout;
|
||||
do_div(tmpfout, KHZ);
|
||||
if (tmprate == tmpfout) {
|
||||
rate_table->rate = fout;
|
||||
rate_table->pdiv = p;
|
||||
rate_table->mdiv = m;
|
||||
rate_table->sdiv = s;
|
||||
rate_table->kdiv = 0;
|
||||
return 0;
|
||||
}
|
||||
if (tmpfout < tmprate && mindiffrate > tmprate - tmpfout) {
|
||||
mindiffrate = tmprate - tmpfout;
|
||||
min_fout = fout;
|
||||
min_p = p;
|
||||
min_m = m;
|
||||
min_s = s;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (mindiffrate != 0xFFFFFFFFFFFFFFFF) {
|
||||
rate_table->rate = min_fout;
|
||||
rate_table->pdiv = min_p;
|
||||
rate_table->mdiv = min_m;
|
||||
rate_table->sdiv = min_s;
|
||||
rate_table->kdiv = 0;
|
||||
return 0;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
static int _clk_pll1419x_find_pms(struct pll_spec *pll_spec,
|
||||
struct pwrcal_pll_rate_table *rate_table,
|
||||
unsigned long long rate)
|
||||
{
|
||||
unsigned int p, m, s;
|
||||
unsigned long long fref, fvco, fout;
|
||||
unsigned long long tmprate, tmpfout;
|
||||
unsigned long long mindiffrate = 0xFFFFFFFFFFFFFFFF;
|
||||
unsigned int min_p, min_m, min_s, min_fout;
|
||||
|
||||
for (p = pll_spec->pdiv_min; p <= pll_spec->pdiv_max; p++) {
|
||||
fref = FIN_HZ_26M / p;
|
||||
if ((fref < pll_spec->fref_min) || (fref > pll_spec->fref_max))
|
||||
continue;
|
||||
|
||||
for (s = pll_spec->sdiv_min; s <= pll_spec->sdiv_max; s++) {
|
||||
/*tmprate = rate;*/
|
||||
tmprate = rate/2; /*for PLL1419*/
|
||||
do_div(tmprate, MHZ);
|
||||
tmprate = tmprate * p * (1 << s);
|
||||
do_div(tmprate, (FIN_HZ_26M / MHZ));
|
||||
m = (unsigned int)tmprate;
|
||||
|
||||
if ((m < pll_spec->mdiv_min)
|
||||
|| (m > pll_spec->mdiv_max))
|
||||
continue;
|
||||
|
||||
fvco = ((unsigned long long)FIN_HZ_26M) * m;
|
||||
do_div(fvco, p);
|
||||
if ((fvco < pll_spec->fvco_min)
|
||||
|| (fvco > pll_spec->fvco_max))
|
||||
continue;
|
||||
|
||||
fout = fvco >> s;
|
||||
if ((fout >= pll_spec->fout_min)
|
||||
&& (fout <= pll_spec->fout_max)) {
|
||||
tmprate = rate;
|
||||
do_div(tmprate, KHZ);
|
||||
tmpfout = fout;
|
||||
do_div(tmpfout, KHZ);
|
||||
if (tmprate == tmpfout) {
|
||||
rate_table->rate = fout;
|
||||
rate_table->pdiv = p;
|
||||
rate_table->mdiv = m;
|
||||
rate_table->sdiv = s;
|
||||
rate_table->kdiv = 0;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
if (tmpfout < tmprate && mindiffrate > tmprate - tmpfout) {
|
||||
mindiffrate = tmprate - tmpfout;
|
||||
min_fout = fout;
|
||||
min_p = p;
|
||||
min_m = m;
|
||||
min_s = s;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (mindiffrate != 0xFFFFFFFFFFFFFFFF) {
|
||||
rate_table->rate = min_fout;
|
||||
rate_table->pdiv = min_p;
|
||||
rate_table->mdiv = min_m;
|
||||
rate_table->sdiv = min_s;
|
||||
rate_table->kdiv = 0;
|
||||
return 0;
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int _clk_pll141xx_is_enabled(struct pwrcal_clk *clk)
|
||||
{
|
||||
return (int)(pwrcal_getbit(clk->offset, PLL141XX_ENABLE));
|
||||
}
|
||||
|
||||
static int _clk_pll141xx_enable(struct pwrcal_clk *clk)
|
||||
{
|
||||
int timeout;
|
||||
|
||||
if (pwrcal_getbit(clk->offset, PLL141XX_ENABLE))
|
||||
return 0;
|
||||
|
||||
pwrcal_setbit(clk->offset, PLL141XX_ENABLE, 1);
|
||||
|
||||
for (timeout = 0;; timeout++) {
|
||||
if (pwrcal_getbit(clk->offset, PLL141XX_LOCKED))
|
||||
break;
|
||||
if (timeout > CLK_WAIT_CNT)
|
||||
return -1;
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _clk_pll1419x_enable(struct pwrcal_clk *clk)
|
||||
{
|
||||
int timeout;
|
||||
|
||||
if (pwrcal_getbit(clk->offset, PLL141XX_ENABLE))
|
||||
return 0;
|
||||
|
||||
pwrcal_setbit(clk->offset, PLL141XX_ENABLE, 1);
|
||||
|
||||
for (timeout = 0;; timeout++) {
|
||||
if (pwrcal_getbit(MIF0_PLL_CON0, PLL141XX_LOCKED))
|
||||
break;
|
||||
if (timeout > CLK_WAIT_CNT)
|
||||
return -1;
|
||||
cpu_relax();
|
||||
}
|
||||
for (timeout = 0;; timeout++) {
|
||||
if (pwrcal_getbit(MIF1_PLL_CON0, PLL141XX_LOCKED))
|
||||
break;
|
||||
if (timeout > CLK_WAIT_CNT)
|
||||
return -1;
|
||||
cpu_relax();
|
||||
}
|
||||
for (timeout = 0;; timeout++) {
|
||||
if (pwrcal_getbit(MIF2_PLL_CON0, PLL141XX_LOCKED))
|
||||
break;
|
||||
if (timeout > CLK_WAIT_CNT)
|
||||
return -1;
|
||||
cpu_relax();
|
||||
}
|
||||
for (timeout = 0;; timeout++) {
|
||||
if (pwrcal_getbit(MIF3_PLL_CON0, PLL141XX_LOCKED))
|
||||
break;
|
||||
if (timeout > CLK_WAIT_CNT)
|
||||
return -1;
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
static int _clk_pll141xx_disable(struct pwrcal_clk *clk)
|
||||
{
|
||||
pwrcal_setbit(clk->offset, PLL141XX_ENABLE, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int _clk_pll141xx_is_disabled_bypass(struct pwrcal_clk *clk)
|
||||
{
|
||||
if (pwrcal_getbit(clk->offset + 1, PLL141XX_BYPASS))
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
int _clk_pll141xx_set_bypass(struct pwrcal_clk *clk, int bypass_disable)
|
||||
{
|
||||
if (bypass_disable == 0)
|
||||
pwrcal_setbit(clk + 1, PLL141XX_BYPASS, 1);
|
||||
else
|
||||
pwrcal_setbit(clk + 1, PLL141XX_BYPASS, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _clk_pll141xx_set_pms(struct pwrcal_clk *clk,
|
||||
const struct pwrcal_pll_rate_table *rate_table)
|
||||
{
|
||||
unsigned int mdiv, pdiv, sdiv, pll_con0;
|
||||
|
||||
int timeout;
|
||||
|
||||
pdiv = rate_table->pdiv;
|
||||
mdiv = rate_table->mdiv;
|
||||
sdiv = rate_table->sdiv;
|
||||
|
||||
pll_con0 = pwrcal_readl(clk->offset);
|
||||
pll_con0 &= ~((PLL141XX_MDIV_MASK << PLL141XX_MDIV_SHIFT)
|
||||
| (PLL141XX_PDIV_MASK << PLL141XX_PDIV_SHIFT)
|
||||
| (PLL141XX_SDIV_MASK << PLL141XX_SDIV_SHIFT));
|
||||
pll_con0 |= (mdiv << PLL141XX_MDIV_SHIFT)
|
||||
| (pdiv << PLL141XX_PDIV_SHIFT)
|
||||
| (sdiv << PLL141XX_SDIV_SHIFT);
|
||||
pll_con0 &= ~(1<<26);
|
||||
pll_con0 |= (1<<5);
|
||||
|
||||
pwrcal_writel(clk->status, pdiv*150);
|
||||
pwrcal_writel(clk->offset, pll_con0);
|
||||
|
||||
if (pll_con0 & (1 << PLL141XX_ENABLE)) {
|
||||
for (timeout = 0;; timeout++) {
|
||||
if (pwrcal_getbit(clk->offset, PLL141XX_LOCKED))
|
||||
break;
|
||||
if (timeout > CLK_WAIT_CNT)
|
||||
return -1;
|
||||
cpu_relax();
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
static int _clk_pll1419x_set_pms(struct pwrcal_clk *clk,
|
||||
const struct pwrcal_pll_rate_table *rate_table)
|
||||
{
|
||||
unsigned int mdiv, pdiv, sdiv, pll_con0;
|
||||
|
||||
int timeout;
|
||||
|
||||
pdiv = rate_table->pdiv;
|
||||
mdiv = rate_table->mdiv;
|
||||
sdiv = rate_table->sdiv;
|
||||
|
||||
pll_con0 = pwrcal_readl(clk->offset);
|
||||
pll_con0 &= ~((PLL141XX_MDIV_MASK << PLL141XX_MDIV_SHIFT)
|
||||
| (PLL141XX_PDIV_MASK << PLL141XX_PDIV_SHIFT)
|
||||
| (PLL141XX_SDIV_MASK << PLL141XX_SDIV_SHIFT));
|
||||
pll_con0 |= (mdiv << PLL141XX_MDIV_SHIFT)
|
||||
| (pdiv << PLL141XX_PDIV_SHIFT)
|
||||
| (sdiv << PLL141XX_SDIV_SHIFT);
|
||||
|
||||
pwrcal_writel(MIF0_PLL_LOCK, pdiv*150);
|
||||
pwrcal_writel(MIF1_PLL_LOCK, pdiv*150);
|
||||
pwrcal_writel(MIF2_PLL_LOCK, pdiv*150);
|
||||
pwrcal_writel(MIF3_PLL_LOCK, pdiv*150);
|
||||
pwrcal_writel(clk->offset, pll_con0);
|
||||
|
||||
if (pll_con0 & (1 << PLL141XX_ENABLE)) {
|
||||
for (timeout = 0;; timeout++) {
|
||||
if (pwrcal_getbit(MIF0_PLL_CON0, PLL141XX_LOCKED))
|
||||
break;
|
||||
if (timeout > CLK_WAIT_CNT)
|
||||
return -1;
|
||||
cpu_relax();
|
||||
}
|
||||
for (timeout = 0;; timeout++) {
|
||||
if (pwrcal_getbit(MIF1_PLL_CON0, PLL141XX_LOCKED))
|
||||
break;
|
||||
if (timeout > CLK_WAIT_CNT)
|
||||
return -1;
|
||||
cpu_relax();
|
||||
}
|
||||
for (timeout = 0;; timeout++) {
|
||||
if (pwrcal_getbit(MIF2_PLL_CON0, PLL141XX_LOCKED))
|
||||
break;
|
||||
if (timeout > CLK_WAIT_CNT)
|
||||
return -1;
|
||||
cpu_relax();
|
||||
}
|
||||
for (timeout = 0;; timeout++) {
|
||||
if (pwrcal_getbit(MIF3_PLL_CON0, PLL141XX_LOCKED))
|
||||
break;
|
||||
if (timeout > CLK_WAIT_CNT)
|
||||
return -1;
|
||||
cpu_relax();
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
|
||||
static int _clk_pll141xx_set_rate(struct pwrcal_clk *clk,
|
||||
unsigned long long rate)
|
||||
{
|
||||
struct pwrcal_pll *pll = to_pll(clk);
|
||||
struct pll_spec *pll_spec;
|
||||
struct pwrcal_pll_rate_table tmp_rate_table;
|
||||
const struct pwrcal_pll_rate_table *rate_table;
|
||||
|
||||
if (rate == 0) {
|
||||
if (_clk_pll141xx_is_enabled(clk) != 0)
|
||||
if (_clk_pll141xx_disable(clk))
|
||||
goto errorout;
|
||||
return 0;
|
||||
}
|
||||
|
||||
rate_table = _clk_get_pll_settings(pll, rate);
|
||||
if (rate_table == NULL) {
|
||||
pll_spec = clk_pll_get_spec(clk);
|
||||
if (pll_spec == NULL)
|
||||
goto errorout;
|
||||
|
||||
if (_clk_pll141xx_find_pms(pll_spec, &tmp_rate_table, rate)) {
|
||||
pr_err("can't find pms value for rate(%lldHz) of \'%s\'",
|
||||
rate,
|
||||
clk->name);
|
||||
goto errorout;
|
||||
}
|
||||
|
||||
rate_table = &tmp_rate_table;
|
||||
|
||||
pr_warn("not exist in rate table, p(%d), m(%d), s(%d), fout(%lldHz) %s",
|
||||
rate_table->pdiv,
|
||||
rate_table->mdiv,
|
||||
rate_table->sdiv,
|
||||
rate,
|
||||
clk->name);
|
||||
}
|
||||
|
||||
if (_clk_pll141xx_set_pms(clk, rate_table))
|
||||
goto errorout;
|
||||
|
||||
if (rate != 0) {
|
||||
if (_clk_pll141xx_is_enabled(clk) == 0)
|
||||
_clk_pll141xx_enable(clk);
|
||||
}
|
||||
return 0;
|
||||
|
||||
errorout:
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int _clk_pll1419x_set_rate(struct pwrcal_clk *clk,
|
||||
unsigned long long rate)
|
||||
{
|
||||
struct pwrcal_pll *pll = to_pll(clk);
|
||||
struct pll_spec *pll_spec;
|
||||
struct pwrcal_pll_rate_table tmp_rate_table;
|
||||
const struct pwrcal_pll_rate_table *rate_table;
|
||||
|
||||
if (rate == 0) {
|
||||
if (_clk_pll141xx_is_enabled(clk) != 0)
|
||||
if (_clk_pll141xx_disable(clk))
|
||||
goto errorout;
|
||||
return 0;
|
||||
}
|
||||
|
||||
rate_table = _clk_get_pll_settings(pll, rate);
|
||||
if (rate_table == NULL) {
|
||||
pll_spec = clk_pll_get_spec(clk);
|
||||
if (pll_spec == NULL)
|
||||
goto errorout;
|
||||
|
||||
if (_clk_pll1419x_find_pms(pll_spec, &tmp_rate_table, rate)) {
|
||||
pr_err("can't find pms value for rate(%lldHz) of \'%s\'",
|
||||
rate,
|
||||
clk->name);
|
||||
goto errorout;
|
||||
}
|
||||
|
||||
rate_table = &tmp_rate_table;
|
||||
|
||||
pr_warn("not exist in rate table, p(%d), m(%d), s(%d), fout(%lldHz) %s",
|
||||
rate_table->pdiv,
|
||||
rate_table->mdiv,
|
||||
rate_table->sdiv,
|
||||
rate,
|
||||
clk->name);
|
||||
}
|
||||
|
||||
_clk_pll141xx_disable(clk);
|
||||
|
||||
if (_clk_pll1419x_set_pms(clk, rate_table))
|
||||
goto errorout;
|
||||
|
||||
if (rate != 0) {
|
||||
if (_clk_pll141xx_is_enabled(clk) == 0)
|
||||
_clk_pll1419x_enable(clk);
|
||||
}
|
||||
return 0;
|
||||
|
||||
errorout:
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
static unsigned long long _clk_pll141xx_get_rate(struct pwrcal_clk *clk)
|
||||
{
|
||||
unsigned int mdiv, pdiv, sdiv, pll_con0;
|
||||
unsigned long long fout;
|
||||
|
||||
if (_clk_pll141xx_is_enabled(clk) == 0)
|
||||
return 0;
|
||||
pll_con0 = pwrcal_readl(clk->offset);
|
||||
mdiv = (pll_con0 >> PLL141XX_MDIV_SHIFT) & PLL141XX_MDIV_MASK;
|
||||
pdiv = (pll_con0 >> PLL141XX_PDIV_SHIFT) & PLL141XX_PDIV_MASK;
|
||||
sdiv = (pll_con0 >> PLL141XX_SDIV_SHIFT) & PLL141XX_SDIV_MASK;
|
||||
|
||||
if (pdiv == 0) {
|
||||
pr_err("pdiv is 0, id(%s)", clk->name);
|
||||
return 0;
|
||||
}
|
||||
fout = FIN_HZ_26M * mdiv;
|
||||
do_div(fout, (pdiv << sdiv));
|
||||
return (unsigned long long)fout;
|
||||
}
|
||||
|
||||
static unsigned long long _clk_pll1419x_get_rate(struct pwrcal_clk *clk)
|
||||
{
|
||||
unsigned int mdiv, pdiv, sdiv, pll_con0;
|
||||
unsigned long long fout;
|
||||
|
||||
if (_clk_pll141xx_is_enabled(clk) == 0)
|
||||
return 0;
|
||||
|
||||
pll_con0 = pwrcal_readl(clk->offset);
|
||||
mdiv = (pll_con0 >> PLL141XX_MDIV_SHIFT) & PLL141XX_MDIV_MASK;
|
||||
pdiv = (pll_con0 >> PLL141XX_PDIV_SHIFT) & PLL141XX_PDIV_MASK;
|
||||
sdiv = (pll_con0 >> PLL141XX_SDIV_SHIFT) & PLL141XX_SDIV_MASK;
|
||||
|
||||
if (pdiv == 0) {
|
||||
pr_err("pdiv is 0, id(%s)", clk->name);
|
||||
return 0;
|
||||
}
|
||||
fout = FIN_HZ_26M * 2 * mdiv;
|
||||
do_div(fout, (pdiv << sdiv));
|
||||
return (unsigned long long)fout;
|
||||
}
|
||||
|
||||
static int _clk_pll1431x_find_pms(struct pll_spec *pll_spec,
|
||||
struct pwrcal_pll_rate_table *rate_table,
|
||||
unsigned long long rate)
|
||||
{
|
||||
unsigned int p, m, s;
|
||||
signed short k;
|
||||
unsigned long long fref, fvco, fout;
|
||||
unsigned long long tmprate, tmpfout;
|
||||
|
||||
for (p = pll_spec->pdiv_min; p <= pll_spec->pdiv_max; p++) {
|
||||
fref = FIN_HZ_26M / p;
|
||||
if ((fref < pll_spec->fref_min) || (fref > pll_spec->fref_max))
|
||||
continue;
|
||||
|
||||
for (s = pll_spec->sdiv_min; s <= pll_spec->sdiv_max; s++) {
|
||||
tmprate = rate;
|
||||
do_div(tmprate, MHZ);
|
||||
tmprate = tmprate * p * (1 << s);
|
||||
do_div(tmprate, (FIN_HZ_26M / MHZ));
|
||||
m = (unsigned int)tmprate;
|
||||
|
||||
if ((m < pll_spec->mdiv_min)
|
||||
|| (m > pll_spec->mdiv_max))
|
||||
continue;
|
||||
|
||||
tmprate = rate;
|
||||
do_div(tmprate, MHZ);
|
||||
tmprate = tmprate * p * (1 << s);
|
||||
do_div(tmprate, (FIN_HZ_26M / MHZ));
|
||||
tmprate = (tmprate - m) * 65536;
|
||||
k = (unsigned int)tmprate;
|
||||
if ((k < pll_spec->kdiv_min)
|
||||
|| (k > pll_spec->kdiv_max))
|
||||
continue;
|
||||
|
||||
fvco = FIN_HZ_26M * ((m << 16) + k);
|
||||
do_div(fvco, p);
|
||||
fvco >>= 16;
|
||||
if ((fvco < pll_spec->fvco_min)
|
||||
|| (fvco > pll_spec->fvco_max))
|
||||
continue;
|
||||
|
||||
fout = fvco >> s;
|
||||
if ((fout >= pll_spec->fout_min)
|
||||
&& (fout <= pll_spec->fout_max)) {
|
||||
tmprate = rate;
|
||||
do_div(tmprate, KHZ);
|
||||
tmpfout = fout;
|
||||
do_div(tmpfout, KHZ);
|
||||
if (tmprate == tmpfout) {
|
||||
rate_table->rate = fout;
|
||||
rate_table->pdiv = p;
|
||||
rate_table->mdiv = m;
|
||||
rate_table->sdiv = s;
|
||||
rate_table->kdiv = k;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int _clk_pll1431x_is_enabled(struct pwrcal_clk *clk)
|
||||
{
|
||||
return (int)(pwrcal_getbit(clk->offset, PLL1431X_ENABLE));
|
||||
}
|
||||
|
||||
static int _clk_pll1431x_enable(struct pwrcal_clk *clk)
|
||||
{
|
||||
int timeout;
|
||||
|
||||
if (pwrcal_getbit(clk->offset, PLL1431X_ENABLE))
|
||||
return 0;
|
||||
|
||||
pwrcal_setbit(clk->offset, PLL1431X_ENABLE, 1);
|
||||
|
||||
for (timeout = 0;; timeout++) {
|
||||
if (pwrcal_getbit(clk->offset, PLL1431X_LOCKED))
|
||||
break;
|
||||
if (timeout > CLK_WAIT_CNT)
|
||||
return -1;
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _clk_pll1431x_disable(struct pwrcal_clk *clk)
|
||||
{
|
||||
pwrcal_setbit(clk->offset, PLL1431X_ENABLE, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int _clk_pll1431x_is_disabled_bypass(struct pwrcal_clk *clk)
|
||||
{
|
||||
if (pwrcal_getbit(clk->offset + 2, PLL1431X_BYPASS))
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int _clk_pll1431x_set_bypass(struct pwrcal_clk *clk, int bypass_disable)
|
||||
{
|
||||
if (bypass_disable == 0)
|
||||
pwrcal_setbit(clk->offset + 2, PLL1431X_BYPASS, 1);
|
||||
else
|
||||
pwrcal_setbit(clk->offset + 2, PLL1431X_BYPASS, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _clk_pll1431x_set_pms(struct pwrcal_clk *clk,
|
||||
const struct pwrcal_pll_rate_table *rate_table)
|
||||
{
|
||||
unsigned int mdiv, pdiv, sdiv, pll_con0, pll_con1;
|
||||
signed short kdiv;
|
||||
int timeout;
|
||||
|
||||
pdiv = rate_table->pdiv;
|
||||
mdiv = rate_table->mdiv;
|
||||
sdiv = rate_table->sdiv;
|
||||
kdiv = rate_table->kdiv;
|
||||
|
||||
pll_con0 = pwrcal_readl(clk->offset);
|
||||
pll_con1 = pwrcal_readl(clk->offset + 1);
|
||||
pll_con0 &= ~((PLL1431X_MDIV_MASK << PLL1431X_MDIV_SHIFT)
|
||||
| (PLL1431X_PDIV_MASK << PLL1431X_PDIV_SHIFT)
|
||||
| (PLL1431X_SDIV_MASK << PLL1431X_SDIV_SHIFT));
|
||||
pll_con0 |= (mdiv << PLL1431X_MDIV_SHIFT)
|
||||
| (pdiv << PLL1431X_PDIV_SHIFT)
|
||||
| (sdiv << PLL1431X_SDIV_SHIFT);
|
||||
pll_con0 &= ~(1<<26);
|
||||
pll_con0 |= (1<<5);
|
||||
|
||||
pll_con1 &= ~(PLL1431X_K_MASK << PLL1431X_K_SHIFT);
|
||||
pll_con1 |= (kdiv << PLL1431X_K_SHIFT);
|
||||
|
||||
if (kdiv == 0)
|
||||
pwrcal_writel(clk->status, pdiv*3000);
|
||||
else
|
||||
pwrcal_writel(clk->status, pdiv*3000);
|
||||
pwrcal_writel(clk->offset, pll_con0);
|
||||
pwrcal_writel(clk->offset + 1, pll_con1);
|
||||
|
||||
if (pll_con0 & (1 << PLL1431X_ENABLE)) {
|
||||
for (timeout = 0;; timeout++) {
|
||||
if (pwrcal_getbit(clk->offset, PLL1431X_LOCKED))
|
||||
break;
|
||||
if (timeout > CLK_WAIT_CNT)
|
||||
return -1;
|
||||
cpu_relax();
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _clk_pll1431x_set_rate(struct pwrcal_clk *clk,
|
||||
unsigned long long rate)
|
||||
{
|
||||
struct pwrcal_pll *pll = to_pll(clk);
|
||||
struct pwrcal_pll_rate_table tmp_rate_table;
|
||||
const struct pwrcal_pll_rate_table *rate_table;
|
||||
struct pll_spec *pll_spec;
|
||||
|
||||
if (rate == 0) {
|
||||
if (_clk_pll1431x_is_enabled(clk) != 0)
|
||||
if (_clk_pll1431x_disable(clk))
|
||||
goto errorout;
|
||||
return 0;
|
||||
}
|
||||
|
||||
rate_table = _clk_get_pll_settings(pll, rate);
|
||||
if (rate_table == NULL) {
|
||||
pll_spec = clk_pll_get_spec(clk);
|
||||
if (pll_spec == NULL)
|
||||
goto errorout;
|
||||
|
||||
if (_clk_pll1431x_find_pms(pll_spec, &tmp_rate_table, rate) < 0) {
|
||||
pr_err("can't find pms value for rate(%lldHz) of %s",
|
||||
rate,
|
||||
clk->name);
|
||||
goto errorout;
|
||||
}
|
||||
|
||||
rate_table = &tmp_rate_table;
|
||||
pr_warn("not exist in rate table, p(%d) m(%d) s(%d) k(%d) fout(%lld Hz) of %s",
|
||||
rate_table->pdiv,
|
||||
rate_table->mdiv,
|
||||
rate_table->sdiv,
|
||||
rate_table->kdiv,
|
||||
rate,
|
||||
clk->name);
|
||||
}
|
||||
|
||||
if (_clk_pll1431x_set_pms(clk, rate_table))
|
||||
goto errorout;
|
||||
|
||||
if (rate != 0) {
|
||||
if (_clk_pll1431x_is_enabled(clk) == 0)
|
||||
_clk_pll1431x_enable(clk);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
errorout:
|
||||
return -1;
|
||||
}
|
||||
|
||||
static unsigned long long _clk_pll1431x_get_rate(struct pwrcal_clk *clk)
|
||||
{
|
||||
unsigned int mdiv, pdiv, sdiv, pll_con0, pll_con1;
|
||||
signed short kdiv;
|
||||
unsigned long long fout;
|
||||
|
||||
if (_clk_pll1431x_is_enabled(clk) == 0)
|
||||
return 0;
|
||||
|
||||
pll_con0 = pwrcal_readl(clk->offset);
|
||||
pll_con1 = pwrcal_readl(clk->offset + 1);
|
||||
mdiv = (pll_con0 >> PLL1431X_MDIV_SHIFT) & PLL1431X_MDIV_MASK;
|
||||
pdiv = (pll_con0 >> PLL1431X_PDIV_SHIFT) & PLL1431X_PDIV_MASK;
|
||||
sdiv = (pll_con0 >> PLL1431X_SDIV_SHIFT) & PLL1431X_SDIV_MASK;
|
||||
|
||||
kdiv = (short)(pll_con1 >> PLL1431X_K_SHIFT) & PLL1431X_K_MASK;
|
||||
|
||||
if (pdiv == 0) {
|
||||
pr_err("pdiv is 0, id(%s)", clk->name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
fout = FIN_HZ_26M * ((mdiv << 16) + kdiv);
|
||||
do_div(fout, (pdiv << sdiv));
|
||||
fout >>= 16;
|
||||
|
||||
return (unsigned long long)fout;
|
||||
}
|
||||
|
||||
struct pwrcal_pll_ops pll141xx_ops = {
|
||||
.is_enabled = _clk_pll141xx_is_enabled,
|
||||
.enable = _clk_pll141xx_enable,
|
||||
.disable = _clk_pll141xx_disable,
|
||||
.set_rate = _clk_pll141xx_set_rate,
|
||||
.get_rate = _clk_pll141xx_get_rate,
|
||||
};
|
||||
|
||||
struct pwrcal_pll_ops pll1419x_ops = {
|
||||
.is_enabled = _clk_pll141xx_is_enabled,
|
||||
.enable = _clk_pll1419x_enable,
|
||||
.disable = _clk_pll141xx_disable,
|
||||
.set_rate = _clk_pll1419x_set_rate,
|
||||
.get_rate = _clk_pll1419x_get_rate,
|
||||
};
|
||||
|
||||
struct pwrcal_pll_ops pll1431x_ops = {
|
||||
.is_enabled = _clk_pll1431x_is_enabled,
|
||||
.enable = _clk_pll1431x_enable,
|
||||
.disable = _clk_pll1431x_disable,
|
||||
.set_rate = _clk_pll1431x_set_rate,
|
||||
.get_rate = _clk_pll1431x_get_rate,
|
||||
};
|
||||
1063
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-pmu.c
Normal file
1063
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-pmu.c
Normal file
File diff suppressed because it is too large
Load diff
2112
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-pmusfr.h
Executable file
2112
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-pmusfr.h
Executable file
File diff suppressed because it is too large
Load diff
99
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-rae.c
Executable file
99
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-rae.c
Executable file
|
|
@ -0,0 +1,99 @@
|
|||
#include "../pwrcal-rae.h"
|
||||
#include "S5E8890-sfrbase.h"
|
||||
|
||||
#ifdef PWRCAL_TARGET_LINUX
|
||||
|
||||
struct v2p_sfr v2psfrmap[] = {
|
||||
DEFINE_V2P(CMU_PERIS_BASE, 0x10040000),
|
||||
DEFINE_V2P(CMU_TOP_BASE, 0x10570000),
|
||||
DEFINE_V2P(CMU_CCORE_BASE, 0x105B0000),
|
||||
DEFINE_V2P(CMU_MIF0_BASE, 0x10850000),
|
||||
DEFINE_V2P(CMU_MIF1_BASE, 0x10950000),
|
||||
DEFINE_V2P(CMU_MIF2_BASE, 0x10A50000),
|
||||
DEFINE_V2P(CMU_MIF3_BASE, 0x10B50000),
|
||||
DEFINE_V2P(CMU_FSYS0_BASE, 0x10E90000),
|
||||
DEFINE_V2P(CMU_IMEM_BASE, 0x11060000),
|
||||
DEFINE_V2P(CMU_AUD_BASE, 0x114C0000),
|
||||
DEFINE_V2P(CMU_MNGS_BASE, 0x11800000),
|
||||
DEFINE_V2P(CMU_APOLLO_BASE, 0x11900000),
|
||||
DEFINE_V2P(CMU_BUS0_BASE, 0x13400000),
|
||||
DEFINE_V2P(CMU_BUS1_BASE, 0x14800000),
|
||||
DEFINE_V2P(CMU_PERIC0_BASE, 0x13610000),
|
||||
DEFINE_V2P(CMU_DISP0_BASE, 0x13AD0000),
|
||||
DEFINE_V2P(CMU_DISP1_BASE, 0x13F00000),
|
||||
DEFINE_V2P(CMU_CAM0_LOCAL_BASE, 0x140F0000),
|
||||
DEFINE_V2P(CMU_CAM0_BASE, 0x144D0000),
|
||||
DEFINE_V2P(CMU_CAM1_LOCAL_BASE, 0x141F0000),
|
||||
DEFINE_V2P(CMU_CAM1_BASE, 0x145D0000),
|
||||
DEFINE_V2P(CMU_ISP0_LOCAL_BASE, 0x14290000),
|
||||
DEFINE_V2P(CMU_ISP0_BASE, 0x146D0000),
|
||||
DEFINE_V2P(CMU_ISP1_LOCAL_BASE, 0x142F0000),
|
||||
DEFINE_V2P(CMU_ISP1_BASE, 0x147D0000),
|
||||
DEFINE_V2P(CMU_G3D_BASE, 0x14AA0000),
|
||||
DEFINE_V2P(CMU_PERIC1_BASE, 0x14C80000),
|
||||
DEFINE_V2P(CMU_MSCL_BASE, 0x150D0000),
|
||||
DEFINE_V2P(CMU_MFC_BASE, 0x15280000),
|
||||
DEFINE_V2P(CMU_FSYS1_BASE, 0x156E0000),
|
||||
|
||||
|
||||
DEFINE_V2P(PMU_PERIS_BASE, 0x10010000),
|
||||
DEFINE_V2P(PMU_ALIVE_BASE, 0x105C0000),
|
||||
DEFINE_V2P(PMU_CCORE_BASE, 0x105F0000),
|
||||
DEFINE_V2P(PMU_MIF0_BASE, 0x10840000),
|
||||
DEFINE_V2P(PMU_MIF1_BASE, 0x10940000),
|
||||
DEFINE_V2P(PMU_MIF2_BASE, 0x10A40000),
|
||||
DEFINE_V2P(PMU_MIF3_BASE, 0x10B40000),
|
||||
DEFINE_V2P(PMU_FSYS0_BASE, 0x10E70000),
|
||||
DEFINE_V2P(PMU_IMEM_BASE, 0x11070000),
|
||||
DEFINE_V2P(PMU_AUD_BASE, 0x114D0000),
|
||||
DEFINE_V2P(PMU_MNGS_BASE, 0x11820000),
|
||||
DEFINE_V2P(PMU_APOLLO_BASE, 0x11920000),
|
||||
DEFINE_V2P(PMU_BUS0_BASE, 0x13420000),
|
||||
DEFINE_V2P(PMU_BUS1_BASE, 0x14820000),
|
||||
DEFINE_V2P(PMU_PERIC0_BASE, 0x13600000),
|
||||
DEFINE_V2P(PMU_DISP0_BASE, 0x13AE0000),
|
||||
DEFINE_V2P(PMU_DISP1_BASE, 0x13F10000),
|
||||
DEFINE_V2P(PMU_CAM0_BASE, 0x144E0000),
|
||||
DEFINE_V2P(PMU_CAM1_BASE, 0x145E0000),
|
||||
DEFINE_V2P(PMU_ISP0_BASE, 0x146E0000),
|
||||
DEFINE_V2P(PMU_ISP1_BASE, 0x147E0000),
|
||||
DEFINE_V2P(PMU_G3D_BASE, 0x14A40000),
|
||||
DEFINE_V2P(PMU_PERIC1_BASE, 0x14C70000),
|
||||
DEFINE_V2P(PMU_MSCL_BASE, 0x150F0000),
|
||||
DEFINE_V2P(PMU_MFC_BASE, 0x15290000),
|
||||
DEFINE_V2P(PMU_FSYS1_BASE, 0x156C0000),
|
||||
|
||||
DEFINE_V2P(DMC_MISC_CCORE_BASE, 0x10520000),
|
||||
DEFINE_V2P(LPDDR4_PHY0_BASE, 0x10820000),
|
||||
|
||||
DEFINE_V2P(SYSREG_APOLLO_BASE, 0x11940000),
|
||||
DEFINE_V2P(SYSREG_AUD_BASE, 0x11480000),
|
||||
DEFINE_V2P(SYSREG_BUS0_BASE, 0x134C0000),
|
||||
DEFINE_V2P(SYSREG_BUS1_BASE, 0x148C0000),
|
||||
DEFINE_V2P(SYSREG_CAM0_BASE, 0x144F0000),
|
||||
DEFINE_V2P(SYSREG_CAM1_BASE, 0x145F0000),
|
||||
DEFINE_V2P(SYSREG_CCORE_BASE, 0x105D0000),
|
||||
DEFINE_V2P(SYSREG_DISP0_BASE, 0x13A60000),
|
||||
DEFINE_V2P(SYSREG_DISP1_BASE, 0x13F20000),
|
||||
DEFINE_V2P(SYSREG_FSYS0_BASE, 0x10E50000),
|
||||
DEFINE_V2P(SYSREG_FSYS1_BASE, 0x15600000),
|
||||
DEFINE_V2P(SYSREG_G3D_BASE, 0x14AE0000),
|
||||
DEFINE_V2P(SYSREG_IMEM_BASE, 0x11080000),
|
||||
DEFINE_V2P(SYSREG_ISP0_BASE, 0x146F0000),
|
||||
DEFINE_V2P(SYSREG_ISP1_BASE, 0x147F0000),
|
||||
DEFINE_V2P(SYSREG_MFC_BASE, 0x152A0000),
|
||||
DEFINE_V2P(SYSREG_MIF0_BASE, 0x10830000),
|
||||
DEFINE_V2P(SYSREG_MIF1_BASE, 0x10930000),
|
||||
DEFINE_V2P(SYSREG_MIF2_BASE, 0x10A30000),
|
||||
DEFINE_V2P(SYSREG_MIF3_BASE, 0x10B30000),
|
||||
DEFINE_V2P(SYSREG_MNGS_BASE, 0x11850000),
|
||||
DEFINE_V2P(SYSREG_MSCL_BASE, 0x151C0000),
|
||||
DEFINE_V2P(SYSREG_PERIC0_BASE, 0x136E0000),
|
||||
DEFINE_V2P(SYSREG_PERIC1_BASE, 0x14C60000),
|
||||
DEFINE_V2P(SYSREG_PERIS_BASE, 0x10050000),
|
||||
};
|
||||
|
||||
int num_of_v2psfrmap = sizeof(v2psfrmap) / sizeof(v2psfrmap[0]);
|
||||
void *spinlock_enable_offset = (void *)PMU_PERIS_BASE;
|
||||
|
||||
#endif
|
||||
190
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-sfrbase.h
Executable file
190
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-sfrbase.h
Executable file
|
|
@ -0,0 +1,190 @@
|
|||
#ifndef __EXYNOS8890_SFRBASE_H__
|
||||
#define __EXYNOS8890_SFRBASE_H__
|
||||
|
||||
#include "../pwrcal-env.h"
|
||||
|
||||
#ifdef PWRCAL_TARGET_FW
|
||||
|
||||
#define CMU_PERIS_BASE 0x10040000
|
||||
#define CMU_TOP_BASE 0x10570000
|
||||
#define CMU_CCORE_BASE 0x105B0000
|
||||
#define CMU_MIF0_BASE 0x10850000
|
||||
#define CMU_MIF1_BASE 0x10950000
|
||||
#define CMU_MIF2_BASE 0x10A50000
|
||||
#define CMU_MIF3_BASE 0x10B50000
|
||||
#define CMU_FSYS0_BASE 0x10E90000
|
||||
#define CMU_IMEM_BASE 0x11060000
|
||||
#define CMU_AUD_BASE 0x114C0000
|
||||
#define CMU_MNGS_BASE 0x11800000
|
||||
#define CMU_APOLLO_BASE 0x11900000
|
||||
#define CMU_BUS0_BASE 0x13400000
|
||||
#define CMU_BUS1_BASE 0x14800000
|
||||
#define CMU_PERIC0_BASE 0x13610000
|
||||
#define CMU_DISP0_BASE 0x13AD0000
|
||||
#define CMU_DISP1_BASE 0x13F00000
|
||||
#define CMU_CAM0_LOCAL_BASE 0x140F0000
|
||||
#define CMU_CAM0_BASE 0x144D0000
|
||||
#define CMU_CAM1_LOCAL_BASE 0x141F0000
|
||||
#define CMU_CAM1_BASE 0x145D0000
|
||||
#define CMU_ISP0_LOCAL_BASE 0x14290000
|
||||
#define CMU_ISP0_BASE 0x146D0000
|
||||
#define CMU_ISP1_LOCAL_BASE 0x142F0000
|
||||
#define CMU_ISP1_BASE 0x147D0000
|
||||
#define CMU_G3D_BASE 0x14AA0000
|
||||
#define CMU_PERIC1_BASE 0x14C80000
|
||||
#define CMU_MSCL_BASE 0x150D0000
|
||||
#define CMU_MFC_BASE 0x15280000
|
||||
#define CMU_FSYS1_BASE 0x156E0000
|
||||
|
||||
|
||||
#define PMU_PERIS_BASE 0x10010000
|
||||
#define PMU_ALIVE_BASE 0x105C0000
|
||||
#define PMU_CCORE_BASE 0x105F0000
|
||||
#define PMU_MIF0_BASE 0x10840000
|
||||
#define PMU_MIF1_BASE 0x10940000
|
||||
#define PMU_MIF2_BASE 0x10A40000
|
||||
#define PMU_MIF3_BASE 0x10B40000
|
||||
#define PMU_FSYS0_BASE 0x10E70000
|
||||
#define PMU_IMEM_BASE 0x11070000
|
||||
#define PMU_AUD_BASE 0x114D0000
|
||||
#define PMU_MNGS_BASE 0x11820000
|
||||
#define PMU_APOLLO_BASE 0x11920000
|
||||
#define PMU_BUS0_BASE 0x13420000
|
||||
#define PMU_BUS1_BASE 0x14820000
|
||||
#define PMU_PERIC0_BASE 0x13600000
|
||||
#define PMU_DISP0_BASE 0x13AE0000
|
||||
#define PMU_DISP1_BASE 0x13F10000
|
||||
#define PMU_CAM0_BASE 0x144E0000
|
||||
#define PMU_CAM1_BASE 0x145E0000
|
||||
#define PMU_ISP0_BASE 0x146E0000
|
||||
#define PMU_ISP1_BASE 0x147E0000
|
||||
#define PMU_G3D_BASE 0x14A40000
|
||||
#define PMU_PERIC1_BASE 0x14C70000
|
||||
#define PMU_MSCL_BASE 0x150F0000
|
||||
#define PMU_MFC_BASE 0x15290000
|
||||
#define PMU_FSYS1_BASE 0x156C0000
|
||||
|
||||
#define DMC_MISC_CCORE_BASE 0x10520000
|
||||
#define LPDDR4_PHY0_BASE 0x10820000
|
||||
|
||||
#define SYSREG_APOLLO_BASE 0x11940000
|
||||
#define SYSREG_AUD_BASE 0x11480000
|
||||
#define SYSREG_BUS0_BASE 0x134C0000
|
||||
#define SYSREG_BUS1_BASE 0x148C0000
|
||||
#define SYSREG_CAM0_BASE 0x144F0000
|
||||
#define SYSREG_CAM1_BASE 0x145F0000
|
||||
#define SYSREG_CCORE_BASE 0x105D0000
|
||||
#define SYSREG_DISP0_BASE 0x13A60000
|
||||
#define SYSREG_DISP1_BASE 0x13F20000
|
||||
#define SYSREG_FSYS0_BASE 0x10E50000
|
||||
#define SYSREG_FSYS1_BASE 0x15600000
|
||||
#define SYSREG_G3D_BASE 0x14AE0000
|
||||
#define SYSREG_IMEM_BASE 0x11080000
|
||||
#define SYSREG_ISP0_BASE 0x146F0000
|
||||
#define SYSREG_ISP1_BASE 0x147F0000
|
||||
#define SYSREG_MFC_BASE 0x152A0000
|
||||
#define SYSREG_MIF0_BASE 0x10830000
|
||||
#define SYSREG_MIF1_BASE 0x10930000
|
||||
#define SYSREG_MIF2_BASE 0x10A30000
|
||||
#define SYSREG_MIF3_BASE 0x10B30000
|
||||
#define SYSREG_MNGS_BASE 0x11850000
|
||||
#define SYSREG_MSCL_BASE 0x151C0000
|
||||
#define SYSREG_PERIC0_BASE 0x136E0000
|
||||
#define SYSREG_PERIC1_BASE 0x14C60000
|
||||
#define SYSREG_PERIS_BASE 0x10050000
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef PWRCAL_TARGET_LINUX
|
||||
|
||||
#define CMU_PERIS_BASE 0x00010000
|
||||
#define CMU_TOP_BASE 0x00020000
|
||||
#define CMU_CCORE_BASE 0x00030000
|
||||
#define CMU_MIF0_BASE 0x00040000
|
||||
#define CMU_MIF1_BASE 0x00050000
|
||||
#define CMU_MIF2_BASE 0x00060000
|
||||
#define CMU_MIF3_BASE 0x00070000
|
||||
#define CMU_FSYS0_BASE 0x00080000
|
||||
#define CMU_IMEM_BASE 0x00090000
|
||||
#define CMU_AUD_BASE 0x000A0000
|
||||
#define CMU_MNGS_BASE 0x000B0000
|
||||
#define CMU_APOLLO_BASE 0x000C0000
|
||||
#define CMU_BUS0_BASE 0x000D0000
|
||||
#define CMU_BUS1_BASE 0x000E0000
|
||||
#define CMU_PERIC0_BASE 0x000F0000
|
||||
#define CMU_DISP0_BASE 0x00100000
|
||||
#define CMU_DISP1_BASE 0x00110000
|
||||
#define CMU_CAM0_LOCAL_BASE 0x00120000
|
||||
#define CMU_CAM0_BASE 0x00130000
|
||||
#define CMU_CAM1_LOCAL_BASE 0x00140000
|
||||
#define CMU_CAM1_BASE 0x00150000
|
||||
#define CMU_ISP0_LOCAL_BASE 0x00160000
|
||||
#define CMU_ISP0_BASE 0x00170000
|
||||
#define CMU_ISP1_LOCAL_BASE 0x00180000
|
||||
#define CMU_ISP1_BASE 0x00190000
|
||||
#define CMU_G3D_BASE 0x001A0000
|
||||
#define CMU_PERIC1_BASE 0x001B0000
|
||||
#define CMU_MSCL_BASE 0x001C0000
|
||||
#define CMU_MFC_BASE 0x001D0000
|
||||
#define CMU_FSYS1_BASE 0x001E0000
|
||||
|
||||
|
||||
#define PMU_PERIS_BASE 0x001F0000
|
||||
#define PMU_ALIVE_BASE 0x00200000
|
||||
#define PMU_CCORE_BASE 0x00210000
|
||||
#define PMU_MIF0_BASE 0x00220000
|
||||
#define PMU_MIF1_BASE 0x00230000
|
||||
#define PMU_MIF2_BASE 0x00240000
|
||||
#define PMU_MIF3_BASE 0x00250000
|
||||
#define PMU_FSYS0_BASE 0x00260000
|
||||
#define PMU_IMEM_BASE 0x00270000
|
||||
#define PMU_AUD_BASE 0x00280000
|
||||
#define PMU_MNGS_BASE 0x00290000
|
||||
#define PMU_APOLLO_BASE 0x002A0000
|
||||
#define PMU_BUS0_BASE 0x002B0000
|
||||
#define PMU_BUS1_BASE 0x002C0000
|
||||
#define PMU_PERIC0_BASE 0x002D0000
|
||||
#define PMU_DISP0_BASE 0x002E0000
|
||||
#define PMU_DISP1_BASE 0x002F0000
|
||||
#define PMU_CAM0_BASE 0x00300000
|
||||
#define PMU_CAM1_BASE 0x00310000
|
||||
#define PMU_ISP0_BASE 0x00320000
|
||||
#define PMU_ISP1_BASE 0x00330000
|
||||
#define PMU_G3D_BASE 0x00340000
|
||||
#define PMU_PERIC1_BASE 0x00350000
|
||||
#define PMU_MSCL_BASE 0x00360000
|
||||
#define PMU_MFC_BASE 0x00370000
|
||||
#define PMU_FSYS1_BASE 0x00380000
|
||||
|
||||
#define DMC_MISC_CCORE_BASE 0x00390000
|
||||
#define LPDDR4_PHY0_BASE 0x003A0000
|
||||
|
||||
#define SYSREG_APOLLO_BASE 0x003B0000
|
||||
#define SYSREG_AUD_BASE 0x003C0000
|
||||
#define SYSREG_BUS0_BASE 0x003D0000
|
||||
#define SYSREG_BUS1_BASE 0x003E0000
|
||||
#define SYSREG_CAM0_BASE 0x003F0000
|
||||
#define SYSREG_CAM1_BASE 0x00400000
|
||||
#define SYSREG_CCORE_BASE 0x00410000
|
||||
#define SYSREG_DISP0_BASE 0x00420000
|
||||
#define SYSREG_DISP1_BASE 0x00430000
|
||||
#define SYSREG_FSYS0_BASE 0x00440000
|
||||
#define SYSREG_FSYS1_BASE 0x00450000
|
||||
#define SYSREG_G3D_BASE 0x00460000
|
||||
#define SYSREG_IMEM_BASE 0x00470000
|
||||
#define SYSREG_ISP0_BASE 0x00480000
|
||||
#define SYSREG_ISP1_BASE 0x00490000
|
||||
#define SYSREG_MFC_BASE 0x004A0000
|
||||
#define SYSREG_MIF0_BASE 0x004B0000
|
||||
#define SYSREG_MIF1_BASE 0x004C0000
|
||||
#define SYSREG_MIF2_BASE 0x004D0000
|
||||
#define SYSREG_MIF3_BASE 0x004E0000
|
||||
#define SYSREG_MNGS_BASE 0x004F0000
|
||||
#define SYSREG_MSCL_BASE 0x00500000
|
||||
#define SYSREG_PERIC0_BASE 0x00510000
|
||||
#define SYSREG_PERIC1_BASE 0x00520000
|
||||
#define SYSREG_PERIS_BASE 0x00530000
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
2331
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-syspwr.c
Normal file
2331
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-syspwr.c
Normal file
File diff suppressed because it is too large
Load diff
406
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-vclk-internal.h
Normal file
406
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-vclk-internal.h
Normal file
|
|
@ -0,0 +1,406 @@
|
|||
#ifndef __EXYNOS8890_VCLKS_H__
|
||||
#define __EXYNOS8890_VCLKS_H__
|
||||
|
||||
#include "../pwrcal-vclk.h"
|
||||
#include "../pwrcal-pmu.h"
|
||||
#include "S5E8890-vclk.h"
|
||||
|
||||
|
||||
GRPGATE_EXTERN(gate_apollo_ppmu)
|
||||
GRPGATE_EXTERN(gate_apollo_bts)
|
||||
GRPGATE_EXTERN(gate_mngs_ppmu)
|
||||
GRPGATE_EXTERN(gate_mngs_bts)
|
||||
GRPGATE_EXTERN(gate_aud_common)
|
||||
GRPGATE_EXTERN(gate_aud_lpass)
|
||||
GRPGATE_EXTERN(gate_aud_mi2s)
|
||||
GRPGATE_EXTERN(gate_aud_pcm)
|
||||
GRPGATE_EXTERN(gate_aud_uart)
|
||||
GRPGATE_EXTERN(gate_aud_dma)
|
||||
GRPGATE_EXTERN(gate_aud_slimbus)
|
||||
GRPGATE_EXTERN(gate_aud_sysmmu)
|
||||
GRPGATE_EXTERN(gate_aud_ppmu)
|
||||
GRPGATE_EXTERN(gate_aud_bts)
|
||||
GRPGATE_EXTERN(gate_aud_sclk_mi2s)
|
||||
GRPGATE_EXTERN(gate_aud_sclk_pcm)
|
||||
GRPGATE_EXTERN(gate_aud_sclk_slimbus)
|
||||
GRPGATE_EXTERN(gate_bus0_display)
|
||||
GRPGATE_EXTERN(gate_bus0_cam)
|
||||
GRPGATE_EXTERN(gate_bus0_fsys1)
|
||||
GRPGATE_EXTERN(gate_bus1_mfc)
|
||||
GRPGATE_EXTERN(gate_bus1_mscl)
|
||||
GRPGATE_EXTERN(gate_bus1_fsys0)
|
||||
GRPGATE_EXTERN(gate_cam0_common)
|
||||
GRPGATE_EXTERN(gate_cam0_csis0)
|
||||
GRPGATE_EXTERN(gate_cam0_csis1)
|
||||
GRPGATE_EXTERN(gate_cam0_fimc_bns)
|
||||
GRPGATE_EXTERN(gate_cam0_fimc_3aa0)
|
||||
GRPGATE_EXTERN(gate_cam0_fimc_3aa1)
|
||||
GRPGATE_EXTERN(gate_cam0_hpm)
|
||||
GRPGATE_EXTERN(gate_cam0_sysmmu)
|
||||
GRPGATE_EXTERN(gate_cam0_ppmu)
|
||||
GRPGATE_EXTERN(gate_cam0_bts)
|
||||
GRPGATE_EXTERN(gate_cam0_phyclk_hs0_csis0_rx_byte)
|
||||
GRPGATE_EXTERN(gate_cam0_phyclk_hs1_csis0_rx_byte)
|
||||
GRPGATE_EXTERN(gate_cam0_phyclk_hs2_csis0_rx_byte)
|
||||
GRPGATE_EXTERN(gate_cam0_phyclk_hs3_csis0_rx_byte)
|
||||
GRPGATE_EXTERN(gate_cam0_phyclk_hs0_csis1_rx_byte)
|
||||
GRPGATE_EXTERN(gate_cam0_phyclk_hs1_csis1_rx_byte)
|
||||
GRPGATE_EXTERN(gate_cam1_common)
|
||||
GRPGATE_EXTERN(gate_cam1_isp_cpu_gic_common)
|
||||
GRPGATE_EXTERN(gate_cam1_isp_cpu)
|
||||
GRPGATE_EXTERN(gate_cam1_gic_is)
|
||||
GRPGATE_EXTERN(gate_cam1_csis2)
|
||||
GRPGATE_EXTERN(gate_cam1_csis3)
|
||||
GRPGATE_EXTERN(gate_cam1_fimc_vra)
|
||||
GRPGATE_EXTERN(gate_cam1_mc_scaler)
|
||||
GRPGATE_EXTERN(gate_cam1_i2c0_isp)
|
||||
GRPGATE_EXTERN(gate_cam1_i2c1_isp)
|
||||
GRPGATE_EXTERN(gate_cam1_i2c2_isp)
|
||||
GRPGATE_EXTERN(gate_cam1_i2c3_isp)
|
||||
GRPGATE_EXTERN(gate_cam1_wdt_isp)
|
||||
GRPGATE_EXTERN(gate_cam1_mcuctl_isp)
|
||||
GRPGATE_EXTERN(gate_cam1_uart_isp)
|
||||
GRPGATE_EXTERN(gate_cam1_sclk_uart_isp)
|
||||
GRPGATE_EXTERN(gate_cam1_spi0_isp)
|
||||
GRPGATE_EXTERN(gate_cam1_spi1_isp)
|
||||
GRPGATE_EXTERN(gate_cam1_pdma_isp)
|
||||
GRPGATE_EXTERN(gate_cam1_pwm_isp)
|
||||
GRPGATE_EXTERN(gate_cam1_sclk_pwm_isp)
|
||||
GRPGATE_EXTERN(gate_cam1_sysmmu)
|
||||
GRPGATE_EXTERN(gate_cam1_ppmu)
|
||||
GRPGATE_EXTERN(gate_cam1_bts)
|
||||
GRPGATE_EXTERN(gate_cam1_phyclk_hs0_csis2_rx_byte)
|
||||
GRPGATE_EXTERN(gate_cam1_phyclk_hs1_csis2_rx_byte)
|
||||
GRPGATE_EXTERN(gate_cam1_phyclk_hs2_csis2_rx_byte)
|
||||
GRPGATE_EXTERN(gate_cam1_phyclk_hs3_csis2_rx_byte)
|
||||
GRPGATE_EXTERN(gate_cam1_phyclk_hs0_csis3_rx_byte)
|
||||
GRPGATE_EXTERN(gate_disp0_common)
|
||||
GRPGATE_EXTERN(gate_disp0_decon0)
|
||||
GRPGATE_EXTERN(gate_disp0_dsim0)
|
||||
GRPGATE_EXTERN(gate_disp0_dsim1)
|
||||
GRPGATE_EXTERN(gate_disp0_dsim2)
|
||||
GRPGATE_EXTERN(gate_disp0_hdmi)
|
||||
GRPGATE_EXTERN(gate_disp0_dp)
|
||||
GRPGATE_EXTERN(gate_disp0_hpm_apbif_disp0)
|
||||
GRPGATE_EXTERN(gate_disp0_sysmmu)
|
||||
GRPGATE_EXTERN(gate_disp0_ppmu)
|
||||
GRPGATE_EXTERN(gate_disp0_bts)
|
||||
GRPGATE_EXTERN(gate_disp0_phyclk_hdmiphy_tmds_20b_clko)
|
||||
GRPGATE_EXTERN(gate_disp0_phyclk_hdmiphy_tmds_10b_clko)
|
||||
GRPGATE_EXTERN(gate_disp0_phyclk_hdmiphy_pixel_clko)
|
||||
GRPGATE_EXTERN(gate_disp0_phyclk_mipidphy0_rxclkesc0)
|
||||
GRPGATE_EXTERN(gate_disp0_phyclk_mipidphy0_bitclkdiv8)
|
||||
GRPGATE_EXTERN(gate_disp0_phyclk_mipidphy1_rxclkesc0)
|
||||
GRPGATE_EXTERN(gate_disp0_phyclk_mipidphy1_bitclkdiv8)
|
||||
GRPGATE_EXTERN(gate_disp0_phyclk_mipidphy2_rxclkesc0)
|
||||
GRPGATE_EXTERN(gate_disp0_phyclk_mipidphy2_bitclkdiv8)
|
||||
GRPGATE_EXTERN(gate_disp0_phyclk_dpphy_ch0_txd_clk)
|
||||
GRPGATE_EXTERN(gate_disp0_phyclk_dpphy_ch1_txd_clk)
|
||||
GRPGATE_EXTERN(gate_disp0_phyclk_dpphy_ch2_txd_clk)
|
||||
GRPGATE_EXTERN(gate_disp0_phyclk_dpphy_ch3_txd_clk)
|
||||
GRPGATE_EXTERN(gate_disp0_oscclk_dp_i_clk_24m)
|
||||
GRPGATE_EXTERN(gate_disp0_oscclk_i_dptx_phy_i_ref_clk_24m)
|
||||
GRPGATE_EXTERN(gate_disp0_oscclk_i_mipi_dphy_m1s0_m_xi)
|
||||
GRPGATE_EXTERN(gate_disp0_oscclk_i_mipi_dphy_m4s0_m_xi)
|
||||
GRPGATE_EXTERN(gate_disp0_oscclk_i_mipi_dphy_m4s4_m_xi)
|
||||
GRPGATE_EXTERN(gate_disp1_common)
|
||||
GRPGATE_EXTERN(gate_disp1_decon1)
|
||||
GRPGATE_EXTERN(gate_disp1_hpmdisp1)
|
||||
GRPGATE_EXTERN(gate_disp1_sysmmu)
|
||||
GRPGATE_EXTERN(gate_disp1_ppmu)
|
||||
GRPGATE_EXTERN(gate_disp1_bts)
|
||||
GRPGATE_EXTERN(gate_fsys0_common)
|
||||
GRPGATE_EXTERN(gate_fsys0_usbdrd_etrusb_common)
|
||||
GRPGATE_EXTERN(gate_fsys0_usbdrd30)
|
||||
GRPGATE_EXTERN(gate_fsys0_etr_usb)
|
||||
GRPGATE_EXTERN(gate_fsys0_usbhost20)
|
||||
GRPGATE_EXTERN(gate_fsys0_mmc0_ufs_common)
|
||||
GRPGATE_EXTERN(gate_fsys0_mmc0)
|
||||
GRPGATE_EXTERN(gate_fsys0_ufs_linkemedded)
|
||||
GRPGATE_EXTERN(gate_fsys0_pdma_common)
|
||||
GRPGATE_EXTERN(gate_fsys0_pdma0)
|
||||
GRPGATE_EXTERN(gate_fsys0_pdmas)
|
||||
GRPGATE_EXTERN(gate_fsys0_ppmu)
|
||||
GRPGATE_EXTERN(gate_fsys0_bts)
|
||||
GRPGATE_EXTERN(gate_fsys0_hpm)
|
||||
GRPGATE_EXTERN(gate_fsys0_phyclk_usbdrd30_udrd30_phyclock)
|
||||
GRPGATE_EXTERN(gate_fsys0_phyclk_usbdrd30_udrd30_pipe_pclk)
|
||||
GRPGATE_EXTERN(gate_fsys0_phyclk_ufs_tx0_symbol)
|
||||
GRPGATE_EXTERN(gate_fsys0_phyclk_ufs_rx0_symbol)
|
||||
GRPGATE_EXTERN(gate_fsys0_phyclk_usbhost20_phyclock)
|
||||
GRPGATE_EXTERN(gate_fsys0_phyclk_usbhost20_freeclk)
|
||||
GRPGATE_EXTERN(gate_fsys0_phyclk_usbhost20_clk48mohci)
|
||||
GRPGATE_EXTERN(gate_fsys0_phyclk_usbhost20phy_ref_clk)
|
||||
GRPGATE_EXTERN(gate_fsys0_phyclk_ufs_rx_pwm_clk)
|
||||
GRPGATE_EXTERN(gate_fsys0_phyclk_ufs_tx_pwm_clk)
|
||||
GRPGATE_EXTERN(gate_fsys0_phyclk_ufs_refclk_out_soc)
|
||||
GRPGATE_EXTERN(gate_fsys1_common)
|
||||
GRPGATE_EXTERN(gate_fsys1_mmc2_ufs_common)
|
||||
GRPGATE_EXTERN(gate_fsys1_mmc2)
|
||||
GRPGATE_EXTERN(gate_fsys1_ufs20_sdcard)
|
||||
GRPGATE_EXTERN(gate_fsys1_sromc)
|
||||
GRPGATE_EXTERN(gate_fsys1_pciewifi0)
|
||||
GRPGATE_EXTERN(gate_fsys1_pciewifi1)
|
||||
GRPGATE_EXTERN(gate_fsys1_ppmu)
|
||||
GRPGATE_EXTERN(gate_fsys1_bts)
|
||||
GRPGATE_EXTERN(gate_fsys1_hpm)
|
||||
GRPGATE_EXTERN(gate_fsys1_phyclk_ufs_link_sdcard_tx0_symbol)
|
||||
GRPGATE_EXTERN(gate_fsys1_phyclk_ufs_link_sdcard_rx0_symbol)
|
||||
GRPGATE_EXTERN(gate_fsys1_phyclk_pcie_wifi0_tx0)
|
||||
GRPGATE_EXTERN(gate_fsys1_phyclk_pcie_wifi0_rx0)
|
||||
GRPGATE_EXTERN(gate_fsys1_phyclk_pcie_wifi1_tx0)
|
||||
GRPGATE_EXTERN(gate_fsys1_phyclk_pcie_wifi1_rx0)
|
||||
GRPGATE_EXTERN(gate_fsys1_phyclk_pcie_wifi0_dig_refclk)
|
||||
GRPGATE_EXTERN(gate_fsys1_phyclk_pcie_wifi1_dig_refclk)
|
||||
GRPGATE_EXTERN(gate_fsys1_phyclk_ufs_link_sdcard_rx_pwm_clk)
|
||||
GRPGATE_EXTERN(gate_fsys1_phyclk_ufs_link_sdcard_tx_pwm_clk)
|
||||
GRPGATE_EXTERN(gate_fsys1_phyclk_ufs_link_sdcard_refclk_out_soc)
|
||||
GRPGATE_EXTERN(gate_g3d_common)
|
||||
GRPGATE_EXTERN(gate_g3d_g3d_common)
|
||||
GRPGATE_EXTERN(gate_g3d_g3d)
|
||||
GRPGATE_EXTERN(gate_g3d_iram_path_test)
|
||||
GRPGATE_EXTERN(gate_g3d_ppmu)
|
||||
GRPGATE_EXTERN(gate_g3d_bts)
|
||||
GRPGATE_EXTERN(gate_imem_common)
|
||||
GRPGATE_EXTERN(gate_imem_apm_sss_rtic_mc_common)
|
||||
GRPGATE_EXTERN(gate_imem_apm)
|
||||
GRPGATE_EXTERN(gate_imem_sss)
|
||||
GRPGATE_EXTERN(gate_imem_rtic)
|
||||
GRPGATE_EXTERN(gate_imem_mc)
|
||||
GRPGATE_EXTERN(gate_imem_intmem)
|
||||
GRPGATE_EXTERN(gate_imem_intmem_alv)
|
||||
GRPGATE_EXTERN(gate_imem_gic400)
|
||||
GRPGATE_EXTERN(gate_imem_ppmu)
|
||||
GRPGATE_EXTERN(gate_isp0_common)
|
||||
GRPGATE_EXTERN(gate_isp0_fimc_isp0)
|
||||
GRPGATE_EXTERN(gate_isp0_fimc_tpu)
|
||||
GRPGATE_EXTERN(gate_isp0_sysmmu)
|
||||
GRPGATE_EXTERN(gate_isp0_ppmu)
|
||||
GRPGATE_EXTERN(gate_isp0_bts)
|
||||
GRPGATE_EXTERN(gate_isp1_fimc_isp1)
|
||||
GRPGATE_EXTERN(gate_isp1_sysmmu)
|
||||
GRPGATE_EXTERN(gate_isp1_ppmu)
|
||||
GRPGATE_EXTERN(gate_isp1_bts)
|
||||
GRPGATE_EXTERN(gate_mfc_common)
|
||||
GRPGATE_EXTERN(gate_mfc_mfc)
|
||||
GRPGATE_EXTERN(gate_mfc_hpm)
|
||||
GRPGATE_EXTERN(gate_mfc_sysmmu)
|
||||
GRPGATE_EXTERN(gate_mfc_ppmu)
|
||||
GRPGATE_EXTERN(gate_mscl_common)
|
||||
GRPGATE_EXTERN(gate_mscl_mscl0_jpeg_common)
|
||||
GRPGATE_EXTERN(gate_mscl_mscl0)
|
||||
GRPGATE_EXTERN(gate_mscl_jpeg)
|
||||
GRPGATE_EXTERN(gate_mscl_mscl1_g2d_common)
|
||||
GRPGATE_EXTERN(gate_mscl_mscl1)
|
||||
GRPGATE_EXTERN(gate_mscl_g2d)
|
||||
GRPGATE_EXTERN(gate_mscl_sysmmu)
|
||||
GRPGATE_EXTERN(gate_mscl_ppmu)
|
||||
GRPGATE_EXTERN(gate_mscl_bts)
|
||||
GRPGATE_EXTERN(gate_peric0_hsi2c0)
|
||||
GRPGATE_EXTERN(gate_peric0_hsi2c1)
|
||||
GRPGATE_EXTERN(gate_peric0_hsi2c4)
|
||||
GRPGATE_EXTERN(gate_peric0_hsi2c5)
|
||||
GRPGATE_EXTERN(gate_peric0_hsi2c9)
|
||||
GRPGATE_EXTERN(gate_peric0_hsi2c10)
|
||||
GRPGATE_EXTERN(gate_peric0_hsi2c11)
|
||||
GRPGATE_EXTERN(gate_peric0_uart0)
|
||||
GRPGATE_EXTERN(gate_peric0_adcif)
|
||||
GRPGATE_EXTERN(gate_peric0_pwm)
|
||||
GRPGATE_EXTERN(gate_peric0_sclk_pwm)
|
||||
GRPGATE_EXTERN(gate_peric1_hsi2c_common)
|
||||
GRPGATE_EXTERN(gate_peric1_hsi2c2)
|
||||
GRPGATE_EXTERN(gate_peric1_hsi2c3)
|
||||
GRPGATE_EXTERN(gate_peric1_hsi2c6)
|
||||
GRPGATE_EXTERN(gate_peric1_hsi2c7)
|
||||
GRPGATE_EXTERN(gate_peric1_hsi2c8)
|
||||
GRPGATE_EXTERN(gate_peric1_hsi2c12)
|
||||
GRPGATE_EXTERN(gate_peric1_hsi2c13)
|
||||
GRPGATE_EXTERN(gate_peric1_hsi2c14)
|
||||
GRPGATE_EXTERN(gate_peric1_spi_i2s_pcm1_spdif_common)
|
||||
GRPGATE_EXTERN(gate_peric1_uart1)
|
||||
GRPGATE_EXTERN(gate_peric1_uart2)
|
||||
GRPGATE_EXTERN(gate_peric1_uart3)
|
||||
GRPGATE_EXTERN(gate_peric1_uart4)
|
||||
GRPGATE_EXTERN(gate_peric1_uart5)
|
||||
GRPGATE_EXTERN(gate_peric1_spi0)
|
||||
GRPGATE_EXTERN(gate_peric1_spi1)
|
||||
GRPGATE_EXTERN(gate_peric1_spi2)
|
||||
GRPGATE_EXTERN(gate_peric1_spi3)
|
||||
GRPGATE_EXTERN(gate_peric1_spi4)
|
||||
GRPGATE_EXTERN(gate_peric1_spi5)
|
||||
GRPGATE_EXTERN(gate_peric1_spi6)
|
||||
GRPGATE_EXTERN(gate_peric1_spi7)
|
||||
GRPGATE_EXTERN(gate_peric1_i2s1)
|
||||
GRPGATE_EXTERN(gate_peric1_pcm1)
|
||||
GRPGATE_EXTERN(gate_peric1_spdif)
|
||||
GRPGATE_EXTERN(gate_peric1_gpio_nfc)
|
||||
GRPGATE_EXTERN(gate_peric1_gpio_touch)
|
||||
GRPGATE_EXTERN(gate_peric1_gpio_fp)
|
||||
GRPGATE_EXTERN(gate_peric1_gpio_ese)
|
||||
GRPGATE_EXTERN(gate_peris_sfr_apbif_hdmi_cec)
|
||||
GRPGATE_EXTERN(gate_peris_hpm)
|
||||
GRPGATE_EXTERN(gate_peris_mct)
|
||||
GRPGATE_EXTERN(gate_peris_wdt_mngs)
|
||||
GRPGATE_EXTERN(gate_peris_wdt_apollo)
|
||||
GRPGATE_EXTERN(gate_peris_sysreg_peris)
|
||||
GRPGATE_EXTERN(gate_peris_monocnt_apbif)
|
||||
GRPGATE_EXTERN(gate_peris_rtc_apbif)
|
||||
GRPGATE_EXTERN(gate_peris_top_rtc)
|
||||
GRPGATE_EXTERN(gate_peris_otp_con_top)
|
||||
GRPGATE_EXTERN(gate_peris_chipid)
|
||||
GRPGATE_EXTERN(gate_peris_tmu)
|
||||
|
||||
M1D1G1_EXTERN(sclk_decon0_eclk0)
|
||||
M1D1G1_EXTERN(sclk_decon0_vclk0)
|
||||
M1D1G1_EXTERN(sclk_decon0_vclk1)
|
||||
M1D1G1_EXTERN(sclk_hdmi_audio)
|
||||
M1D1G1_EXTERN(sclk_decon1_eclk0)
|
||||
M1D1G1_EXTERN(sclk_decon1_eclk1)
|
||||
M1D1G1_EXTERN(sclk_usbdrd30)
|
||||
M1D1G1_EXTERN(sclk_mmc0)
|
||||
M1D1G1_EXTERN(sclk_ufsunipro20)
|
||||
M1D1G1_EXTERN(sclk_phy24m)
|
||||
M1D1G1_EXTERN(sclk_ufsunipro_cfg)
|
||||
M1D1G1_EXTERN(sclk_mmc2)
|
||||
M1D1G1_EXTERN(sclk_ufsunipro20_sdcard)
|
||||
M1D1G1_EXTERN(sclk_pcie_phy)
|
||||
M1D1G1_EXTERN(sclk_ufsunipro_sdcard_cfg)
|
||||
M1D1G1_EXTERN(sclk_uart0)
|
||||
M1D1G1_EXTERN(sclk_spi0)
|
||||
M1D1G1_EXTERN(sclk_spi1)
|
||||
M1D1G1_EXTERN(sclk_spi2)
|
||||
M1D1G1_EXTERN(sclk_spi3)
|
||||
M1D1G1_EXTERN(sclk_spi4)
|
||||
M1D1G1_EXTERN(sclk_spi5)
|
||||
M1D1G1_EXTERN(sclk_spi6)
|
||||
M1D1G1_EXTERN(sclk_spi7)
|
||||
M1D1G1_EXTERN(sclk_uart1)
|
||||
M1D1G1_EXTERN(sclk_uart2)
|
||||
M1D1G1_EXTERN(sclk_uart3)
|
||||
M1D1G1_EXTERN(sclk_uart4)
|
||||
M1D1G1_EXTERN(sclk_uart5)
|
||||
M1D1G1_EXTERN(sclk_promise_int)
|
||||
M1D1G1_EXTERN(sclk_promise_disp)
|
||||
M1D1G1_EXTERN(sclk_ap2cp_mif_pll_out)
|
||||
M1D1G1_EXTERN(sclk_isp_spi0)
|
||||
M1D1G1_EXTERN(sclk_isp_spi1)
|
||||
M1D1G1_EXTERN(sclk_isp_uart)
|
||||
M1D1G1_EXTERN(sclk_isp_sensor0)
|
||||
M1D1G1_EXTERN(sclk_isp_sensor1)
|
||||
M1D1G1_EXTERN(sclk_isp_sensor2)
|
||||
M1D1G1_EXTERN(sclk_isp_sensor3)
|
||||
M1D1G1_EXTERN(sclk_decon0_eclk0_local)
|
||||
M1D1G1_EXTERN(sclk_decon0_vclk0_local)
|
||||
M1D1G1_EXTERN(sclk_decon0_vclk1_local)
|
||||
M1D1G1_EXTERN(sclk_decon1_eclk0_local)
|
||||
M1D1G1_EXTERN(sclk_decon1_eclk1_local)
|
||||
|
||||
P1_EXTERN(p1_disp_pll)
|
||||
P1_EXTERN(p1_aud_pll)
|
||||
P1_EXTERN(p1_mfc_pll)
|
||||
|
||||
D1_EXTERN(d1_sclk_i2s_local)
|
||||
D1_EXTERN(d1_sclk_pcm_local)
|
||||
D1_EXTERN(d1_sclk_slimbus)
|
||||
D1_EXTERN(d1_sclk_cp_i2s)
|
||||
D1_EXTERN(d1_sclk_asrc)
|
||||
|
||||
PXMXDX_EXTERN(pxmxdx_top)
|
||||
PXMXDX_EXTERN(pxmxdx_mfc)
|
||||
PXMXDX_EXTERN(pxmxdx_mscl)
|
||||
PXMXDX_EXTERN(pxmxdx_imem)
|
||||
PXMXDX_EXTERN(pxmxdx_fsys0)
|
||||
PXMXDX_EXTERN(pxmxdx_fsys1)
|
||||
PXMXDX_EXTERN(pxmxdx_disp0)
|
||||
PXMXDX_EXTERN(pxmxdx_disp1)
|
||||
PXMXDX_EXTERN(pxmxdx_aud)
|
||||
PXMXDX_EXTERN(pxmxdx_aud_cp)
|
||||
PXMXDX_EXTERN(pxmxdx_isp0_isp0)
|
||||
PXMXDX_EXTERN(pxmxdx_isp0_tpu)
|
||||
PXMXDX_EXTERN(pxmxdx_isp0_trex)
|
||||
PXMXDX_EXTERN(pxmxdx_isp1_isp1)
|
||||
PXMXDX_EXTERN(pxmxdx_cam0_csis0)
|
||||
PXMXDX_EXTERN(pxmxdx_cam0_csis1)
|
||||
PXMXDX_EXTERN(pxmxdx_cam0_csis2)
|
||||
PXMXDX_EXTERN(pxmxdx_cam0_csis3)
|
||||
PXMXDX_EXTERN(pxmxdx_cam0_3aa0)
|
||||
PXMXDX_EXTERN(pxmxdx_cam0_3aa1)
|
||||
PXMXDX_EXTERN(pxmxdx_cam0_trex)
|
||||
PXMXDX_EXTERN(pxmxdx_cam1_arm)
|
||||
PXMXDX_EXTERN(pxmxdx_cam1_vra)
|
||||
PXMXDX_EXTERN(pxmxdx_cam1_trex)
|
||||
PXMXDX_EXTERN(pxmxdx_cam1_bus)
|
||||
PXMXDX_EXTERN(pxmxdx_cam1_peri)
|
||||
PXMXDX_EXTERN(pxmxdx_cam1_csis2)
|
||||
PXMXDX_EXTERN(pxmxdx_cam1_csis3)
|
||||
PXMXDX_EXTERN(pxmxdx_cam1_scl)
|
||||
PXMXDX_EXTERN(pxmxdx_oscclk_nfc)
|
||||
PXMXDX_EXTERN(pxmxdx_oscclk_aud)
|
||||
|
||||
UMUX_EXTERN(umux_bus0_aclk_bus0_528)
|
||||
UMUX_EXTERN(umux_bus0_aclk_bus0_200)
|
||||
UMUX_EXTERN(umux_bus1_aclk_bus1_528)
|
||||
UMUX_EXTERN(umux_cam0_phyclk_rxbyteclkhs0_csis0_user)
|
||||
UMUX_EXTERN(umux_cam0_phyclk_rxbyteclkhs1_csis0_user)
|
||||
UMUX_EXTERN(umux_cam0_phyclk_rxbyteclkhs2_csis0_user)
|
||||
UMUX_EXTERN(umux_cam0_phyclk_rxbyteclkhs3_csis0_user)
|
||||
UMUX_EXTERN(umux_cam0_phyclk_rxbyteclkhs0_csis1_user)
|
||||
UMUX_EXTERN(umux_cam0_phyclk_rxbyteclkhs1_csis1_user)
|
||||
UMUX_EXTERN(umux_cam1_phyclk_rxbyteclkhs0_csis2_user)
|
||||
UMUX_EXTERN(umux_cam1_phyclk_rxbyteclkhs1_csis2_user)
|
||||
UMUX_EXTERN(umux_cam1_phyclk_rxbyteclkhs2_csis2_user)
|
||||
UMUX_EXTERN(umux_cam1_phyclk_rxbyteclkhs3_csis2_user)
|
||||
UMUX_EXTERN(umux_cam1_phyclk_rxbyteclkhs0_csis3_user)
|
||||
UMUX_EXTERN(umux_disp0_phyclk_hdmiphy_pixel_clko_user)
|
||||
UMUX_EXTERN(umux_disp0_phyclk_hdmiphy_tmds_clko_user)
|
||||
UMUX_EXTERN(umux_disp0_phyclk_mipidphy0_rxclkesc0_user)
|
||||
UMUX_EXTERN(umux_disp0_phyclk_mipidphy0_bitclkdiv2_user)
|
||||
UMUX_EXTERN(umux_disp0_phyclk_mipidphy0_bitclkdiv8_user)
|
||||
UMUX_EXTERN(umux_disp0_phyclk_mipidphy1_rxclkesc0_user)
|
||||
UMUX_EXTERN(umux_disp0_phyclk_mipidphy1_bitclkdiv2_user)
|
||||
UMUX_EXTERN(umux_disp0_phyclk_mipidphy1_bitclkdiv8_user)
|
||||
UMUX_EXTERN(umux_disp0_phyclk_mipidphy2_rxclkesc0_user)
|
||||
UMUX_EXTERN(umux_disp0_phyclk_mipidphy2_bitclkdiv2_user)
|
||||
UMUX_EXTERN(umux_disp0_phyclk_mipidphy2_bitclkdiv8_user)
|
||||
UMUX_EXTERN(umux_disp0_phyclk_dpphy_ch0_txd_clk_user)
|
||||
UMUX_EXTERN(umux_disp0_phyclk_dpphy_ch1_txd_clk_user)
|
||||
UMUX_EXTERN(umux_disp0_phyclk_dpphy_ch2_txd_clk_user)
|
||||
UMUX_EXTERN(umux_disp0_phyclk_dpphy_ch3_txd_clk_user)
|
||||
UMUX_EXTERN(umux_disp1_phyclk_mipidphy0_bitclkdiv2_user)
|
||||
UMUX_EXTERN(umux_disp1_phyclk_mipidphy1_bitclkdiv2_user)
|
||||
UMUX_EXTERN(umux_disp1_phyclk_mipidphy2_bitclkdiv2_user)
|
||||
UMUX_EXTERN(umux_disp1_phyclk_disp1_hdmiphy_pixel_clko_user)
|
||||
UMUX_EXTERN(umux_fsys0_phyclk_usbdrd30_udrd30_phyclock_user)
|
||||
UMUX_EXTERN(umux_fsys0_phyclk_usbdrd30_udrd30_pipe_pclk_user)
|
||||
UMUX_EXTERN(umux_fsys0_phyclk_ufs_tx0_symbol_user)
|
||||
UMUX_EXTERN(umux_fsys0_phyclk_ufs_rx0_symbol_user)
|
||||
UMUX_EXTERN(umux_fsys0_phyclk_usbhost20_phyclock_user)
|
||||
UMUX_EXTERN(umux_fsys0_phyclk_usbhost20_freeclk_user)
|
||||
UMUX_EXTERN(umux_fsys0_phyclk_usbhost20_clk48mohci_user)
|
||||
UMUX_EXTERN(umux_fsys0_phyclk_usbhost20phy_ref_clk)
|
||||
UMUX_EXTERN(umux_fsys0_phyclk_ufs_rx_pwm_clk_user)
|
||||
UMUX_EXTERN(umux_fsys0_phyclk_ufs_tx_pwm_clk_user)
|
||||
UMUX_EXTERN(umux_fsys0_phyclk_ufs_refclk_out_soc_user)
|
||||
UMUX_EXTERN(umux_fsys1_phyclk_ufs_link_sdcard_tx0_symbol_user)
|
||||
UMUX_EXTERN(umux_fsys1_phyclk_ufs_link_sdcard_rx0_symbol_user)
|
||||
UMUX_EXTERN(umux_fsys1_phyclk_pcie_wifi0_tx0_user)
|
||||
UMUX_EXTERN(umux_fsys1_phyclk_pcie_wifi0_rx0_user)
|
||||
UMUX_EXTERN(umux_fsys1_phyclk_pcie_wifi1_tx0_user)
|
||||
UMUX_EXTERN(umux_fsys1_phyclk_pcie_wifi1_rx0_user)
|
||||
UMUX_EXTERN(umux_fsys1_phyclk_pcie_wifi0_dig_refclk_user)
|
||||
UMUX_EXTERN(umux_fsys1_phyclk_pcie_wifi1_dig_refclk_user)
|
||||
UMUX_EXTERN(umux_fsys1_phyclk_ufs_link_sdcard_rx_pwm_clk_user)
|
||||
UMUX_EXTERN(umux_fsys1_phyclk_ufs_link_sdcard_tx_pwm_clk_user)
|
||||
UMUX_EXTERN(umux_fsys1_phyclk_ufs_link_sdcard_refclk_out_soc_user)
|
||||
|
||||
DFS_EXTERN(dvfs_big)
|
||||
DFS_EXTERN(dvfs_little)
|
||||
DFS_EXTERN(dvfs_g3d)
|
||||
DFS_EXTERN(dvfs_mif)
|
||||
DFS_EXTERN(dvfs_int)
|
||||
DFS_EXTERN(dvfs_cam)
|
||||
DFS_EXTERN(dvfs_disp)
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
2303
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-vclk.c
Normal file
2303
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-vclk.c
Normal file
File diff suppressed because it is too large
Load diff
422
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-vclk.h
Normal file
422
drivers/soc/samsung/pwrcal/S5E8890_EVT0/S5E8890-vclk.h
Normal file
|
|
@ -0,0 +1,422 @@
|
|||
#ifndef __EXYNOS8890_VCLK_H__
|
||||
#define __EXYNOS8890_VCLK_H__
|
||||
|
||||
enum {
|
||||
invalid_vclk_id = 0x00000FFF,
|
||||
|
||||
gate_apollo_ppmu = 0x0A000000,
|
||||
gate_apollo_bts,
|
||||
gate_mngs_ppmu,
|
||||
gate_mngs_bts,
|
||||
gate_aud_common,
|
||||
gate_aud_lpass,
|
||||
gate_aud_mi2s,
|
||||
gate_aud_pcm,
|
||||
gate_aud_uart,
|
||||
gate_aud_dma,
|
||||
gate_aud_slimbus,
|
||||
gate_aud_sysmmu,
|
||||
gate_aud_ppmu,
|
||||
gate_aud_bts,
|
||||
gate_aud_sclk_mi2s,
|
||||
gate_aud_sclk_pcm,
|
||||
gate_aud_sclk_slimbus,
|
||||
gate_bus0_display,
|
||||
gate_bus0_cam,
|
||||
gate_bus0_fsys1,
|
||||
gate_bus1_mfc,
|
||||
gate_bus1_mscl,
|
||||
gate_bus1_fsys0,
|
||||
gate_cam0_common,
|
||||
gate_cam0_csis0,
|
||||
gate_cam0_csis1,
|
||||
gate_cam0_fimc_bns,
|
||||
gate_cam0_fimc_3aa0,
|
||||
gate_cam0_fimc_3aa1,
|
||||
gate_cam0_hpm,
|
||||
gate_cam0_sysmmu,
|
||||
gate_cam0_ppmu,
|
||||
gate_cam0_bts,
|
||||
gate_cam0_phyclk_hs0_csis0_rx_byte,
|
||||
gate_cam0_phyclk_hs1_csis0_rx_byte,
|
||||
gate_cam0_phyclk_hs2_csis0_rx_byte,
|
||||
gate_cam0_phyclk_hs3_csis0_rx_byte,
|
||||
gate_cam0_phyclk_hs0_csis1_rx_byte,
|
||||
gate_cam0_phyclk_hs1_csis1_rx_byte,
|
||||
gate_cam1_common,
|
||||
gate_cam1_isp_cpu_gic_common,
|
||||
gate_cam1_isp_cpu,
|
||||
gate_cam1_gic_is,
|
||||
gate_cam1_csis2,
|
||||
gate_cam1_csis3,
|
||||
gate_cam1_fimc_vra,
|
||||
gate_cam1_mc_scaler,
|
||||
gate_cam1_i2c0_isp,
|
||||
gate_cam1_i2c1_isp,
|
||||
gate_cam1_i2c2_isp,
|
||||
gate_cam1_i2c3_isp,
|
||||
gate_cam1_wdt_isp,
|
||||
gate_cam1_mcuctl_isp,
|
||||
gate_cam1_uart_isp,
|
||||
gate_cam1_sclk_uart_isp,
|
||||
gate_cam1_spi0_isp,
|
||||
gate_cam1_spi1_isp,
|
||||
gate_cam1_pdma_isp,
|
||||
gate_cam1_pwm_isp,
|
||||
gate_cam1_sclk_pwm_isp,
|
||||
gate_cam1_sysmmu,
|
||||
gate_cam1_ppmu,
|
||||
gate_cam1_bts,
|
||||
gate_cam1_phyclk_hs0_csis2_rx_byte,
|
||||
gate_cam1_phyclk_hs1_csis2_rx_byte,
|
||||
gate_cam1_phyclk_hs2_csis2_rx_byte,
|
||||
gate_cam1_phyclk_hs3_csis2_rx_byte,
|
||||
gate_cam1_phyclk_hs0_csis3_rx_byte,
|
||||
gate_ccore_i2c,
|
||||
gate_disp0_common,
|
||||
gate_disp0_decon0,
|
||||
gate_disp0_dsim0,
|
||||
gate_disp0_dsim1,
|
||||
gate_disp0_dsim2,
|
||||
gate_disp0_hdmi,
|
||||
gate_disp0_dp,
|
||||
gate_disp0_hpm_apbif_disp0,
|
||||
gate_disp0_sysmmu,
|
||||
gate_disp0_ppmu,
|
||||
gate_disp0_bts,
|
||||
gate_disp0_phyclk_hdmiphy_tmds_20b_clko,
|
||||
gate_disp0_phyclk_hdmiphy_tmds_10b_clko,
|
||||
gate_disp0_phyclk_hdmiphy_pixel_clko,
|
||||
gate_disp0_phyclk_mipidphy0_rxclkesc0,
|
||||
gate_disp0_phyclk_mipidphy0_bitclkdiv8,
|
||||
gate_disp0_phyclk_mipidphy1_rxclkesc0,
|
||||
gate_disp0_phyclk_mipidphy1_bitclkdiv8,
|
||||
gate_disp0_phyclk_mipidphy2_rxclkesc0,
|
||||
gate_disp0_phyclk_mipidphy2_bitclkdiv8,
|
||||
gate_disp0_phyclk_dpphy_ch0_txd_clk,
|
||||
gate_disp0_phyclk_dpphy_ch1_txd_clk,
|
||||
gate_disp0_phyclk_dpphy_ch2_txd_clk,
|
||||
gate_disp0_phyclk_dpphy_ch3_txd_clk,
|
||||
gate_disp0_oscclk_dp_i_clk_24m,
|
||||
gate_disp0_oscclk_i_dptx_phy_i_ref_clk_24m,
|
||||
gate_disp0_oscclk_i_mipi_dphy_m1s0_m_xi,
|
||||
gate_disp0_oscclk_i_mipi_dphy_m4s0_m_xi,
|
||||
gate_disp0_oscclk_i_mipi_dphy_m4s4_m_xi,
|
||||
gate_disp1_common,
|
||||
gate_disp1_decon1,
|
||||
gate_disp1_hpmdisp1,
|
||||
gate_disp1_sysmmu,
|
||||
gate_disp1_ppmu,
|
||||
gate_disp1_bts,
|
||||
gate_fsys0_common,
|
||||
gate_fsys0_usbdrd_etrusb_common,
|
||||
gate_fsys0_usbdrd30,
|
||||
gate_fsys0_etr_usb,
|
||||
gate_fsys0_usbhost20,
|
||||
gate_fsys0_mmc0_ufs_common,
|
||||
gate_fsys0_mmc0,
|
||||
gate_fsys0_ufs_linkemedded,
|
||||
gate_fsys0_pdma_common,
|
||||
gate_fsys0_pdma0,
|
||||
gate_fsys0_pdmas,
|
||||
gate_fsys0_ppmu,
|
||||
gate_fsys0_bts,
|
||||
gate_fsys0_hpm,
|
||||
gate_fsys0_phyclk_usbdrd30_udrd30_phyclock,
|
||||
gate_fsys0_phyclk_usbdrd30_udrd30_pipe_pclk,
|
||||
gate_fsys0_phyclk_ufs_tx0_symbol,
|
||||
gate_fsys0_phyclk_ufs_rx0_symbol,
|
||||
gate_fsys0_phyclk_usbhost20_phyclock,
|
||||
gate_fsys0_phyclk_usbhost20_freeclk,
|
||||
gate_fsys0_phyclk_usbhost20_clk48mohci,
|
||||
gate_fsys0_phyclk_usbhost20phy_ref_clk,
|
||||
gate_fsys0_phyclk_ufs_rx_pwm_clk,
|
||||
gate_fsys0_phyclk_ufs_tx_pwm_clk,
|
||||
gate_fsys0_phyclk_ufs_refclk_out_soc,
|
||||
gate_fsys1_common,
|
||||
gate_fsys1_mmc2_ufs_common,
|
||||
gate_fsys1_mmc2,
|
||||
gate_fsys1_ufs20_sdcard,
|
||||
gate_fsys1_sromc,
|
||||
gate_fsys1_pciewifi0,
|
||||
gate_fsys1_pciewifi1,
|
||||
gate_fsys1_ppmu,
|
||||
gate_fsys1_bts,
|
||||
gate_fsys1_hpm,
|
||||
gate_fsys1_phyclk_ufs_link_sdcard_tx0_symbol,
|
||||
gate_fsys1_phyclk_ufs_link_sdcard_rx0_symbol,
|
||||
gate_fsys1_phyclk_pcie_wifi0_tx0,
|
||||
gate_fsys1_phyclk_pcie_wifi0_rx0,
|
||||
gate_fsys1_phyclk_pcie_wifi1_tx0,
|
||||
gate_fsys1_phyclk_pcie_wifi1_rx0,
|
||||
gate_fsys1_phyclk_pcie_wifi0_dig_refclk,
|
||||
gate_fsys1_phyclk_pcie_wifi1_dig_refclk,
|
||||
gate_fsys1_phyclk_ufs_link_sdcard_rx_pwm_clk,
|
||||
gate_fsys1_phyclk_ufs_link_sdcard_tx_pwm_clk,
|
||||
gate_fsys1_phyclk_ufs_link_sdcard_refclk_out_soc,
|
||||
gate_g3d_common,
|
||||
gate_g3d_g3d_common,
|
||||
gate_g3d_g3d,
|
||||
gate_g3d_iram_path_test,
|
||||
gate_g3d_ppmu,
|
||||
gate_g3d_bts,
|
||||
gate_imem_common,
|
||||
gate_imem_apm_sss_rtic_mc_common,
|
||||
gate_imem_apm,
|
||||
gate_imem_sss,
|
||||
gate_imem_rtic,
|
||||
gate_imem_mc,
|
||||
gate_imem_intmem,
|
||||
gate_imem_intmem_alv,
|
||||
gate_imem_gic400,
|
||||
gate_imem_ppmu,
|
||||
gate_isp0_common,
|
||||
gate_isp0_fimc_isp0,
|
||||
gate_isp0_fimc_tpu,
|
||||
gate_isp0_sysmmu,
|
||||
gate_isp0_ppmu,
|
||||
gate_isp0_bts,
|
||||
gate_isp1_fimc_isp1,
|
||||
gate_isp1_sysmmu,
|
||||
gate_isp1_ppmu,
|
||||
gate_isp1_bts,
|
||||
gate_mfc_common,
|
||||
gate_mfc_mfc,
|
||||
gate_mfc_hpm,
|
||||
gate_mfc_sysmmu,
|
||||
gate_mfc_ppmu,
|
||||
gate_mscl_common,
|
||||
gate_mscl_mscl0_jpeg_common,
|
||||
gate_mscl_mscl0,
|
||||
gate_mscl_jpeg,
|
||||
gate_mscl_mscl1_g2d_common,
|
||||
gate_mscl_mscl1,
|
||||
gate_mscl_g2d,
|
||||
gate_mscl_sysmmu,
|
||||
gate_mscl_ppmu,
|
||||
gate_mscl_bts,
|
||||
gate_peric0_hsi2c0,
|
||||
gate_peric0_hsi2c1,
|
||||
gate_peric0_hsi2c4,
|
||||
gate_peric0_hsi2c5,
|
||||
gate_peric0_hsi2c9,
|
||||
gate_peric0_hsi2c10,
|
||||
gate_peric0_hsi2c11,
|
||||
gate_peric0_uart0,
|
||||
gate_peric0_adcif,
|
||||
gate_peric0_pwm,
|
||||
gate_peric0_sclk_pwm,
|
||||
gate_peric1_hsi2c_common,
|
||||
gate_peric1_hsi2c2,
|
||||
gate_peric1_hsi2c3,
|
||||
gate_peric1_hsi2c6,
|
||||
gate_peric1_hsi2c7,
|
||||
gate_peric1_hsi2c8,
|
||||
gate_peric1_hsi2c12,
|
||||
gate_peric1_hsi2c13,
|
||||
gate_peric1_hsi2c14,
|
||||
gate_peric1_spi_i2s_pcm1_spdif_common,
|
||||
gate_peric1_uart1,
|
||||
gate_peric1_uart2,
|
||||
gate_peric1_uart3,
|
||||
gate_peric1_uart4,
|
||||
gate_peric1_uart5,
|
||||
gate_peric1_spi0,
|
||||
gate_peric1_spi1,
|
||||
gate_peric1_spi2,
|
||||
gate_peric1_spi3,
|
||||
gate_peric1_spi4,
|
||||
gate_peric1_spi5,
|
||||
gate_peric1_spi6,
|
||||
gate_peric1_spi7,
|
||||
gate_peric1_i2s1,
|
||||
gate_peric1_pcm1,
|
||||
gate_peric1_spdif,
|
||||
gate_peric1_gpio_nfc,
|
||||
gate_peric1_gpio_touch,
|
||||
gate_peric1_gpio_fp,
|
||||
gate_peric1_gpio_ese,
|
||||
gate_peris_sfr_apbif_hdmi_cec,
|
||||
gate_peris_hpm,
|
||||
gate_peris_mct,
|
||||
gate_peris_wdt_mngs,
|
||||
gate_peris_wdt_apollo,
|
||||
gate_peris_sysreg_peris,
|
||||
gate_peris_monocnt_apbif,
|
||||
gate_peris_rtc_apbif,
|
||||
gate_peris_top_rtc,
|
||||
gate_peris_otp_con_top,
|
||||
gate_peris_chipid,
|
||||
gate_peris_tmu,
|
||||
vclk_group_grpgate_end,
|
||||
num_of_grpgate = vclk_group_grpgate_end - 0x0A000000,
|
||||
|
||||
sclk_decon0_eclk0 = 0x0A010000,
|
||||
sclk_decon0_vclk0,
|
||||
sclk_decon0_vclk1,
|
||||
sclk_hdmi_audio,
|
||||
sclk_decon1_eclk0,
|
||||
sclk_decon1_eclk1,
|
||||
sclk_usbdrd30,
|
||||
sclk_mmc0,
|
||||
sclk_ufsunipro20,
|
||||
sclk_phy24m,
|
||||
sclk_ufsunipro_cfg,
|
||||
sclk_mmc2,
|
||||
sclk_ufsunipro20_sdcard,
|
||||
sclk_pcie_phy,
|
||||
sclk_ufsunipro_sdcard_cfg,
|
||||
sclk_uart0,
|
||||
sclk_spi0,
|
||||
sclk_spi1,
|
||||
sclk_spi2,
|
||||
sclk_spi3,
|
||||
sclk_spi4,
|
||||
sclk_spi5,
|
||||
sclk_spi6,
|
||||
sclk_spi7,
|
||||
sclk_uart1,
|
||||
sclk_uart2,
|
||||
sclk_uart3,
|
||||
sclk_uart4,
|
||||
sclk_uart5,
|
||||
sclk_promise_int,
|
||||
sclk_promise_disp,
|
||||
sclk_ap2cp_mif_pll_out,
|
||||
sclk_isp_spi0,
|
||||
sclk_isp_spi1,
|
||||
sclk_isp_uart,
|
||||
sclk_isp_sensor0,
|
||||
sclk_isp_sensor1,
|
||||
sclk_isp_sensor2,
|
||||
sclk_isp_sensor3,
|
||||
sclk_decon0_eclk0_local,
|
||||
sclk_decon0_vclk0_local,
|
||||
sclk_decon0_vclk1_local,
|
||||
sclk_decon1_eclk0_local,
|
||||
sclk_decon1_eclk1_local,
|
||||
vclk_group_m1d1g1_end,
|
||||
num_of_m1d1g1 = vclk_group_m1d1g1_end - 0x0A010000,
|
||||
|
||||
p1_disp_pll = 0x0A020000,
|
||||
p1_aud_pll,
|
||||
p1_mfc_pll,
|
||||
vclk_group_p1_end,
|
||||
num_of_p1 = vclk_group_p1_end - 0x0A020000,
|
||||
|
||||
m1_dummy = 0x0A030000,
|
||||
vclk_group_m1_end,
|
||||
num_of_m1 = vclk_group_m1_end - 0x0A030000,
|
||||
|
||||
d1_sclk_i2s_local = 0x0A040000,
|
||||
d1_sclk_pcm_local,
|
||||
d1_sclk_slimbus,
|
||||
d1_sclk_cp_i2s,
|
||||
d1_sclk_asrc,
|
||||
vclk_group_d1_end,
|
||||
num_of_d1 = vclk_group_d1_end - 0x0A040000,
|
||||
|
||||
pxmxdx_top = 0x0A050000,
|
||||
pxmxdx_mfc,
|
||||
pxmxdx_mscl,
|
||||
pxmxdx_imem,
|
||||
pxmxdx_fsys0,
|
||||
pxmxdx_fsys1,
|
||||
pxmxdx_disp0,
|
||||
pxmxdx_disp1,
|
||||
pxmxdx_aud,
|
||||
pxmxdx_aud_cp,
|
||||
pxmxdx_isp0_isp0,
|
||||
pxmxdx_isp0_tpu,
|
||||
pxmxdx_isp0_trex,
|
||||
pxmxdx_isp1_isp1,
|
||||
pxmxdx_cam0_csis0,
|
||||
pxmxdx_cam0_csis1,
|
||||
pxmxdx_cam0_csis2,
|
||||
pxmxdx_cam0_csis3,
|
||||
pxmxdx_cam0_3aa0,
|
||||
pxmxdx_cam0_3aa1,
|
||||
pxmxdx_cam0_trex,
|
||||
pxmxdx_cam1_arm,
|
||||
pxmxdx_cam1_vra,
|
||||
pxmxdx_cam1_trex,
|
||||
pxmxdx_cam1_bus,
|
||||
pxmxdx_cam1_peri,
|
||||
pxmxdx_cam1_csis2,
|
||||
pxmxdx_cam1_csis3,
|
||||
pxmxdx_cam1_scl,
|
||||
pxmxdx_oscclk_nfc,
|
||||
pxmxdx_oscclk_aud,
|
||||
vclk_group_pxmxdx_end,
|
||||
num_of_pxmxdx = vclk_group_pxmxdx_end - 0x0A050000,
|
||||
|
||||
umux_bus0_aclk_bus0_528 = 0x0A060000,
|
||||
umux_bus0_aclk_bus0_200,
|
||||
umux_bus1_aclk_bus1_528,
|
||||
umux_cam0_phyclk_rxbyteclkhs0_csis0_user,
|
||||
umux_cam0_phyclk_rxbyteclkhs1_csis0_user,
|
||||
umux_cam0_phyclk_rxbyteclkhs2_csis0_user,
|
||||
umux_cam0_phyclk_rxbyteclkhs3_csis0_user,
|
||||
umux_cam0_phyclk_rxbyteclkhs0_csis1_user,
|
||||
umux_cam0_phyclk_rxbyteclkhs1_csis1_user,
|
||||
umux_cam1_phyclk_rxbyteclkhs0_csis2_user,
|
||||
umux_cam1_phyclk_rxbyteclkhs1_csis2_user,
|
||||
umux_cam1_phyclk_rxbyteclkhs2_csis2_user,
|
||||
umux_cam1_phyclk_rxbyteclkhs3_csis2_user,
|
||||
umux_cam1_phyclk_rxbyteclkhs0_csis3_user,
|
||||
umux_disp0_phyclk_hdmiphy_pixel_clko_user,
|
||||
umux_disp0_phyclk_hdmiphy_tmds_clko_user,
|
||||
umux_disp0_phyclk_mipidphy0_rxclkesc0_user,
|
||||
umux_disp0_phyclk_mipidphy0_bitclkdiv2_user,
|
||||
umux_disp0_phyclk_mipidphy0_bitclkdiv8_user,
|
||||
umux_disp0_phyclk_mipidphy1_rxclkesc0_user,
|
||||
umux_disp0_phyclk_mipidphy1_bitclkdiv2_user,
|
||||
umux_disp0_phyclk_mipidphy1_bitclkdiv8_user,
|
||||
umux_disp0_phyclk_mipidphy2_rxclkesc0_user,
|
||||
umux_disp0_phyclk_mipidphy2_bitclkdiv2_user,
|
||||
umux_disp0_phyclk_mipidphy2_bitclkdiv8_user,
|
||||
umux_disp0_phyclk_dpphy_ch0_txd_clk_user,
|
||||
umux_disp0_phyclk_dpphy_ch1_txd_clk_user,
|
||||
umux_disp0_phyclk_dpphy_ch2_txd_clk_user,
|
||||
umux_disp0_phyclk_dpphy_ch3_txd_clk_user,
|
||||
umux_disp1_phyclk_mipidphy0_bitclkdiv2_user,
|
||||
umux_disp1_phyclk_mipidphy1_bitclkdiv2_user,
|
||||
umux_disp1_phyclk_mipidphy2_bitclkdiv2_user,
|
||||
umux_disp1_phyclk_disp1_hdmiphy_pixel_clko_user,
|
||||
umux_fsys0_phyclk_usbdrd30_udrd30_phyclock_user,
|
||||
umux_fsys0_phyclk_usbdrd30_udrd30_pipe_pclk_user,
|
||||
umux_fsys0_phyclk_ufs_tx0_symbol_user,
|
||||
umux_fsys0_phyclk_ufs_rx0_symbol_user,
|
||||
umux_fsys0_phyclk_usbhost20_phyclock_user,
|
||||
umux_fsys0_phyclk_usbhost20_freeclk_user,
|
||||
umux_fsys0_phyclk_usbhost20_clk48mohci_user,
|
||||
umux_fsys0_phyclk_usbhost20phy_ref_clk,
|
||||
umux_fsys0_phyclk_ufs_rx_pwm_clk_user,
|
||||
umux_fsys0_phyclk_ufs_tx_pwm_clk_user,
|
||||
umux_fsys0_phyclk_ufs_refclk_out_soc_user,
|
||||
umux_fsys1_phyclk_ufs_link_sdcard_tx0_symbol_user,
|
||||
umux_fsys1_phyclk_ufs_link_sdcard_rx0_symbol_user,
|
||||
umux_fsys1_phyclk_pcie_wifi0_tx0_user,
|
||||
umux_fsys1_phyclk_pcie_wifi0_rx0_user,
|
||||
umux_fsys1_phyclk_pcie_wifi1_tx0_user,
|
||||
umux_fsys1_phyclk_pcie_wifi1_rx0_user,
|
||||
umux_fsys1_phyclk_pcie_wifi0_dig_refclk_user,
|
||||
umux_fsys1_phyclk_pcie_wifi1_dig_refclk_user,
|
||||
umux_fsys1_phyclk_ufs_link_sdcard_rx_pwm_clk_user,
|
||||
umux_fsys1_phyclk_ufs_link_sdcard_tx_pwm_clk_user,
|
||||
umux_fsys1_phyclk_ufs_link_sdcard_refclk_out_soc_user,
|
||||
vclk_group_umux_end,
|
||||
num_of_umux = vclk_group_umux_end - 0x0A060000,
|
||||
|
||||
dvfs_big = 0x0A070000,
|
||||
dvfs_little,
|
||||
dvfs_g3d,
|
||||
dvfs_mif,
|
||||
dvfs_int,
|
||||
dvfs_cam,
|
||||
dvfs_disp,
|
||||
vclk_group_dfs_end,
|
||||
num_of_dfs = vclk_group_dfs_end - 0x0A070000,
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue