mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-09 01:28:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
552
drivers/spi/spi-mpc52xx.c
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552
drivers/spi/spi-mpc52xx.c
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@ -0,0 +1,552 @@
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/*
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* MPC52xx SPI bus driver.
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*
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* Copyright (C) 2008 Secret Lab Technologies Ltd.
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*
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* This file is released under the GPLv2
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*
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* This is the driver for the MPC5200's dedicated SPI controller.
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*
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* Note: this driver does not support the MPC5200 PSC in SPI mode. For
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* that driver see drivers/spi/mpc52xx_psc_spi.c
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*/
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/of_platform.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/spi/spi.h>
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#include <linux/io.h>
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#include <linux/of_gpio.h>
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#include <linux/slab.h>
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#include <asm/time.h>
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#include <asm/mpc52xx.h>
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MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
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MODULE_DESCRIPTION("MPC52xx SPI (non-PSC) Driver");
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MODULE_LICENSE("GPL");
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/* Register offsets */
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#define SPI_CTRL1 0x00
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#define SPI_CTRL1_SPIE (1 << 7)
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#define SPI_CTRL1_SPE (1 << 6)
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#define SPI_CTRL1_MSTR (1 << 4)
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#define SPI_CTRL1_CPOL (1 << 3)
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#define SPI_CTRL1_CPHA (1 << 2)
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#define SPI_CTRL1_SSOE (1 << 1)
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#define SPI_CTRL1_LSBFE (1 << 0)
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#define SPI_CTRL2 0x01
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#define SPI_BRR 0x04
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#define SPI_STATUS 0x05
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#define SPI_STATUS_SPIF (1 << 7)
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#define SPI_STATUS_WCOL (1 << 6)
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#define SPI_STATUS_MODF (1 << 4)
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#define SPI_DATA 0x09
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#define SPI_PORTDATA 0x0d
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#define SPI_DATADIR 0x10
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/* FSM state return values */
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#define FSM_STOP 0 /* Nothing more for the state machine to */
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/* do. If something interesting happens */
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/* then an IRQ will be received */
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#define FSM_POLL 1 /* need to poll for completion, an IRQ is */
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/* not expected */
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#define FSM_CONTINUE 2 /* Keep iterating the state machine */
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/* Driver internal data */
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struct mpc52xx_spi {
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struct spi_master *master;
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void __iomem *regs;
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int irq0; /* MODF irq */
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int irq1; /* SPIF irq */
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unsigned int ipb_freq;
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/* Statistics; not used now, but will be reintroduced for debugfs */
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int msg_count;
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int wcol_count;
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int wcol_ticks;
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u32 wcol_tx_timestamp;
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int modf_count;
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int byte_count;
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struct list_head queue; /* queue of pending messages */
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spinlock_t lock;
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struct work_struct work;
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/* Details of current transfer (length, and buffer pointers) */
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struct spi_message *message; /* current message */
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struct spi_transfer *transfer; /* current transfer */
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int (*state)(int irq, struct mpc52xx_spi *ms, u8 status, u8 data);
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int len;
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int timestamp;
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u8 *rx_buf;
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const u8 *tx_buf;
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int cs_change;
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int gpio_cs_count;
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unsigned int *gpio_cs;
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};
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/*
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* CS control function
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*/
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static void mpc52xx_spi_chipsel(struct mpc52xx_spi *ms, int value)
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{
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int cs;
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if (ms->gpio_cs_count > 0) {
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cs = ms->message->spi->chip_select;
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gpio_set_value(ms->gpio_cs[cs], value ? 0 : 1);
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} else
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out_8(ms->regs + SPI_PORTDATA, value ? 0 : 0x08);
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}
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/*
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* Start a new transfer. This is called both by the idle state
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* for the first transfer in a message, and by the wait state when the
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* previous transfer in a message is complete.
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*/
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static void mpc52xx_spi_start_transfer(struct mpc52xx_spi *ms)
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{
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ms->rx_buf = ms->transfer->rx_buf;
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ms->tx_buf = ms->transfer->tx_buf;
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ms->len = ms->transfer->len;
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/* Activate the chip select */
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if (ms->cs_change)
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mpc52xx_spi_chipsel(ms, 1);
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ms->cs_change = ms->transfer->cs_change;
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/* Write out the first byte */
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ms->wcol_tx_timestamp = get_tbl();
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if (ms->tx_buf)
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out_8(ms->regs + SPI_DATA, *ms->tx_buf++);
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else
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out_8(ms->regs + SPI_DATA, 0);
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}
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/* Forward declaration of state handlers */
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static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms,
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u8 status, u8 data);
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static int mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms,
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u8 status, u8 data);
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/*
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* IDLE state
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*
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* No transfers are in progress; if another transfer is pending then retrieve
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* it and kick it off. Otherwise, stop processing the state machine
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*/
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static int
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mpc52xx_spi_fsmstate_idle(int irq, struct mpc52xx_spi *ms, u8 status, u8 data)
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{
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struct spi_device *spi;
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int spr, sppr;
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u8 ctrl1;
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if (status && (irq != NO_IRQ))
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dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n",
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status);
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/* Check if there is another transfer waiting. */
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if (list_empty(&ms->queue))
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return FSM_STOP;
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/* get the head of the queue */
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ms->message = list_first_entry(&ms->queue, struct spi_message, queue);
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list_del_init(&ms->message->queue);
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/* Setup the controller parameters */
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ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR;
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spi = ms->message->spi;
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if (spi->mode & SPI_CPHA)
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ctrl1 |= SPI_CTRL1_CPHA;
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if (spi->mode & SPI_CPOL)
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ctrl1 |= SPI_CTRL1_CPOL;
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if (spi->mode & SPI_LSB_FIRST)
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ctrl1 |= SPI_CTRL1_LSBFE;
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out_8(ms->regs + SPI_CTRL1, ctrl1);
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/* Setup the controller speed */
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/* minimum divider is '2'. Also, add '1' to force rounding the
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* divider up. */
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sppr = ((ms->ipb_freq / ms->message->spi->max_speed_hz) + 1) >> 1;
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spr = 0;
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if (sppr < 1)
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sppr = 1;
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while (((sppr - 1) & ~0x7) != 0) {
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sppr = (sppr + 1) >> 1; /* add '1' to force rounding up */
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spr++;
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}
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sppr--; /* sppr quantity in register is offset by 1 */
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if (spr > 7) {
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/* Don't overrun limits of SPI baudrate register */
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spr = 7;
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sppr = 7;
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}
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out_8(ms->regs + SPI_BRR, sppr << 4 | spr); /* Set speed */
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ms->cs_change = 1;
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ms->transfer = container_of(ms->message->transfers.next,
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struct spi_transfer, transfer_list);
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mpc52xx_spi_start_transfer(ms);
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ms->state = mpc52xx_spi_fsmstate_transfer;
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return FSM_CONTINUE;
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}
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/*
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* TRANSFER state
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*
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* In the middle of a transfer. If the SPI core has completed processing
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* a byte, then read out the received data and write out the next byte
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* (unless this transfer is finished; in which case go on to the wait
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* state)
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*/
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static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms,
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u8 status, u8 data)
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{
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if (!status)
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return ms->irq0 ? FSM_STOP : FSM_POLL;
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if (status & SPI_STATUS_WCOL) {
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/* The SPI controller is stoopid. At slower speeds, it may
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* raise the SPIF flag before the state machine is actually
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* finished, which causes a collision (internal to the state
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* machine only). The manual recommends inserting a delay
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* between receiving the interrupt and sending the next byte,
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* but it can also be worked around simply by retrying the
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* transfer which is what we do here. */
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ms->wcol_count++;
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ms->wcol_ticks += get_tbl() - ms->wcol_tx_timestamp;
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ms->wcol_tx_timestamp = get_tbl();
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data = 0;
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if (ms->tx_buf)
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data = *(ms->tx_buf - 1);
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out_8(ms->regs + SPI_DATA, data); /* try again */
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return FSM_CONTINUE;
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} else if (status & SPI_STATUS_MODF) {
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ms->modf_count++;
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dev_err(&ms->master->dev, "mode fault\n");
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mpc52xx_spi_chipsel(ms, 0);
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ms->message->status = -EIO;
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if (ms->message->complete)
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ms->message->complete(ms->message->context);
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ms->state = mpc52xx_spi_fsmstate_idle;
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return FSM_CONTINUE;
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}
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/* Read data out of the spi device */
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ms->byte_count++;
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if (ms->rx_buf)
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*ms->rx_buf++ = data;
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/* Is the transfer complete? */
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ms->len--;
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if (ms->len == 0) {
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ms->timestamp = get_tbl();
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ms->timestamp += ms->transfer->delay_usecs * tb_ticks_per_usec;
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ms->state = mpc52xx_spi_fsmstate_wait;
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return FSM_CONTINUE;
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}
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/* Write out the next byte */
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ms->wcol_tx_timestamp = get_tbl();
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if (ms->tx_buf)
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out_8(ms->regs + SPI_DATA, *ms->tx_buf++);
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else
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out_8(ms->regs + SPI_DATA, 0);
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return FSM_CONTINUE;
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}
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/*
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* WAIT state
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*
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* A transfer has completed; need to wait for the delay period to complete
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* before starting the next transfer
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*/
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static int
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mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms, u8 status, u8 data)
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{
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if (status && irq)
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dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n",
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status);
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if (((int)get_tbl()) - ms->timestamp < 0)
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return FSM_POLL;
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ms->message->actual_length += ms->transfer->len;
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/* Check if there is another transfer in this message. If there
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* aren't then deactivate CS, notify sender, and drop back to idle
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* to start the next message. */
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if (ms->transfer->transfer_list.next == &ms->message->transfers) {
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ms->msg_count++;
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mpc52xx_spi_chipsel(ms, 0);
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ms->message->status = 0;
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if (ms->message->complete)
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ms->message->complete(ms->message->context);
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ms->state = mpc52xx_spi_fsmstate_idle;
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return FSM_CONTINUE;
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||||
}
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|
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/* There is another transfer; kick it off */
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||||
|
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if (ms->cs_change)
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mpc52xx_spi_chipsel(ms, 0);
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ms->transfer = container_of(ms->transfer->transfer_list.next,
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struct spi_transfer, transfer_list);
|
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mpc52xx_spi_start_transfer(ms);
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ms->state = mpc52xx_spi_fsmstate_transfer;
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return FSM_CONTINUE;
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}
|
||||
|
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/**
|
||||
* mpc52xx_spi_fsm_process - Finite State Machine iteration function
|
||||
* @irq: irq number that triggered the FSM or 0 for polling
|
||||
* @ms: pointer to mpc52xx_spi driver data
|
||||
*/
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||||
static void mpc52xx_spi_fsm_process(int irq, struct mpc52xx_spi *ms)
|
||||
{
|
||||
int rc = FSM_CONTINUE;
|
||||
u8 status, data;
|
||||
|
||||
while (rc == FSM_CONTINUE) {
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||||
/* Interrupt cleared by read of STATUS followed by
|
||||
* read of DATA registers */
|
||||
status = in_8(ms->regs + SPI_STATUS);
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||||
data = in_8(ms->regs + SPI_DATA);
|
||||
rc = ms->state(irq, ms, status, data);
|
||||
}
|
||||
|
||||
if (rc == FSM_POLL)
|
||||
schedule_work(&ms->work);
|
||||
}
|
||||
|
||||
/**
|
||||
* mpc52xx_spi_irq - IRQ handler
|
||||
*/
|
||||
static irqreturn_t mpc52xx_spi_irq(int irq, void *_ms)
|
||||
{
|
||||
struct mpc52xx_spi *ms = _ms;
|
||||
spin_lock(&ms->lock);
|
||||
mpc52xx_spi_fsm_process(irq, ms);
|
||||
spin_unlock(&ms->lock);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/**
|
||||
* mpc52xx_spi_wq - Workqueue function for polling the state machine
|
||||
*/
|
||||
static void mpc52xx_spi_wq(struct work_struct *work)
|
||||
{
|
||||
struct mpc52xx_spi *ms = container_of(work, struct mpc52xx_spi, work);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&ms->lock, flags);
|
||||
mpc52xx_spi_fsm_process(0, ms);
|
||||
spin_unlock_irqrestore(&ms->lock, flags);
|
||||
}
|
||||
|
||||
/*
|
||||
* spi_master ops
|
||||
*/
|
||||
|
||||
static int mpc52xx_spi_transfer(struct spi_device *spi, struct spi_message *m)
|
||||
{
|
||||
struct mpc52xx_spi *ms = spi_master_get_devdata(spi->master);
|
||||
unsigned long flags;
|
||||
|
||||
m->actual_length = 0;
|
||||
m->status = -EINPROGRESS;
|
||||
|
||||
spin_lock_irqsave(&ms->lock, flags);
|
||||
list_add_tail(&m->queue, &ms->queue);
|
||||
spin_unlock_irqrestore(&ms->lock, flags);
|
||||
schedule_work(&ms->work);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* OF Platform Bus Binding
|
||||
*/
|
||||
static int mpc52xx_spi_probe(struct platform_device *op)
|
||||
{
|
||||
struct spi_master *master;
|
||||
struct mpc52xx_spi *ms;
|
||||
void __iomem *regs;
|
||||
u8 ctrl1;
|
||||
int rc, i = 0;
|
||||
int gpio_cs;
|
||||
|
||||
/* MMIO registers */
|
||||
dev_dbg(&op->dev, "probing mpc5200 SPI device\n");
|
||||
regs = of_iomap(op->dev.of_node, 0);
|
||||
if (!regs)
|
||||
return -ENODEV;
|
||||
|
||||
/* initialize the device */
|
||||
ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR;
|
||||
out_8(regs + SPI_CTRL1, ctrl1);
|
||||
out_8(regs + SPI_CTRL2, 0x0);
|
||||
out_8(regs + SPI_DATADIR, 0xe); /* Set output pins */
|
||||
out_8(regs + SPI_PORTDATA, 0x8); /* Deassert /SS signal */
|
||||
|
||||
/* Clear the status register and re-read it to check for a MODF
|
||||
* failure. This driver cannot currently handle multiple masters
|
||||
* on the SPI bus. This fault will also occur if the SPI signals
|
||||
* are not connected to any pins (port_config setting) */
|
||||
in_8(regs + SPI_STATUS);
|
||||
out_8(regs + SPI_CTRL1, ctrl1);
|
||||
|
||||
in_8(regs + SPI_DATA);
|
||||
if (in_8(regs + SPI_STATUS) & SPI_STATUS_MODF) {
|
||||
dev_err(&op->dev, "mode fault; is port_config correct?\n");
|
||||
rc = -EIO;
|
||||
goto err_init;
|
||||
}
|
||||
|
||||
dev_dbg(&op->dev, "allocating spi_master struct\n");
|
||||
master = spi_alloc_master(&op->dev, sizeof *ms);
|
||||
if (!master) {
|
||||
rc = -ENOMEM;
|
||||
goto err_alloc;
|
||||
}
|
||||
|
||||
master->transfer = mpc52xx_spi_transfer;
|
||||
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
|
||||
master->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
master->dev.of_node = op->dev.of_node;
|
||||
|
||||
platform_set_drvdata(op, master);
|
||||
|
||||
ms = spi_master_get_devdata(master);
|
||||
ms->master = master;
|
||||
ms->regs = regs;
|
||||
ms->irq0 = irq_of_parse_and_map(op->dev.of_node, 0);
|
||||
ms->irq1 = irq_of_parse_and_map(op->dev.of_node, 1);
|
||||
ms->state = mpc52xx_spi_fsmstate_idle;
|
||||
ms->ipb_freq = mpc5xxx_get_bus_frequency(op->dev.of_node);
|
||||
ms->gpio_cs_count = of_gpio_count(op->dev.of_node);
|
||||
if (ms->gpio_cs_count > 0) {
|
||||
master->num_chipselect = ms->gpio_cs_count;
|
||||
ms->gpio_cs = kmalloc(ms->gpio_cs_count * sizeof(unsigned int),
|
||||
GFP_KERNEL);
|
||||
if (!ms->gpio_cs) {
|
||||
rc = -ENOMEM;
|
||||
goto err_alloc_gpio;
|
||||
}
|
||||
|
||||
for (i = 0; i < ms->gpio_cs_count; i++) {
|
||||
gpio_cs = of_get_gpio(op->dev.of_node, i);
|
||||
if (gpio_cs < 0) {
|
||||
dev_err(&op->dev,
|
||||
"could not parse the gpio field "
|
||||
"in oftree\n");
|
||||
rc = -ENODEV;
|
||||
goto err_gpio;
|
||||
}
|
||||
|
||||
rc = gpio_request(gpio_cs, dev_name(&op->dev));
|
||||
if (rc) {
|
||||
dev_err(&op->dev,
|
||||
"can't request spi cs gpio #%d "
|
||||
"on gpio line %d\n", i, gpio_cs);
|
||||
goto err_gpio;
|
||||
}
|
||||
|
||||
gpio_direction_output(gpio_cs, 1);
|
||||
ms->gpio_cs[i] = gpio_cs;
|
||||
}
|
||||
}
|
||||
|
||||
spin_lock_init(&ms->lock);
|
||||
INIT_LIST_HEAD(&ms->queue);
|
||||
INIT_WORK(&ms->work, mpc52xx_spi_wq);
|
||||
|
||||
/* Decide if interrupts can be used */
|
||||
if (ms->irq0 && ms->irq1) {
|
||||
rc = request_irq(ms->irq0, mpc52xx_spi_irq, 0,
|
||||
"mpc5200-spi-modf", ms);
|
||||
rc |= request_irq(ms->irq1, mpc52xx_spi_irq, 0,
|
||||
"mpc5200-spi-spif", ms);
|
||||
if (rc) {
|
||||
free_irq(ms->irq0, ms);
|
||||
free_irq(ms->irq1, ms);
|
||||
ms->irq0 = ms->irq1 = 0;
|
||||
}
|
||||
} else {
|
||||
/* operate in polled mode */
|
||||
ms->irq0 = ms->irq1 = 0;
|
||||
}
|
||||
|
||||
if (!ms->irq0)
|
||||
dev_info(&op->dev, "using polled mode\n");
|
||||
|
||||
dev_dbg(&op->dev, "registering spi_master struct\n");
|
||||
rc = spi_register_master(master);
|
||||
if (rc)
|
||||
goto err_register;
|
||||
|
||||
dev_info(&ms->master->dev, "registered MPC5200 SPI bus\n");
|
||||
|
||||
return rc;
|
||||
|
||||
err_register:
|
||||
dev_err(&ms->master->dev, "initialization failed\n");
|
||||
err_gpio:
|
||||
while (i-- > 0)
|
||||
gpio_free(ms->gpio_cs[i]);
|
||||
|
||||
kfree(ms->gpio_cs);
|
||||
err_alloc_gpio:
|
||||
spi_master_put(master);
|
||||
err_alloc:
|
||||
err_init:
|
||||
iounmap(regs);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int mpc52xx_spi_remove(struct platform_device *op)
|
||||
{
|
||||
struct spi_master *master = spi_master_get(platform_get_drvdata(op));
|
||||
struct mpc52xx_spi *ms = spi_master_get_devdata(master);
|
||||
int i;
|
||||
|
||||
free_irq(ms->irq0, ms);
|
||||
free_irq(ms->irq1, ms);
|
||||
|
||||
for (i = 0; i < ms->gpio_cs_count; i++)
|
||||
gpio_free(ms->gpio_cs[i]);
|
||||
|
||||
kfree(ms->gpio_cs);
|
||||
spi_unregister_master(master);
|
||||
iounmap(ms->regs);
|
||||
spi_master_put(master);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id mpc52xx_spi_match[] = {
|
||||
{ .compatible = "fsl,mpc5200-spi", },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mpc52xx_spi_match);
|
||||
|
||||
static struct platform_driver mpc52xx_spi_of_driver = {
|
||||
.driver = {
|
||||
.name = "mpc52xx-spi",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = mpc52xx_spi_match,
|
||||
},
|
||||
.probe = mpc52xx_spi_probe,
|
||||
.remove = mpc52xx_spi_remove,
|
||||
};
|
||||
module_platform_driver(mpc52xx_spi_of_driver);
|
||||
Loading…
Add table
Add a link
Reference in a new issue