mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-09 01:28:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
674
drivers/spi/spi-s3c24xx.c
Normal file
674
drivers/spi/spi-s3c24xx.c
Normal file
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@ -0,0 +1,674 @@
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/*
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* Copyright (c) 2006 Ben Dooks
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* Copyright 2006-2009 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/platform_device.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/spi_bitbang.h>
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#include <linux/spi/s3c24xx.h>
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#include <linux/module.h>
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#include <plat/regs-spi.h>
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#include <asm/fiq.h>
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#include "spi-s3c24xx-fiq.h"
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/**
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* s3c24xx_spi_devstate - per device data
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* @hz: Last frequency calculated for @sppre field.
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* @mode: Last mode setting for the @spcon field.
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* @spcon: Value to write to the SPCON register.
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* @sppre: Value to write to the SPPRE register.
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*/
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struct s3c24xx_spi_devstate {
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unsigned int hz;
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unsigned int mode;
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u8 spcon;
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u8 sppre;
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};
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enum spi_fiq_mode {
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FIQ_MODE_NONE = 0,
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FIQ_MODE_TX = 1,
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FIQ_MODE_RX = 2,
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FIQ_MODE_TXRX = 3,
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};
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struct s3c24xx_spi {
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/* bitbang has to be first */
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struct spi_bitbang bitbang;
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struct completion done;
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void __iomem *regs;
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int irq;
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int len;
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int count;
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struct fiq_handler fiq_handler;
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enum spi_fiq_mode fiq_mode;
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unsigned char fiq_inuse;
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unsigned char fiq_claimed;
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void (*set_cs)(struct s3c2410_spi_info *spi,
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int cs, int pol);
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/* data buffers */
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const unsigned char *tx;
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unsigned char *rx;
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struct clk *clk;
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struct spi_master *master;
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struct spi_device *curdev;
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struct device *dev;
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struct s3c2410_spi_info *pdata;
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};
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#define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
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#define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
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static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
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{
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return spi_master_get_devdata(sdev->master);
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}
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static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
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{
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gpio_set_value(spi->pin_cs, pol);
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}
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static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
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{
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struct s3c24xx_spi_devstate *cs = spi->controller_state;
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struct s3c24xx_spi *hw = to_hw(spi);
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unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
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/* change the chipselect state and the state of the spi engine clock */
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switch (value) {
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case BITBANG_CS_INACTIVE:
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hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
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writeb(cs->spcon, hw->regs + S3C2410_SPCON);
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break;
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case BITBANG_CS_ACTIVE:
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writeb(cs->spcon | S3C2410_SPCON_ENSCK,
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hw->regs + S3C2410_SPCON);
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hw->set_cs(hw->pdata, spi->chip_select, cspol);
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break;
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}
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}
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static int s3c24xx_spi_update_state(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct s3c24xx_spi *hw = to_hw(spi);
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struct s3c24xx_spi_devstate *cs = spi->controller_state;
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unsigned int hz;
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unsigned int div;
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unsigned long clk;
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hz = t ? t->speed_hz : spi->max_speed_hz;
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if (!hz)
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hz = spi->max_speed_hz;
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if (spi->mode != cs->mode) {
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u8 spcon = SPCON_DEFAULT | S3C2410_SPCON_ENSCK;
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if (spi->mode & SPI_CPHA)
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spcon |= S3C2410_SPCON_CPHA_FMTB;
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if (spi->mode & SPI_CPOL)
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spcon |= S3C2410_SPCON_CPOL_HIGH;
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cs->mode = spi->mode;
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cs->spcon = spcon;
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}
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if (cs->hz != hz) {
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clk = clk_get_rate(hw->clk);
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div = DIV_ROUND_UP(clk, hz * 2) - 1;
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if (div > 255)
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div = 255;
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dev_dbg(&spi->dev, "pre-scaler=%d (wanted %d, got %ld)\n",
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div, hz, clk / (2 * (div + 1)));
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cs->hz = hz;
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cs->sppre = div;
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}
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return 0;
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}
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static int s3c24xx_spi_setupxfer(struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct s3c24xx_spi_devstate *cs = spi->controller_state;
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struct s3c24xx_spi *hw = to_hw(spi);
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int ret;
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ret = s3c24xx_spi_update_state(spi, t);
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if (!ret)
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writeb(cs->sppre, hw->regs + S3C2410_SPPRE);
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return ret;
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}
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static int s3c24xx_spi_setup(struct spi_device *spi)
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{
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struct s3c24xx_spi_devstate *cs = spi->controller_state;
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struct s3c24xx_spi *hw = to_hw(spi);
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int ret;
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/* allocate settings on the first call */
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if (!cs) {
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cs = devm_kzalloc(&spi->dev,
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sizeof(struct s3c24xx_spi_devstate),
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GFP_KERNEL);
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if (!cs)
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return -ENOMEM;
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cs->spcon = SPCON_DEFAULT;
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cs->hz = -1;
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spi->controller_state = cs;
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}
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/* initialise the state from the device */
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ret = s3c24xx_spi_update_state(spi, NULL);
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if (ret)
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return ret;
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spin_lock(&hw->bitbang.lock);
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if (!hw->bitbang.busy) {
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hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
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/* need to ndelay for 0.5 clocktick ? */
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}
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spin_unlock(&hw->bitbang.lock);
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return 0;
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}
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static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
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{
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return hw->tx ? hw->tx[count] : 0;
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}
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#ifdef CONFIG_SPI_S3C24XX_FIQ
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/* Support for FIQ based pseudo-DMA to improve the transfer speed.
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*
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* This code uses the assembly helper in spi_s3c24xx_spi.S which is
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* used by the FIQ core to move data between main memory and the peripheral
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* block. Since this is code running on the processor, there is no problem
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* with cache coherency of the buffers, so we can use any buffer we like.
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*/
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/**
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* struct spi_fiq_code - FIQ code and header
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* @length: The length of the code fragment, excluding this header.
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* @ack_offset: The offset from @data to the word to place the IRQ ACK bit at.
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* @data: The code itself to install as a FIQ handler.
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*/
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struct spi_fiq_code {
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u32 length;
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u32 ack_offset;
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u8 data[0];
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};
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extern struct spi_fiq_code s3c24xx_spi_fiq_txrx;
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extern struct spi_fiq_code s3c24xx_spi_fiq_tx;
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extern struct spi_fiq_code s3c24xx_spi_fiq_rx;
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/**
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* ack_bit - turn IRQ into IRQ acknowledgement bit
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* @irq: The interrupt number
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*
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* Returns the bit to write to the interrupt acknowledge register.
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*/
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static inline u32 ack_bit(unsigned int irq)
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{
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return 1 << (irq - IRQ_EINT0);
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}
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/**
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* s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
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* @hw: The hardware state.
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*
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* Claim the FIQ handler (only one can be active at any one time) and
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* then setup the correct transfer code for this transfer.
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*
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* This call updates all the necessary state information if successful,
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* so the caller does not need to do anything more than start the transfer
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* as normal, since the IRQ will have been re-routed to the FIQ handler.
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*/
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static void s3c24xx_spi_tryfiq(struct s3c24xx_spi *hw)
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{
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struct pt_regs regs;
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enum spi_fiq_mode mode;
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struct spi_fiq_code *code;
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int ret;
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if (!hw->fiq_claimed) {
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/* try and claim fiq if we haven't got it, and if not
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* then return and simply use another transfer method */
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ret = claim_fiq(&hw->fiq_handler);
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if (ret)
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return;
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}
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if (hw->tx && !hw->rx)
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mode = FIQ_MODE_TX;
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else if (hw->rx && !hw->tx)
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mode = FIQ_MODE_RX;
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else
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mode = FIQ_MODE_TXRX;
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regs.uregs[fiq_rspi] = (long)hw->regs;
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regs.uregs[fiq_rrx] = (long)hw->rx;
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regs.uregs[fiq_rtx] = (long)hw->tx + 1;
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regs.uregs[fiq_rcount] = hw->len - 1;
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regs.uregs[fiq_rirq] = (long)S3C24XX_VA_IRQ;
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set_fiq_regs(®s);
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if (hw->fiq_mode != mode) {
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u32 *ack_ptr;
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hw->fiq_mode = mode;
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switch (mode) {
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case FIQ_MODE_TX:
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code = &s3c24xx_spi_fiq_tx;
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break;
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case FIQ_MODE_RX:
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code = &s3c24xx_spi_fiq_rx;
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break;
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case FIQ_MODE_TXRX:
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code = &s3c24xx_spi_fiq_txrx;
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break;
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default:
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code = NULL;
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}
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BUG_ON(!code);
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ack_ptr = (u32 *)&code->data[code->ack_offset];
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*ack_ptr = ack_bit(hw->irq);
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set_fiq_handler(&code->data, code->length);
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}
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s3c24xx_set_fiq(hw->irq, true);
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hw->fiq_mode = mode;
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hw->fiq_inuse = 1;
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}
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|
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/**
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* s3c24xx_spi_fiqop - FIQ core code callback
|
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* @pw: Data registered with the handler
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* @release: Whether this is a release or a return.
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||||
*
|
||||
* Called by the FIQ code when another module wants to use the FIQ, so
|
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* return whether we are currently using this or not and then update our
|
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* internal state.
|
||||
*/
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static int s3c24xx_spi_fiqop(void *pw, int release)
|
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{
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struct s3c24xx_spi *hw = pw;
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int ret = 0;
|
||||
|
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if (release) {
|
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if (hw->fiq_inuse)
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ret = -EBUSY;
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||||
|
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/* note, we do not need to unroute the FIQ, as the FIQ
|
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* vector code de-routes it to signal the end of transfer */
|
||||
|
||||
hw->fiq_mode = FIQ_MODE_NONE;
|
||||
hw->fiq_claimed = 0;
|
||||
} else {
|
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hw->fiq_claimed = 1;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* s3c24xx_spi_initfiq - setup the information for the FIQ core
|
||||
* @hw: The hardware state.
|
||||
*
|
||||
* Setup the fiq_handler block to pass to the FIQ core.
|
||||
*/
|
||||
static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *hw)
|
||||
{
|
||||
hw->fiq_handler.dev_id = hw;
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hw->fiq_handler.name = dev_name(hw->dev);
|
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hw->fiq_handler.fiq_op = s3c24xx_spi_fiqop;
|
||||
}
|
||||
|
||||
/**
|
||||
* s3c24xx_spi_usefiq - return if we should be using FIQ.
|
||||
* @hw: The hardware state.
|
||||
*
|
||||
* Return true if the platform data specifies whether this channel is
|
||||
* allowed to use the FIQ.
|
||||
*/
|
||||
static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *hw)
|
||||
{
|
||||
return hw->pdata->use_fiq;
|
||||
}
|
||||
|
||||
/**
|
||||
* s3c24xx_spi_usingfiq - return if channel is using FIQ
|
||||
* @spi: The hardware state.
|
||||
*
|
||||
* Return whether the channel is currently using the FIQ (separate from
|
||||
* whether the FIQ is claimed).
|
||||
*/
|
||||
static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *spi)
|
||||
{
|
||||
return spi->fiq_inuse;
|
||||
}
|
||||
#else
|
||||
|
||||
static inline void s3c24xx_spi_initfiq(struct s3c24xx_spi *s) { }
|
||||
static inline void s3c24xx_spi_tryfiq(struct s3c24xx_spi *s) { }
|
||||
static inline bool s3c24xx_spi_usefiq(struct s3c24xx_spi *s) { return false; }
|
||||
static inline bool s3c24xx_spi_usingfiq(struct s3c24xx_spi *s) { return false; }
|
||||
|
||||
#endif /* CONFIG_SPI_S3C24XX_FIQ */
|
||||
|
||||
static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
|
||||
{
|
||||
struct s3c24xx_spi *hw = to_hw(spi);
|
||||
|
||||
hw->tx = t->tx_buf;
|
||||
hw->rx = t->rx_buf;
|
||||
hw->len = t->len;
|
||||
hw->count = 0;
|
||||
|
||||
init_completion(&hw->done);
|
||||
|
||||
hw->fiq_inuse = 0;
|
||||
if (s3c24xx_spi_usefiq(hw) && t->len >= 3)
|
||||
s3c24xx_spi_tryfiq(hw);
|
||||
|
||||
/* send the first byte */
|
||||
writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
|
||||
|
||||
wait_for_completion(&hw->done);
|
||||
return hw->count;
|
||||
}
|
||||
|
||||
static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
|
||||
{
|
||||
struct s3c24xx_spi *hw = dev;
|
||||
unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
|
||||
unsigned int count = hw->count;
|
||||
|
||||
if (spsta & S3C2410_SPSTA_DCOL) {
|
||||
dev_dbg(hw->dev, "data-collision\n");
|
||||
complete(&hw->done);
|
||||
goto irq_done;
|
||||
}
|
||||
|
||||
if (!(spsta & S3C2410_SPSTA_READY)) {
|
||||
dev_dbg(hw->dev, "spi not ready for tx?\n");
|
||||
complete(&hw->done);
|
||||
goto irq_done;
|
||||
}
|
||||
|
||||
if (!s3c24xx_spi_usingfiq(hw)) {
|
||||
hw->count++;
|
||||
|
||||
if (hw->rx)
|
||||
hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
|
||||
|
||||
count++;
|
||||
|
||||
if (count < hw->len)
|
||||
writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
|
||||
else
|
||||
complete(&hw->done);
|
||||
} else {
|
||||
hw->count = hw->len;
|
||||
hw->fiq_inuse = 0;
|
||||
|
||||
if (hw->rx)
|
||||
hw->rx[hw->len-1] = readb(hw->regs + S3C2410_SPRDAT);
|
||||
|
||||
complete(&hw->done);
|
||||
}
|
||||
|
||||
irq_done:
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
|
||||
{
|
||||
/* for the moment, permanently enable the clock */
|
||||
|
||||
clk_enable(hw->clk);
|
||||
|
||||
/* program defaults into the registers */
|
||||
|
||||
writeb(0xff, hw->regs + S3C2410_SPPRE);
|
||||
writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
|
||||
writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
|
||||
|
||||
if (hw->pdata) {
|
||||
if (hw->set_cs == s3c24xx_spi_gpiocs)
|
||||
gpio_direction_output(hw->pdata->pin_cs, 1);
|
||||
|
||||
if (hw->pdata->gpio_setup)
|
||||
hw->pdata->gpio_setup(hw->pdata, 1);
|
||||
}
|
||||
}
|
||||
|
||||
static int s3c24xx_spi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct s3c2410_spi_info *pdata;
|
||||
struct s3c24xx_spi *hw;
|
||||
struct spi_master *master;
|
||||
struct resource *res;
|
||||
int err = 0;
|
||||
|
||||
master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
|
||||
if (master == NULL) {
|
||||
dev_err(&pdev->dev, "No memory for spi_master\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
hw = spi_master_get_devdata(master);
|
||||
memset(hw, 0, sizeof(struct s3c24xx_spi));
|
||||
|
||||
hw->master = master;
|
||||
hw->pdata = pdata = dev_get_platdata(&pdev->dev);
|
||||
hw->dev = &pdev->dev;
|
||||
|
||||
if (pdata == NULL) {
|
||||
dev_err(&pdev->dev, "No platform data supplied\n");
|
||||
err = -ENOENT;
|
||||
goto err_no_pdata;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, hw);
|
||||
init_completion(&hw->done);
|
||||
|
||||
/* initialise fiq handler */
|
||||
|
||||
s3c24xx_spi_initfiq(hw);
|
||||
|
||||
/* setup the master state. */
|
||||
|
||||
/* the spi->mode bits understood by this driver: */
|
||||
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
|
||||
|
||||
master->num_chipselect = hw->pdata->num_cs;
|
||||
master->bus_num = pdata->bus_num;
|
||||
master->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
|
||||
/* setup the state for the bitbang driver */
|
||||
|
||||
hw->bitbang.master = hw->master;
|
||||
hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
|
||||
hw->bitbang.chipselect = s3c24xx_spi_chipsel;
|
||||
hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
|
||||
|
||||
hw->master->setup = s3c24xx_spi_setup;
|
||||
|
||||
dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
|
||||
|
||||
/* find and map our resources */
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
hw->regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(hw->regs)) {
|
||||
err = PTR_ERR(hw->regs);
|
||||
goto err_no_pdata;
|
||||
}
|
||||
|
||||
hw->irq = platform_get_irq(pdev, 0);
|
||||
if (hw->irq < 0) {
|
||||
dev_err(&pdev->dev, "No IRQ specified\n");
|
||||
err = -ENOENT;
|
||||
goto err_no_pdata;
|
||||
}
|
||||
|
||||
err = devm_request_irq(&pdev->dev, hw->irq, s3c24xx_spi_irq, 0,
|
||||
pdev->name, hw);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "Cannot claim IRQ\n");
|
||||
goto err_no_pdata;
|
||||
}
|
||||
|
||||
hw->clk = devm_clk_get(&pdev->dev, "spi");
|
||||
if (IS_ERR(hw->clk)) {
|
||||
dev_err(&pdev->dev, "No clock for device\n");
|
||||
err = PTR_ERR(hw->clk);
|
||||
goto err_no_pdata;
|
||||
}
|
||||
|
||||
/* setup any gpio we can */
|
||||
|
||||
if (!pdata->set_cs) {
|
||||
if (pdata->pin_cs < 0) {
|
||||
dev_err(&pdev->dev, "No chipselect pin\n");
|
||||
err = -EINVAL;
|
||||
goto err_register;
|
||||
}
|
||||
|
||||
err = devm_gpio_request(&pdev->dev, pdata->pin_cs,
|
||||
dev_name(&pdev->dev));
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "Failed to get gpio for cs\n");
|
||||
goto err_register;
|
||||
}
|
||||
|
||||
hw->set_cs = s3c24xx_spi_gpiocs;
|
||||
gpio_direction_output(pdata->pin_cs, 1);
|
||||
} else
|
||||
hw->set_cs = pdata->set_cs;
|
||||
|
||||
s3c24xx_spi_initialsetup(hw);
|
||||
|
||||
/* register our spi controller */
|
||||
|
||||
err = spi_bitbang_start(&hw->bitbang);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "Failed to register SPI master\n");
|
||||
goto err_register;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_register:
|
||||
clk_disable(hw->clk);
|
||||
|
||||
err_no_pdata:
|
||||
spi_master_put(hw->master);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int s3c24xx_spi_remove(struct platform_device *dev)
|
||||
{
|
||||
struct s3c24xx_spi *hw = platform_get_drvdata(dev);
|
||||
|
||||
spi_bitbang_stop(&hw->bitbang);
|
||||
clk_disable(hw->clk);
|
||||
spi_master_put(hw->master);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
||||
static int s3c24xx_spi_suspend(struct device *dev)
|
||||
{
|
||||
struct s3c24xx_spi *hw = dev_get_drvdata(dev);
|
||||
int ret;
|
||||
|
||||
ret = spi_master_suspend(hw->master);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (hw->pdata && hw->pdata->gpio_setup)
|
||||
hw->pdata->gpio_setup(hw->pdata, 0);
|
||||
|
||||
clk_disable(hw->clk);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int s3c24xx_spi_resume(struct device *dev)
|
||||
{
|
||||
struct s3c24xx_spi *hw = dev_get_drvdata(dev);
|
||||
|
||||
s3c24xx_spi_initialsetup(hw);
|
||||
return spi_master_resume(hw->master);
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops s3c24xx_spi_pmops = {
|
||||
.suspend = s3c24xx_spi_suspend,
|
||||
.resume = s3c24xx_spi_resume,
|
||||
};
|
||||
|
||||
#define S3C24XX_SPI_PMOPS &s3c24xx_spi_pmops
|
||||
#else
|
||||
#define S3C24XX_SPI_PMOPS NULL
|
||||
#endif /* CONFIG_PM */
|
||||
|
||||
MODULE_ALIAS("platform:s3c2410-spi");
|
||||
static struct platform_driver s3c24xx_spi_driver = {
|
||||
.probe = s3c24xx_spi_probe,
|
||||
.remove = s3c24xx_spi_remove,
|
||||
.driver = {
|
||||
.name = "s3c2410-spi",
|
||||
.owner = THIS_MODULE,
|
||||
.pm = S3C24XX_SPI_PMOPS,
|
||||
},
|
||||
};
|
||||
module_platform_driver(s3c24xx_spi_driver);
|
||||
|
||||
MODULE_DESCRIPTION("S3C24XX SPI Driver");
|
||||
MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Add table
Add a link
Reference in a new issue