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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
commit f6dfaef42e
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60
drivers/thermal/ti-soc-thermal/Kconfig Normal file
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config TI_SOC_THERMAL
tristate "Texas Instruments SoCs temperature sensor driver"
depends on THERMAL
depends on ARCH_HAS_BANDGAP
help
If you say yes here you get support for the Texas Instruments
OMAP4460+ on die bandgap temperature sensor support. The register
set is part of system control module.
This includes alert interrupts generation and also the TSHUT
support.
config TI_THERMAL
bool "Texas Instruments SoCs thermal framework support"
depends on TI_SOC_THERMAL
depends on CPU_THERMAL
help
If you say yes here you want to get support for generic thermal
framework for the Texas Instruments on die bandgap temperature sensor.
This includes trip points definitions, extrapolation rules and
CPU cooling device bindings.
config OMAP4_THERMAL
bool "Texas Instruments OMAP4 thermal support"
depends on TI_SOC_THERMAL
depends on ARCH_OMAP4
help
If you say yes here you get thermal support for the Texas Instruments
OMAP4 SoC family. The current chip supported are:
- OMAP4430
- OMAP4460
- OMAP4470
This includes alert interrupts generation and also the TSHUT
support.
config OMAP5_THERMAL
bool "Texas Instruments OMAP5 thermal support"
depends on TI_SOC_THERMAL
depends on SOC_OMAP5
help
If you say yes here you get thermal support for the Texas Instruments
OMAP5 SoC family. The current chip supported are:
- OMAP5430
This includes alert interrupts generation and also the TSHUT
support.
config DRA752_THERMAL
bool "Texas Instruments DRA752 thermal support"
depends on TI_SOC_THERMAL
depends on SOC_DRA7XX
help
If you say yes here you get thermal support for the Texas Instruments
DRA752 SoC family. The current chip supported are:
- DRA752
This includes alert interrupts generation and also the TSHUT
support.

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drivers/thermal/ti-soc-thermal/Makefile Normal file
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obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-thermal.o
ti-soc-thermal-y := ti-bandgap.o
ti-soc-thermal-$(CONFIG_TI_THERMAL) += ti-thermal-common.o
ti-soc-thermal-$(CONFIG_DRA752_THERMAL) += dra752-thermal-data.o
ti-soc-thermal-$(CONFIG_OMAP4_THERMAL) += omap4-thermal-data.o
ti-soc-thermal-$(CONFIG_OMAP5_THERMAL) += omap5-thermal-data.o

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drivers/thermal/ti-soc-thermal/TODO Normal file
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List of TODOs (by Eduardo Valentin)
on ti-bandgap.c:
- Revisit PM support
on ti-thermal-common.c/ti-thermal.h:
- Revisit need for locking
generally:
- make sure this code works on OMAP4430, OMAP4460 and OMAP5430
Copy patches to Eduardo Valentin <eduardo.valentin@ti.com>

280
drivers/thermal/ti-soc-thermal/dra752-bandgap.h Normal file
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/*
* DRA752 bandgap registers, bitfields and temperature definitions
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
* Contact:
* Eduardo Valentin <eduardo.valentin@ti.com>
* Tero Kristo <t-kristo@ti.com>
*
* This is an auto generated file.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#ifndef __DRA752_BANDGAP_H
#define __DRA752_BANDGAP_H
/**
* *** DRA752 ***
*
* Below, in sequence, are the Register definitions,
* the bitfields and the temperature definitions for DRA752.
*/
/**
* DRA752 register definitions
*
* Registers are defined as offsets. The offsets are
* relative to FUSE_OPP_BGAP_GPU on DRA752.
* DRA752_BANDGAP_BASE 0x4a0021e0
*
* Register below are grouped by domain (not necessarily in offset order)
*/
/* DRA752.common register offsets */
#define DRA752_BANDGAP_CTRL_1_OFFSET 0x1a0
#define DRA752_BANDGAP_STATUS_1_OFFSET 0x1c8
#define DRA752_BANDGAP_CTRL_2_OFFSET 0x39c
#define DRA752_BANDGAP_STATUS_2_OFFSET 0x3b8
/* DRA752.core register offsets */
#define DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET 0x8
#define DRA752_TEMP_SENSOR_CORE_OFFSET 0x154
#define DRA752_BANDGAP_THRESHOLD_CORE_OFFSET 0x1ac
#define DRA752_BANDGAP_TSHUT_CORE_OFFSET 0x1b8
#define DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET 0x1c4
#define DRA752_DTEMP_CORE_0_OFFSET 0x208
#define DRA752_DTEMP_CORE_1_OFFSET 0x20c
#define DRA752_DTEMP_CORE_2_OFFSET 0x210
#define DRA752_DTEMP_CORE_3_OFFSET 0x214
#define DRA752_DTEMP_CORE_4_OFFSET 0x218
/* DRA752.iva register offsets */
#define DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET 0x388
#define DRA752_TEMP_SENSOR_IVA_OFFSET 0x398
#define DRA752_BANDGAP_THRESHOLD_IVA_OFFSET 0x3a4
#define DRA752_BANDGAP_TSHUT_IVA_OFFSET 0x3ac
#define DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET 0x3b4
#define DRA752_DTEMP_IVA_0_OFFSET 0x3d0
#define DRA752_DTEMP_IVA_1_OFFSET 0x3d4
#define DRA752_DTEMP_IVA_2_OFFSET 0x3d8
#define DRA752_DTEMP_IVA_3_OFFSET 0x3dc
#define DRA752_DTEMP_IVA_4_OFFSET 0x3e0
/* DRA752.mpu register offsets */
#define DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET 0x4
#define DRA752_TEMP_SENSOR_MPU_OFFSET 0x14c
#define DRA752_BANDGAP_THRESHOLD_MPU_OFFSET 0x1a4
#define DRA752_BANDGAP_TSHUT_MPU_OFFSET 0x1b0
#define DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET 0x1bc
#define DRA752_DTEMP_MPU_0_OFFSET 0x1e0
#define DRA752_DTEMP_MPU_1_OFFSET 0x1e4
#define DRA752_DTEMP_MPU_2_OFFSET 0x1e8
#define DRA752_DTEMP_MPU_3_OFFSET 0x1ec
#define DRA752_DTEMP_MPU_4_OFFSET 0x1f0
/* DRA752.dspeve register offsets */
#define DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET 0x384
#define DRA752_TEMP_SENSOR_DSPEVE_OFFSET 0x394
#define DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET 0x3a0
#define DRA752_BANDGAP_TSHUT_DSPEVE_OFFSET 0x3a8
#define DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET 0x3b0
#define DRA752_DTEMP_DSPEVE_0_OFFSET 0x3bc
#define DRA752_DTEMP_DSPEVE_1_OFFSET 0x3c0
#define DRA752_DTEMP_DSPEVE_2_OFFSET 0x3c4
#define DRA752_DTEMP_DSPEVE_3_OFFSET 0x3c8
#define DRA752_DTEMP_DSPEVE_4_OFFSET 0x3cc
/* DRA752.gpu register offsets */
#define DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET 0x0
#define DRA752_TEMP_SENSOR_GPU_OFFSET 0x150
#define DRA752_BANDGAP_THRESHOLD_GPU_OFFSET 0x1a8
#define DRA752_BANDGAP_TSHUT_GPU_OFFSET 0x1b4
#define DRA752_BANDGAP_CUMUL_DTEMP_GPU_OFFSET 0x1c0
#define DRA752_DTEMP_GPU_0_OFFSET 0x1f4
#define DRA752_DTEMP_GPU_1_OFFSET 0x1f8
#define DRA752_DTEMP_GPU_2_OFFSET 0x1fc
#define DRA752_DTEMP_GPU_3_OFFSET 0x200
#define DRA752_DTEMP_GPU_4_OFFSET 0x204
/**
* Register bitfields for DRA752
*
* All the macros bellow define the required bits for
* controlling temperature on DRA752. Bit defines are
* grouped by register.
*/
/* DRA752.BANDGAP_STATUS_1 */
#define DRA752_BANDGAP_STATUS_1_ALERT_MASK BIT(31)
#define DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK BIT(5)
#define DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK BIT(4)
#define DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK BIT(3)
#define DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK BIT(2)
#define DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK BIT(1)
#define DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK BIT(0)
/* DRA752.BANDGAP_CTRL_2 */
#define DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK BIT(22)
#define DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK BIT(21)
#define DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK BIT(19)
#define DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK BIT(18)
#define DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK BIT(16)
#define DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK BIT(15)
#define DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK BIT(3)
#define DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK BIT(2)
#define DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK BIT(1)
#define DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK BIT(0)
/* DRA752.BANDGAP_STATUS_2 */
#define DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK BIT(3)
#define DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK BIT(2)
#define DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK BIT(1)
#define DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK BIT(0)
/* DRA752.BANDGAP_CTRL_1 */
#define DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK (0x3 << 30)
#define DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK (0x7 << 27)
#define DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK BIT(23)
#define DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK BIT(22)
#define DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK BIT(21)
#define DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK BIT(20)
#define DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK BIT(19)
#define DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK BIT(18)
#define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK BIT(17)
#define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK BIT(16)
#define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK BIT(15)
#define DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK BIT(5)
#define DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK BIT(4)
#define DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK BIT(3)
#define DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK BIT(2)
#define DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK BIT(1)
#define DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK BIT(0)
/* DRA752.TEMP_SENSOR */
#define DRA752_TEMP_SENSOR_TMPSOFF_MASK BIT(11)
#define DRA752_TEMP_SENSOR_EOCZ_MASK BIT(10)
#define DRA752_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0)
/* DRA752.BANDGAP_THRESHOLD */
#define DRA752_BANDGAP_THRESHOLD_HOT_MASK (0x3ff << 16)
#define DRA752_BANDGAP_THRESHOLD_COLD_MASK (0x3ff << 0)
/* DRA752.TSHUT_THRESHOLD */
#define DRA752_TSHUT_THRESHOLD_MUXCTRL_MASK BIT(31)
#define DRA752_TSHUT_THRESHOLD_HOT_MASK (0x3ff << 16)
#define DRA752_TSHUT_THRESHOLD_COLD_MASK (0x3ff << 0)
/* DRA752.BANDGAP_CUMUL_DTEMP_CORE */
#define DRA752_BANDGAP_CUMUL_DTEMP_CORE_MASK (0xffffffff << 0)
/* DRA752.BANDGAP_CUMUL_DTEMP_IVA */
#define DRA752_BANDGAP_CUMUL_DTEMP_IVA_MASK (0xffffffff << 0)
/* DRA752.BANDGAP_CUMUL_DTEMP_MPU */
#define DRA752_BANDGAP_CUMUL_DTEMP_MPU_MASK (0xffffffff << 0)
/* DRA752.BANDGAP_CUMUL_DTEMP_DSPEVE */
#define DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_MASK (0xffffffff << 0)
/* DRA752.BANDGAP_CUMUL_DTEMP_GPU */
#define DRA752_BANDGAP_CUMUL_DTEMP_GPU_MASK (0xffffffff << 0)
/**
* Temperature limits and thresholds for DRA752
*
* All the macros bellow are definitions for handling the
* ADC conversions and representation of temperature limits
* and thresholds for DRA752. Definitions are grouped
* by temperature domain.
*/
/* DRA752.common temperature definitions */
/* ADC conversion table limits */
#define DRA752_ADC_START_VALUE 540
#define DRA752_ADC_END_VALUE 945
/* DRA752.GPU temperature definitions */
/* bandgap clock limits */
#define DRA752_GPU_MAX_FREQ 1500000
#define DRA752_GPU_MIN_FREQ 1000000
/* sensor limits */
#define DRA752_GPU_MIN_TEMP -40000
#define DRA752_GPU_MAX_TEMP 125000
#define DRA752_GPU_HYST_VAL 5000
/* interrupts thresholds */
#define DRA752_GPU_TSHUT_HOT 915
#define DRA752_GPU_TSHUT_COLD 900
#define DRA752_GPU_T_HOT 800
#define DRA752_GPU_T_COLD 795
/* DRA752.MPU temperature definitions */
/* bandgap clock limits */
#define DRA752_MPU_MAX_FREQ 1500000
#define DRA752_MPU_MIN_FREQ 1000000
/* sensor limits */
#define DRA752_MPU_MIN_TEMP -40000
#define DRA752_MPU_MAX_TEMP 125000
#define DRA752_MPU_HYST_VAL 5000
/* interrupts thresholds */
#define DRA752_MPU_TSHUT_HOT 915
#define DRA752_MPU_TSHUT_COLD 900
#define DRA752_MPU_T_HOT 800
#define DRA752_MPU_T_COLD 795
/* DRA752.CORE temperature definitions */
/* bandgap clock limits */
#define DRA752_CORE_MAX_FREQ 1500000
#define DRA752_CORE_MIN_FREQ 1000000
/* sensor limits */
#define DRA752_CORE_MIN_TEMP -40000
#define DRA752_CORE_MAX_TEMP 125000
#define DRA752_CORE_HYST_VAL 5000
/* interrupts thresholds */
#define DRA752_CORE_TSHUT_HOT 915
#define DRA752_CORE_TSHUT_COLD 900
#define DRA752_CORE_T_HOT 800
#define DRA752_CORE_T_COLD 795
/* DRA752.DSPEVE temperature definitions */
/* bandgap clock limits */
#define DRA752_DSPEVE_MAX_FREQ 1500000
#define DRA752_DSPEVE_MIN_FREQ 1000000
/* sensor limits */
#define DRA752_DSPEVE_MIN_TEMP -40000
#define DRA752_DSPEVE_MAX_TEMP 125000
#define DRA752_DSPEVE_HYST_VAL 5000
/* interrupts thresholds */
#define DRA752_DSPEVE_TSHUT_HOT 915
#define DRA752_DSPEVE_TSHUT_COLD 900
#define DRA752_DSPEVE_T_HOT 800
#define DRA752_DSPEVE_T_COLD 795
/* DRA752.IVA temperature definitions */
/* bandgap clock limits */
#define DRA752_IVA_MAX_FREQ 1500000
#define DRA752_IVA_MIN_FREQ 1000000
/* sensor limits */
#define DRA752_IVA_MIN_TEMP -40000
#define DRA752_IVA_MAX_TEMP 125000
#define DRA752_IVA_HYST_VAL 5000
/* interrupts thresholds */
#define DRA752_IVA_TSHUT_HOT 915
#define DRA752_IVA_TSHUT_COLD 900
#define DRA752_IVA_T_HOT 800
#define DRA752_IVA_T_COLD 795
#endif /* __DRA752_BANDGAP_H */

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drivers/thermal/ti-soc-thermal/dra752-thermal-data.c Normal file
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/*
* DRA752 thermal data.
*
* Copyright (C) 2013 Texas Instruments Inc.
* Contact:
* Eduardo Valentin <eduardo.valentin@ti.com>
* Tero Kristo <t-kristo@ti.com>
*
* This file is partially autogenerated.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include "ti-thermal.h"
#include "ti-bandgap.h"
#include "dra752-bandgap.h"
/*
* DRA752 has five instances of thermal sensor: MPU, GPU, CORE,
* IVA and DSPEVE need to describe the individual registers and
* bit fields.
*/
/*
* DRA752 CORE thermal sensor register offsets and bit-fields
*/
static struct temp_sensor_registers
dra752_core_temp_sensor_registers = {
.temp_sensor_ctrl = DRA752_TEMP_SENSOR_CORE_OFFSET,
.bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
.bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
.bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
.mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK,
.mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK,
.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
.mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK,
.mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK,
.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK,
.bgap_threshold = DRA752_BANDGAP_THRESHOLD_CORE_OFFSET,
.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
.tshut_threshold = DRA752_BANDGAP_TSHUT_CORE_OFFSET,
.tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
.tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
.bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
.status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK,
.status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK,
.bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET,
.ctrl_dtemp_0 = DRA752_DTEMP_CORE_0_OFFSET,
.ctrl_dtemp_1 = DRA752_DTEMP_CORE_1_OFFSET,
.ctrl_dtemp_2 = DRA752_DTEMP_CORE_2_OFFSET,
.ctrl_dtemp_3 = DRA752_DTEMP_CORE_3_OFFSET,
.ctrl_dtemp_4 = DRA752_DTEMP_CORE_4_OFFSET,
.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET,
};
/*
* DRA752 IVA thermal sensor register offsets and bit-fields
*/
static struct temp_sensor_registers
dra752_iva_temp_sensor_registers = {
.temp_sensor_ctrl = DRA752_TEMP_SENSOR_IVA_OFFSET,
.bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
.bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
.bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
.mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK,
.mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK,
.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
.mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK,
.mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK,
.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK,
.bgap_threshold = DRA752_BANDGAP_THRESHOLD_IVA_OFFSET,
.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
.tshut_threshold = DRA752_BANDGAP_TSHUT_IVA_OFFSET,
.tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
.tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
.bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
.status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK,
.status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK,
.bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET,
.ctrl_dtemp_0 = DRA752_DTEMP_IVA_0_OFFSET,
.ctrl_dtemp_1 = DRA752_DTEMP_IVA_1_OFFSET,
.ctrl_dtemp_2 = DRA752_DTEMP_IVA_2_OFFSET,
.ctrl_dtemp_3 = DRA752_DTEMP_IVA_3_OFFSET,
.ctrl_dtemp_4 = DRA752_DTEMP_IVA_4_OFFSET,
.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET,
};
/*
* DRA752 MPU thermal sensor register offsets and bit-fields
*/
static struct temp_sensor_registers
dra752_mpu_temp_sensor_registers = {
.temp_sensor_ctrl = DRA752_TEMP_SENSOR_MPU_OFFSET,
.bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
.bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
.bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
.mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK,
.mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK,
.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
.mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK,
.mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK,
.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK,
.bgap_threshold = DRA752_BANDGAP_THRESHOLD_MPU_OFFSET,
.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
.tshut_threshold = DRA752_BANDGAP_TSHUT_MPU_OFFSET,
.tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
.tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
.bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
.status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK,
.status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK,
.bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET,
.ctrl_dtemp_0 = DRA752_DTEMP_MPU_0_OFFSET,
.ctrl_dtemp_1 = DRA752_DTEMP_MPU_1_OFFSET,
.ctrl_dtemp_2 = DRA752_DTEMP_MPU_2_OFFSET,
.ctrl_dtemp_3 = DRA752_DTEMP_MPU_3_OFFSET,
.ctrl_dtemp_4 = DRA752_DTEMP_MPU_4_OFFSET,
.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET,
};
/*
* DRA752 DSPEVE thermal sensor register offsets and bit-fields
*/
static struct temp_sensor_registers
dra752_dspeve_temp_sensor_registers = {
.temp_sensor_ctrl = DRA752_TEMP_SENSOR_DSPEVE_OFFSET,
.bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
.bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
.bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
.mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK,
.mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK,
.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
.mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK,
.mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK,
.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK,
.bgap_threshold = DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET,
.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
.tshut_threshold = DRA752_BANDGAP_TSHUT_DSPEVE_OFFSET,
.tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
.tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
.bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
.status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK,
.status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK,
.bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET,
.ctrl_dtemp_0 = DRA752_DTEMP_DSPEVE_0_OFFSET,
.ctrl_dtemp_1 = DRA752_DTEMP_DSPEVE_1_OFFSET,
.ctrl_dtemp_2 = DRA752_DTEMP_DSPEVE_2_OFFSET,
.ctrl_dtemp_3 = DRA752_DTEMP_DSPEVE_3_OFFSET,
.ctrl_dtemp_4 = DRA752_DTEMP_DSPEVE_4_OFFSET,
.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET,
};
/*
* DRA752 GPU thermal sensor register offsets and bit-fields
*/
static struct temp_sensor_registers
dra752_gpu_temp_sensor_registers = {
.temp_sensor_ctrl = DRA752_TEMP_SENSOR_GPU_OFFSET,
.bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
.bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
.bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
.bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
.mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK,
.mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK,
.mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
.mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK,
.mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK,
.mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK,
.mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK,
.bgap_threshold = DRA752_BANDGAP_THRESHOLD_GPU_OFFSET,
.threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
.threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
.tshut_threshold = DRA752_BANDGAP_TSHUT_GPU_OFFSET,
.tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
.tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
.bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
.status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
.status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK,
.status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK,
.bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_GPU_OFFSET,
.ctrl_dtemp_0 = DRA752_DTEMP_GPU_0_OFFSET,
.ctrl_dtemp_1 = DRA752_DTEMP_GPU_1_OFFSET,
.ctrl_dtemp_2 = DRA752_DTEMP_GPU_2_OFFSET,
.ctrl_dtemp_3 = DRA752_DTEMP_GPU_3_OFFSET,
.ctrl_dtemp_4 = DRA752_DTEMP_GPU_4_OFFSET,
.bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET,
};
/* Thresholds and limits for DRA752 MPU temperature sensor */
static struct temp_sensor_data dra752_mpu_temp_sensor_data = {
.tshut_hot = DRA752_MPU_TSHUT_HOT,
.tshut_cold = DRA752_MPU_TSHUT_COLD,
.t_hot = DRA752_MPU_T_HOT,
.t_cold = DRA752_MPU_T_COLD,
.min_freq = DRA752_MPU_MIN_FREQ,
.max_freq = DRA752_MPU_MAX_FREQ,
.max_temp = DRA752_MPU_MAX_TEMP,
.min_temp = DRA752_MPU_MIN_TEMP,
.hyst_val = DRA752_MPU_HYST_VAL,
.update_int1 = 1000,
.update_int2 = 2000,
};
/* Thresholds and limits for DRA752 GPU temperature sensor */
static struct temp_sensor_data dra752_gpu_temp_sensor_data = {
.tshut_hot = DRA752_GPU_TSHUT_HOT,
.tshut_cold = DRA752_GPU_TSHUT_COLD,
.t_hot = DRA752_GPU_T_HOT,
.t_cold = DRA752_GPU_T_COLD,
.min_freq = DRA752_GPU_MIN_FREQ,
.max_freq = DRA752_GPU_MAX_FREQ,
.max_temp = DRA752_GPU_MAX_TEMP,
.min_temp = DRA752_GPU_MIN_TEMP,
.hyst_val = DRA752_GPU_HYST_VAL,
.update_int1 = 1000,
.update_int2 = 2000,
};
/* Thresholds and limits for DRA752 CORE temperature sensor */
static struct temp_sensor_data dra752_core_temp_sensor_data = {
.tshut_hot = DRA752_CORE_TSHUT_HOT,
.tshut_cold = DRA752_CORE_TSHUT_COLD,
.t_hot = DRA752_CORE_T_HOT,
.t_cold = DRA752_CORE_T_COLD,
.min_freq = DRA752_CORE_MIN_FREQ,
.max_freq = DRA752_CORE_MAX_FREQ,
.max_temp = DRA752_CORE_MAX_TEMP,
.min_temp = DRA752_CORE_MIN_TEMP,
.hyst_val = DRA752_CORE_HYST_VAL,
.update_int1 = 1000,
.update_int2 = 2000,
};
/* Thresholds and limits for DRA752 DSPEVE temperature sensor */
static struct temp_sensor_data dra752_dspeve_temp_sensor_data = {
.tshut_hot = DRA752_DSPEVE_TSHUT_HOT,
.tshut_cold = DRA752_DSPEVE_TSHUT_COLD,
.t_hot = DRA752_DSPEVE_T_HOT,
.t_cold = DRA752_DSPEVE_T_COLD,
.min_freq = DRA752_DSPEVE_MIN_FREQ,
.max_freq = DRA752_DSPEVE_MAX_FREQ,
.max_temp = DRA752_DSPEVE_MAX_TEMP,
.min_temp = DRA752_DSPEVE_MIN_TEMP,
.hyst_val = DRA752_DSPEVE_HYST_VAL,
.update_int1 = 1000,
.update_int2 = 2000,
};
/* Thresholds and limits for DRA752 IVA temperature sensor */
static struct temp_sensor_data dra752_iva_temp_sensor_data = {
.tshut_hot = DRA752_IVA_TSHUT_HOT,
.tshut_cold = DRA752_IVA_TSHUT_COLD,
.t_hot = DRA752_IVA_T_HOT,
.t_cold = DRA752_IVA_T_COLD,
.min_freq = DRA752_IVA_MIN_FREQ,
.max_freq = DRA752_IVA_MAX_FREQ,
.max_temp = DRA752_IVA_MAX_TEMP,
.min_temp = DRA752_IVA_MIN_TEMP,
.hyst_val = DRA752_IVA_HYST_VAL,
.update_int1 = 1000,
.update_int2 = 2000,
};
/*
* DRA752 : Temperature values in milli degree celsius
* ADC code values from 540 to 945
*/
static
int dra752_adc_to_temp[DRA752_ADC_END_VALUE - DRA752_ADC_START_VALUE + 1] = {
/* Index 540 - 549 */
-40000, -40000, -40000, -40000, -39800, -39400, -39000, -38600, -38200,
-37800,
/* Index 550 - 559 */
-37400, -37000, -36600, -36200, -35800, -35300, -34700, -34200, -33800,
-33400,
/* Index 560 - 569 */
-33000, -32600, -32200, -31800, -31400, -31000, -30600, -30200, -29800,
-29400,
/* Index 570 - 579 */
-29000, -28600, -28200, -27700, -27100, -26600, -26200, -25800, -25400,
-25000,
/* Index 580 - 589 */
-24600, -24200, -23800, -23400, -23000, -22600, -22200, -21800, -21400,
-21000,
/* Index 590 - 599 */
-20500, -19900, -19400, -19000, -18600, -18200, -17800, -17400, -17000,
-16600,
/* Index 600 - 609 */
-16200, -15800, -15400, -15000, -14600, -14200, -13800, -13400, -13000,
-12500,
/* Index 610 - 619 */
-11900, -11400, -11000, -10600, -10200, -9800, -9400, -9000, -8600,
-8200,
/* Index 620 - 629 */
-7800, -7400, -7000, -6600, -6200, -5800, -5400, -5000, -4500,
-3900,
/* Index 630 - 639 */
-3400, -3000, -2600, -2200, -1800, -1400, -1000, -600, -200,
200,
/* Index 640 - 649 */
600, 1000, 1400, 1800, 2200, 2600, 3000, 3400, 3900,
4500,
/* Index 650 - 659 */
5000, 5400, 5800, 6200, 6600, 7000, 7400, 7800, 8200,
8600,
/* Index 660 - 669 */
9000, 9400, 9800, 10200, 10600, 11000, 11400, 11800, 12200,
12700,
/* Index 670 - 679 */
13300, 13800, 14200, 14600, 15000, 15400, 15800, 16200, 16600,
17000,
/* Index 680 - 689 */
17400, 17800, 18200, 18600, 19000, 19400, 19800, 20200, 20600,
21000,
/* Index 690 - 699 */
21400, 21900, 22500, 23000, 23400, 23800, 24200, 24600, 25000,
25400,
/* Index 700 - 709 */
25800, 26200, 26600, 27000, 27400, 27800, 28200, 28600, 29000,
29400,
/* Index 710 - 719 */
29800, 30200, 30600, 31000, 31400, 31900, 32500, 33000, 33400,
33800,
/* Index 720 - 729 */
34200, 34600, 35000, 35400, 35800, 36200, 36600, 37000, 37400,
37800,
/* Index 730 - 739 */
38200, 38600, 39000, 39400, 39800, 40200, 40600, 41000, 41400,
41800,
/* Index 740 - 749 */
42200, 42600, 43100, 43700, 44200, 44600, 45000, 45400, 45800,
46200,
/* Index 750 - 759 */
46600, 47000, 47400, 47800, 48200, 48600, 49000, 49400, 49800,
50200,
/* Index 760 - 769 */
50600, 51000, 51400, 51800, 52200, 52600, 53000, 53400, 53800,
54200,
/* Index 770 - 779 */
54600, 55000, 55400, 55900, 56500, 57000, 57400, 57800, 58200,
58600,
/* Index 780 - 789 */
59000, 59400, 59800, 60200, 60600, 61000, 61400, 61800, 62200,
62600,
/* Index 790 - 799 */
63000, 63400, 63800, 64200, 64600, 65000, 65400, 65800, 66200,
66600,
/* Index 800 - 809 */
67000, 67400, 67800, 68200, 68600, 69000, 69400, 69800, 70200,
70600,
/* Index 810 - 819 */
71000, 71500, 72100, 72600, 73000, 73400, 73800, 74200, 74600,
75000,
/* Index 820 - 829 */
75400, 75800, 76200, 76600, 77000, 77400, 77800, 78200, 78600,
79000,
/* Index 830 - 839 */
79400, 79800, 80200, 80600, 81000, 81400, 81800, 82200, 82600,
83000,
/* Index 840 - 849 */
83400, 83800, 84200, 84600, 85000, 85400, 85800, 86200, 86600,
87000,
/* Index 850 - 859 */
87400, 87800, 88200, 88600, 89000, 89400, 89800, 90200, 90600,
91000,
/* Index 860 - 869 */
91400, 91800, 92200, 92600, 93000, 93400, 93800, 94200, 94600,
95000,
/* Index 870 - 879 */
95400, 95800, 96200, 96600, 97000, 97500, 98100, 98600, 99000,
99400,
/* Index 880 - 889 */
99800, 100200, 100600, 101000, 101400, 101800, 102200, 102600, 103000,
103400,
/* Index 890 - 899 */
103800, 104200, 104600, 105000, 105400, 105800, 106200, 106600, 107000,
107400,
/* Index 900 - 909 */
107800, 108200, 108600, 109000, 109400, 109800, 110200, 110600, 111000,
111400,
/* Index 910 - 919 */
111800, 112200, 112600, 113000, 113400, 113800, 114200, 114600, 115000,
115400,
/* Index 920 - 929 */
115800, 116200, 116600, 117000, 117400, 117800, 118200, 118600, 119000,
119400,
/* Index 930 - 939 */
119800, 120200, 120600, 121000, 121400, 121800, 122200, 122600, 123000,
123400,
/* Index 940 - 945 */
123800, 124200, 124600, 124900, 125000, 125000,
};
/* DRA752 data */
const struct ti_bandgap_data dra752_data = {
.features = TI_BANDGAP_FEATURE_TSHUT_CONFIG |
TI_BANDGAP_FEATURE_FREEZE_BIT |
TI_BANDGAP_FEATURE_TALERT |
TI_BANDGAP_FEATURE_COUNTER_DELAY |
TI_BANDGAP_FEATURE_HISTORY_BUFFER,
.fclock_name = "l3instr_ts_gclk_div",
.div_ck_name = "l3instr_ts_gclk_div",
.conv_table = dra752_adc_to_temp,
.adc_start_val = DRA752_ADC_START_VALUE,
.adc_end_val = DRA752_ADC_END_VALUE,
.expose_sensor = ti_thermal_expose_sensor,
.remove_sensor = ti_thermal_remove_sensor,
.sensors = {
{
.registers = &dra752_mpu_temp_sensor_registers,
.ts_data = &dra752_mpu_temp_sensor_data,
.domain = "cpu",
.register_cooling = ti_thermal_register_cpu_cooling,
.unregister_cooling = ti_thermal_unregister_cpu_cooling,
.slope = DRA752_GRADIENT_SLOPE,
.constant = DRA752_GRADIENT_CONST,
.slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
.constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
},
{
.registers = &dra752_gpu_temp_sensor_registers,
.ts_data = &dra752_gpu_temp_sensor_data,
.domain = "gpu",
.slope = DRA752_GRADIENT_SLOPE,
.constant = DRA752_GRADIENT_CONST,
.slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
.constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
},
{
.registers = &dra752_core_temp_sensor_registers,
.ts_data = &dra752_core_temp_sensor_data,
.domain = "core",
.slope = DRA752_GRADIENT_SLOPE,
.constant = DRA752_GRADIENT_CONST,
.slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
.constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
},
{
.registers = &dra752_dspeve_temp_sensor_registers,
.ts_data = &dra752_dspeve_temp_sensor_data,
.domain = "dspeve",
.slope = DRA752_GRADIENT_SLOPE,
.constant = DRA752_GRADIENT_CONST,
.slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
.constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
},
{
.registers = &dra752_iva_temp_sensor_registers,
.ts_data = &dra752_iva_temp_sensor_data,
.domain = "iva",
.slope = DRA752_GRADIENT_SLOPE,
.constant = DRA752_GRADIENT_CONST,
.slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
.constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
},
},
.sensor_count = 5,
};

267
drivers/thermal/ti-soc-thermal/omap4-thermal-data.c Normal file
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/*
* OMAP4 thermal driver.
*
* Copyright (C) 2011-2012 Texas Instruments Inc.
* Contact:
* Eduardo Valentin <eduardo.valentin@ti.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include "ti-thermal.h"
#include "ti-bandgap.h"
#include "omap4xxx-bandgap.h"
/*
* OMAP4430 has one instance of thermal sensor for MPU
* need to describe the individual bit fields
*/
static struct temp_sensor_registers
omap4430_mpu_temp_sensor_registers = {
.temp_sensor_ctrl = OMAP4430_TEMP_SENSOR_CTRL_OFFSET,
.bgap_tempsoff_mask = OMAP4430_BGAP_TEMPSOFF_MASK,
.bgap_soc_mask = OMAP4430_BGAP_TEMP_SENSOR_SOC_MASK,
.bgap_eocz_mask = OMAP4430_BGAP_TEMP_SENSOR_EOCZ_MASK,
.bgap_dtemp_mask = OMAP4430_BGAP_TEMP_SENSOR_DTEMP_MASK,
.bgap_mode_ctrl = OMAP4430_TEMP_SENSOR_CTRL_OFFSET,
.mode_ctrl_mask = OMAP4430_SINGLE_MODE_MASK,
.bgap_efuse = OMAP4430_FUSE_OPP_BGAP,
};
/* Thresholds and limits for OMAP4430 MPU temperature sensor */
static struct temp_sensor_data omap4430_mpu_temp_sensor_data = {
.min_freq = OMAP4430_MIN_FREQ,
.max_freq = OMAP4430_MAX_FREQ,
.max_temp = OMAP4430_MAX_TEMP,
.min_temp = OMAP4430_MIN_TEMP,
.hyst_val = OMAP4430_HYST_VAL,
};
/*
* Temperature values in milli degree celsius
* ADC code values from 530 to 923
*/
static const int
omap4430_adc_to_temp[OMAP4430_ADC_END_VALUE - OMAP4430_ADC_START_VALUE + 1] = {
-38000, -35000, -34000, -32000, -30000, -28000, -26000, -24000, -22000,
-20000, -18000, -17000, -15000, -13000, -12000, -10000, -8000, -6000,
-5000, -3000, -1000, 0, 2000, 3000, 5000, 6000, 8000, 10000, 12000,
13000, 15000, 17000, 19000, 21000, 23000, 25000, 27000, 28000, 30000,
32000, 33000, 35000, 37000, 38000, 40000, 42000, 43000, 45000, 47000,
48000, 50000, 52000, 53000, 55000, 57000, 58000, 60000, 62000, 64000,
66000, 68000, 70000, 71000, 73000, 75000, 77000, 78000, 80000, 82000,
83000, 85000, 87000, 88000, 90000, 92000, 93000, 95000, 97000, 98000,
100000, 102000, 103000, 105000, 107000, 109000, 111000, 113000, 115000,
117000, 118000, 120000, 122000, 123000,
};
/* OMAP4430 data */
const struct ti_bandgap_data omap4430_data = {
.features = TI_BANDGAP_FEATURE_MODE_CONFIG |
TI_BANDGAP_FEATURE_CLK_CTRL |
TI_BANDGAP_FEATURE_POWER_SWITCH,
.fclock_name = "bandgap_fclk",
.div_ck_name = "bandgap_fclk",
.conv_table = omap4430_adc_to_temp,
.adc_start_val = OMAP4430_ADC_START_VALUE,
.adc_end_val = OMAP4430_ADC_END_VALUE,
.expose_sensor = ti_thermal_expose_sensor,
.remove_sensor = ti_thermal_remove_sensor,
.sensors = {
{
.registers = &omap4430_mpu_temp_sensor_registers,
.ts_data = &omap4430_mpu_temp_sensor_data,
.domain = "cpu",
.slope = OMAP_GRADIENT_SLOPE_4430,
.constant = OMAP_GRADIENT_CONST_4430,
.slope_pcb = OMAP_GRADIENT_SLOPE_W_PCB_4430,
.constant_pcb = OMAP_GRADIENT_CONST_W_PCB_4430,
.register_cooling = ti_thermal_register_cpu_cooling,
.unregister_cooling = ti_thermal_unregister_cpu_cooling,
},
},
.sensor_count = 1,
};
/*
* OMAP4460 has one instance of thermal sensor for MPU
* need to describe the individual bit fields
*/
static struct temp_sensor_registers
omap4460_mpu_temp_sensor_registers = {
.temp_sensor_ctrl = OMAP4460_TEMP_SENSOR_CTRL_OFFSET,
.bgap_tempsoff_mask = OMAP4460_BGAP_TEMPSOFF_MASK,
.bgap_soc_mask = OMAP4460_BGAP_TEMP_SENSOR_SOC_MASK,
.bgap_eocz_mask = OMAP4460_BGAP_TEMP_SENSOR_EOCZ_MASK,
.bgap_dtemp_mask = OMAP4460_BGAP_TEMP_SENSOR_DTEMP_MASK,
.bgap_mask_ctrl = OMAP4460_BGAP_CTRL_OFFSET,
.mask_hot_mask = OMAP4460_MASK_HOT_MASK,
.mask_cold_mask = OMAP4460_MASK_COLD_MASK,
.bgap_mode_ctrl = OMAP4460_BGAP_CTRL_OFFSET,
.mode_ctrl_mask = OMAP4460_SINGLE_MODE_MASK,
.bgap_counter = OMAP4460_BGAP_COUNTER_OFFSET,
.counter_mask = OMAP4460_COUNTER_MASK,
.bgap_threshold = OMAP4460_BGAP_THRESHOLD_OFFSET,
.threshold_thot_mask = OMAP4460_T_HOT_MASK,
.threshold_tcold_mask = OMAP4460_T_COLD_MASK,
.tshut_threshold = OMAP4460_BGAP_TSHUT_OFFSET,
.tshut_hot_mask = OMAP4460_TSHUT_HOT_MASK,
.tshut_cold_mask = OMAP4460_TSHUT_COLD_MASK,
.bgap_status = OMAP4460_BGAP_STATUS_OFFSET,
.status_clean_stop_mask = OMAP4460_CLEAN_STOP_MASK,
.status_bgap_alert_mask = OMAP4460_BGAP_ALERT_MASK,
.status_hot_mask = OMAP4460_HOT_FLAG_MASK,
.status_cold_mask = OMAP4460_COLD_FLAG_MASK,
.bgap_efuse = OMAP4460_FUSE_OPP_BGAP,
};
/* Thresholds and limits for OMAP4460 MPU temperature sensor */
static struct temp_sensor_data omap4460_mpu_temp_sensor_data = {
.tshut_hot = OMAP4460_TSHUT_HOT,
.tshut_cold = OMAP4460_TSHUT_COLD,
.t_hot = OMAP4460_T_HOT,
.t_cold = OMAP4460_T_COLD,
.min_freq = OMAP4460_MIN_FREQ,
.max_freq = OMAP4460_MAX_FREQ,
.max_temp = OMAP4460_MAX_TEMP,
.min_temp = OMAP4460_MIN_TEMP,
.hyst_val = OMAP4460_HYST_VAL,
.update_int1 = 1000,
.update_int2 = 2000,
};
/*
* Temperature values in milli degree celsius
* ADC code values from 530 to 923
*/
static const int
omap4460_adc_to_temp[OMAP4460_ADC_END_VALUE - OMAP4460_ADC_START_VALUE + 1] = {
-40000, -40000, -40000, -40000, -39800, -39400, -39000, -38600, -38200,
-37800, -37300, -36800, -36400, -36000, -35600, -35200, -34800,
-34300, -33800, -33400, -33000, -32600, -32200, -31800, -31300,
-30800, -30400, -30000, -29600, -29200, -28700, -28200, -27800,
-27400, -27000, -26600, -26200, -25700, -25200, -24800, -24400,
-24000, -23600, -23200, -22700, -22200, -21800, -21400, -21000,
-20600, -20200, -19700, -19200, -18800, -18400, -18000, -17600,
-17200, -16700, -16200, -15800, -15400, -15000, -14600, -14200,
-13700, -13200, -12800, -12400, -12000, -11600, -11200, -10700,
-10200, -9800, -9400, -9000, -8600, -8200, -7700, -7200, -6800,
-6400, -6000, -5600, -5200, -4800, -4300, -3800, -3400, -3000,
-2600, -2200, -1800, -1300, -800, -400, 0, 400, 800, 1200, 1600,
2100, 2600, 3000, 3400, 3800, 4200, 4600, 5100, 5600, 6000, 6400,
6800, 7200, 7600, 8000, 8500, 9000, 9400, 9800, 10200, 10600, 11000,
11400, 11900, 12400, 12800, 13200, 13600, 14000, 14400, 14800,
15300, 15800, 16200, 16600, 17000, 17400, 17800, 18200, 18700,
19200, 19600, 20000, 20400, 20800, 21200, 21600, 22100, 22600,
23000, 23400, 23800, 24200, 24600, 25000, 25400, 25900, 26400,
26800, 27200, 27600, 28000, 28400, 28800, 29300, 29800, 30200,
30600, 31000, 31400, 31800, 32200, 32600, 33100, 33600, 34000,
34400, 34800, 35200, 35600, 36000, 36400, 36800, 37300, 37800,
38200, 38600, 39000, 39400, 39800, 40200, 40600, 41100, 41600,
42000, 42400, 42800, 43200, 43600, 44000, 44400, 44800, 45300,
45800, 46200, 46600, 47000, 47400, 47800, 48200, 48600, 49000,
49500, 50000, 50400, 50800, 51200, 51600, 52000, 52400, 52800,
53200, 53700, 54200, 54600, 55000, 55400, 55800, 56200, 56600,
57000, 57400, 57800, 58200, 58700, 59200, 59600, 60000, 60400,
60800, 61200, 61600, 62000, 62400, 62800, 63300, 63800, 64200,
64600, 65000, 65400, 65800, 66200, 66600, 67000, 67400, 67800,
68200, 68700, 69200, 69600, 70000, 70400, 70800, 71200, 71600,
72000, 72400, 72800, 73200, 73600, 74100, 74600, 75000, 75400,
75800, 76200, 76600, 77000, 77400, 77800, 78200, 78600, 79000,
79400, 79800, 80300, 80800, 81200, 81600, 82000, 82400, 82800,
83200, 83600, 84000, 84400, 84800, 85200, 85600, 86000, 86400,
86800, 87300, 87800, 88200, 88600, 89000, 89400, 89800, 90200,
90600, 91000, 91400, 91800, 92200, 92600, 93000, 93400, 93800,
94200, 94600, 95000, 95500, 96000, 96400, 96800, 97200, 97600,
98000, 98400, 98800, 99200, 99600, 100000, 100400, 100800, 101200,
101600, 102000, 102400, 102800, 103200, 103600, 104000, 104400,
104800, 105200, 105600, 106100, 106600, 107000, 107400, 107800,
108200, 108600, 109000, 109400, 109800, 110200, 110600, 111000,
111400, 111800, 112200, 112600, 113000, 113400, 113800, 114200,
114600, 115000, 115400, 115800, 116200, 116600, 117000, 117400,
117800, 118200, 118600, 119000, 119400, 119800, 120200, 120600,
121000, 121400, 121800, 122200, 122600, 123000, 123400, 123800, 124200,
124600, 124900, 125000, 125000, 125000, 125000
};
/* OMAP4460 data */
const struct ti_bandgap_data omap4460_data = {
.features = TI_BANDGAP_FEATURE_TSHUT |
TI_BANDGAP_FEATURE_TSHUT_CONFIG |
TI_BANDGAP_FEATURE_TALERT |
TI_BANDGAP_FEATURE_MODE_CONFIG |
TI_BANDGAP_FEATURE_POWER_SWITCH |
TI_BANDGAP_FEATURE_CLK_CTRL |
TI_BANDGAP_FEATURE_COUNTER,
.fclock_name = "bandgap_ts_fclk",
.div_ck_name = "div_ts_ck",
.conv_table = omap4460_adc_to_temp,
.adc_start_val = OMAP4460_ADC_START_VALUE,
.adc_end_val = OMAP4460_ADC_END_VALUE,
.expose_sensor = ti_thermal_expose_sensor,
.remove_sensor = ti_thermal_remove_sensor,
.report_temperature = ti_thermal_report_sensor_temperature,
.sensors = {
{
.registers = &omap4460_mpu_temp_sensor_registers,
.ts_data = &omap4460_mpu_temp_sensor_data,
.domain = "cpu",
.slope = OMAP_GRADIENT_SLOPE_4460,
.constant = OMAP_GRADIENT_CONST_4460,
.slope_pcb = OMAP_GRADIENT_SLOPE_W_PCB_4460,
.constant_pcb = OMAP_GRADIENT_CONST_W_PCB_4460,
.register_cooling = ti_thermal_register_cpu_cooling,
.unregister_cooling = ti_thermal_unregister_cpu_cooling,
},
},
.sensor_count = 1,
};
/* OMAP4470 data */
const struct ti_bandgap_data omap4470_data = {
.features = TI_BANDGAP_FEATURE_TSHUT |
TI_BANDGAP_FEATURE_TSHUT_CONFIG |
TI_BANDGAP_FEATURE_TALERT |
TI_BANDGAP_FEATURE_MODE_CONFIG |
TI_BANDGAP_FEATURE_POWER_SWITCH |
TI_BANDGAP_FEATURE_CLK_CTRL |
TI_BANDGAP_FEATURE_COUNTER,
.fclock_name = "bandgap_ts_fclk",
.div_ck_name = "div_ts_ck",
.conv_table = omap4460_adc_to_temp,
.adc_start_val = OMAP4460_ADC_START_VALUE,
.adc_end_val = OMAP4460_ADC_END_VALUE,
.expose_sensor = ti_thermal_expose_sensor,
.remove_sensor = ti_thermal_remove_sensor,
.report_temperature = ti_thermal_report_sensor_temperature,
.sensors = {
{
.registers = &omap4460_mpu_temp_sensor_registers,
.ts_data = &omap4460_mpu_temp_sensor_data,
.domain = "cpu",
.slope = OMAP_GRADIENT_SLOPE_4470,
.constant = OMAP_GRADIENT_CONST_4470,
.slope_pcb = OMAP_GRADIENT_SLOPE_W_PCB_4470,
.constant_pcb = OMAP_GRADIENT_CONST_W_PCB_4470,
.register_cooling = ti_thermal_register_cpu_cooling,
.unregister_cooling = ti_thermal_unregister_cpu_cooling,
},
},
.sensor_count = 1,
};

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/*
* OMAP4xxx bandgap registers, bitfields and temperature definitions
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
* Contact:
* Eduardo Valentin <eduardo.valentin@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#ifndef __OMAP4XXX_BANDGAP_H
#define __OMAP4XXX_BANDGAP_H
/**
* *** OMAP4430 ***
*
* Below, in sequence, are the Register definitions,
* the bitfields and the temperature definitions for OMAP4430.
*/
/**
* OMAP4430 register definitions
*
* Registers are defined as offsets. The offsets are
* relative to FUSE_OPP_BGAP on 4430.
*/
/* OMAP4430.FUSE_OPP_BGAP */
#define OMAP4430_FUSE_OPP_BGAP 0x0
/* OMAP4430.TEMP_SENSOR */
#define OMAP4430_TEMP_SENSOR_CTRL_OFFSET 0xCC
/**
* Register and bit definitions for OMAP4430
*
* All the macros bellow define the required bits for
* controlling temperature on OMAP4430. Bit defines are
* grouped by register.
*/
/* OMAP4430.TEMP_SENSOR bits */
#define OMAP4430_BGAP_TEMPSOFF_MASK BIT(12)
#define OMAP4430_BGAP_TSHUT_MASK BIT(11)
#define OMAP4430_SINGLE_MODE_MASK BIT(10)
#define OMAP4430_BGAP_TEMP_SENSOR_SOC_MASK BIT(9)
#define OMAP4430_BGAP_TEMP_SENSOR_EOCZ_MASK BIT(8)
#define OMAP4430_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0)
/**
* Temperature limits and thresholds for OMAP4430
*
* All the macros bellow are definitions for handling the
* ADC conversions and representation of temperature limits
* and thresholds for OMAP4430.
*/
/* ADC conversion table limits */
#define OMAP4430_ADC_START_VALUE 0
#define OMAP4430_ADC_END_VALUE 127
/* bandgap clock limits (no control on 4430) */
#define OMAP4430_MAX_FREQ 32768
#define OMAP4430_MIN_FREQ 32768
/* sensor limits */
#define OMAP4430_MIN_TEMP -40000
#define OMAP4430_MAX_TEMP 125000
#define OMAP4430_HYST_VAL 5000
/**
* *** OMAP4460 *** Applicable for OMAP4470
*
* Below, in sequence, are the Register definitions,
* the bitfields and the temperature definitions for OMAP4460.
*/
/**
* OMAP4460 register definitions
*
* Registers are defined as offsets. The offsets are
* relative to FUSE_OPP_BGAP on 4460.
*/
/* OMAP4460.FUSE_OPP_BGAP */
#define OMAP4460_FUSE_OPP_BGAP 0x0
/* OMAP4460.TEMP_SENSOR */
#define OMAP4460_TEMP_SENSOR_CTRL_OFFSET 0xCC
/* OMAP4460.BANDGAP_CTRL */
#define OMAP4460_BGAP_CTRL_OFFSET 0x118
/* OMAP4460.BANDGAP_COUNTER */
#define OMAP4460_BGAP_COUNTER_OFFSET 0x11C
/* OMAP4460.BANDGAP_THRESHOLD */
#define OMAP4460_BGAP_THRESHOLD_OFFSET 0x120
/* OMAP4460.TSHUT_THRESHOLD */
#define OMAP4460_BGAP_TSHUT_OFFSET 0x124
/* OMAP4460.BANDGAP_STATUS */
#define OMAP4460_BGAP_STATUS_OFFSET 0x128
/**
* Register bitfields for OMAP4460
*
* All the macros bellow define the required bits for
* controlling temperature on OMAP4460. Bit defines are
* grouped by register.
*/
/* OMAP4460.TEMP_SENSOR bits */
#define OMAP4460_BGAP_TEMPSOFF_MASK BIT(13)
#define OMAP4460_BGAP_TEMP_SENSOR_SOC_MASK BIT(11)
#define OMAP4460_BGAP_TEMP_SENSOR_EOCZ_MASK BIT(10)
#define OMAP4460_BGAP_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0)
/* OMAP4460.BANDGAP_CTRL bits */
#define OMAP4460_SINGLE_MODE_MASK BIT(31)
#define OMAP4460_MASK_HOT_MASK BIT(1)
#define OMAP4460_MASK_COLD_MASK BIT(0)
/* OMAP4460.BANDGAP_COUNTER bits */
#define OMAP4460_COUNTER_MASK (0xffffff << 0)
/* OMAP4460.BANDGAP_THRESHOLD bits */
#define OMAP4460_T_HOT_MASK (0x3ff << 16)
#define OMAP4460_T_COLD_MASK (0x3ff << 0)
/* OMAP4460.TSHUT_THRESHOLD bits */
#define OMAP4460_TSHUT_HOT_MASK (0x3ff << 16)
#define OMAP4460_TSHUT_COLD_MASK (0x3ff << 0)
/* OMAP4460.BANDGAP_STATUS bits */
#define OMAP4460_CLEAN_STOP_MASK BIT(3)
#define OMAP4460_BGAP_ALERT_MASK BIT(2)
#define OMAP4460_HOT_FLAG_MASK BIT(1)
#define OMAP4460_COLD_FLAG_MASK BIT(0)
/**
* Temperature limits and thresholds for OMAP4460
*
* All the macros bellow are definitions for handling the
* ADC conversions and representation of temperature limits
* and thresholds for OMAP4460.
*/
/* ADC conversion table limits */
#define OMAP4460_ADC_START_VALUE 530
#define OMAP4460_ADC_END_VALUE 932
/* bandgap clock limits */
#define OMAP4460_MAX_FREQ 1500000
#define OMAP4460_MIN_FREQ 1000000
/* sensor limits */
#define OMAP4460_MIN_TEMP -40000
#define OMAP4460_MAX_TEMP 123000
#define OMAP4460_HYST_VAL 5000
/* interrupts thresholds */
#define OMAP4460_TSHUT_HOT 900 /* 122 deg C */
#define OMAP4460_TSHUT_COLD 895 /* 100 deg C */
#define OMAP4460_T_HOT 800 /* 73 deg C */
#define OMAP4460_T_COLD 795 /* 71 deg C */
#endif /* __OMAP4XXX_BANDGAP_H */

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/*
* OMAP5 thermal driver.
*
* Copyright (C) 2011-2012 Texas Instruments Inc.
* Contact:
* Eduardo Valentin <eduardo.valentin@ti.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include "ti-thermal.h"
#include "ti-bandgap.h"
#include "omap5xxx-bandgap.h"
/*
* OMAP5430 has three instances of thermal sensor for MPU, GPU & CORE,
* need to describe the individual registers and bit fields.
*/
/*
* OMAP5430 MPU thermal sensor register offset and bit-fields
*/
static struct temp_sensor_registers
omap5430_mpu_temp_sensor_registers = {
.temp_sensor_ctrl = OMAP5430_TEMP_SENSOR_MPU_OFFSET,
.bgap_tempsoff_mask = OMAP5430_BGAP_TEMPSOFF_MASK,
.bgap_eocz_mask = OMAP5430_BGAP_TEMP_SENSOR_EOCZ_MASK,
.bgap_dtemp_mask = OMAP5430_BGAP_TEMP_SENSOR_DTEMP_MASK,
.bgap_mask_ctrl = OMAP5430_BGAP_CTRL_OFFSET,
.mask_hot_mask = OMAP5430_MASK_HOT_MPU_MASK,
.mask_cold_mask = OMAP5430_MASK_COLD_MPU_MASK,
.mask_sidlemode_mask = OMAP5430_MASK_SIDLEMODE_MASK,
.mask_counter_delay_mask = OMAP5430_MASK_COUNTER_DELAY_MASK,
.mask_freeze_mask = OMAP5430_MASK_FREEZE_MPU_MASK,
.mask_clear_mask = OMAP5430_MASK_CLEAR_MPU_MASK,
.mask_clear_accum_mask = OMAP5430_MASK_CLEAR_ACCUM_MPU_MASK,
.bgap_counter = OMAP5430_BGAP_CTRL_OFFSET,
.counter_mask = OMAP5430_COUNTER_MASK,
.bgap_threshold = OMAP5430_BGAP_THRESHOLD_MPU_OFFSET,
.threshold_thot_mask = OMAP5430_T_HOT_MASK,
.threshold_tcold_mask = OMAP5430_T_COLD_MASK,
.tshut_threshold = OMAP5430_BGAP_TSHUT_MPU_OFFSET,
.tshut_hot_mask = OMAP5430_TSHUT_HOT_MASK,
.tshut_cold_mask = OMAP5430_TSHUT_COLD_MASK,
.bgap_status = OMAP5430_BGAP_STATUS_OFFSET,
.status_clean_stop_mask = 0x0,
.status_bgap_alert_mask = OMAP5430_BGAP_ALERT_MASK,
.status_hot_mask = OMAP5430_HOT_MPU_FLAG_MASK,
.status_cold_mask = OMAP5430_COLD_MPU_FLAG_MASK,
.bgap_cumul_dtemp = OMAP5430_BGAP_CUMUL_DTEMP_MPU_OFFSET,
.ctrl_dtemp_0 = OMAP5430_BGAP_DTEMP_MPU_0_OFFSET,
.ctrl_dtemp_1 = OMAP5430_BGAP_DTEMP_MPU_1_OFFSET,
.ctrl_dtemp_2 = OMAP5430_BGAP_DTEMP_MPU_2_OFFSET,
.ctrl_dtemp_3 = OMAP5430_BGAP_DTEMP_MPU_3_OFFSET,
.ctrl_dtemp_4 = OMAP5430_BGAP_DTEMP_MPU_4_OFFSET,
.bgap_efuse = OMAP5430_FUSE_OPP_BGAP_MPU,
};
/*
* OMAP5430 GPU thermal sensor register offset and bit-fields
*/
static struct temp_sensor_registers
omap5430_gpu_temp_sensor_registers = {
.temp_sensor_ctrl = OMAP5430_TEMP_SENSOR_GPU_OFFSET,
.bgap_tempsoff_mask = OMAP5430_BGAP_TEMPSOFF_MASK,
.bgap_eocz_mask = OMAP5430_BGAP_TEMP_SENSOR_EOCZ_MASK,
.bgap_dtemp_mask = OMAP5430_BGAP_TEMP_SENSOR_DTEMP_MASK,
.bgap_mask_ctrl = OMAP5430_BGAP_CTRL_OFFSET,
.mask_hot_mask = OMAP5430_MASK_HOT_GPU_MASK,
.mask_cold_mask = OMAP5430_MASK_COLD_GPU_MASK,
.mask_sidlemode_mask = OMAP5430_MASK_SIDLEMODE_MASK,
.mask_counter_delay_mask = OMAP5430_MASK_COUNTER_DELAY_MASK,
.mask_freeze_mask = OMAP5430_MASK_FREEZE_GPU_MASK,
.mask_clear_mask = OMAP5430_MASK_CLEAR_GPU_MASK,
.mask_clear_accum_mask = OMAP5430_MASK_CLEAR_ACCUM_GPU_MASK,
.bgap_counter = OMAP5430_BGAP_CTRL_OFFSET,
.counter_mask = OMAP5430_COUNTER_MASK,
.bgap_threshold = OMAP5430_BGAP_THRESHOLD_GPU_OFFSET,
.threshold_thot_mask = OMAP5430_T_HOT_MASK,
.threshold_tcold_mask = OMAP5430_T_COLD_MASK,
.tshut_threshold = OMAP5430_BGAP_TSHUT_GPU_OFFSET,
.tshut_hot_mask = OMAP5430_TSHUT_HOT_MASK,
.tshut_cold_mask = OMAP5430_TSHUT_COLD_MASK,
.bgap_status = OMAP5430_BGAP_STATUS_OFFSET,
.status_clean_stop_mask = 0x0,
.status_bgap_alert_mask = OMAP5430_BGAP_ALERT_MASK,
.status_hot_mask = OMAP5430_HOT_GPU_FLAG_MASK,
.status_cold_mask = OMAP5430_COLD_GPU_FLAG_MASK,
.bgap_cumul_dtemp = OMAP5430_BGAP_CUMUL_DTEMP_GPU_OFFSET,
.ctrl_dtemp_0 = OMAP5430_BGAP_DTEMP_GPU_0_OFFSET,
.ctrl_dtemp_1 = OMAP5430_BGAP_DTEMP_GPU_1_OFFSET,
.ctrl_dtemp_2 = OMAP5430_BGAP_DTEMP_GPU_2_OFFSET,
.ctrl_dtemp_3 = OMAP5430_BGAP_DTEMP_GPU_3_OFFSET,
.ctrl_dtemp_4 = OMAP5430_BGAP_DTEMP_GPU_4_OFFSET,
.bgap_efuse = OMAP5430_FUSE_OPP_BGAP_GPU,
};
/*
* OMAP5430 CORE thermal sensor register offset and bit-fields
*/
static struct temp_sensor_registers
omap5430_core_temp_sensor_registers = {
.temp_sensor_ctrl = OMAP5430_TEMP_SENSOR_CORE_OFFSET,
.bgap_tempsoff_mask = OMAP5430_BGAP_TEMPSOFF_MASK,
.bgap_eocz_mask = OMAP5430_BGAP_TEMP_SENSOR_EOCZ_MASK,
.bgap_dtemp_mask = OMAP5430_BGAP_TEMP_SENSOR_DTEMP_MASK,
.bgap_mask_ctrl = OMAP5430_BGAP_CTRL_OFFSET,
.mask_hot_mask = OMAP5430_MASK_HOT_CORE_MASK,
.mask_cold_mask = OMAP5430_MASK_COLD_CORE_MASK,
.mask_sidlemode_mask = OMAP5430_MASK_SIDLEMODE_MASK,
.mask_counter_delay_mask = OMAP5430_MASK_COUNTER_DELAY_MASK,
.mask_freeze_mask = OMAP5430_MASK_FREEZE_CORE_MASK,
.mask_clear_mask = OMAP5430_MASK_CLEAR_CORE_MASK,
.mask_clear_accum_mask = OMAP5430_MASK_CLEAR_ACCUM_CORE_MASK,
.bgap_counter = OMAP5430_BGAP_CTRL_OFFSET,
.counter_mask = OMAP5430_COUNTER_MASK,
.bgap_threshold = OMAP5430_BGAP_THRESHOLD_CORE_OFFSET,
.threshold_thot_mask = OMAP5430_T_HOT_MASK,
.threshold_tcold_mask = OMAP5430_T_COLD_MASK,
.tshut_threshold = OMAP5430_BGAP_TSHUT_CORE_OFFSET,
.tshut_hot_mask = OMAP5430_TSHUT_HOT_MASK,
.tshut_cold_mask = OMAP5430_TSHUT_COLD_MASK,
.bgap_status = OMAP5430_BGAP_STATUS_OFFSET,
.status_clean_stop_mask = 0x0,
.status_bgap_alert_mask = OMAP5430_BGAP_ALERT_MASK,
.status_hot_mask = OMAP5430_HOT_CORE_FLAG_MASK,
.status_cold_mask = OMAP5430_COLD_CORE_FLAG_MASK,
.bgap_cumul_dtemp = OMAP5430_BGAP_CUMUL_DTEMP_CORE_OFFSET,
.ctrl_dtemp_0 = OMAP5430_BGAP_DTEMP_CORE_0_OFFSET,
.ctrl_dtemp_1 = OMAP5430_BGAP_DTEMP_CORE_1_OFFSET,
.ctrl_dtemp_2 = OMAP5430_BGAP_DTEMP_CORE_2_OFFSET,
.ctrl_dtemp_3 = OMAP5430_BGAP_DTEMP_CORE_3_OFFSET,
.ctrl_dtemp_4 = OMAP5430_BGAP_DTEMP_CORE_4_OFFSET,
.bgap_efuse = OMAP5430_FUSE_OPP_BGAP_CORE,
};
/* Thresholds and limits for OMAP5430 MPU temperature sensor */
static struct temp_sensor_data omap5430_mpu_temp_sensor_data = {
.tshut_hot = OMAP5430_MPU_TSHUT_HOT,
.tshut_cold = OMAP5430_MPU_TSHUT_COLD,
.t_hot = OMAP5430_MPU_T_HOT,
.t_cold = OMAP5430_MPU_T_COLD,
.min_freq = OMAP5430_MPU_MIN_FREQ,
.max_freq = OMAP5430_MPU_MAX_FREQ,
.max_temp = OMAP5430_MPU_MAX_TEMP,
.min_temp = OMAP5430_MPU_MIN_TEMP,
.hyst_val = OMAP5430_MPU_HYST_VAL,
.update_int1 = 1000,
.update_int2 = 2000,
};
/* Thresholds and limits for OMAP5430 GPU temperature sensor */
static struct temp_sensor_data omap5430_gpu_temp_sensor_data = {
.tshut_hot = OMAP5430_GPU_TSHUT_HOT,
.tshut_cold = OMAP5430_GPU_TSHUT_COLD,
.t_hot = OMAP5430_GPU_T_HOT,
.t_cold = OMAP5430_GPU_T_COLD,
.min_freq = OMAP5430_GPU_MIN_FREQ,
.max_freq = OMAP5430_GPU_MAX_FREQ,
.max_temp = OMAP5430_GPU_MAX_TEMP,
.min_temp = OMAP5430_GPU_MIN_TEMP,
.hyst_val = OMAP5430_GPU_HYST_VAL,
.update_int1 = 1000,
.update_int2 = 2000,
};
/* Thresholds and limits for OMAP5430 CORE temperature sensor */
static struct temp_sensor_data omap5430_core_temp_sensor_data = {
.tshut_hot = OMAP5430_CORE_TSHUT_HOT,
.tshut_cold = OMAP5430_CORE_TSHUT_COLD,
.t_hot = OMAP5430_CORE_T_HOT,
.t_cold = OMAP5430_CORE_T_COLD,
.min_freq = OMAP5430_CORE_MIN_FREQ,
.max_freq = OMAP5430_CORE_MAX_FREQ,
.max_temp = OMAP5430_CORE_MAX_TEMP,
.min_temp = OMAP5430_CORE_MIN_TEMP,
.hyst_val = OMAP5430_CORE_HYST_VAL,
.update_int1 = 1000,
.update_int2 = 2000,
};
/*
* OMAP54xx ES2.0 : Temperature values in milli degree celsius
* ADC code values from 540 to 945
*/
static int
omap5430_adc_to_temp[
OMAP5430_ADC_END_VALUE - OMAP5430_ADC_START_VALUE + 1] = {
/* Index 540 - 549 */
-40000, -40000, -40000, -40000, -39800, -39400, -39000, -38600, -38200,
-37800,
/* Index 550 - 559 */
-37400, -37000, -36600, -36200, -35800, -35300, -34700, -34200, -33800,
-33400,
/* Index 560 - 569 */
-33000, -32600, -32200, -31800, -31400, -31000, -30600, -30200, -29800,
-29400,
/* Index 570 - 579 */
-29000, -28600, -28200, -27700, -27100, -26600, -26200, -25800, -25400,
-25000,
/* Index 580 - 589 */
-24600, -24200, -23800, -23400, -23000, -22600, -22200, -21600, -21400,
-21000,
/* Index 590 - 599 */
-20500, -19900, -19400, -19000, -18600, -18200, -17800, -17400, -17000,
-16600,
/* Index 600 - 609 */
-16200, -15800, -15400, -15000, -14600, -14200, -13800, -13400, -13000,
-12500,
/* Index 610 - 619 */
-11900, -11400, -11000, -10600, -10200, -9800, -9400, -9000, -8600,
-8200,
/* Index 620 - 629 */
-7800, -7400, -7000, -6600, -6200, -5800, -5400, -5000, -4500, -3900,
/* Index 630 - 639 */
-3400, -3000, -2600, -2200, -1800, -1400, -1000, -600, -200, 200,
/* Index 640 - 649 */
600, 1000, 1400, 1800, 2200, 2600, 3000, 3400, 3900, 4500,
/* Index 650 - 659 */
5000, 5400, 5800, 6200, 6600, 7000, 7400, 7800, 8200, 8600,
/* Index 660 - 669 */
9000, 9400, 9800, 10200, 10600, 11000, 11400, 11800, 12200, 12700,
/* Index 670 - 679 */
13300, 13800, 14200, 14600, 15000, 15400, 15800, 16200, 16600, 17000,
/* Index 680 - 689 */
17400, 17800, 18200, 18600, 19000, 19400, 19800, 20200, 20600, 21100,
/* Index 690 - 699 */
21400, 21900, 22500, 23000, 23400, 23800, 24200, 24600, 25000, 25400,
/* Index 700 - 709 */
25800, 26200, 26600, 27000, 27400, 27800, 28200, 28600, 29000, 29400,
/* Index 710 - 719 */
29800, 30200, 30600, 31000, 31400, 31900, 32500, 33000, 33400, 33800,
/* Index 720 - 729 */
34200, 34600, 35000, 35400, 35800, 36200, 36600, 37000, 37400, 37800,
/* Index 730 - 739 */
38200, 38600, 39000, 39400, 39800, 40200, 40600, 41000, 41400, 41800,
/* Index 740 - 749 */
42200, 42600, 43100, 43700, 44200, 44600, 45000, 45400, 45800, 46200,
/* Index 750 - 759 */
46600, 47000, 47400, 47800, 48200, 48600, 49000, 49400, 49800, 50200,
/* Index 760 - 769 */
50600, 51000, 51400, 51800, 52200, 52600, 53000, 53400, 53800, 54200,
/* Index 770 - 779 */
54600, 55000, 55400, 55900, 56500, 57000, 57400, 57800, 58200, 58600,
/* Index 780 - 789 */
59000, 59400, 59800, 60200, 60600, 61000, 61400, 61800, 62200, 62600,
/* Index 790 - 799 */
63000, 63400, 63800, 64200, 64600, 65000, 65400, 65800, 66200, 66600,
/* Index 800 - 809 */
67000, 67400, 67800, 68200, 68600, 69000, 69400, 69800, 70200, 70600,
/* Index 810 - 819 */
71000, 71500, 72100, 72600, 73000, 73400, 73800, 74200, 74600, 75000,
/* Index 820 - 829 */
75400, 75800, 76200, 76600, 77000, 77400, 77800, 78200, 78600, 79000,
/* Index 830 - 839 */
79400, 79800, 80200, 80600, 81000, 81400, 81800, 82200, 82600, 83000,
/* Index 840 - 849 */
83400, 83800, 84200, 84600, 85000, 85400, 85800, 86200, 86600, 87000,
/* Index 850 - 859 */
87400, 87800, 88200, 88600, 89000, 89400, 89800, 90200, 90600, 91000,
/* Index 860 - 869 */
91400, 91800, 92200, 92600, 93000, 93400, 93800, 94200, 94600, 95000,
/* Index 870 - 879 */
95400, 95800, 96200, 96600, 97000, 97500, 98100, 98600, 99000, 99400,
/* Index 880 - 889 */
99800, 100200, 100600, 101000, 101400, 101800, 102200, 102600, 103000,
103400,
/* Index 890 - 899 */
103800, 104200, 104600, 105000, 105400, 105800, 106200, 106600, 107000,
107400,
/* Index 900 - 909 */
107800, 108200, 108600, 109000, 109400, 109800, 110200, 110600, 111000,
111400,
/* Index 910 - 919 */
111800, 112200, 112600, 113000, 113400, 113800, 114200, 114600, 115000,
115400,
/* Index 920 - 929 */
115800, 116200, 116600, 117000, 117400, 117800, 118200, 118600, 119000,
119400,
/* Index 930 - 939 */
119800, 120200, 120600, 121000, 121400, 121800, 122400, 122600, 123000,
123400,
/* Index 940 - 945 */
123800, 1242000, 124600, 124900, 125000, 125000,
};
/* OMAP54xx ES2.0 data */
const struct ti_bandgap_data omap5430_data = {
.features = TI_BANDGAP_FEATURE_TSHUT_CONFIG |
TI_BANDGAP_FEATURE_FREEZE_BIT |
TI_BANDGAP_FEATURE_TALERT |
TI_BANDGAP_FEATURE_COUNTER_DELAY |
TI_BANDGAP_FEATURE_HISTORY_BUFFER,
.fclock_name = "l3instr_ts_gclk_div",
.div_ck_name = "l3instr_ts_gclk_div",
.conv_table = omap5430_adc_to_temp,
.adc_start_val = OMAP5430_ADC_START_VALUE,
.adc_end_val = OMAP5430_ADC_END_VALUE,
.expose_sensor = ti_thermal_expose_sensor,
.remove_sensor = ti_thermal_remove_sensor,
.report_temperature = ti_thermal_report_sensor_temperature,
.sensors = {
{
.registers = &omap5430_mpu_temp_sensor_registers,
.ts_data = &omap5430_mpu_temp_sensor_data,
.domain = "cpu",
.register_cooling = ti_thermal_register_cpu_cooling,
.unregister_cooling = ti_thermal_unregister_cpu_cooling,
.slope = OMAP_GRADIENT_SLOPE_5430_CPU,
.constant = OMAP_GRADIENT_CONST_5430_CPU,
.slope_pcb = OMAP_GRADIENT_SLOPE_W_PCB_5430_CPU,
.constant_pcb = OMAP_GRADIENT_CONST_W_PCB_5430_CPU,
},
{
.registers = &omap5430_gpu_temp_sensor_registers,
.ts_data = &omap5430_gpu_temp_sensor_data,
.domain = "gpu",
.slope = OMAP_GRADIENT_SLOPE_5430_GPU,
.constant = OMAP_GRADIENT_CONST_5430_GPU,
.slope_pcb = OMAP_GRADIENT_SLOPE_W_PCB_5430_GPU,
.constant_pcb = OMAP_GRADIENT_CONST_W_PCB_5430_GPU,
},
{
.registers = &omap5430_core_temp_sensor_registers,
.ts_data = &omap5430_core_temp_sensor_data,
.domain = "core",
},
},
.sensor_count = 3,
};

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/*
* OMAP5xxx bandgap registers, bitfields and temperature definitions
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
* Contact:
* Eduardo Valentin <eduardo.valentin@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#ifndef __OMAP5XXX_BANDGAP_H
#define __OMAP5XXX_BANDGAP_H
/**
* *** OMAP5430 ***
*
* Below, in sequence, are the Register definitions,
* the bitfields and the temperature definitions for OMAP5430.
*/
/**
* OMAP5430 register definitions
*
* Registers are defined as offsets. The offsets are
* relative to FUSE_OPP_BGAP_GPU on 5430.
*
* Register below are grouped by domain (not necessarily in offset order)
*/
/* OMAP5430.GPU register offsets */
#define OMAP5430_FUSE_OPP_BGAP_GPU 0x0
#define OMAP5430_TEMP_SENSOR_GPU_OFFSET 0x150
#define OMAP5430_BGAP_THRESHOLD_GPU_OFFSET 0x1A8
#define OMAP5430_BGAP_TSHUT_GPU_OFFSET 0x1B4
#define OMAP5430_BGAP_CUMUL_DTEMP_GPU_OFFSET 0x1C0
#define OMAP5430_BGAP_DTEMP_GPU_0_OFFSET 0x1F4
#define OMAP5430_BGAP_DTEMP_GPU_1_OFFSET 0x1F8
#define OMAP5430_BGAP_DTEMP_GPU_2_OFFSET 0x1FC
#define OMAP5430_BGAP_DTEMP_GPU_3_OFFSET 0x200
#define OMAP5430_BGAP_DTEMP_GPU_4_OFFSET 0x204
/* OMAP5430.MPU register offsets */
#define OMAP5430_FUSE_OPP_BGAP_MPU 0x4
#define OMAP5430_TEMP_SENSOR_MPU_OFFSET 0x14C
#define OMAP5430_BGAP_THRESHOLD_MPU_OFFSET 0x1A4
#define OMAP5430_BGAP_TSHUT_MPU_OFFSET 0x1B0
#define OMAP5430_BGAP_CUMUL_DTEMP_MPU_OFFSET 0x1BC
#define OMAP5430_BGAP_DTEMP_MPU_0_OFFSET 0x1E0
#define OMAP5430_BGAP_DTEMP_MPU_1_OFFSET 0x1E4
#define OMAP5430_BGAP_DTEMP_MPU_2_OFFSET 0x1E8
#define OMAP5430_BGAP_DTEMP_MPU_3_OFFSET 0x1EC
#define OMAP5430_BGAP_DTEMP_MPU_4_OFFSET 0x1F0
/* OMAP5430.MPU register offsets */
#define OMAP5430_FUSE_OPP_BGAP_CORE 0x8
#define OMAP5430_TEMP_SENSOR_CORE_OFFSET 0x154
#define OMAP5430_BGAP_THRESHOLD_CORE_OFFSET 0x1AC
#define OMAP5430_BGAP_TSHUT_CORE_OFFSET 0x1B8
#define OMAP5430_BGAP_CUMUL_DTEMP_CORE_OFFSET 0x1C4
#define OMAP5430_BGAP_DTEMP_CORE_0_OFFSET 0x208
#define OMAP5430_BGAP_DTEMP_CORE_1_OFFSET 0x20C
#define OMAP5430_BGAP_DTEMP_CORE_2_OFFSET 0x210
#define OMAP5430_BGAP_DTEMP_CORE_3_OFFSET 0x214
#define OMAP5430_BGAP_DTEMP_CORE_4_OFFSET 0x218
/* OMAP5430.common register offsets */
#define OMAP5430_BGAP_CTRL_OFFSET 0x1A0
#define OMAP5430_BGAP_STATUS_OFFSET 0x1C8
/**
* Register bitfields for OMAP5430
*
* All the macros bellow define the required bits for
* controlling temperature on OMAP5430. Bit defines are
* grouped by register.
*/
/* OMAP5430.TEMP_SENSOR */
#define OMAP5430_BGAP_TEMP_SENSOR_SOC_MASK BIT(12)
#define OMAP5430_BGAP_TEMPSOFF_MASK BIT(11)
#define OMAP5430_BGAP_TEMP_SENSOR_EOCZ_MASK BIT(10)
#define OMAP5430_BGAP_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0)
/* OMAP5430.BANDGAP_CTRL */
#define OMAP5430_MASK_SIDLEMODE_MASK (0x3 << 30)
#define OMAP5430_MASK_COUNTER_DELAY_MASK (0x7 << 27)
#define OMAP5430_MASK_FREEZE_CORE_MASK BIT(23)
#define OMAP5430_MASK_FREEZE_GPU_MASK BIT(22)
#define OMAP5430_MASK_FREEZE_MPU_MASK BIT(21)
#define OMAP5430_MASK_CLEAR_CORE_MASK BIT(20)
#define OMAP5430_MASK_CLEAR_GPU_MASK BIT(19)
#define OMAP5430_MASK_CLEAR_MPU_MASK BIT(18)
#define OMAP5430_MASK_CLEAR_ACCUM_CORE_MASK BIT(17)
#define OMAP5430_MASK_CLEAR_ACCUM_GPU_MASK BIT(16)
#define OMAP5430_MASK_CLEAR_ACCUM_MPU_MASK BIT(15)
#define OMAP5430_MASK_HOT_CORE_MASK BIT(5)
#define OMAP5430_MASK_COLD_CORE_MASK BIT(4)
#define OMAP5430_MASK_HOT_GPU_MASK BIT(3)
#define OMAP5430_MASK_COLD_GPU_MASK BIT(2)
#define OMAP5430_MASK_HOT_MPU_MASK BIT(1)
#define OMAP5430_MASK_COLD_MPU_MASK BIT(0)
/* OMAP5430.BANDGAP_COUNTER */
#define OMAP5430_COUNTER_MASK (0xffffff << 0)
/* OMAP5430.BANDGAP_THRESHOLD */
#define OMAP5430_T_HOT_MASK (0x3ff << 16)
#define OMAP5430_T_COLD_MASK (0x3ff << 0)
/* OMAP5430.TSHUT_THRESHOLD */
#define OMAP5430_TSHUT_HOT_MASK (0x3ff << 16)
#define OMAP5430_TSHUT_COLD_MASK (0x3ff << 0)
/* OMAP5430.BANDGAP_CUMUL_DTEMP_MPU */
#define OMAP5430_CUMUL_DTEMP_MPU_MASK (0xffffffff << 0)
/* OMAP5430.BANDGAP_CUMUL_DTEMP_GPU */
#define OMAP5430_CUMUL_DTEMP_GPU_MASK (0xffffffff << 0)
/* OMAP5430.BANDGAP_CUMUL_DTEMP_CORE */
#define OMAP5430_CUMUL_DTEMP_CORE_MASK (0xffffffff << 0)
/* OMAP5430.BANDGAP_STATUS */
#define OMAP5430_BGAP_ALERT_MASK BIT(31)
#define OMAP5430_HOT_CORE_FLAG_MASK BIT(5)
#define OMAP5430_COLD_CORE_FLAG_MASK BIT(4)
#define OMAP5430_HOT_GPU_FLAG_MASK BIT(3)
#define OMAP5430_COLD_GPU_FLAG_MASK BIT(2)
#define OMAP5430_HOT_MPU_FLAG_MASK BIT(1)
#define OMAP5430_COLD_MPU_FLAG_MASK BIT(0)
/**
* Temperature limits and thresholds for OMAP5430
*
* All the macros bellow are definitions for handling the
* ADC conversions and representation of temperature limits
* and thresholds for OMAP5430. Definitions are grouped
* by temperature domain.
*/
/* OMAP5430.common temperature definitions */
/* ADC conversion table limits */
#define OMAP5430_ADC_START_VALUE 540
#define OMAP5430_ADC_END_VALUE 945
/* OMAP5430.GPU temperature definitions */
/* bandgap clock limits */
#define OMAP5430_GPU_MAX_FREQ 1500000
#define OMAP5430_GPU_MIN_FREQ 1000000
/* sensor limits */
#define OMAP5430_GPU_MIN_TEMP -40000
#define OMAP5430_GPU_MAX_TEMP 125000
#define OMAP5430_GPU_HYST_VAL 5000
/* interrupts thresholds */
#define OMAP5430_GPU_TSHUT_HOT 915
#define OMAP5430_GPU_TSHUT_COLD 900
#define OMAP5430_GPU_T_HOT 800
#define OMAP5430_GPU_T_COLD 795
/* OMAP5430.MPU temperature definitions */
/* bandgap clock limits */
#define OMAP5430_MPU_MAX_FREQ 1500000
#define OMAP5430_MPU_MIN_FREQ 1000000
/* sensor limits */
#define OMAP5430_MPU_MIN_TEMP -40000
#define OMAP5430_MPU_MAX_TEMP 125000
#define OMAP5430_MPU_HYST_VAL 5000
/* interrupts thresholds */
#define OMAP5430_MPU_TSHUT_HOT 915
#define OMAP5430_MPU_TSHUT_COLD 900
#define OMAP5430_MPU_T_HOT 800
#define OMAP5430_MPU_T_COLD 795
/* OMAP5430.CORE temperature definitions */
/* bandgap clock limits */
#define OMAP5430_CORE_MAX_FREQ 1500000
#define OMAP5430_CORE_MIN_FREQ 1000000
/* sensor limits */
#define OMAP5430_CORE_MIN_TEMP -40000
#define OMAP5430_CORE_MAX_TEMP 125000
#define OMAP5430_CORE_HYST_VAL 5000
/* interrupts thresholds */
#define OMAP5430_CORE_TSHUT_HOT 915
#define OMAP5430_CORE_TSHUT_COLD 900
#define OMAP5430_CORE_T_HOT 800
#define OMAP5430_CORE_T_COLD 795
#endif /* __OMAP5XXX_BANDGAP_H */

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/*
* OMAP4 Bandgap temperature sensor driver
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
* Contact:
* Eduardo Valentin <eduardo.valentin@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#ifndef __TI_BANDGAP_H
#define __TI_BANDGAP_H
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/err.h>
/**
* DOC: bandgap driver data structure
* ==================================
*
* +----------+----------------+
* | struct temp_sensor_regval |
* +---------------------------+
* * (Array of)
* |
* |
* +-------------------+ +-----------------+
* | struct ti_bandgap |-->| struct device * |
* +----------+--------+ +-----------------+
* |
* |
* V
* +------------------------+
* | struct ti_bandgap_data |
* +------------------------+
* |
* |
* * (Array of)
* +------------+------------------------------------------------------+
* | +----------+------------+ +-------------------------+ |
* | | struct ti_temp_sensor |-->| struct temp_sensor_data | |
* | +-----------------------+ +------------+------------+ |
* | | |
* | + |
* | V |
* | +----------+-------------------+ |
* | | struct temp_sensor_registers | |
* | +------------------------------+ |
* | |
* +-------------------------------------------------------------------+
*
* Above is a simple diagram describing how the data structure below
* are organized. For each bandgap device there should be a ti_bandgap_data
* containing the device instance configuration, as well as, an array of
* sensors, representing every sensor instance present in this bandgap.
*/
/**
* struct temp_sensor_registers - descriptor to access registers and bitfields
* @temp_sensor_ctrl: TEMP_SENSOR_CTRL register offset
* @bgap_tempsoff_mask: mask to temp_sensor_ctrl.tempsoff
* @bgap_soc_mask: mask to temp_sensor_ctrl.soc
* @bgap_eocz_mask: mask to temp_sensor_ctrl.eocz
* @bgap_dtemp_mask: mask to temp_sensor_ctrl.dtemp
* @bgap_mask_ctrl: BANDGAP_MASK_CTRL register offset
* @mask_hot_mask: mask to bandgap_mask_ctrl.mask_hot
* @mask_cold_mask: mask to bandgap_mask_ctrl.mask_cold
* @mask_sidlemode_mask: mask to bandgap_mask_ctrl.mask_sidlemode
* @mask_counter_delay_mask: mask to bandgap_mask_ctrl.mask_counter_delay
* @mask_freeze_mask: mask to bandgap_mask_ctrl.mask_free
* @mask_clear_mask: mask to bandgap_mask_ctrl.mask_clear
* @mask_clear_accum_mask: mask to bandgap_mask_ctrl.mask_clear_accum
* @bgap_mode_ctrl: BANDGAP_MODE_CTRL register offset
* @mode_ctrl_mask: mask to bandgap_mode_ctrl.mode_ctrl
* @bgap_counter: BANDGAP_COUNTER register offset
* @counter_mask: mask to bandgap_counter.counter
* @bgap_threshold: BANDGAP_THRESHOLD register offset (TALERT thresholds)
* @threshold_thot_mask: mask to bandgap_threhold.thot
* @threshold_tcold_mask: mask to bandgap_threhold.tcold
* @tshut_threshold: TSHUT_THRESHOLD register offset (TSHUT thresholds)
* @tshut_efuse_mask: mask to tshut_threshold.tshut_efuse
* @tshut_efuse_shift: shift to tshut_threshold.tshut_efuse
* @tshut_hot_mask: mask to tshut_threhold.thot
* @tshut_cold_mask: mask to tshut_threhold.thot
* @bgap_status: BANDGAP_STATUS register offset
* @status_clean_stop_mask: mask to bandgap_status.clean_stop
* @status_bgap_alert_mask: mask to bandgap_status.bandgap_alert
* @status_hot_mask: mask to bandgap_status.hot
* @status_cold_mask: mask to bandgap_status.cold
* @bgap_cumul_dtemp: BANDGAP_CUMUL_DTEMP register offset
* @ctrl_dtemp_0: CTRL_DTEMP0 register offset
* @ctrl_dtemp_1: CTRL_DTEMP1 register offset
* @ctrl_dtemp_2: CTRL_DTEMP2 register offset
* @ctrl_dtemp_3: CTRL_DTEMP3 register offset
* @ctrl_dtemp_4: CTRL_DTEMP4 register offset
* @bgap_efuse: BANDGAP_EFUSE register offset
*
* The register offsets and bitfields might change across
* OMAP and variants versions. Hence this struct serves as a
* descriptor map on how to access the registers and the bitfields.
*
* This descriptor contains registers of all versions of bandgap chips.
* Not all versions will use all registers, depending on the available
* features. Please read TRMs for descriptive explanation on each bitfield.
*/
struct temp_sensor_registers {
u32 temp_sensor_ctrl;
u32 bgap_tempsoff_mask;
u32 bgap_soc_mask;
u32 bgap_eocz_mask; /* not used: but needs revisit */
u32 bgap_dtemp_mask;
u32 bgap_mask_ctrl;
u32 mask_hot_mask;
u32 mask_cold_mask;
u32 mask_sidlemode_mask; /* not used: but may be needed for pm */
u32 mask_counter_delay_mask;
u32 mask_freeze_mask;
u32 mask_clear_mask; /* not used: but needed for trending */
u32 mask_clear_accum_mask; /* not used: but needed for trending */
u32 bgap_mode_ctrl;
u32 mode_ctrl_mask;
u32 bgap_counter;
u32 counter_mask;
u32 bgap_threshold;
u32 threshold_thot_mask;
u32 threshold_tcold_mask;
u32 tshut_threshold;
u32 tshut_efuse_mask; /* not used */
u32 tshut_efuse_shift; /* not used */
u32 tshut_hot_mask;
u32 tshut_cold_mask;
u32 bgap_status;
u32 status_clean_stop_mask; /* not used: but needed for trending */
u32 status_bgap_alert_mask; /* not used */
u32 status_hot_mask;
u32 status_cold_mask;
u32 bgap_cumul_dtemp; /* not used: but needed for trending */
u32 ctrl_dtemp_0; /* not used: but needed for trending */
u32 ctrl_dtemp_1; /* not used: but needed for trending */
u32 ctrl_dtemp_2; /* not used: but needed for trending */
u32 ctrl_dtemp_3; /* not used: but needed for trending */
u32 ctrl_dtemp_4; /* not used: but needed for trending */
u32 bgap_efuse;
};
/**
* struct temp_sensor_data - The thresholds and limits for temperature sensors.
* @tshut_hot: temperature to trigger a thermal reset (initial value)
* @tshut_cold: temp to get the plat out of reset due to thermal (init val)
* @t_hot: temperature to trigger a thermal alert (high initial value)
* @t_cold: temperature to trigger a thermal alert (low initial value)
* @min_freq: sensor minimum clock rate
* @max_freq: sensor maximum clock rate
* @max_temp: sensor maximum temperature
* @min_temp: sensor minimum temperature
* @hyst_val: temperature hysteresis considered while converting ADC values
* @update_int1: update interval
* @update_int2: update interval
*
* This data structure will hold the required thresholds and temperature limits
* for a specific temperature sensor, like shutdown temperature, alert
* temperature, clock / rate used, ADC conversion limits and update intervals
*/
struct temp_sensor_data {
u32 tshut_hot;
u32 tshut_cold;
u32 t_hot;
u32 t_cold;
u32 min_freq;
u32 max_freq;
int max_temp;
int min_temp;
int hyst_val;
u32 update_int1; /* not used */
u32 update_int2; /* not used */
};
struct ti_bandgap_data;
/**
* struct temp_sensor_regval - temperature sensor register values and priv data
* @bg_mode_ctrl: temp sensor control register value
* @bg_ctrl: bandgap ctrl register value
* @bg_counter: bandgap counter value
* @bg_threshold: bandgap threshold register value
* @tshut_threshold: bandgap tshut register value
* @data: private data
*
* Data structure to save and restore bandgap register set context. Only
* required registers are shadowed, when needed.
*/
struct temp_sensor_regval {
u32 bg_mode_ctrl;
u32 bg_ctrl;
u32 bg_counter;
u32 bg_threshold;
u32 tshut_threshold;
void *data;
};
/**
* struct ti_bandgap - bandgap device structure
* @dev: struct device pointer
* @base: io memory base address
* @conf: struct with bandgap configuration set (# sensors, conv_table, etc)
* @regval: temperature sensor register values
* @fclock: pointer to functional clock of temperature sensor
* @div_clk: pointer to divider clock of temperature sensor fclk
* @lock: spinlock for ti_bandgap structure
* @irq: MPU IRQ number for thermal alert
* @tshut_gpio: GPIO where Tshut signal is routed
* @clk_rate: Holds current clock rate
*
* The bandgap device structure representing the bandgap device instance.
* It holds most of the dynamic stuff. Configurations and sensor specific
* entries are inside the @conf structure.
*/
struct ti_bandgap {
struct device *dev;
void __iomem *base;
const struct ti_bandgap_data *conf;
struct temp_sensor_regval *regval;
struct clk *fclock;
struct clk *div_clk;
spinlock_t lock; /* shields this struct */
int irq;
int tshut_gpio;
u32 clk_rate;
};
/**
* struct ti_temp_sensor - bandgap temperature sensor configuration data
* @ts_data: pointer to struct with thresholds, limits of temperature sensor
* @registers: pointer to the list of register offsets and bitfields
* @domain: the name of the domain where the sensor is located
* @slope: sensor gradient slope info for hotspot extrapolation equation
* @constant: sensor gradient const info for hotspot extrapolation equation
* @slope_pcb: sensor gradient slope info for hotspot extrapolation equation
* with no external influence
* @constant_pcb: sensor gradient const info for hotspot extrapolation equation
* with no external influence
* @register_cooling: function to describe how this sensor is going to be cooled
* @unregister_cooling: function to release cooling data
*
* Data structure to describe a temperature sensor handled by a bandgap device.
* It should provide configuration details on this sensor, such as how to
* access the registers affecting this sensor, shadow register buffer, how to
* assess the gradient from hotspot, how to cooldown the domain when sensor
* reports too hot temperature.
*/
struct ti_temp_sensor {
struct temp_sensor_data *ts_data;
struct temp_sensor_registers *registers;
char *domain;
/* for hotspot extrapolation */
const int slope;
const int constant;
const int slope_pcb;
const int constant_pcb;
int (*register_cooling)(struct ti_bandgap *bgp, int id);
int (*unregister_cooling)(struct ti_bandgap *bgp, int id);
};
/**
* DOC: ti bandgap feature types
*
* TI_BANDGAP_FEATURE_TSHUT - used when the thermal shutdown signal output
* of a bandgap device instance is routed to the processor. This means
* the system must react and perform the shutdown by itself (handle an
* IRQ, for instance).
*
* TI_BANDGAP_FEATURE_TSHUT_CONFIG - used when the bandgap device has control
* over the thermal shutdown configuration. This means that the thermal
* shutdown thresholds are programmable, for instance.
*
* TI_BANDGAP_FEATURE_TALERT - used when the bandgap device instance outputs
* a signal representing violation of programmable alert thresholds.
*
* TI_BANDGAP_FEATURE_MODE_CONFIG - used when it is possible to choose which
* mode, continuous or one shot, the bandgap device instance will operate.
*
* TI_BANDGAP_FEATURE_COUNTER - used when the bandgap device instance allows
* programming the update interval of its internal state machine.
*
* TI_BANDGAP_FEATURE_POWER_SWITCH - used when the bandgap device allows
* itself to be switched on/off.
*
* TI_BANDGAP_FEATURE_CLK_CTRL - used when the clocks feeding the bandgap
* device are gateable or not.
*
* TI_BANDGAP_FEATURE_FREEZE_BIT - used when the bandgap device features
* a history buffer that its update can be freezed/unfreezed.
*
* TI_BANDGAP_FEATURE_COUNTER_DELAY - used when the bandgap device features
* a delay programming based on distinct values.
*
* TI_BANDGAP_FEATURE_HISTORY_BUFFER - used when the bandgap device features
* a history buffer of temperatures.
*
* TI_BANDGAP_HAS(b, f) - macro to check if a bandgap device is capable of a
* specific feature (above) or not. Return non-zero, if yes.
*/
#define TI_BANDGAP_FEATURE_TSHUT BIT(0)
#define TI_BANDGAP_FEATURE_TSHUT_CONFIG BIT(1)
#define TI_BANDGAP_FEATURE_TALERT BIT(2)
#define TI_BANDGAP_FEATURE_MODE_CONFIG BIT(3)
#define TI_BANDGAP_FEATURE_COUNTER BIT(4)
#define TI_BANDGAP_FEATURE_POWER_SWITCH BIT(5)
#define TI_BANDGAP_FEATURE_CLK_CTRL BIT(6)
#define TI_BANDGAP_FEATURE_FREEZE_BIT BIT(7)
#define TI_BANDGAP_FEATURE_COUNTER_DELAY BIT(8)
#define TI_BANDGAP_FEATURE_HISTORY_BUFFER BIT(9)
#define TI_BANDGAP_HAS(b, f) \
((b)->conf->features & TI_BANDGAP_FEATURE_ ## f)
/**
* struct ti_bandgap_data - ti bandgap data configuration structure
* @features: a bitwise flag set to describe the device features
* @conv_table: Pointer to ADC to temperature conversion table
* @adc_start_val: ADC conversion table starting value
* @adc_end_val: ADC conversion table ending value
* @fclock_name: clock name of the functional clock
* @div_ck_name: clock name of the clock divisor
* @sensor_count: count of temperature sensor within this bandgap device
* @report_temperature: callback to report thermal alert to thermal API
* @expose_sensor: callback to export sensor to thermal API
* @remove_sensor: callback to destroy sensor from thermal API
* @sensors: array of sensors present in this bandgap instance
*
* This is a data structure which should hold most of the static configuration
* of a bandgap device instance. It should describe which features this instance
* is capable of, the clock names to feed this device, the amount of sensors and
* their configuration representation, and how to export and unexport them to
* a thermal API.
*/
struct ti_bandgap_data {
unsigned int features;
const int *conv_table;
u32 adc_start_val;
u32 adc_end_val;
char *fclock_name;
char *div_ck_name;
int sensor_count;
int (*report_temperature)(struct ti_bandgap *bgp, int id);
int (*expose_sensor)(struct ti_bandgap *bgp, int id, char *domain);
int (*remove_sensor)(struct ti_bandgap *bgp, int id);
/* this needs to be at the end */
struct ti_temp_sensor sensors[];
};
int ti_bandgap_read_thot(struct ti_bandgap *bgp, int id, int *thot);
int ti_bandgap_write_thot(struct ti_bandgap *bgp, int id, int val);
int ti_bandgap_read_tcold(struct ti_bandgap *bgp, int id, int *tcold);
int ti_bandgap_write_tcold(struct ti_bandgap *bgp, int id, int val);
int ti_bandgap_read_update_interval(struct ti_bandgap *bgp, int id,
int *interval);
int ti_bandgap_write_update_interval(struct ti_bandgap *bgp, int id,
u32 interval);
int ti_bandgap_read_temperature(struct ti_bandgap *bgp, int id,
int *temperature);
int ti_bandgap_set_sensor_data(struct ti_bandgap *bgp, int id, void *data);
void *ti_bandgap_get_sensor_data(struct ti_bandgap *bgp, int id);
int ti_bandgap_get_trend(struct ti_bandgap *bgp, int id, int *trend);
#ifdef CONFIG_OMAP4_THERMAL
extern const struct ti_bandgap_data omap4430_data;
extern const struct ti_bandgap_data omap4460_data;
extern const struct ti_bandgap_data omap4470_data;
#else
#define omap4430_data NULL
#define omap4460_data NULL
#define omap4470_data NULL
#endif
#ifdef CONFIG_OMAP5_THERMAL
extern const struct ti_bandgap_data omap5430_data;
#else
#define omap5430_data NULL
#endif
#ifdef CONFIG_DRA752_THERMAL
extern const struct ti_bandgap_data dra752_data;
#else
#define dra752_data NULL
#endif
#endif

433
drivers/thermal/ti-soc-thermal/ti-thermal-common.c Normal file
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/*
* OMAP thermal driver interface
*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Contact:
* Eduardo Valentin <eduardo.valentin@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#include <linux/device.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <linux/gfp.h>
#include <linux/kernel.h>
#include <linux/workqueue.h>
#include <linux/thermal.h>
#include <linux/cpufreq.h>
#include <linux/cpumask.h>
#include <linux/cpu_cooling.h>
#include <linux/of.h>
#include "ti-thermal.h"
#include "ti-bandgap.h"
/* common data structures */
struct ti_thermal_data {
struct thermal_zone_device *ti_thermal;
struct thermal_zone_device *pcb_tz;
struct thermal_cooling_device *cool_dev;
struct ti_bandgap *bgp;
enum thermal_device_mode mode;
struct work_struct thermal_wq;
int sensor_id;
bool our_zone;
};
static void ti_thermal_work(struct work_struct *work)
{
struct ti_thermal_data *data = container_of(work,
struct ti_thermal_data, thermal_wq);
thermal_zone_device_update(data->ti_thermal);
dev_dbg(&data->ti_thermal->device, "updated thermal zone %s\n",
data->ti_thermal->type);
}
/**
* ti_thermal_hotspot_temperature - returns sensor extrapolated temperature
* @t: omap sensor temperature
* @s: omap sensor slope value
* @c: omap sensor const value
*/
static inline int ti_thermal_hotspot_temperature(int t, int s, int c)
{
int delta = t * s / 1000 + c;
if (delta < 0)
delta = 0;
return t + delta;
}
/* thermal zone ops */
/* Get temperature callback function for thermal zone*/
static inline int __ti_thermal_get_temp(void *devdata, long *temp)
{
struct thermal_zone_device *pcb_tz = NULL;
struct ti_thermal_data *data = devdata;
struct ti_bandgap *bgp;
const struct ti_temp_sensor *s;
int ret, tmp, slope, constant;
unsigned long pcb_temp;
if (!data)
return 0;
bgp = data->bgp;
s = &bgp->conf->sensors[data->sensor_id];
ret = ti_bandgap_read_temperature(bgp, data->sensor_id, &tmp);
if (ret)
return ret;
/* Default constants */
slope = s->slope;
constant = s->constant;
pcb_tz = data->pcb_tz;
/* In case pcb zone is available, use the extrapolation rule with it */
if (!IS_ERR(pcb_tz)) {
ret = thermal_zone_get_temp(pcb_tz, &pcb_temp);
if (!ret) {
tmp -= pcb_temp; /* got a valid PCB temp */
slope = s->slope_pcb;
constant = s->constant_pcb;
} else {
dev_err(bgp->dev,
"Failed to read PCB state. Using defaults\n");
ret = 0;
}
}
*temp = ti_thermal_hotspot_temperature(tmp, slope, constant);
return ret;
}
static inline int ti_thermal_get_temp(struct thermal_zone_device *thermal,
unsigned long *temp)
{
struct ti_thermal_data *data = thermal->devdata;
return __ti_thermal_get_temp(data, temp);
}
/* Bind callback functions for thermal zone */
static int ti_thermal_bind(struct thermal_zone_device *thermal,
struct thermal_cooling_device *cdev)
{
struct ti_thermal_data *data = thermal->devdata;
int id;
if (!data || IS_ERR(data))
return -ENODEV;
/* check if this is the cooling device we registered */
if (data->cool_dev != cdev)
return 0;
id = data->sensor_id;
/* Simple thing, two trips, one passive another critical */
return thermal_zone_bind_cooling_device(thermal, 0, cdev,
/* bind with min and max states defined by cpu_cooling */
THERMAL_NO_LIMIT,
THERMAL_NO_LIMIT);
}
/* Unbind callback functions for thermal zone */
static int ti_thermal_unbind(struct thermal_zone_device *thermal,
struct thermal_cooling_device *cdev)
{
struct ti_thermal_data *data = thermal->devdata;
if (!data || IS_ERR(data))
return -ENODEV;
/* check if this is the cooling device we registered */
if (data->cool_dev != cdev)
return 0;
/* Simple thing, two trips, one passive another critical */
return thermal_zone_unbind_cooling_device(thermal, 0, cdev);
}
/* Get mode callback functions for thermal zone */
static int ti_thermal_get_mode(struct thermal_zone_device *thermal,
enum thermal_device_mode *mode)
{
struct ti_thermal_data *data = thermal->devdata;
if (data)
*mode = data->mode;
return 0;
}
/* Set mode callback functions for thermal zone */
static int ti_thermal_set_mode(struct thermal_zone_device *thermal,
enum thermal_device_mode mode)
{
struct ti_thermal_data *data = thermal->devdata;
struct ti_bandgap *bgp;
bgp = data->bgp;
if (!data->ti_thermal) {
dev_notice(&thermal->device, "thermal zone not registered\n");
return 0;
}
mutex_lock(&data->ti_thermal->lock);
if (mode == THERMAL_DEVICE_ENABLED)
data->ti_thermal->polling_delay = FAST_TEMP_MONITORING_RATE;
else
data->ti_thermal->polling_delay = 0;
mutex_unlock(&data->ti_thermal->lock);
data->mode = mode;
ti_bandgap_write_update_interval(bgp, data->sensor_id,
data->ti_thermal->polling_delay);
thermal_zone_device_update(data->ti_thermal);
dev_dbg(&thermal->device, "thermal polling set for duration=%d msec\n",
data->ti_thermal->polling_delay);
return 0;
}
/* Get trip type callback functions for thermal zone */
static int ti_thermal_get_trip_type(struct thermal_zone_device *thermal,
int trip, enum thermal_trip_type *type)
{
if (!ti_thermal_is_valid_trip(trip))
return -EINVAL;
if (trip + 1 == OMAP_TRIP_NUMBER)
*type = THERMAL_TRIP_CRITICAL;
else
*type = THERMAL_TRIP_PASSIVE;
return 0;
}
/* Get trip temperature callback functions for thermal zone */
static int ti_thermal_get_trip_temp(struct thermal_zone_device *thermal,
int trip, unsigned long *temp)
{
if (!ti_thermal_is_valid_trip(trip))
return -EINVAL;
*temp = ti_thermal_get_trip_value(trip);
return 0;
}
static int __ti_thermal_get_trend(void *p, long *trend)
{
struct ti_thermal_data *data = p;
struct ti_bandgap *bgp;
int id, tr, ret = 0;
bgp = data->bgp;
id = data->sensor_id;
ret = ti_bandgap_get_trend(bgp, id, &tr);
if (ret)
return ret;
*trend = tr;
return 0;
}
/* Get the temperature trend callback functions for thermal zone */
static int ti_thermal_get_trend(struct thermal_zone_device *thermal,
int trip, enum thermal_trend *trend)
{
int ret;
long tr;
ret = __ti_thermal_get_trend(thermal->devdata, &tr);
if (ret)
return ret;
if (tr > 0)
*trend = THERMAL_TREND_RAISING;
else if (tr < 0)
*trend = THERMAL_TREND_DROPPING;
else
*trend = THERMAL_TREND_STABLE;
return 0;
}
/* Get critical temperature callback functions for thermal zone */
static int ti_thermal_get_crit_temp(struct thermal_zone_device *thermal,
unsigned long *temp)
{
/* shutdown zone */
return ti_thermal_get_trip_temp(thermal, OMAP_TRIP_NUMBER - 1, temp);
}
static struct thermal_zone_device_ops ti_thermal_ops = {
.get_temp = ti_thermal_get_temp,
.get_trend = ti_thermal_get_trend,
.bind = ti_thermal_bind,
.unbind = ti_thermal_unbind,
.get_mode = ti_thermal_get_mode,
.set_mode = ti_thermal_set_mode,
.get_trip_type = ti_thermal_get_trip_type,
.get_trip_temp = ti_thermal_get_trip_temp,
.get_crit_temp = ti_thermal_get_crit_temp,
};
static struct ti_thermal_data
*ti_thermal_build_data(struct ti_bandgap *bgp, int id)
{
struct ti_thermal_data *data;
data = devm_kzalloc(bgp->dev, sizeof(*data), GFP_KERNEL);
if (!data) {
dev_err(bgp->dev, "kzalloc fail\n");
return NULL;
}
data->sensor_id = id;
data->bgp = bgp;
data->mode = THERMAL_DEVICE_ENABLED;
/* pcb_tz will be either valid or PTR_ERR() */
data->pcb_tz = thermal_zone_get_zone_by_name("pcb");
INIT_WORK(&data->thermal_wq, ti_thermal_work);
return data;
}
int ti_thermal_expose_sensor(struct ti_bandgap *bgp, int id,
char *domain)
{
struct ti_thermal_data *data;
data = ti_bandgap_get_sensor_data(bgp, id);
if (!data || IS_ERR(data))
data = ti_thermal_build_data(bgp, id);
if (!data)
return -EINVAL;
/* in case this is specified by DT */
data->ti_thermal = thermal_zone_of_sensor_register(bgp->dev, id,
data, __ti_thermal_get_temp,
__ti_thermal_get_trend);
if (IS_ERR(data->ti_thermal)) {
/* Create thermal zone */
data->ti_thermal = thermal_zone_device_register(domain,
OMAP_TRIP_NUMBER, 0, data, &ti_thermal_ops,
NULL, FAST_TEMP_MONITORING_RATE,
FAST_TEMP_MONITORING_RATE);
if (IS_ERR(data->ti_thermal)) {
dev_err(bgp->dev, "thermal zone device is NULL\n");
return PTR_ERR(data->ti_thermal);
}
data->ti_thermal->polling_delay = FAST_TEMP_MONITORING_RATE;
data->our_zone = true;
}
ti_bandgap_set_sensor_data(bgp, id, data);
ti_bandgap_write_update_interval(bgp, data->sensor_id,
data->ti_thermal->polling_delay);
return 0;
}
int ti_thermal_remove_sensor(struct ti_bandgap *bgp, int id)
{
struct ti_thermal_data *data;
data = ti_bandgap_get_sensor_data(bgp, id);
if (data && data->ti_thermal) {
if (data->our_zone)
thermal_zone_device_unregister(data->ti_thermal);
else
thermal_zone_of_sensor_unregister(bgp->dev,
data->ti_thermal);
}
return 0;
}
int ti_thermal_report_sensor_temperature(struct ti_bandgap *bgp, int id)
{
struct ti_thermal_data *data;
data = ti_bandgap_get_sensor_data(bgp, id);
schedule_work(&data->thermal_wq);
return 0;
}
int ti_thermal_register_cpu_cooling(struct ti_bandgap *bgp, int id)
{
struct ti_thermal_data *data;
struct device_node *np = bgp->dev->of_node;
/*
* We are assuming here that if one deploys the zone
* using DT, then it must be aware that the cooling device
* loading has to happen via cpufreq driver.
*/
if (of_find_property(np, "#thermal-sensor-cells", NULL))
return 0;
data = ti_bandgap_get_sensor_data(bgp, id);
if (!data || IS_ERR(data))
data = ti_thermal_build_data(bgp, id);
if (!data)
return -EINVAL;
if (!cpufreq_get_current_driver()) {
dev_dbg(bgp->dev, "no cpufreq driver yet\n");
return -EPROBE_DEFER;
}
/* Register cooling device */
data->cool_dev = cpufreq_cooling_register(cpu_present_mask);
if (IS_ERR(data->cool_dev)) {
dev_err(bgp->dev,
"Failed to register cpufreq cooling device\n");
return PTR_ERR(data->cool_dev);
}
ti_bandgap_set_sensor_data(bgp, id, data);
return 0;
}
int ti_thermal_unregister_cpu_cooling(struct ti_bandgap *bgp, int id)
{
struct ti_thermal_data *data;
data = ti_bandgap_get_sensor_data(bgp, id);
if (data && data->cool_dev)
cpufreq_cooling_unregister(data->cool_dev);
return 0;
}

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drivers/thermal/ti-soc-thermal/ti-thermal.h Normal file
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/*
* OMAP thermal definitions
*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
* Contact:
* Eduardo Valentin <eduardo.valentin@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*
*/
#ifndef __TI_THERMAL_H
#define __TI_THERMAL_H
#include "ti-bandgap.h"
/* sensors gradient and offsets */
#define OMAP_GRADIENT_SLOPE_4430 0
#define OMAP_GRADIENT_CONST_4430 20000
#define OMAP_GRADIENT_SLOPE_4460 348
#define OMAP_GRADIENT_CONST_4460 -9301
#define OMAP_GRADIENT_SLOPE_4470 308
#define OMAP_GRADIENT_CONST_4470 -7896
#define OMAP_GRADIENT_SLOPE_5430_CPU 65
#define OMAP_GRADIENT_CONST_5430_CPU -1791
#define OMAP_GRADIENT_SLOPE_5430_GPU 117
#define OMAP_GRADIENT_CONST_5430_GPU -2992
#define DRA752_GRADIENT_SLOPE 0
#define DRA752_GRADIENT_CONST 2000
/* PCB sensor calculation constants */
#define OMAP_GRADIENT_SLOPE_W_PCB_4430 0
#define OMAP_GRADIENT_CONST_W_PCB_4430 20000
#define OMAP_GRADIENT_SLOPE_W_PCB_4460 1142
#define OMAP_GRADIENT_CONST_W_PCB_4460 -393
#define OMAP_GRADIENT_SLOPE_W_PCB_4470 1063
#define OMAP_GRADIENT_CONST_W_PCB_4470 -477
#define OMAP_GRADIENT_SLOPE_W_PCB_5430_CPU 100
#define OMAP_GRADIENT_CONST_W_PCB_5430_CPU 484
#define OMAP_GRADIENT_SLOPE_W_PCB_5430_GPU 464
#define OMAP_GRADIENT_CONST_W_PCB_5430_GPU -5102
#define DRA752_GRADIENT_SLOPE_W_PCB 0
#define DRA752_GRADIENT_CONST_W_PCB 2000
/* trip points of interest in milicelsius (at hotspot level) */
#define OMAP_TRIP_COLD 100000
#define OMAP_TRIP_HOT 110000
#define OMAP_TRIP_SHUTDOWN 125000
#define OMAP_TRIP_NUMBER 2
#define OMAP_TRIP_STEP \
((OMAP_TRIP_SHUTDOWN - OMAP_TRIP_HOT) / (OMAP_TRIP_NUMBER - 1))
/* Update rates */
#define FAST_TEMP_MONITORING_RATE 250
/* helper macros */
/**
* ti_thermal_get_trip_value - returns trip temperature based on index
* @i: trip index
*/
#define ti_thermal_get_trip_value(i) \
(OMAP_TRIP_HOT + ((i) * OMAP_TRIP_STEP))
/**
* ti_thermal_is_valid_trip - check for trip index
* @i: trip index
*/
#define ti_thermal_is_valid_trip(trip) \
((trip) >= 0 && (trip) < OMAP_TRIP_NUMBER)
#ifdef CONFIG_TI_THERMAL
int ti_thermal_expose_sensor(struct ti_bandgap *bgp, int id, char *domain);
int ti_thermal_remove_sensor(struct ti_bandgap *bgp, int id);
int ti_thermal_report_sensor_temperature(struct ti_bandgap *bgp, int id);
int ti_thermal_register_cpu_cooling(struct ti_bandgap *bgp, int id);
int ti_thermal_unregister_cpu_cooling(struct ti_bandgap *bgp, int id);
#else
static inline
int ti_thermal_expose_sensor(struct ti_bandgap *bgp, int id, char *domain)
{
return 0;
}
static inline
int ti_thermal_remove_sensor(struct ti_bandgap *bgp, int id)
{
return 0;
}
static inline
int ti_thermal_report_sensor_temperature(struct ti_bandgap *bgp, int id)
{
return 0;
}
static inline
int ti_thermal_register_cpu_cooling(struct ti_bandgap *bgp, int id)
{
return 0;
}
static inline
int ti_thermal_unregister_cpu_cooling(struct ti_bandgap *bgp, int id)
{
return 0;
}
#endif
#endif