mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-11-02 00:55:37 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
403
drivers/usb/gadget/udc/net2280.h
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403
drivers/usb/gadget/udc/net2280.h
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@ -0,0 +1,403 @@
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/*
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* NetChip 2280 high/full speed USB device controller.
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* Unlike many such controllers, this one talks PCI.
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*/
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/*
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* Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com)
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* Copyright (C) 2003 David Brownell
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* Copyright (C) 2014 Ricardo Ribalda - Qtechnology/AS
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/usb/net2280.h>
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#include <linux/usb/usb338x.h>
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/*-------------------------------------------------------------------------*/
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#ifdef __KERNEL__
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/* indexed registers [11.10] are accessed indirectly
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* caller must own the device lock.
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*/
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static inline u32 get_idx_reg(struct net2280_regs __iomem *regs, u32 index)
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{
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writel(index, ®s->idxaddr);
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/* NOTE: synchs device/cpu memory views */
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return readl(®s->idxdata);
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}
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static inline void
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set_idx_reg(struct net2280_regs __iomem *regs, u32 index, u32 value)
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{
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writel(index, ®s->idxaddr);
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writel(value, ®s->idxdata);
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/* posted, may not be visible yet */
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}
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#endif /* __KERNEL__ */
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#define PCI_VENDOR_ID_PLX_LEGACY 0x17cc
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#define PLX_LEGACY BIT(0)
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#define PLX_2280 BIT(1)
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#define PLX_SUPERSPEED BIT(2)
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#define REG_DIAG 0x0
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#define RETRY_COUNTER 16
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#define FORCE_PCI_SERR 11
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#define FORCE_PCI_INTERRUPT 10
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#define FORCE_USB_INTERRUPT 9
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#define FORCE_CPU_INTERRUPT 8
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#define ILLEGAL_BYTE_ENABLES 5
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#define FAST_TIMES 4
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#define FORCE_RECEIVE_ERROR 2
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#define FORCE_TRANSMIT_CRC_ERROR 0
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#define REG_FRAME 0x02 /* from last sof */
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#define REG_CHIPREV 0x03 /* in bcd */
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#define REG_HS_NAK_RATE 0x0a /* NAK per N uframes */
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#define CHIPREV_1 0x0100
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#define CHIPREV_1A 0x0110
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/* DEFECT 7374 */
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#define DEFECT_7374_NUMBEROF_MAX_WAIT_LOOPS 200
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#define DEFECT_7374_PROCESSOR_WAIT_TIME 10
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/* ep0 max packet size */
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#define EP0_SS_MAX_PACKET_SIZE 0x200
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#define EP0_HS_MAX_PACKET_SIZE 0x40
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#ifdef __KERNEL__
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/*-------------------------------------------------------------------------*/
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/* [8.3] for scatter/gather i/o
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* use struct net2280_dma_regs bitfields
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*/
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struct net2280_dma {
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__le32 dmacount;
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__le32 dmaaddr; /* the buffer */
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__le32 dmadesc; /* next dma descriptor */
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__le32 _reserved;
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} __aligned(16);
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/*-------------------------------------------------------------------------*/
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/* DRIVER DATA STRUCTURES and UTILITIES */
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struct net2280_ep {
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struct usb_ep ep;
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struct net2280_ep_regs __iomem *cfg;
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struct net2280_ep_regs __iomem *regs;
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struct net2280_dma_regs __iomem *dma;
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struct net2280_dma *dummy;
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struct usb338x_fifo_regs __iomem *fiforegs;
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dma_addr_t td_dma; /* of dummy */
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struct net2280 *dev;
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unsigned long irqs;
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unsigned is_halt:1, dma_started:1;
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/* analogous to a host-side qh */
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struct list_head queue;
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const struct usb_endpoint_descriptor *desc;
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unsigned num : 8,
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fifo_size : 12,
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in_fifo_validate : 1,
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out_overflow : 1,
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stopped : 1,
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wedged : 1,
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is_in : 1,
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is_iso : 1,
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responded : 1;
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};
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static inline void allow_status(struct net2280_ep *ep)
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{
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/* ep0 only */
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writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) |
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BIT(CLEAR_NAK_OUT_PACKETS) |
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BIT(CLEAR_NAK_OUT_PACKETS_MODE),
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&ep->regs->ep_rsp);
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ep->stopped = 1;
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}
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static void allow_status_338x(struct net2280_ep *ep)
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{
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/*
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* Control Status Phase Handshake was set by the chip when the setup
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* packet arrived. While set, the chip automatically NAKs the host's
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* Status Phase tokens.
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*/
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writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE), &ep->regs->ep_rsp);
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ep->stopped = 1;
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/* TD 9.9 Halt Endpoint test. TD 9.22 set feature test. */
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ep->responded = 0;
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}
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struct net2280_request {
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struct usb_request req;
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struct net2280_dma *td;
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dma_addr_t td_dma;
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struct list_head queue;
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unsigned mapped : 1,
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valid : 1;
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};
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struct net2280 {
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/* each pci device provides one gadget, several endpoints */
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struct usb_gadget gadget;
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spinlock_t lock;
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struct net2280_ep ep[9];
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struct usb_gadget_driver *driver;
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unsigned enabled : 1,
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protocol_stall : 1,
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softconnect : 1,
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got_irq : 1,
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region:1,
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u1_enable:1,
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u2_enable:1,
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ltm_enable:1,
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wakeup_enable:1,
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selfpowered:1,
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addressed_state:1;
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u16 chiprev;
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int enhanced_mode;
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int n_ep;
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kernel_ulong_t quirks;
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/* pci state used to access those endpoints */
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struct pci_dev *pdev;
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struct net2280_regs __iomem *regs;
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struct net2280_usb_regs __iomem *usb;
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struct usb338x_usb_ext_regs __iomem *usb_ext;
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struct net2280_pci_regs __iomem *pci;
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struct net2280_dma_regs __iomem *dma;
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struct net2280_dep_regs __iomem *dep;
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struct net2280_ep_regs __iomem *epregs;
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struct usb338x_fifo_regs __iomem *fiforegs;
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struct usb338x_ll_regs __iomem *llregs;
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struct usb338x_ll_lfps_regs __iomem *ll_lfps_regs;
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struct usb338x_ll_tsn_regs __iomem *ll_tsn_regs;
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struct usb338x_ll_chi_regs __iomem *ll_chicken_reg;
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struct usb338x_pl_regs __iomem *plregs;
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struct pci_pool *requests;
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/* statistics...*/
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};
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static inline void set_halt(struct net2280_ep *ep)
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{
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/* ep0 and bulk/intr endpoints */
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writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) |
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/* set NAK_OUT for erratum 0114 */
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((ep->dev->chiprev == CHIPREV_1) << SET_NAK_OUT_PACKETS) |
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BIT(SET_ENDPOINT_HALT),
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&ep->regs->ep_rsp);
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}
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static inline void clear_halt(struct net2280_ep *ep)
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{
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/* ep0 and bulk/intr endpoints */
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writel(BIT(CLEAR_ENDPOINT_HALT) |
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BIT(CLEAR_ENDPOINT_TOGGLE) |
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/*
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* unless the gadget driver left a short packet in the
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* fifo, this reverses the erratum 0114 workaround.
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*/
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((ep->dev->chiprev == CHIPREV_1) << CLEAR_NAK_OUT_PACKETS),
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&ep->regs->ep_rsp);
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}
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/*
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* FSM value for Defect 7374 (U1U2 Test) is managed in
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* chip's SCRATCH register:
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*/
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#define DEFECT7374_FSM_FIELD 28
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/* Waiting for Control Read:
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* - A transition to this state indicates a fresh USB connection,
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* before the first Setup Packet. The connection speed is not
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* known. Firmware is waiting for the first Control Read.
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* - Starting state: This state can be thought of as the FSM's typical
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* starting state.
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* - Tip: Upon the first SS Control Read the FSM never
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* returns to this state.
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*/
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#define DEFECT7374_FSM_WAITING_FOR_CONTROL_READ BIT(DEFECT7374_FSM_FIELD)
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/* Non-SS Control Read:
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* - A transition to this state indicates detection of the first HS
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* or FS Control Read.
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* - Tip: Upon the first SS Control Read the FSM never
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* returns to this state.
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*/
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#define DEFECT7374_FSM_NON_SS_CONTROL_READ (2 << DEFECT7374_FSM_FIELD)
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/* SS Control Read:
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* - A transition to this state indicates detection of the
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* first SS Control Read.
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* - This state indicates workaround completion. Workarounds no longer
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* need to be applied (as long as the chip remains powered up).
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* - Tip: Once in this state the FSM state does not change (until
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* the chip's power is lost and restored).
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* - This can be thought of as the final state of the FSM;
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* the FSM 'locks-up' in this state until the chip loses power.
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*/
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#define DEFECT7374_FSM_SS_CONTROL_READ (3 << DEFECT7374_FSM_FIELD)
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#ifdef USE_RDK_LEDS
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static inline void net2280_led_init(struct net2280 *dev)
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{
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/* LED3 (green) is on during USB activity. note erratum 0113. */
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writel(BIT(GPIO3_LED_SELECT) |
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BIT(GPIO3_OUTPUT_ENABLE) |
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BIT(GPIO2_OUTPUT_ENABLE) |
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BIT(GPIO1_OUTPUT_ENABLE) |
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BIT(GPIO0_OUTPUT_ENABLE),
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&dev->regs->gpioctl);
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}
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/* indicate speed with bi-color LED 0/1 */
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static inline
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void net2280_led_speed(struct net2280 *dev, enum usb_device_speed speed)
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{
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u32 val = readl(&dev->regs->gpioctl);
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switch (speed) {
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case USB_SPEED_SUPER: /* green + red */
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val |= BIT(GPIO0_DATA) | BIT(GPIO1_DATA);
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break;
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case USB_SPEED_HIGH: /* green */
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val &= ~BIT(GPIO0_DATA);
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val |= BIT(GPIO1_DATA);
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break;
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case USB_SPEED_FULL: /* red */
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val &= ~BIT(GPIO1_DATA);
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val |= BIT(GPIO0_DATA);
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break;
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default: /* (off/black) */
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val &= ~(BIT(GPIO1_DATA) | BIT(GPIO0_DATA));
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break;
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}
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writel(val, &dev->regs->gpioctl);
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}
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/* indicate power with LED 2 */
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static inline void net2280_led_active(struct net2280 *dev, int is_active)
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{
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u32 val = readl(&dev->regs->gpioctl);
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/* FIXME this LED never seems to turn on.*/
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if (is_active)
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val |= GPIO2_DATA;
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else
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val &= ~GPIO2_DATA;
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writel(val, &dev->regs->gpioctl);
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}
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static inline void net2280_led_shutdown(struct net2280 *dev)
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{
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/* turn off all four GPIO*_DATA bits */
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writel(readl(&dev->regs->gpioctl) & ~0x0f,
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&dev->regs->gpioctl);
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}
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#else
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#define net2280_led_init(dev) do { } while (0)
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#define net2280_led_speed(dev, speed) do { } while (0)
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#define net2280_led_shutdown(dev) do { } while (0)
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#endif
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/*-------------------------------------------------------------------------*/
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#define ep_dbg(ndev, fmt, args...) \
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dev_dbg((&((ndev)->pdev->dev)), fmt, ##args)
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#define ep_vdbg(ndev, fmt, args...) \
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dev_vdbg((&((ndev)->pdev->dev)), fmt, ##args)
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#define ep_info(ndev, fmt, args...) \
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dev_info((&((ndev)->pdev->dev)), fmt, ##args)
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#define ep_warn(ndev, fmt, args...) \
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dev_warn((&((ndev)->pdev->dev)), fmt, ##args)
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#define ep_err(ndev, fmt, args...) \
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dev_err((&((ndev)->pdev->dev)), fmt, ##args)
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/*-------------------------------------------------------------------------*/
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static inline void set_fifo_bytecount(struct net2280_ep *ep, unsigned count)
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{
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if (ep->dev->pdev->vendor == 0x17cc)
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writeb(count, 2 + (u8 __iomem *) &ep->regs->ep_cfg);
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else{
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u32 tmp = readl(&ep->cfg->ep_cfg) &
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(~(0x07 << EP_FIFO_BYTE_COUNT));
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writel(tmp | (count << EP_FIFO_BYTE_COUNT), &ep->cfg->ep_cfg);
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}
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}
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static inline void start_out_naking(struct net2280_ep *ep)
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{
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/* NOTE: hardware races lurk here, and PING protocol issues */
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writel(BIT(SET_NAK_OUT_PACKETS), &ep->regs->ep_rsp);
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/* synch with device */
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readl(&ep->regs->ep_rsp);
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}
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#ifdef DEBUG
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static inline void assert_out_naking(struct net2280_ep *ep, const char *where)
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{
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u32 tmp = readl(&ep->regs->ep_stat);
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if ((tmp & BIT(NAK_OUT_PACKETS)) == 0) {
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ep_dbg(ep->dev, "%s %s %08x !NAK\n",
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ep->ep.name, where, tmp);
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writel(BIT(SET_NAK_OUT_PACKETS),
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&ep->regs->ep_rsp);
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}
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}
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#define ASSERT_OUT_NAKING(ep) assert_out_naking(ep, __func__)
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#else
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#define ASSERT_OUT_NAKING(ep) do {} while (0)
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#endif
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static inline void stop_out_naking(struct net2280_ep *ep)
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{
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u32 tmp;
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tmp = readl(&ep->regs->ep_stat);
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if ((tmp & BIT(NAK_OUT_PACKETS)) != 0)
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writel(BIT(CLEAR_NAK_OUT_PACKETS), &ep->regs->ep_rsp);
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}
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static inline void set_max_speed(struct net2280_ep *ep, u32 max)
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{
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u32 reg;
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static const u32 ep_enhanced[9] = { 0x10, 0x60, 0x30, 0x80,
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0x50, 0x20, 0x70, 0x40, 0x90 };
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if (ep->dev->enhanced_mode)
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reg = ep_enhanced[ep->num];
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else{
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reg = (ep->num + 1) * 0x10;
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if (ep->dev->gadget.speed != USB_SPEED_HIGH)
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reg += 1;
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}
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set_idx_reg(ep->dev->regs, reg, max);
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}
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#endif /* __KERNEL__ */
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