mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 08:08:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
17
drivers/video/fbdev/i810/Makefile
Normal file
17
drivers/video/fbdev/i810/Makefile
Normal file
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@ -0,0 +1,17 @@
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#
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# Makefile for the Intel 810/815 framebuffer driver
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#
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obj-$(CONFIG_FB_I810) += i810fb.o
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i810fb-objs := i810_main.o i810_accel.o
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ifdef CONFIG_FB_I810_GTF
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i810fb-objs += i810_gtf.o
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else
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i810fb-objs += i810_dvt.o
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endif
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ifdef CONFIG_FB_I810_I2C
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i810fb-objs += i810-i2c.o
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endif
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175
drivers/video/fbdev/i810/i810-i2c.c
Normal file
175
drivers/video/fbdev/i810/i810-i2c.c
Normal file
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@ -0,0 +1,175 @@
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/*-*- linux-c -*-
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* linux/drivers/video/i810-i2c.c -- Intel 810/815 I2C support
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*
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* Copyright (C) 2004 Antonino Daplas<adaplas@pol.net>
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* All Rights Reserved
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*
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* This file is subject to the terms and conditions of the GNU General Public
|
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* License. See the file COPYING in the main directory of this archive for
|
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* more details.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/gfp.h>
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#include <linux/pci.h>
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#include <linux/fb.h>
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#include "i810.h"
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#include "i810_regs.h"
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#include "i810_main.h"
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#include "../edid.h"
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/* bit locations in the registers */
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#define SCL_DIR_MASK 0x0001
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#define SCL_DIR 0x0002
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#define SCL_VAL_MASK 0x0004
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#define SCL_VAL_OUT 0x0008
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#define SCL_VAL_IN 0x0010
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#define SDA_DIR_MASK 0x0100
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#define SDA_DIR 0x0200
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#define SDA_VAL_MASK 0x0400
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#define SDA_VAL_OUT 0x0800
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#define SDA_VAL_IN 0x1000
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#define DEBUG /* define this for verbose EDID parsing output */
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#ifdef DEBUG
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#define DPRINTK(fmt, args...) printk(fmt,## args)
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#else
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#define DPRINTK(fmt, args...)
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#endif
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static void i810i2c_setscl(void *data, int state)
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{
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struct i810fb_i2c_chan *chan = data;
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struct i810fb_par *par = chan->par;
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u8 __iomem *mmio = par->mmio_start_virtual;
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if (state)
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i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK | SCL_VAL_MASK);
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else
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i810_writel(mmio, chan->ddc_base, SCL_DIR | SCL_DIR_MASK | SCL_VAL_MASK);
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i810_readl(mmio, chan->ddc_base); /* flush posted write */
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}
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static void i810i2c_setsda(void *data, int state)
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{
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struct i810fb_i2c_chan *chan = data;
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struct i810fb_par *par = chan->par;
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u8 __iomem *mmio = par->mmio_start_virtual;
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if (state)
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i810_writel(mmio, chan->ddc_base, SDA_DIR_MASK | SDA_VAL_MASK);
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else
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i810_writel(mmio, chan->ddc_base, SDA_DIR | SDA_DIR_MASK | SDA_VAL_MASK);
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i810_readl(mmio, chan->ddc_base); /* flush posted write */
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}
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static int i810i2c_getscl(void *data)
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{
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struct i810fb_i2c_chan *chan = data;
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struct i810fb_par *par = chan->par;
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u8 __iomem *mmio = par->mmio_start_virtual;
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i810_writel(mmio, chan->ddc_base, SCL_DIR_MASK);
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i810_writel(mmio, chan->ddc_base, 0);
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return ((i810_readl(mmio, chan->ddc_base) & SCL_VAL_IN) != 0);
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}
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static int i810i2c_getsda(void *data)
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{
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struct i810fb_i2c_chan *chan = data;
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struct i810fb_par *par = chan->par;
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u8 __iomem *mmio = par->mmio_start_virtual;
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i810_writel(mmio, chan->ddc_base, SDA_DIR_MASK);
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i810_writel(mmio, chan->ddc_base, 0);
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return ((i810_readl(mmio, chan->ddc_base) & SDA_VAL_IN) != 0);
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}
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static int i810_setup_i2c_bus(struct i810fb_i2c_chan *chan, const char *name)
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{
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int rc;
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strcpy(chan->adapter.name, name);
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chan->adapter.owner = THIS_MODULE;
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chan->adapter.algo_data = &chan->algo;
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chan->adapter.dev.parent = &chan->par->dev->dev;
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chan->algo.setsda = i810i2c_setsda;
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chan->algo.setscl = i810i2c_setscl;
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chan->algo.getsda = i810i2c_getsda;
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chan->algo.getscl = i810i2c_getscl;
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chan->algo.udelay = 10;
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chan->algo.timeout = (HZ/2);
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chan->algo.data = chan;
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i2c_set_adapdata(&chan->adapter, chan);
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/* Raise SCL and SDA */
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chan->algo.setsda(chan, 1);
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chan->algo.setscl(chan, 1);
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udelay(20);
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rc = i2c_bit_add_bus(&chan->adapter);
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if (rc == 0)
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dev_dbg(&chan->par->dev->dev, "I2C bus %s registered.\n",name);
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else {
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dev_warn(&chan->par->dev->dev, "Failed to register I2C bus "
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"%s.\n", name);
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chan->par = NULL;
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}
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return rc;
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}
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void i810_create_i2c_busses(struct i810fb_par *par)
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{
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par->chan[0].par = par;
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par->chan[1].par = par;
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par->chan[2].par = par;
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par->chan[0].ddc_base = GPIOA;
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i810_setup_i2c_bus(&par->chan[0], "I810-DDC");
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par->chan[1].ddc_base = GPIOB;
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i810_setup_i2c_bus(&par->chan[1], "I810-I2C");
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par->chan[2].ddc_base = GPIOC;
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i810_setup_i2c_bus(&par->chan[2], "I810-GPIOC");
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}
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void i810_delete_i2c_busses(struct i810fb_par *par)
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{
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if (par->chan[0].par)
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i2c_del_adapter(&par->chan[0].adapter);
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par->chan[0].par = NULL;
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if (par->chan[1].par)
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i2c_del_adapter(&par->chan[1].adapter);
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par->chan[1].par = NULL;
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if (par->chan[2].par)
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i2c_del_adapter(&par->chan[2].adapter);
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par->chan[2].par = NULL;
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}
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int i810_probe_i2c_connector(struct fb_info *info, u8 **out_edid, int conn)
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{
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struct i810fb_par *par = info->par;
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u8 *edid = NULL;
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DPRINTK("i810-i2c: Probe DDC%i Bus\n", conn+1);
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if (conn < par->ddc_num) {
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edid = fb_ddc_read(&par->chan[conn].adapter);
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} else {
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const u8 *e = fb_firmware_edid(info->device);
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if (e != NULL) {
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DPRINTK("i810-i2c: Getting EDID from BIOS\n");
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edid = kmemdup(e, EDID_LENGTH, GFP_KERNEL);
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}
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}
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*out_edid = edid;
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return (edid) ? 0 : 1;
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}
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299
drivers/video/fbdev/i810/i810.h
Normal file
299
drivers/video/fbdev/i810/i810.h
Normal file
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@ -0,0 +1,299 @@
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/*-*- linux-c -*-
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* linux/drivers/video/i810.h -- Intel 810 General Definitions/Declarations
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*
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* Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>
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* All Rights Reserved
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*
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*
|
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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* more details.
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*/
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#ifndef __I810_H__
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#define __I810_H__
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#include <linux/list.h>
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#include <linux/agp_backend.h>
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#include <linux/fb.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <video/vga.h>
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/* Fence */
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#define TILEWALK_X (0 << 12)
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#define TILEWALK_Y (1 << 12)
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/* Raster ops */
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#define COLOR_COPY_ROP 0xF0
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#define PAT_COPY_ROP 0xCC
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#define CLEAR_ROP 0x00
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#define WHITE_ROP 0xFF
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#define INVERT_ROP 0x55
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#define XOR_ROP 0x5A
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/* 2D Engine definitions */
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#define SOLIDPATTERN 0x80000000
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#define NONSOLID 0x00000000
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#define BPP8 (0 << 24)
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#define BPP16 (1 << 24)
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#define BPP24 (2 << 24)
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#define PIXCONF8 (2 << 16)
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#define PIXCONF15 (4 << 16)
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#define PIXCONF16 (5 << 16)
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#define PIXCONF24 (6 << 16)
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#define PIXCONF32 (7 << 16)
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#define DYN_COLOR_EN (1 << 26)
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#define DYN_COLOR_DIS (0 << 26)
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#define INCREMENT 0x00000000
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#define DECREMENT (0x01 << 30)
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#define ARB_ON 0x00000001
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#define ARB_OFF 0x00000000
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#define SYNC_FLIP 0x00000000
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#define ASYNC_FLIP 0x00000040
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#define OPTYPE_MASK 0xE0000000
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#define PARSER_MASK 0x001F8000
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#define D2_MASK 0x001FC000 /* 2D mask */
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/* Instruction type */
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/* There are more but pertains to 3D */
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#define PARSER 0x00000000
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#define BLIT (0x02 << 29)
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#define RENDER (0x03 << 29)
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/* Parser */
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#define NOP 0x00 /* No operation, padding */
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#define BP_INT (0x01 << 23) /* Breakpoint interrupt */
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#define USR_INT (0x02 << 23) /* User interrupt */
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#define WAIT_FOR_EVNT (0x03 << 23) /* Wait for event */
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#define FLUSH (0x04 << 23)
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#define CONTEXT_SEL (0x05 << 23)
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#define REPORT_HEAD (0x07 << 23)
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#define ARB_ON_OFF (0x08 << 23)
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#define OVERLAY_FLIP (0x11 << 23)
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#define LOAD_SCAN_INC (0x12 << 23)
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#define LOAD_SCAN_EX (0x13 << 23)
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#define FRONT_BUFFER (0x14 << 23)
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#define DEST_BUFFER (0x15 << 23)
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#define Z_BUFFER (0x16 << 23)
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|
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#define STORE_DWORD_IMM (0x20 << 23)
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#define STORE_DWORD_IDX (0x21 << 23)
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#define BATCH_BUFFER (0x30 << 23)
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|
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/* Blit */
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#define SETUP_BLIT 0x00
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#define SETUP_MONO_PATTERN_SL_BLT (0x10 << 22)
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#define PIXEL_BLT (0x20 << 22)
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#define SCANLINE_BLT (0x21 << 22)
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#define TEXT_BLT (0x22 << 22)
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#define TEXT_IMM_BLT (0x30 << 22)
|
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#define COLOR_BLT (0x40 << 22)
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#define MONO_PAT_BLIT (0x42 << 22)
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#define SOURCE_COPY_BLIT (0x43 << 22)
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#define MONO_SOURCE_COPY_BLIT (0x44 << 22)
|
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#define SOURCE_COPY_IMMEDIATE (0x60 << 22)
|
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#define MONO_SOURCE_COPY_IMMEDIATE (0x61 << 22)
|
||||
|
||||
#define VERSION_MAJOR 0
|
||||
#define VERSION_MINOR 9
|
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#define VERSION_TEENIE 0
|
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#define BRANCH_VERSION ""
|
||||
|
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|
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/* mvo: intel i815 */
|
||||
#ifndef PCI_DEVICE_ID_INTEL_82815_100
|
||||
#define PCI_DEVICE_ID_INTEL_82815_100 0x1102
|
||||
#endif
|
||||
#ifndef PCI_DEVICE_ID_INTEL_82815_NOAGP
|
||||
#define PCI_DEVICE_ID_INTEL_82815_NOAGP 0x1112
|
||||
#endif
|
||||
#ifndef PCI_DEVICE_ID_INTEL_82815_FULL_CTRL
|
||||
#define PCI_DEVICE_ID_INTEL_82815_FULL_CTRL 0x1130
|
||||
#endif
|
||||
|
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/* General Defines */
|
||||
#define I810_PAGESIZE 4096
|
||||
#define MAX_DMA_SIZE (1024 * 4096)
|
||||
#define SAREA_SIZE 4096
|
||||
#define PCI_I810_MISCC 0x72
|
||||
#define MMIO_SIZE (512*1024)
|
||||
#define GTT_SIZE (16*1024)
|
||||
#define RINGBUFFER_SIZE (64*1024)
|
||||
#define CURSOR_SIZE 4096
|
||||
#define OFF 0
|
||||
#define ON 1
|
||||
#define MAX_KEY 256
|
||||
#define WAIT_COUNT 10000000
|
||||
#define IRING_PAD 8
|
||||
#define FONTDATAMAX 8192
|
||||
/* Masks (AND ops) and OR's */
|
||||
#define FB_START_MASK (0x3f << (32 - 6))
|
||||
#define MMIO_ADDR_MASK (0x1FFF << (32 - 13))
|
||||
#define FREQ_MASK (1 << 4)
|
||||
#define SCR_OFF 0x20
|
||||
#define DRAM_ON 0x08
|
||||
#define DRAM_OFF 0xE7
|
||||
#define PG_ENABLE_MASK 0x01
|
||||
#define RING_SIZE_MASK (RINGBUFFER_SIZE - 1)
|
||||
|
||||
/* defines for restoring registers partially */
|
||||
#define ADDR_MAP_MASK (0x07 << 5)
|
||||
#define DISP_CTRL ~0
|
||||
#define PIXCONF_0 (0x64 << 8)
|
||||
#define PIXCONF_2 (0xF3 << 24)
|
||||
#define PIXCONF_1 (0xF0 << 16)
|
||||
#define MN_MASK 0x3FF03FF
|
||||
#define P_OR (0x7 << 4)
|
||||
#define DAC_BIT (1 << 16)
|
||||
#define INTERLACE_BIT (1 << 7)
|
||||
#define IER_MASK (3 << 13)
|
||||
#define IMR_MASK (3 << 13)
|
||||
|
||||
/* Power Management */
|
||||
#define DPMS_MASK 0xF0000
|
||||
#define POWERON 0x00000
|
||||
#define STANDBY 0x20000
|
||||
#define SUSPEND 0x80000
|
||||
#define POWERDOWN 0xA0000
|
||||
#define EMR_MASK ~0x3F
|
||||
#define FW_BLC_MASK ~(0x3F|(7 << 8)|(0x3F << 12)|(7 << 20))
|
||||
|
||||
/* Ringbuffer */
|
||||
#define RBUFFER_START_MASK 0xFFFFF000
|
||||
#define RBUFFER_SIZE_MASK 0x001FF000
|
||||
#define RBUFFER_HEAD_MASK 0x001FFFFC
|
||||
#define RBUFFER_TAIL_MASK 0x001FFFF8
|
||||
|
||||
/* Video Timings */
|
||||
#define REF_FREQ 24000000
|
||||
#define TARGET_N_MAX 30
|
||||
|
||||
#define MAX_PIXELCLOCK 230000000
|
||||
#define MIN_PIXELCLOCK 15000000
|
||||
#define VFMAX 60
|
||||
#define VFMIN 60
|
||||
#define HFMAX 30000
|
||||
#define HFMIN 29000
|
||||
|
||||
/* Cursor */
|
||||
#define CURSOR_ENABLE_MASK 0x1000
|
||||
#define CURSOR_MODE_64_TRANS 4
|
||||
#define CURSOR_MODE_64_XOR 5
|
||||
#define CURSOR_MODE_64_3C 6
|
||||
#define COORD_INACTIVE 0
|
||||
#define COORD_ACTIVE (1 << 4)
|
||||
#define EXTENDED_PALETTE 1
|
||||
|
||||
/* AGP Memory Types*/
|
||||
#define AGP_NORMAL_MEMORY 0
|
||||
#define AGP_DCACHE_MEMORY 1
|
||||
#define AGP_PHYSICAL_MEMORY 2
|
||||
|
||||
/* Allocated resource Flags */
|
||||
#define FRAMEBUFFER_REQ 1
|
||||
#define MMIO_REQ 2
|
||||
#define PCI_DEVICE_ENABLED 4
|
||||
#define HAS_FONTCACHE 8
|
||||
|
||||
/* driver flags */
|
||||
#define HAS_MTRR 1
|
||||
#define HAS_ACCELERATION 2
|
||||
#define ALWAYS_SYNC 4
|
||||
#define LOCKUP 8
|
||||
|
||||
struct gtt_data {
|
||||
struct agp_memory *i810_fb_memory;
|
||||
struct agp_memory *i810_cursor_memory;
|
||||
};
|
||||
|
||||
struct mode_registers {
|
||||
u32 pixclock, M, N, P;
|
||||
u8 cr00, cr01, cr02, cr03;
|
||||
u8 cr04, cr05, cr06, cr07;
|
||||
u8 cr09, cr10, cr11, cr12;
|
||||
u8 cr13, cr15, cr16, cr30;
|
||||
u8 cr31, cr32, cr33, cr35, cr39;
|
||||
u32 bpp8_100, bpp16_100;
|
||||
u32 bpp24_100, bpp8_133;
|
||||
u32 bpp16_133, bpp24_133;
|
||||
u8 msr;
|
||||
};
|
||||
|
||||
struct heap_data {
|
||||
unsigned long physical;
|
||||
__u8 __iomem *virtual;
|
||||
u32 offset;
|
||||
u32 size;
|
||||
};
|
||||
|
||||
struct state_registers {
|
||||
u32 dclk_1d, dclk_2d, dclk_0ds;
|
||||
u32 pixconf, fw_blc, pgtbl_ctl;
|
||||
u32 fence0, hws_pga, dplystas;
|
||||
u16 bltcntl, hwstam, ier, iir, imr;
|
||||
u8 cr00, cr01, cr02, cr03, cr04;
|
||||
u8 cr05, cr06, cr07, cr08, cr09;
|
||||
u8 cr10, cr11, cr12, cr13, cr14;
|
||||
u8 cr15, cr16, cr17, cr80, gr10;
|
||||
u8 cr30, cr31, cr32, cr33, cr35;
|
||||
u8 cr39, cr41, cr70, sr01, msr;
|
||||
};
|
||||
|
||||
struct i810fb_par;
|
||||
|
||||
struct i810fb_i2c_chan {
|
||||
struct i810fb_par *par;
|
||||
struct i2c_adapter adapter;
|
||||
struct i2c_algo_bit_data algo;
|
||||
unsigned long ddc_base;
|
||||
};
|
||||
|
||||
struct i810fb_par {
|
||||
struct mode_registers regs;
|
||||
struct state_registers hw_state;
|
||||
struct gtt_data i810_gtt;
|
||||
struct fb_ops i810fb_ops;
|
||||
struct pci_dev *dev;
|
||||
struct heap_data aperture;
|
||||
struct heap_data fb;
|
||||
struct heap_data iring;
|
||||
struct heap_data cursor_heap;
|
||||
struct vgastate state;
|
||||
struct i810fb_i2c_chan chan[3];
|
||||
struct mutex open_lock;
|
||||
unsigned int use_count;
|
||||
u32 pseudo_palette[16];
|
||||
unsigned long mmio_start_phys;
|
||||
u8 __iomem *mmio_start_virtual;
|
||||
u8 *edid;
|
||||
u32 pitch;
|
||||
u32 pixconf;
|
||||
u32 watermark;
|
||||
u32 mem_freq;
|
||||
u32 res_flags;
|
||||
u32 dev_flags;
|
||||
u32 cur_tail;
|
||||
u32 depth;
|
||||
u32 blit_bpp;
|
||||
u32 ovract;
|
||||
u32 cur_state;
|
||||
u32 ddc_num;
|
||||
int mtrr_reg;
|
||||
u16 bltcntl;
|
||||
u8 interlace;
|
||||
};
|
||||
|
||||
/*
|
||||
* Register I/O
|
||||
*/
|
||||
#define i810_readb(where, mmio) readb(mmio + where)
|
||||
#define i810_readw(where, mmio) readw(mmio + where)
|
||||
#define i810_readl(where, mmio) readl(mmio + where)
|
||||
#define i810_writeb(where, mmio, val) writeb(val, mmio + where)
|
||||
#define i810_writew(where, mmio, val) writew(val, mmio + where)
|
||||
#define i810_writel(where, mmio, val) writel(val, mmio + where)
|
||||
|
||||
#endif /* __I810_H__ */
|
||||
456
drivers/video/fbdev/i810/i810_accel.c
Normal file
456
drivers/video/fbdev/i810/i810_accel.c
Normal file
|
|
@ -0,0 +1,456 @@
|
|||
/*-*- linux-c -*-
|
||||
* linux/drivers/video/i810_accel.c -- Hardware Acceleration
|
||||
*
|
||||
* Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>
|
||||
* All Rights Reserved
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file COPYING in the main directory of this archive for
|
||||
* more details.
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/fb.h>
|
||||
|
||||
#include "i810_regs.h"
|
||||
#include "i810.h"
|
||||
#include "i810_main.h"
|
||||
|
||||
static u32 i810fb_rop[] = {
|
||||
COLOR_COPY_ROP, /* ROP_COPY */
|
||||
XOR_ROP /* ROP_XOR */
|
||||
};
|
||||
|
||||
/* Macros */
|
||||
#define PUT_RING(n) { \
|
||||
i810_writel(par->cur_tail, par->iring.virtual, n); \
|
||||
par->cur_tail += 4; \
|
||||
par->cur_tail &= RING_SIZE_MASK; \
|
||||
}
|
||||
|
||||
extern void flush_cache(void);
|
||||
|
||||
/************************************************************/
|
||||
|
||||
/* BLT Engine Routines */
|
||||
static inline void i810_report_error(u8 __iomem *mmio)
|
||||
{
|
||||
printk("IIR : 0x%04x\n"
|
||||
"EIR : 0x%04x\n"
|
||||
"PGTBL_ER: 0x%04x\n"
|
||||
"IPEIR : 0x%04x\n"
|
||||
"IPEHR : 0x%04x\n",
|
||||
i810_readw(IIR, mmio),
|
||||
i810_readb(EIR, mmio),
|
||||
i810_readl(PGTBL_ER, mmio),
|
||||
i810_readl(IPEIR, mmio),
|
||||
i810_readl(IPEHR, mmio));
|
||||
}
|
||||
|
||||
/**
|
||||
* wait_for_space - check ring buffer free space
|
||||
* @space: amount of ringbuffer space needed in bytes
|
||||
* @par: pointer to i810fb_par structure
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* The function waits until a free space from the ringbuffer
|
||||
* is available
|
||||
*/
|
||||
static inline int wait_for_space(struct fb_info *info, u32 space)
|
||||
{
|
||||
struct i810fb_par *par = info->par;
|
||||
u32 head, count = WAIT_COUNT, tail;
|
||||
u8 __iomem *mmio = par->mmio_start_virtual;
|
||||
|
||||
tail = par->cur_tail;
|
||||
while (count--) {
|
||||
head = i810_readl(IRING + 4, mmio) & RBUFFER_HEAD_MASK;
|
||||
if ((tail == head) ||
|
||||
(tail > head &&
|
||||
(par->iring.size - tail + head) >= space) ||
|
||||
(tail < head && (head - tail) >= space)) {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
printk("ringbuffer lockup!!!\n");
|
||||
i810_report_error(mmio);
|
||||
par->dev_flags |= LOCKUP;
|
||||
info->pixmap.scan_align = 1;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* wait_for_engine_idle - waits for all hardware engines to finish
|
||||
* @par: pointer to i810fb_par structure
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* This waits for lring(0), iring(1), and batch(3), etc to finish and
|
||||
* waits until ringbuffer is empty.
|
||||
*/
|
||||
static inline int wait_for_engine_idle(struct fb_info *info)
|
||||
{
|
||||
struct i810fb_par *par = info->par;
|
||||
u8 __iomem *mmio = par->mmio_start_virtual;
|
||||
int count = WAIT_COUNT;
|
||||
|
||||
if (wait_for_space(info, par->iring.size)) /* flush */
|
||||
return 1;
|
||||
|
||||
while((i810_readw(INSTDONE, mmio) & 0x7B) != 0x7B && --count);
|
||||
if (count) return 0;
|
||||
|
||||
printk("accel engine lockup!!!\n");
|
||||
printk("INSTDONE: 0x%04x\n", i810_readl(INSTDONE, mmio));
|
||||
i810_report_error(mmio);
|
||||
par->dev_flags |= LOCKUP;
|
||||
info->pixmap.scan_align = 1;
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* begin_iring - prepares the ringbuffer
|
||||
* @space: length of sequence in dwords
|
||||
* @par: pointer to i810fb_par structure
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* Checks/waits for sufficient space in ringbuffer of size
|
||||
* space. Returns the tail of the buffer
|
||||
*/
|
||||
static inline u32 begin_iring(struct fb_info *info, u32 space)
|
||||
{
|
||||
struct i810fb_par *par = info->par;
|
||||
|
||||
if (par->dev_flags & ALWAYS_SYNC)
|
||||
wait_for_engine_idle(info);
|
||||
return wait_for_space(info, space);
|
||||
}
|
||||
|
||||
/**
|
||||
* end_iring - advances the buffer
|
||||
* @par: pointer to i810fb_par structure
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* This advances the tail of the ringbuffer, effectively
|
||||
* beginning the execution of the graphics instruction sequence.
|
||||
*/
|
||||
static inline void end_iring(struct i810fb_par *par)
|
||||
{
|
||||
u8 __iomem *mmio = par->mmio_start_virtual;
|
||||
|
||||
i810_writel(IRING, mmio, par->cur_tail);
|
||||
}
|
||||
|
||||
/**
|
||||
* source_copy_blit - BLIT transfer operation
|
||||
* @dwidth: width of rectangular graphics data
|
||||
* @dheight: height of rectangular graphics data
|
||||
* @dpitch: bytes per line of destination buffer
|
||||
* @xdir: direction of copy (left to right or right to left)
|
||||
* @src: address of first pixel to read from
|
||||
* @dest: address of first pixel to write to
|
||||
* @from: source address
|
||||
* @where: destination address
|
||||
* @rop: raster operation
|
||||
* @blit_bpp: pixel format which can be different from the
|
||||
* framebuffer's pixelformat
|
||||
* @par: pointer to i810fb_par structure
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* This is a BLIT operation typically used when doing
|
||||
* a 'Copy and Paste'
|
||||
*/
|
||||
static inline void source_copy_blit(int dwidth, int dheight, int dpitch,
|
||||
int xdir, int src, int dest, int rop,
|
||||
int blit_bpp, struct fb_info *info)
|
||||
{
|
||||
struct i810fb_par *par = info->par;
|
||||
|
||||
if (begin_iring(info, 24 + IRING_PAD)) return;
|
||||
|
||||
PUT_RING(BLIT | SOURCE_COPY_BLIT | 4);
|
||||
PUT_RING(xdir | rop << 16 | dpitch | DYN_COLOR_EN | blit_bpp);
|
||||
PUT_RING(dheight << 16 | dwidth);
|
||||
PUT_RING(dest);
|
||||
PUT_RING(dpitch);
|
||||
PUT_RING(src);
|
||||
|
||||
end_iring(par);
|
||||
}
|
||||
|
||||
/**
|
||||
* color_blit - solid color BLIT operation
|
||||
* @width: width of destination
|
||||
* @height: height of destination
|
||||
* @pitch: pixels per line of the buffer
|
||||
* @dest: address of first pixel to write to
|
||||
* @where: destination
|
||||
* @rop: raster operation
|
||||
* @what: color to transfer
|
||||
* @blit_bpp: pixel format which can be different from the
|
||||
* framebuffer's pixelformat
|
||||
* @par: pointer to i810fb_par structure
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* A BLIT operation which can be used for color fill/rectangular fill
|
||||
*/
|
||||
static inline void color_blit(int width, int height, int pitch, int dest,
|
||||
int rop, int what, int blit_bpp,
|
||||
struct fb_info *info)
|
||||
{
|
||||
struct i810fb_par *par = info->par;
|
||||
|
||||
if (begin_iring(info, 24 + IRING_PAD)) return;
|
||||
|
||||
PUT_RING(BLIT | COLOR_BLT | 3);
|
||||
PUT_RING(rop << 16 | pitch | SOLIDPATTERN | DYN_COLOR_EN | blit_bpp);
|
||||
PUT_RING(height << 16 | width);
|
||||
PUT_RING(dest);
|
||||
PUT_RING(what);
|
||||
PUT_RING(NOP);
|
||||
|
||||
end_iring(par);
|
||||
}
|
||||
|
||||
/**
|
||||
* mono_src_copy_imm_blit - color expand from system memory to framebuffer
|
||||
* @dwidth: width of destination
|
||||
* @dheight: height of destination
|
||||
* @dpitch: pixels per line of the buffer
|
||||
* @dsize: size of bitmap in double words
|
||||
* @dest: address of first byte of pixel;
|
||||
* @rop: raster operation
|
||||
* @blit_bpp: pixelformat to use which can be different from the
|
||||
* framebuffer's pixelformat
|
||||
* @src: address of image data
|
||||
* @bg: backgound color
|
||||
* @fg: forground color
|
||||
* @par: pointer to i810fb_par structure
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* A color expand operation where the source data is placed in the
|
||||
* ringbuffer itself. Useful for drawing text.
|
||||
*
|
||||
* REQUIREMENT:
|
||||
* The end of a scanline must be padded to the next word.
|
||||
*/
|
||||
static inline void mono_src_copy_imm_blit(int dwidth, int dheight, int dpitch,
|
||||
int dsize, int blit_bpp, int rop,
|
||||
int dest, const u32 *src, int bg,
|
||||
int fg, struct fb_info *info)
|
||||
{
|
||||
struct i810fb_par *par = info->par;
|
||||
|
||||
if (begin_iring(info, 24 + (dsize << 2) + IRING_PAD)) return;
|
||||
|
||||
PUT_RING(BLIT | MONO_SOURCE_COPY_IMMEDIATE | (4 + dsize));
|
||||
PUT_RING(DYN_COLOR_EN | blit_bpp | rop << 16 | dpitch);
|
||||
PUT_RING(dheight << 16 | dwidth);
|
||||
PUT_RING(dest);
|
||||
PUT_RING(bg);
|
||||
PUT_RING(fg);
|
||||
while (dsize--)
|
||||
PUT_RING(*src++);
|
||||
|
||||
end_iring(par);
|
||||
}
|
||||
|
||||
static inline void load_front(int offset, struct fb_info *info)
|
||||
{
|
||||
struct i810fb_par *par = info->par;
|
||||
|
||||
if (begin_iring(info, 8 + IRING_PAD)) return;
|
||||
|
||||
PUT_RING(PARSER | FLUSH);
|
||||
PUT_RING(NOP);
|
||||
|
||||
end_iring(par);
|
||||
|
||||
if (begin_iring(info, 8 + IRING_PAD)) return;
|
||||
|
||||
PUT_RING(PARSER | FRONT_BUFFER | ((par->pitch >> 3) << 8));
|
||||
PUT_RING((par->fb.offset << 12) + offset);
|
||||
|
||||
end_iring(par);
|
||||
}
|
||||
|
||||
/**
|
||||
* i810fb_iring_enable - enables/disables the ringbuffer
|
||||
* @mode: enable or disable
|
||||
* @par: pointer to i810fb_par structure
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* Enables or disables the ringbuffer, effectively enabling or
|
||||
* disabling the instruction/acceleration engine.
|
||||
*/
|
||||
static inline void i810fb_iring_enable(struct i810fb_par *par, u32 mode)
|
||||
{
|
||||
u32 tmp;
|
||||
u8 __iomem *mmio = par->mmio_start_virtual;
|
||||
|
||||
tmp = i810_readl(IRING + 12, mmio);
|
||||
if (mode == OFF)
|
||||
tmp &= ~1;
|
||||
else
|
||||
tmp |= 1;
|
||||
flush_cache();
|
||||
i810_writel(IRING + 12, mmio, tmp);
|
||||
}
|
||||
|
||||
void i810fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
|
||||
{
|
||||
struct i810fb_par *par = info->par;
|
||||
u32 dx, dy, width, height, dest, rop = 0, color = 0;
|
||||
|
||||
if (!info->var.accel_flags || par->dev_flags & LOCKUP ||
|
||||
par->depth == 4) {
|
||||
cfb_fillrect(info, rect);
|
||||
return;
|
||||
}
|
||||
|
||||
if (par->depth == 1)
|
||||
color = rect->color;
|
||||
else
|
||||
color = ((u32 *) (info->pseudo_palette))[rect->color];
|
||||
|
||||
rop = i810fb_rop[rect->rop];
|
||||
|
||||
dx = rect->dx * par->depth;
|
||||
width = rect->width * par->depth;
|
||||
dy = rect->dy;
|
||||
height = rect->height;
|
||||
|
||||
dest = info->fix.smem_start + (dy * info->fix.line_length) + dx;
|
||||
color_blit(width, height, info->fix.line_length, dest, rop, color,
|
||||
par->blit_bpp, info);
|
||||
}
|
||||
|
||||
void i810fb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
|
||||
{
|
||||
struct i810fb_par *par = info->par;
|
||||
u32 sx, sy, dx, dy, pitch, width, height, src, dest, xdir;
|
||||
|
||||
if (!info->var.accel_flags || par->dev_flags & LOCKUP ||
|
||||
par->depth == 4) {
|
||||
cfb_copyarea(info, region);
|
||||
return;
|
||||
}
|
||||
|
||||
dx = region->dx * par->depth;
|
||||
sx = region->sx * par->depth;
|
||||
width = region->width * par->depth;
|
||||
sy = region->sy;
|
||||
dy = region->dy;
|
||||
height = region->height;
|
||||
|
||||
if (dx <= sx) {
|
||||
xdir = INCREMENT;
|
||||
}
|
||||
else {
|
||||
xdir = DECREMENT;
|
||||
sx += width - 1;
|
||||
dx += width - 1;
|
||||
}
|
||||
if (dy <= sy) {
|
||||
pitch = info->fix.line_length;
|
||||
}
|
||||
else {
|
||||
pitch = (-(info->fix.line_length)) & 0xFFFF;
|
||||
sy += height - 1;
|
||||
dy += height - 1;
|
||||
}
|
||||
src = info->fix.smem_start + (sy * info->fix.line_length) + sx;
|
||||
dest = info->fix.smem_start + (dy * info->fix.line_length) + dx;
|
||||
|
||||
source_copy_blit(width, height, pitch, xdir, src, dest,
|
||||
PAT_COPY_ROP, par->blit_bpp, info);
|
||||
}
|
||||
|
||||
void i810fb_imageblit(struct fb_info *info, const struct fb_image *image)
|
||||
{
|
||||
struct i810fb_par *par = info->par;
|
||||
u32 fg = 0, bg = 0, size, dst;
|
||||
|
||||
if (!info->var.accel_flags || par->dev_flags & LOCKUP ||
|
||||
par->depth == 4 || image->depth != 1) {
|
||||
cfb_imageblit(info, image);
|
||||
return;
|
||||
}
|
||||
|
||||
switch (info->var.bits_per_pixel) {
|
||||
case 8:
|
||||
fg = image->fg_color;
|
||||
bg = image->bg_color;
|
||||
break;
|
||||
case 16:
|
||||
case 24:
|
||||
fg = ((u32 *)(info->pseudo_palette))[image->fg_color];
|
||||
bg = ((u32 *)(info->pseudo_palette))[image->bg_color];
|
||||
break;
|
||||
}
|
||||
|
||||
dst = info->fix.smem_start + (image->dy * info->fix.line_length) +
|
||||
(image->dx * par->depth);
|
||||
|
||||
size = (image->width+7)/8 + 1;
|
||||
size &= ~1;
|
||||
size *= image->height;
|
||||
size += 7;
|
||||
size &= ~7;
|
||||
mono_src_copy_imm_blit(image->width * par->depth,
|
||||
image->height, info->fix.line_length,
|
||||
size/4, par->blit_bpp,
|
||||
PAT_COPY_ROP, dst, (u32 *) image->data,
|
||||
bg, fg, info);
|
||||
}
|
||||
|
||||
int i810fb_sync(struct fb_info *info)
|
||||
{
|
||||
struct i810fb_par *par = info->par;
|
||||
|
||||
if (!info->var.accel_flags || par->dev_flags & LOCKUP)
|
||||
return 0;
|
||||
|
||||
return wait_for_engine_idle(info);
|
||||
}
|
||||
|
||||
void i810fb_load_front(u32 offset, struct fb_info *info)
|
||||
{
|
||||
struct i810fb_par *par = info->par;
|
||||
u8 __iomem *mmio = par->mmio_start_virtual;
|
||||
|
||||
if (!info->var.accel_flags || par->dev_flags & LOCKUP)
|
||||
i810_writel(DPLYBASE, mmio, par->fb.physical + offset);
|
||||
else
|
||||
load_front(offset, info);
|
||||
}
|
||||
|
||||
/**
|
||||
* i810fb_init_ringbuffer - initialize the ringbuffer
|
||||
* @par: pointer to i810fb_par structure
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* Initializes the ringbuffer by telling the device the
|
||||
* size and location of the ringbuffer. It also sets
|
||||
* the head and tail pointers = 0
|
||||
*/
|
||||
void i810fb_init_ringbuffer(struct fb_info *info)
|
||||
{
|
||||
struct i810fb_par *par = info->par;
|
||||
u32 tmp1, tmp2;
|
||||
u8 __iomem *mmio = par->mmio_start_virtual;
|
||||
|
||||
wait_for_engine_idle(info);
|
||||
i810fb_iring_enable(par, OFF);
|
||||
i810_writel(IRING, mmio, 0);
|
||||
i810_writel(IRING + 4, mmio, 0);
|
||||
par->cur_tail = 0;
|
||||
|
||||
tmp2 = i810_readl(IRING + 8, mmio) & ~RBUFFER_START_MASK;
|
||||
tmp1 = par->iring.physical;
|
||||
i810_writel(IRING + 8, mmio, tmp2 | tmp1);
|
||||
|
||||
tmp1 = i810_readl(IRING + 12, mmio);
|
||||
tmp1 &= ~RBUFFER_SIZE_MASK;
|
||||
tmp2 = (par->iring.size - I810_PAGESIZE) & RBUFFER_SIZE_MASK;
|
||||
i810_writel(IRING + 12, mmio, tmp1 | tmp2);
|
||||
i810fb_iring_enable(par, ON);
|
||||
}
|
||||
312
drivers/video/fbdev/i810/i810_dvt.c
Normal file
312
drivers/video/fbdev/i810/i810_dvt.c
Normal file
|
|
@ -0,0 +1,312 @@
|
|||
/*-*- linux-c -*-
|
||||
* linux/drivers/video/i810_dvt.c -- Intel 810 Discrete Video Timings (Intel)
|
||||
*
|
||||
* Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>
|
||||
* All Rights Reserved
|
||||
*
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file COPYING in the main directory of this archive for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include "i810_regs.h"
|
||||
#include "i810.h"
|
||||
|
||||
struct mode_registers std_modes[] = {
|
||||
/* 640x480 @ 60Hz */
|
||||
{ 25000, 0x0013, 0x0003, 0x40, 0x5F, 0x4F, 0x50, 0x82, 0x51, 0x9D,
|
||||
0x0B, 0x10, 0x40, 0xE9, 0x0B, 0xDF, 0x50, 0xE7, 0x04, 0x02,
|
||||
0x01, 0x01, 0x01, 0x00, 0x01, 0x22002000, 0x22004000, 0x22006000,
|
||||
0x22002000, 0x22004000, 0x22006000, 0xC0 },
|
||||
|
||||
/* 640x480 @ 70Hz */
|
||||
{ 28000, 0x0053, 0x0010, 0x40, 0x61, 0x4F, 0x4F, 0x85, 0x52, 0x9A,
|
||||
0xF2, 0x10, 0x40, 0xE0, 0x03, 0xDF, 0x50, 0xDF, 0xF3, 0x01,
|
||||
0x01, 0x01, 0x01, 0x00, 0x01, 0x22002000, 0x22004000, 0x22005000,
|
||||
0x22002000, 0x22004000, 0x22005000, 0xC0 },
|
||||
|
||||
/* 640x480 @ 72Hz */
|
||||
{ 31000, 0x0013, 0x0002, 0x40, 0x63, 0x4F, 0x4F, 0x87, 0x52, 0x97,
|
||||
0x06, 0x0F, 0x40, 0xE8, 0x0B, 0xDF, 0x50, 0xDF, 0x07, 0x02,
|
||||
0x01, 0x01, 0x01, 0x00, 0x01, 0x22003000, 0x22005000, 0x22007000,
|
||||
0x22003000, 0x22005000, 0x22007000, 0xC0 },
|
||||
|
||||
/* 640x480 @ 75Hz */
|
||||
{ 31000, 0x0013, 0x0002, 0x40, 0x64, 0x4F, 0x4F, 0x88, 0x51, 0x99,
|
||||
0xF2, 0x10, 0x40, 0xE0, 0x03, 0xDF, 0x50, 0xDF, 0xF3, 0x01,
|
||||
0x01, 0x01, 0x01, 0x00, 0x01, 0x22003000, 0x22005000, 0x22007000,
|
||||
0x22003000, 0x22005000, 0x22007000, 0xC0 },
|
||||
|
||||
/* 640x480 @ 85Hz */
|
||||
{ 36000, 0x0010, 0x0001, 0x40, 0x63, 0x4F, 0x4F, 0x87, 0x56, 0x9D,
|
||||
0xFB, 0x10, 0x40, 0xE0, 0x03, 0xDF, 0x50, 0xDF, 0xFC, 0x01,
|
||||
0x01, 0x01, 0x01, 0x00, 0x01, 0x22003000, 0x22005000, 0x22107000,
|
||||
0x22003000, 0x22005000, 0x22107000, 0xC0 },
|
||||
|
||||
/* 800x600 @ 56Hz */
|
||||
{ 36000, 0x0010, 0x0001, 0x40, 0x7B, 0x63, 0x63, 0x9F, 0x66, 0x8F,
|
||||
0x6F, 0x10, 0x40, 0x58, 0x0A, 0x57, 0xC8, 0x57, 0x70, 0x02,
|
||||
0x02, 0x02, 0x02, 0x00, 0x01, 0x22003000, 0x22005000, 0x22107000,
|
||||
0x22003000, 0x22005000, 0x22107000, 0x00 },
|
||||
|
||||
/* 800x600 @ 60Hz */
|
||||
{ 40000, 0x0008, 0x0001, 0x30, 0x7F, 0x63, 0x63, 0x83, 0x68, 0x18,
|
||||
0x72, 0x10, 0x40, 0x58, 0x0C, 0x57, 0xC8, 0x57, 0x73, 0x02,
|
||||
0x02, 0x02, 0x02, 0x00, 0x00, 0x22003000, 0x22006000, 0x22108000,
|
||||
0x22003000, 0x22006000, 0x22108000, 0x00 },
|
||||
|
||||
/* 800x600 @ 70Hz */
|
||||
{ 45000, 0x0054, 0x0015, 0x30, 0x7D, 0x63, 0x63, 0x81, 0x68, 0x12,
|
||||
0x6f, 0x10, 0x40, 0x58, 0x0b, 0x57, 0x64, 0x57, 0x70, 0x02,
|
||||
0x02, 0x02, 0x02, 0x00, 0x00, 0x22004000, 0x22007000, 0x2210A000,
|
||||
0x22004000, 0x22007000, 0x2210A000, 0x00 },
|
||||
|
||||
/* 800x600 @ 72Hz */
|
||||
{ 50000, 0x0017, 0x0004, 0x30, 0x7D, 0x63, 0x63, 0x81, 0x6A, 0x19,
|
||||
0x98, 0x10, 0x40, 0x7C, 0x02, 0x57, 0xC8, 0x57, 0x99, 0x02,
|
||||
0x02, 0x02, 0x02, 0x00, 0x00, 0x22004000, 0x22007000, 0x2210A000,
|
||||
0x22004000, 0x22007000, 0x2210A000, 0x00 },
|
||||
|
||||
/* 800x600 @ 75Hz */
|
||||
{ 49000, 0x001F, 0x0006, 0x30, 0x7F, 0x63, 0x63, 0x83, 0x65, 0x0F,
|
||||
0x6F, 0x10, 0x40, 0x58, 0x0B, 0x57, 0xC8, 0x57, 0x70, 0x02,
|
||||
0x02, 0x02, 0x02, 0x00, 0x00, 0x22004000, 0x22007000, 0x2210B000,
|
||||
0x22004000, 0x22007000, 0x2210B000, 0x00 },
|
||||
|
||||
/* 800x600 @ 85Hz */
|
||||
{ 56000, 0x0049, 0x000E, 0x30, 0x7E, 0x63, 0x63, 0x82, 0x67, 0x0F,
|
||||
0x75, 0x10, 0x40, 0x58, 0x0B, 0x57, 0xC8, 0x57, 0x76, 0x02,
|
||||
0x02, 0x02, 0x02, 0x00, 0x00, 0x22004000, 0x22108000, 0x2210b000,
|
||||
0x22004000, 0x22108000, 0x2210b000, 0x00 },
|
||||
|
||||
/* 1024x768 @ 60Hz */
|
||||
{ 65000, 0x003F, 0x000A, 0x30, 0xA3, 0x7F, 0x7F, 0x87, 0x83, 0x94,
|
||||
0x24, 0x10, 0x40, 0x02, 0x08, 0xFF, 0x80, 0xFF, 0x25, 0x03,
|
||||
0x02, 0x03, 0x02, 0x00, 0x00, 0x22005000, 0x22109000, 0x2220D000,
|
||||
0x22005000, 0x22109000, 0x2220D000, 0xC0 },
|
||||
|
||||
/* 1024x768 @ 70Hz */
|
||||
{ 75000, 0x0017, 0x0002, 0x30, 0xA1, 0x7F, 0x7F, 0x85, 0x82, 0x93,
|
||||
0x24, 0x10, 0x40, 0x02, 0x08, 0xFF, 0x80, 0xFF, 0x25, 0x03,
|
||||
0x02, 0x03, 0x02, 0x00, 0x00, 0x22005000, 0x2210A000, 0x2220F000,
|
||||
0x22005000, 0x2210A000, 0x2220F000, 0xC0 },
|
||||
|
||||
/* 1024x768 @ 75Hz */
|
||||
{ 78000, 0x0050, 0x0017, 0x20, 0x9F, 0x7F, 0x7F, 0x83, 0x81, 0x8D,
|
||||
0x1E, 0x10, 0x40, 0x00, 0x03, 0xFF, 0x80, 0xFF, 0x1F, 0x03,
|
||||
0x02, 0x03, 0x02, 0x00, 0x00, 0x22006000, 0x2210B000, 0x22210000,
|
||||
0x22006000, 0x2210B000, 0x22210000, 0x00 },
|
||||
|
||||
/* 1024x768 @ 85Hz */
|
||||
{ 94000, 0x003D, 0x000E, 0x20, 0xA7, 0x7F, 0x7F, 0x8B, 0x85, 0x91,
|
||||
0x26, 0x10, 0x40, 0x00, 0x03, 0xFF, 0x80, 0xFF, 0x27, 0x03,
|
||||
0x02, 0x03, 0x02, 0x00, 0x00, 0x22007000, 0x2220E000, 0x22212000,
|
||||
0x22007000, 0x2220E000, 0x22212000, 0x00 },
|
||||
|
||||
/* 1152x864 @ 60Hz */
|
||||
{ 80000, 0x0008, 0x0001, 0x20, 0xB3, 0x8F, 0x8F, 0x97, 0x93, 0x9f,
|
||||
0x87, 0x10, 0x40, 0x60, 0x03, 0x5F, 0x90, 0x5f, 0x88, 0x03,
|
||||
0x03, 0x03, 0x03, 0x00, 0x00, 0x2220C000, 0x22210000, 0x22415000,
|
||||
0x2220C000, 0x22210000, 0x22415000, 0x00 },
|
||||
|
||||
/* 1152x864 @ 70Hz */
|
||||
{ 96000, 0x000a, 0x0001, 0x20, 0xbb, 0x8F, 0x8F, 0x9f, 0x98, 0x87,
|
||||
0x82, 0x10, 0x40, 0x60, 0x03, 0x5F, 0x90, 0x5F, 0x83, 0x03,
|
||||
0x03, 0x03, 0x03, 0x00, 0x00, 0x22107000, 0x22210000, 0x22415000,
|
||||
0x22107000, 0x22210000, 0x22415000, 0x00 },
|
||||
|
||||
/* 1152x864 @ 72Hz */
|
||||
{ 99000, 0x001f, 0x0006, 0x20, 0xbb, 0x8F, 0x8F, 0x9f, 0x98, 0x87,
|
||||
0x83, 0x10, 0x40, 0x60, 0x03, 0x5F, 0x90, 0x5F, 0x84, 0x03,
|
||||
0x03, 0x03, 0x03, 0x00, 0x00, 0x22107000, 0x22210000, 0x22415000,
|
||||
0x22107000, 0x22210000, 0x22415000, 0x00 },
|
||||
|
||||
/* 1152x864 @ 75Hz */
|
||||
{ 108000, 0x0010, 0x0002, 0x20, 0xC3, 0x8F, 0x8F, 0x87, 0x97, 0x07,
|
||||
0x82, 0x10, 0x40, 0x60, 0x03, 0x5F, 0x90, 0x5F, 0x83, 0x03,
|
||||
0x03, 0x03, 0x03, 0x00, 0x01, 0x22107000, 0x22210000, 0x22415000,
|
||||
0x22107000, 0x22210000, 0x22415000, 0x00 },
|
||||
|
||||
/* 1152x864 @ 85Hz */
|
||||
{ 121000, 0x006D, 0x0014, 0x20, 0xc0, 0x8F, 0x8F, 0x84, 0x97, 0x07,
|
||||
0x93, 0x10, 0x40, 0x60, 0x03, 0x5F, 0x90, 0x5F, 0x94, 0x03,
|
||||
0x03, 0x03, 0x03, 0x00, 0x01, 0x2220C000, 0x22210000, 0x22415000,
|
||||
0x2220C000, 0x22210000, 0x22415000, 0x0 },
|
||||
|
||||
/* 1280x960 @ 60Hz */
|
||||
{ 108000, 0x0010, 0x0002, 0x20, 0xDC, 0x9F, 0x9F, 0x80, 0xAB, 0x99,
|
||||
0xE6, 0x10, 0x40, 0xC0, 0x03, 0xBF, 0xA0, 0xBF, 0xE7, 0x03,
|
||||
0x03, 0x03, 0x03, 0x00, 0x01, 0x2210A000, 0x22210000, 0x22415000,
|
||||
0x2210A000, 0x22210000, 0x22415000, 0x00 },
|
||||
|
||||
/* 1280x960 @ 75Hz */
|
||||
{ 129000, 0x0029, 0x0006, 0x20, 0xD3, 0x9F, 0x9F, 0x97, 0xaa, 0x1b,
|
||||
0xE8, 0x10, 0x40, 0xC0, 0x03, 0xBF, 0xA0, 0xBF, 0xE9, 0x03,
|
||||
0x03, 0x03, 0x03, 0x00, 0x01, 0x2210A000, 0x22210000, 0x2241B000,
|
||||
0x2210A000, 0x22210000, 0x2241B000, 0x00 },
|
||||
|
||||
/* 1280x960 @ 85Hz */
|
||||
{ 148000, 0x0042, 0x0009, 0x20, 0xD3, 0x9F, 0x9F, 0x97, 0xA7, 0x1B,
|
||||
0xF1, 0x10, 0x40, 0xC0, 0x03, 0xBF, 0xA0, 0xBF, 0xF2, 0x03,
|
||||
0x03, 0x03, 0x03, 0x00, 0x01, 0x2210A000, 0x22220000, 0x2241D000,
|
||||
0x2210A000, 0x22220000, 0x2241D000, 0x00 },
|
||||
|
||||
/* 1600x1200 @ 60Hz */
|
||||
{ 162000, 0x0019, 0x0006, 0x10, 0x09, 0xC7, 0xC7, 0x8D, 0xcf, 0x07,
|
||||
0xE0, 0x10, 0x40, 0xB0, 0x03, 0xAF, 0xC8, 0xAF, 0xE1, 0x04,
|
||||
0x04, 0x04, 0x04, 0x01, 0x00, 0x2210b000, 0x22416000, 0x44419000,
|
||||
0x2210b000, 0x22416000, 0x44419000, 0x00 },
|
||||
|
||||
/* 1600x1200 @ 65 Hz */
|
||||
{ 175000, 0x005d, 0x0018, 0x10, 0x09, 0xC7, 0xC7, 0x8D, 0xcf, 0x07,
|
||||
0xE0, 0x10, 0x40, 0xB0, 0x03, 0xAF, 0xC8, 0xAF, 0xE1, 0x04,
|
||||
0x04, 0x04, 0x04, 0x01, 0x00, 0x2210c000, 0x22416000, 0x44419000,
|
||||
0x2210c000, 0x22416000, 0x44419000, 0x00 },
|
||||
|
||||
/* 1600x1200 @ 70 Hz */
|
||||
{ 189000, 0x003D, 0x000e, 0x10, 0x09, 0xC7, 0xC7, 0x8d, 0xcf, 0x07,
|
||||
0xE0, 0x10, 0x40, 0xb0, 0x03, 0xAF, 0xC8, 0xaf, 0xE1, 0x04,
|
||||
0x04, 0x04, 0x04, 0x01, 0x00, 0x2220e000, 0x22416000, 0x44419000,
|
||||
0x2220e000, 0x22416000, 0x44419000, 0x00 },
|
||||
|
||||
/* 1600x1200 @ 72 Hz */
|
||||
{ 195000, 0x003f, 0x000e, 0x10, 0x0b, 0xC7, 0xC7, 0x8f, 0xd5, 0x0b,
|
||||
0xE1, 0x10, 0x40, 0xb0, 0x03, 0xAF, 0xC8, 0xaf, 0xe2, 0x04, 0x04,
|
||||
0x04, 0x04, 0x01, 0x00, 0x2220e000, 0x22416000, 0x44419000,
|
||||
0x2220e000, 0x22416000, 0x44419000, 0x00 },
|
||||
|
||||
/* 1600x1200 @ 75 Hz */
|
||||
{ 202000, 0x0024, 0x0007, 0x10, 0x09, 0xC7, 0xC7, 0x8d, 0xcf, 0x07,
|
||||
0xE0, 0x10, 0x40, 0xb0, 0x03, 0xAF, 0xC8, 0xaf, 0xE1, 0x04, 0x04,
|
||||
0x04, 0x04, 0x01, 0x00, 0x2220e000, 0x22416000, 0x44419000,
|
||||
0x2220e000, 0x22416000, 0x44419000, 0x00 },
|
||||
|
||||
/* 1600x1200 @ 85 Hz */
|
||||
{ 229000, 0x0029, 0x0007, 0x10, 0x09, 0xC7, 0xC7, 0x8d, 0xcf, 0x07,
|
||||
0xE0, 0x10, 0x40, 0xb0, 0x03, 0xAF, 0xC8, 0xaf, 0xE1, 0x04, 0x04,
|
||||
0x04, 0x04, 0x01, 0x00, 0x22210000, 0x22416000, 0x0,
|
||||
0x22210000, 0x22416000, 0x0, 0x00 },
|
||||
};
|
||||
|
||||
void round_off_xres(u32 *xres)
|
||||
{
|
||||
if (*xres <= 640)
|
||||
*xres = 640;
|
||||
else if (*xres <= 800)
|
||||
*xres = 800;
|
||||
else if (*xres <= 1024)
|
||||
*xres = 1024;
|
||||
else if (*xres <= 1152)
|
||||
*xres = 1152;
|
||||
else if (*xres <= 1280)
|
||||
*xres = 1280;
|
||||
else
|
||||
*xres = 1600;
|
||||
}
|
||||
|
||||
inline void round_off_yres(u32 *xres, u32 *yres)
|
||||
{
|
||||
*yres = (*xres * 3) >> 2;
|
||||
}
|
||||
|
||||
static int i810fb_find_best_mode(u32 xres, u32 yres, u32 pixclock)
|
||||
{
|
||||
u32 diff = 0, diff_best = 0xFFFFFFFF, i = 0, i_best = 0;
|
||||
u8 hfl = (u8) ((xres >> 3) - 1);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(std_modes); i++) {
|
||||
if (std_modes[i].cr01 == hfl) {
|
||||
if (std_modes[i].pixclock <= pixclock)
|
||||
diff = pixclock - std_modes[i].pixclock;
|
||||
if (diff < diff_best) {
|
||||
i_best = i;
|
||||
diff_best = diff;
|
||||
}
|
||||
}
|
||||
}
|
||||
return i_best;
|
||||
}
|
||||
|
||||
void i810fb_encode_registers(const struct fb_var_screeninfo *var,
|
||||
struct i810fb_par *par, u32 xres, u32 yres)
|
||||
{
|
||||
u32 i_best = i810fb_find_best_mode(xres, yres, par->regs.pixclock);
|
||||
|
||||
par->regs = std_modes[i_best];
|
||||
|
||||
/* overlay */
|
||||
par->ovract = ((xres + var->right_margin + var->hsync_len +
|
||||
var->left_margin - 32) | ((xres - 32) << 16));
|
||||
}
|
||||
|
||||
void i810fb_fill_var_timings(struct fb_var_screeninfo *var)
|
||||
{
|
||||
u32 total, xres, yres;
|
||||
u32 mode, pixclock;
|
||||
|
||||
xres = var->xres;
|
||||
yres = var->yres;
|
||||
|
||||
pixclock = 1000000000 / var->pixclock;
|
||||
mode = i810fb_find_best_mode(xres, yres, pixclock);
|
||||
|
||||
total = (std_modes[mode].cr00 | (std_modes[mode].cr35 & 1) << 8) + 3;
|
||||
total <<= 3;
|
||||
|
||||
var->pixclock = 1000000000 / std_modes[mode].pixclock;
|
||||
var->right_margin = (std_modes[mode].cr04 << 3) - xres;
|
||||
var->hsync_len = ((std_modes[mode].cr05 & 0x1F) -
|
||||
(std_modes[mode].cr04 & 0x1F)) << 3;
|
||||
var->left_margin = (total - (xres + var->right_margin +
|
||||
var->hsync_len));
|
||||
var->sync = FB_SYNC_ON_GREEN;
|
||||
if (~(std_modes[mode].msr & (1 << 6)))
|
||||
var->sync |= FB_SYNC_HOR_HIGH_ACT;
|
||||
if (~(std_modes[mode].msr & (1 << 7)))
|
||||
var->sync |= FB_SYNC_VERT_HIGH_ACT;
|
||||
|
||||
total = (std_modes[mode].cr06 | (std_modes[mode].cr30 & 0xF) << 8) + 2;
|
||||
var->lower_margin = (std_modes[mode].cr10 |
|
||||
(std_modes[mode].cr32 & 0x0F) << 8) - yres;
|
||||
var->vsync_len = (std_modes[mode].cr11 & 0x0F) -
|
||||
(var->lower_margin & 0x0F);
|
||||
var->upper_margin = total - (yres + var->lower_margin + var->vsync_len);
|
||||
}
|
||||
|
||||
u32 i810_get_watermark(struct fb_var_screeninfo *var,
|
||||
struct i810fb_par *par)
|
||||
{
|
||||
struct mode_registers *params = &par->regs;
|
||||
u32 wmark = 0;
|
||||
|
||||
if (par->mem_freq == 100) {
|
||||
switch (var->bits_per_pixel) {
|
||||
case 8:
|
||||
wmark = params->bpp8_100;
|
||||
break;
|
||||
case 16:
|
||||
wmark = params->bpp16_100;
|
||||
break;
|
||||
case 24:
|
||||
case 32:
|
||||
wmark = params->bpp24_100;
|
||||
}
|
||||
} else {
|
||||
switch (var->bits_per_pixel) {
|
||||
case 8:
|
||||
wmark = params->bpp8_133;
|
||||
break;
|
||||
case 16:
|
||||
wmark = params->bpp16_133;
|
||||
break;
|
||||
case 24:
|
||||
case 32:
|
||||
wmark = params->bpp24_133;
|
||||
}
|
||||
}
|
||||
return wmark;
|
||||
}
|
||||
|
||||
276
drivers/video/fbdev/i810/i810_gtf.c
Normal file
276
drivers/video/fbdev/i810/i810_gtf.c
Normal file
|
|
@ -0,0 +1,276 @@
|
|||
/*-*- linux-c -*-
|
||||
* linux/drivers/video/i810_main.h -- Intel 810 Non-discrete Video Timings
|
||||
* (VESA GTF)
|
||||
*
|
||||
* Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>
|
||||
* All Rights Reserved
|
||||
*
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file COPYING in the main directory of this archive for
|
||||
* more details.
|
||||
*/
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include "i810_regs.h"
|
||||
#include "i810.h"
|
||||
#include "i810_main.h"
|
||||
|
||||
/*
|
||||
* FIFO and Watermark tables - based almost wholly on i810_wmark.c in
|
||||
* XFree86 v4.03 by Precision Insight. Slightly modified for integer
|
||||
* operation, instead of float
|
||||
*/
|
||||
|
||||
struct wm_info {
|
||||
u32 freq;
|
||||
u32 wm;
|
||||
};
|
||||
|
||||
static struct wm_info i810_wm_8_100[] = {
|
||||
{ 15, 0x0070c000 }, { 19, 0x0070c000 }, { 25, 0x22003000 },
|
||||
{ 28, 0x22003000 }, { 31, 0x22003000 }, { 36, 0x22007000 },
|
||||
{ 40, 0x22007000 }, { 45, 0x22007000 }, { 49, 0x22008000 },
|
||||
{ 50, 0x22008000 }, { 56, 0x22008000 }, { 65, 0x22008000 },
|
||||
{ 75, 0x22008000 }, { 78, 0x22008000 }, { 80, 0x22008000 },
|
||||
{ 94, 0x22008000 }, { 96, 0x22107000 }, { 99, 0x22107000 },
|
||||
{ 108, 0x22107000 }, { 121, 0x22107000 }, { 128, 0x22107000 },
|
||||
{ 132, 0x22109000 }, { 135, 0x22109000 }, { 157, 0x2210b000 },
|
||||
{ 162, 0x2210b000 }, { 175, 0x2210b000 }, { 189, 0x2220e000 },
|
||||
{ 195, 0x2220e000 }, { 202, 0x2220e000 }, { 204, 0x2220e000 },
|
||||
{ 218, 0x2220f000 }, { 229, 0x22210000 }, { 234, 0x22210000 },
|
||||
};
|
||||
|
||||
static struct wm_info i810_wm_16_100[] = {
|
||||
{ 15, 0x0070c000 }, { 19, 0x0020c000 }, { 25, 0x22006000 },
|
||||
{ 28, 0x22006000 }, { 31, 0x22007000 }, { 36, 0x22007000 },
|
||||
{ 40, 0x22007000 }, { 45, 0x22007000 }, { 49, 0x22009000 },
|
||||
{ 50, 0x22009000 }, { 56, 0x22108000 }, { 65, 0x2210e000 },
|
||||
{ 75, 0x2210e000 }, { 78, 0x2210e000 }, { 80, 0x22210000 },
|
||||
{ 94, 0x22210000 }, { 96, 0x22210000 }, { 99, 0x22210000 },
|
||||
{ 108, 0x22210000 }, { 121, 0x22210000 }, { 128, 0x22210000 },
|
||||
{ 132, 0x22314000 }, { 135, 0x22314000 }, { 157, 0x22415000 },
|
||||
{ 162, 0x22416000 }, { 175, 0x22416000 }, { 189, 0x22416000 },
|
||||
{ 195, 0x22416000 }, { 202, 0x22416000 }, { 204, 0x22416000 },
|
||||
{ 218, 0x22416000 }, { 229, 0x22416000 },
|
||||
};
|
||||
|
||||
static struct wm_info i810_wm_24_100[] = {
|
||||
{ 15, 0x0020c000 }, { 19, 0x0040c000 }, { 25, 0x22009000 },
|
||||
{ 28, 0x22009000 }, { 31, 0x2200a000 }, { 36, 0x2210c000 },
|
||||
{ 40, 0x2210c000 }, { 45, 0x2210c000 }, { 49, 0x22111000 },
|
||||
{ 50, 0x22111000 }, { 56, 0x22111000 }, { 65, 0x22214000 },
|
||||
{ 75, 0x22214000 }, { 78, 0x22215000 }, { 80, 0x22216000 },
|
||||
{ 94, 0x22218000 }, { 96, 0x22418000 }, { 99, 0x22418000 },
|
||||
{ 108, 0x22418000 }, { 121, 0x22418000 }, { 128, 0x22419000 },
|
||||
{ 132, 0x22519000 }, { 135, 0x4441d000 }, { 157, 0x44419000 },
|
||||
{ 162, 0x44419000 }, { 175, 0x44419000 }, { 189, 0x44419000 },
|
||||
{ 195, 0x44419000 }, { 202, 0x44419000 }, { 204, 0x44419000 },
|
||||
};
|
||||
|
||||
static struct wm_info i810_wm_8_133[] = {
|
||||
{ 15, 0x0070c000 }, { 19, 0x0070c000 }, { 25, 0x22003000 },
|
||||
{ 28, 0x22003000 }, { 31, 0x22003000 }, { 36, 0x22007000 },
|
||||
{ 40, 0x22007000 }, { 45, 0x22007000 }, { 49, 0x22008000 },
|
||||
{ 50, 0x22008000 }, { 56, 0x22008000 }, { 65, 0x22008000 },
|
||||
{ 75, 0x22008000 }, { 78, 0x22008000 }, { 80, 0x22008000 },
|
||||
{ 94, 0x22008000 }, { 96, 0x22107000 }, { 99, 0x22107000 },
|
||||
{ 108, 0x22107000 }, { 121, 0x22107000 }, { 128, 0x22107000 },
|
||||
{ 132, 0x22109000 }, { 135, 0x22109000 }, { 157, 0x2210b000 },
|
||||
{ 162, 0x2210b000 }, { 175, 0x2210b000 }, { 189, 0x2220e000 },
|
||||
{ 195, 0x2220e000 }, { 202, 0x2220e000 }, { 204, 0x2220e000 },
|
||||
{ 218, 0x2220f000 }, { 229, 0x22210000 }, { 234, 0x22210000 },
|
||||
};
|
||||
|
||||
static struct wm_info i810_wm_16_133[] = {
|
||||
{ 15, 0x0020c000 }, { 19, 0x0020c000 }, { 25, 0x22006000 },
|
||||
{ 28, 0x22006000 }, { 31, 0x22007000 }, { 36, 0x22007000 },
|
||||
{ 40, 0x22007000 }, { 45, 0x22007000 }, { 49, 0x22009000 },
|
||||
{ 50, 0x22009000 }, { 56, 0x22108000 }, { 65, 0x2210e000 },
|
||||
{ 75, 0x2210e000 }, { 78, 0x2210e000 }, { 80, 0x22210000 },
|
||||
{ 94, 0x22210000 }, { 96, 0x22210000 }, { 99, 0x22210000 },
|
||||
{ 108, 0x22210000 }, { 121, 0x22210000 }, { 128, 0x22210000 },
|
||||
{ 132, 0x22314000 }, { 135, 0x22314000 }, { 157, 0x22415000 },
|
||||
{ 162, 0x22416000 }, { 175, 0x22416000 }, { 189, 0x22416000 },
|
||||
{ 195, 0x22416000 }, { 202, 0x22416000 }, { 204, 0x22416000 },
|
||||
{ 218, 0x22416000 }, { 229, 0x22416000 },
|
||||
};
|
||||
|
||||
static struct wm_info i810_wm_24_133[] = {
|
||||
{ 15, 0x0020c000 }, { 19, 0x00408000 }, { 25, 0x22009000 },
|
||||
{ 28, 0x22009000 }, { 31, 0x2200a000 }, { 36, 0x2210c000 },
|
||||
{ 40, 0x2210c000 }, { 45, 0x2210c000 }, { 49, 0x22111000 },
|
||||
{ 50, 0x22111000 }, { 56, 0x22111000 }, { 65, 0x22214000 },
|
||||
{ 75, 0x22214000 }, { 78, 0x22215000 }, { 80, 0x22216000 },
|
||||
{ 94, 0x22218000 }, { 96, 0x22418000 }, { 99, 0x22418000 },
|
||||
{ 108, 0x22418000 }, { 121, 0x22418000 }, { 128, 0x22419000 },
|
||||
{ 132, 0x22519000 }, { 135, 0x4441d000 }, { 157, 0x44419000 },
|
||||
{ 162, 0x44419000 }, { 175, 0x44419000 }, { 189, 0x44419000 },
|
||||
{ 195, 0x44419000 }, { 202, 0x44419000 }, { 204, 0x44419000 },
|
||||
};
|
||||
|
||||
void round_off_xres(u32 *xres) { }
|
||||
void round_off_yres(u32 *xres, u32 *yres) { }
|
||||
|
||||
/**
|
||||
* i810fb_encode_registers - encode @var to hardware register values
|
||||
* @var: pointer to var structure
|
||||
* @par: pointer to hardware par structure
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* Timing values in @var will be converted to appropriate
|
||||
* register values of @par.
|
||||
*/
|
||||
void i810fb_encode_registers(const struct fb_var_screeninfo *var,
|
||||
struct i810fb_par *par, u32 xres, u32 yres)
|
||||
{
|
||||
int n, blank_s, blank_e;
|
||||
u8 __iomem *mmio = par->mmio_start_virtual;
|
||||
u8 msr = 0;
|
||||
|
||||
/* Horizontal */
|
||||
/* htotal */
|
||||
n = ((xres + var->right_margin + var->hsync_len +
|
||||
var->left_margin) >> 3) - 5;
|
||||
par->regs.cr00 = (u8) n;
|
||||
par->regs.cr35 = (u8) ((n >> 8) & 1);
|
||||
|
||||
/* xres */
|
||||
par->regs.cr01 = (u8) ((xres >> 3) - 1);
|
||||
|
||||
/* hblank */
|
||||
blank_e = (xres + var->right_margin + var->hsync_len +
|
||||
var->left_margin) >> 3;
|
||||
blank_e--;
|
||||
blank_s = blank_e - 127;
|
||||
if (blank_s < (xres >> 3))
|
||||
blank_s = xres >> 3;
|
||||
par->regs.cr02 = (u8) blank_s;
|
||||
par->regs.cr03 = (u8) (blank_e & 0x1F);
|
||||
par->regs.cr05 = (u8) ((blank_e & (1 << 5)) << 2);
|
||||
par->regs.cr39 = (u8) ((blank_e >> 6) & 1);
|
||||
|
||||
/* hsync */
|
||||
par->regs.cr04 = (u8) ((xres + var->right_margin) >> 3);
|
||||
par->regs.cr05 |= (u8) (((xres + var->right_margin +
|
||||
var->hsync_len) >> 3) & 0x1F);
|
||||
|
||||
/* Vertical */
|
||||
/* vtotal */
|
||||
n = yres + var->lower_margin + var->vsync_len + var->upper_margin - 2;
|
||||
par->regs.cr06 = (u8) (n & 0xFF);
|
||||
par->regs.cr30 = (u8) ((n >> 8) & 0x0F);
|
||||
|
||||
/* vsync */
|
||||
n = yres + var->lower_margin;
|
||||
par->regs.cr10 = (u8) (n & 0xFF);
|
||||
par->regs.cr32 = (u8) ((n >> 8) & 0x0F);
|
||||
par->regs.cr11 = i810_readb(CR11, mmio) & ~0x0F;
|
||||
par->regs.cr11 |= (u8) ((yres + var->lower_margin +
|
||||
var->vsync_len) & 0x0F);
|
||||
|
||||
/* yres */
|
||||
n = yres - 1;
|
||||
par->regs.cr12 = (u8) (n & 0xFF);
|
||||
par->regs.cr31 = (u8) ((n >> 8) & 0x0F);
|
||||
|
||||
/* vblank */
|
||||
blank_e = yres + var->lower_margin + var->vsync_len +
|
||||
var->upper_margin;
|
||||
blank_e--;
|
||||
blank_s = blank_e - 127;
|
||||
if (blank_s < yres)
|
||||
blank_s = yres;
|
||||
par->regs.cr15 = (u8) (blank_s & 0xFF);
|
||||
par->regs.cr33 = (u8) ((blank_s >> 8) & 0x0F);
|
||||
par->regs.cr16 = (u8) (blank_e & 0xFF);
|
||||
par->regs.cr09 = 0;
|
||||
|
||||
/* sync polarity */
|
||||
if (!(var->sync & FB_SYNC_HOR_HIGH_ACT))
|
||||
msr |= 1 << 6;
|
||||
if (!(var->sync & FB_SYNC_VERT_HIGH_ACT))
|
||||
msr |= 1 << 7;
|
||||
par->regs.msr = msr;
|
||||
|
||||
/* interlace */
|
||||
if (var->vmode & FB_VMODE_INTERLACED)
|
||||
par->interlace = (1 << 7) | ((u8) (var->yres >> 4));
|
||||
else
|
||||
par->interlace = 0;
|
||||
|
||||
if (var->vmode & FB_VMODE_DOUBLE)
|
||||
par->regs.cr09 |= 1 << 7;
|
||||
|
||||
/* overlay */
|
||||
par->ovract = ((var->xres + var->right_margin + var->hsync_len +
|
||||
var->left_margin - 32) | ((var->xres - 32) << 16));
|
||||
}
|
||||
|
||||
void i810fb_fill_var_timings(struct fb_var_screeninfo *var) { }
|
||||
|
||||
/**
|
||||
* i810_get_watermark - gets watermark
|
||||
* @var: pointer to fb_var_screeninfo
|
||||
* @par: pointer to i810fb_par structure
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* Gets the required watermark based on
|
||||
* pixelclock and RAMBUS frequency.
|
||||
*
|
||||
* RETURNS:
|
||||
* watermark
|
||||
*/
|
||||
u32 i810_get_watermark(const struct fb_var_screeninfo *var,
|
||||
struct i810fb_par *par)
|
||||
{
|
||||
struct wm_info *wmark = NULL;
|
||||
u32 i, size = 0, pixclock, wm_best = 0, min, diff;
|
||||
|
||||
if (par->mem_freq == 100) {
|
||||
switch (var->bits_per_pixel) {
|
||||
case 8:
|
||||
wmark = i810_wm_8_100;
|
||||
size = ARRAY_SIZE(i810_wm_8_100);
|
||||
break;
|
||||
case 16:
|
||||
wmark = i810_wm_16_100;
|
||||
size = ARRAY_SIZE(i810_wm_16_100);
|
||||
break;
|
||||
case 24:
|
||||
case 32:
|
||||
wmark = i810_wm_24_100;
|
||||
size = ARRAY_SIZE(i810_wm_24_100);
|
||||
}
|
||||
} else {
|
||||
switch(var->bits_per_pixel) {
|
||||
case 8:
|
||||
wmark = i810_wm_8_133;
|
||||
size = ARRAY_SIZE(i810_wm_8_133);
|
||||
break;
|
||||
case 16:
|
||||
wmark = i810_wm_16_133;
|
||||
size = ARRAY_SIZE(i810_wm_16_133);
|
||||
break;
|
||||
case 24:
|
||||
case 32:
|
||||
wmark = i810_wm_24_133;
|
||||
size = ARRAY_SIZE(i810_wm_24_133);
|
||||
}
|
||||
}
|
||||
|
||||
pixclock = 1000000/var->pixclock;
|
||||
min = ~0;
|
||||
for (i = 0; i < size; i++) {
|
||||
if (pixclock <= wmark[i].freq)
|
||||
diff = wmark[i].freq - pixclock;
|
||||
else
|
||||
diff = pixclock - wmark[i].freq;
|
||||
if (diff < min) {
|
||||
wm_best = wmark[i].wm;
|
||||
min = diff;
|
||||
}
|
||||
}
|
||||
return wm_best;
|
||||
}
|
||||
|
||||
2218
drivers/video/fbdev/i810/i810_main.c
Normal file
2218
drivers/video/fbdev/i810/i810_main.c
Normal file
File diff suppressed because it is too large
Load diff
95
drivers/video/fbdev/i810/i810_main.h
Normal file
95
drivers/video/fbdev/i810/i810_main.h
Normal file
|
|
@ -0,0 +1,95 @@
|
|||
/*-*- linux-c -*-
|
||||
* linux/drivers/video/i810fb_main.h -- Intel 810 frame buffer device
|
||||
* main header file
|
||||
*
|
||||
* Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>
|
||||
* All Rights Reserved
|
||||
*
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file COPYING in the main directory of this archive for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef __I810_MAIN_H__
|
||||
#define __I810_MAIN_H__
|
||||
|
||||
/* Video Timings */
|
||||
extern void round_off_xres (u32 *xres);
|
||||
extern void round_off_yres (u32 *xres, u32 *yres);
|
||||
extern u32 i810_get_watermark (const struct fb_var_screeninfo *var,
|
||||
struct i810fb_par *par);
|
||||
extern void i810fb_encode_registers(const struct fb_var_screeninfo *var,
|
||||
struct i810fb_par *par, u32 xres, u32 yres);
|
||||
extern void i810fb_fill_var_timings(struct fb_var_screeninfo *var);
|
||||
|
||||
/* Accelerated Functions */
|
||||
extern void i810fb_fillrect (struct fb_info *p,
|
||||
const struct fb_fillrect *rect);
|
||||
extern void i810fb_copyarea (struct fb_info *p,
|
||||
const struct fb_copyarea *region);
|
||||
extern void i810fb_imageblit(struct fb_info *p, const struct fb_image *image);
|
||||
extern int i810fb_sync (struct fb_info *p);
|
||||
|
||||
extern void i810fb_init_ringbuffer(struct fb_info *info);
|
||||
extern void i810fb_load_front (u32 offset, struct fb_info *info);
|
||||
|
||||
#ifdef CONFIG_FB_I810_I2C
|
||||
/* I2C */
|
||||
extern int i810_probe_i2c_connector(struct fb_info *info, u8 **out_edid,
|
||||
int conn);
|
||||
extern void i810_create_i2c_busses(struct i810fb_par *par);
|
||||
extern void i810_delete_i2c_busses(struct i810fb_par *par);
|
||||
#else
|
||||
static inline int i810_probe_i2c_connector(struct fb_info *info, u8 **out_edid,
|
||||
int conn)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
static inline void i810_create_i2c_busses(struct i810fb_par *par) { }
|
||||
static inline void i810_delete_i2c_busses(struct i810fb_par *par) { }
|
||||
#endif
|
||||
|
||||
/* Conditionals */
|
||||
#ifdef CONFIG_X86
|
||||
static inline void flush_cache(void)
|
||||
{
|
||||
asm volatile ("wbinvd":::"memory");
|
||||
}
|
||||
#else
|
||||
#define flush_cache() do { } while(0)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MTRR
|
||||
|
||||
#include <asm/mtrr.h>
|
||||
|
||||
static inline void set_mtrr(struct i810fb_par *par)
|
||||
{
|
||||
par->mtrr_reg = mtrr_add((u32) par->aperture.physical,
|
||||
par->aperture.size, MTRR_TYPE_WRCOMB, 1);
|
||||
if (par->mtrr_reg < 0) {
|
||||
printk(KERN_ERR "set_mtrr: unable to set MTRR\n");
|
||||
return;
|
||||
}
|
||||
par->dev_flags |= HAS_MTRR;
|
||||
}
|
||||
static inline void unset_mtrr(struct i810fb_par *par)
|
||||
{
|
||||
if (par->dev_flags & HAS_MTRR)
|
||||
mtrr_del(par->mtrr_reg, (u32) par->aperture.physical,
|
||||
par->aperture.size);
|
||||
}
|
||||
#else
|
||||
#define set_mtrr(x) printk("set_mtrr: MTRR is disabled in the kernel\n")
|
||||
|
||||
#define unset_mtrr(x) do { } while (0)
|
||||
#endif /* CONFIG_MTRR */
|
||||
|
||||
#ifdef CONFIG_FB_I810_GTF
|
||||
#define IS_DVT (0)
|
||||
#else
|
||||
#define IS_DVT (1)
|
||||
#endif
|
||||
|
||||
#endif /* __I810_MAIN_H__ */
|
||||
275
drivers/video/fbdev/i810/i810_regs.h
Normal file
275
drivers/video/fbdev/i810/i810_regs.h
Normal file
|
|
@ -0,0 +1,275 @@
|
|||
/*-*- linux-c -*-
|
||||
* linux/drivers/video/i810_regs.h -- Intel 810/815 Register List
|
||||
*
|
||||
* Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>
|
||||
* All Rights Reserved
|
||||
*
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file COPYING in the main directory of this archive for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Intel 810 Chipset Family PRM 15 3.1
|
||||
* GC Register Memory Address Map
|
||||
*
|
||||
* Based on:
|
||||
* Intel (R) 810 Chipset Family
|
||||
* Programmer s Reference Manual
|
||||
* November 1999
|
||||
* Revision 1.0
|
||||
* Order Number: 298026-001 R
|
||||
*
|
||||
* All GC registers are memory-mapped. In addition, the VGA and extended VGA registers
|
||||
* are I/O mapped.
|
||||
*/
|
||||
|
||||
#ifndef __I810_REGS_H__
|
||||
#define __I810_REGS_H__
|
||||
|
||||
/* Instruction and Interrupt Control Registers (01000h 02FFFh) */
|
||||
#define FENCE 0x02000
|
||||
#define PGTBL_CTL 0x02020
|
||||
#define PGTBL_ER 0x02024
|
||||
#define LRING 0x02030
|
||||
#define IRING 0x02040
|
||||
#define HWS_PGA 0x02080
|
||||
#define IPEIR 0x02088
|
||||
#define IPEHR 0x0208C
|
||||
#define INSTDONE 0x02090
|
||||
#define NOPID 0x02094
|
||||
#define HWSTAM 0x02098
|
||||
#define IER 0x020A0
|
||||
#define IIR 0x020A4
|
||||
#define IMR 0x020A8
|
||||
#define ISR 0x020AC
|
||||
#define EIR 0x020B0
|
||||
#define EMR 0x020B4
|
||||
#define ESR 0x020B8
|
||||
#define INSTPM 0x020C0
|
||||
#define INSTPS 0x020C4
|
||||
#define BBP_PTR 0x020C8
|
||||
#define ABB_SRT 0x020CC
|
||||
#define ABB_END 0x020D0
|
||||
#define DMA_FADD 0x020D4
|
||||
#define FW_BLC 0x020D8
|
||||
#define MEM_MODE 0x020DC
|
||||
|
||||
/* Memory Control Registers (03000h 03FFFh) */
|
||||
#define DRT 0x03000
|
||||
#define DRAMCL 0x03001
|
||||
#define DRAMCH 0x03002
|
||||
|
||||
|
||||
/* Span Cursor Registers (04000h 04FFFh) */
|
||||
#define UI_SC_CTL 0x04008
|
||||
|
||||
/* I/O Control Registers (05000h 05FFFh) */
|
||||
#define HVSYNC 0x05000
|
||||
#define GPIOA 0x05010
|
||||
#define GPIOB 0x05014
|
||||
#define GPIOC 0x0501C
|
||||
|
||||
/* Clock Control and Power Management Registers (06000h 06FFFh) */
|
||||
#define DCLK_0D 0x06000
|
||||
#define DCLK_1D 0x06004
|
||||
#define DCLK_2D 0x06008
|
||||
#define LCD_CLKD 0x0600C
|
||||
#define DCLK_0DS 0x06010
|
||||
#define PWR_CLKC 0x06014
|
||||
|
||||
/* Graphics Translation Table Range Definition (10000h 1FFFFh) */
|
||||
#define GTT 0x10000
|
||||
|
||||
/* Overlay Registers (30000h 03FFFFh) */
|
||||
#define OVOADDR 0x30000
|
||||
#define DOVOSTA 0x30008
|
||||
#define GAMMA 0x30010
|
||||
#define OBUF_0Y 0x30100
|
||||
#define OBUF_1Y 0x30104
|
||||
#define OBUF_0U 0x30108
|
||||
#define OBUF_0V 0x3010C
|
||||
#define OBUF_1U 0x30110
|
||||
#define OBUF_1V 0x30114
|
||||
#define OVOSTRIDE 0x30118
|
||||
#define YRGB_VPH 0x3011C
|
||||
#define UV_VPH 0x30120
|
||||
#define HORZ_PH 0x30124
|
||||
#define INIT_PH 0x30128
|
||||
#define DWINPOS 0x3012C
|
||||
#define DWINSZ 0x30130
|
||||
#define SWID 0x30134
|
||||
#define SWIDQW 0x30138
|
||||
#define SHEIGHT 0x3013F
|
||||
#define YRGBSCALE 0x30140
|
||||
#define UVSCALE 0x30144
|
||||
#define OVOCLRCO 0x30148
|
||||
#define OVOCLRC1 0x3014C
|
||||
#define DCLRKV 0x30150
|
||||
#define DLCRKM 0x30154
|
||||
#define SCLRKVH 0x30158
|
||||
#define SCLRKVL 0x3015C
|
||||
#define SCLRKM 0x30160
|
||||
#define OVOCONF 0x30164
|
||||
#define OVOCMD 0x30168
|
||||
#define AWINPOS 0x30170
|
||||
#define AWINZ 0x30174
|
||||
|
||||
/* BLT Engine Status (40000h 4FFFFh) (Software Debug) */
|
||||
#define BR00 0x40000
|
||||
#define BRO1 0x40004
|
||||
#define BR02 0x40008
|
||||
#define BR03 0x4000C
|
||||
#define BR04 0x40010
|
||||
#define BR05 0x40014
|
||||
#define BR06 0x40018
|
||||
#define BR07 0x4001C
|
||||
#define BR08 0x40020
|
||||
#define BR09 0x40024
|
||||
#define BR10 0x40028
|
||||
#define BR11 0x4002C
|
||||
#define BR12 0x40030
|
||||
#define BR13 0x40034
|
||||
#define BR14 0x40038
|
||||
#define BR15 0x4003C
|
||||
#define BR16 0x40040
|
||||
#define BR17 0x40044
|
||||
#define BR18 0x40048
|
||||
#define BR19 0x4004C
|
||||
#define SSLADD 0x40074
|
||||
#define DSLH 0x40078
|
||||
#define DSLRADD 0x4007C
|
||||
|
||||
|
||||
/* LCD/TV-Out and HW DVD Registers (60000h 6FFFFh) */
|
||||
/* LCD/TV-Out */
|
||||
#define HTOTAL 0x60000
|
||||
#define HBLANK 0x60004
|
||||
#define HSYNC 0x60008
|
||||
#define VTOTAL 0x6000C
|
||||
#define VBLANK 0x60010
|
||||
#define VSYNC 0x60014
|
||||
#define LCDTV_C 0x60018
|
||||
#define OVRACT 0x6001C
|
||||
#define BCLRPAT 0x60020
|
||||
|
||||
/* Display and Cursor Control Registers (70000h 7FFFFh) */
|
||||
#define DISP_SL 0x70000
|
||||
#define DISP_SLC 0x70004
|
||||
#define PIXCONF 0x70008
|
||||
#define PIXCONF1 0x70009
|
||||
#define BLTCNTL 0x7000C
|
||||
#define SWF 0x70014
|
||||
#define DPLYBASE 0x70020
|
||||
#define DPLYSTAS 0x70024
|
||||
#define CURCNTR 0x70080
|
||||
#define CURBASE 0x70084
|
||||
#define CURPOS 0x70088
|
||||
|
||||
|
||||
/* VGA Registers */
|
||||
|
||||
/* SMRAM Registers */
|
||||
#define SMRAM 0x10
|
||||
|
||||
/* Graphics Control Registers */
|
||||
#define GR_INDEX 0x3CE
|
||||
#define GR_DATA 0x3CF
|
||||
|
||||
#define GR10 0x10
|
||||
#define GR11 0x11
|
||||
|
||||
/* CRT Controller Registers */
|
||||
#define CR_INDEX_MDA 0x3B4
|
||||
#define CR_INDEX_CGA 0x3D4
|
||||
#define CR_DATA_MDA 0x3B5
|
||||
#define CR_DATA_CGA 0x3D5
|
||||
|
||||
#define CR30 0x30
|
||||
#define CR31 0x31
|
||||
#define CR32 0x32
|
||||
#define CR33 0x33
|
||||
#define CR35 0x35
|
||||
#define CR39 0x39
|
||||
#define CR40 0x40
|
||||
#define CR41 0x41
|
||||
#define CR42 0x42
|
||||
#define CR70 0x70
|
||||
#define CR80 0x80
|
||||
#define CR81 0x82
|
||||
|
||||
/* Extended VGA Registers */
|
||||
|
||||
/* General Control and Status Registers */
|
||||
#define ST00 0x3C2
|
||||
#define ST01_MDA 0x3BA
|
||||
#define ST01_CGA 0x3DA
|
||||
#define FRC_READ 0x3CA
|
||||
#define FRC_WRITE_MDA 0x3BA
|
||||
#define FRC_WRITE_CGA 0x3DA
|
||||
#define MSR_READ 0x3CC
|
||||
#define MSR_WRITE 0x3C2
|
||||
|
||||
/* Sequencer Registers */
|
||||
#define SR_INDEX 0x3C4
|
||||
#define SR_DATA 0x3C5
|
||||
|
||||
#define SR01 0x01
|
||||
#define SR02 0x02
|
||||
#define SR03 0x03
|
||||
#define SR04 0x04
|
||||
#define SR07 0x07
|
||||
|
||||
/* Graphics Controller Registers */
|
||||
#define GR00 0x00
|
||||
#define GR01 0x01
|
||||
#define GR02 0x02
|
||||
#define GR03 0x03
|
||||
#define GR04 0x04
|
||||
#define GR05 0x05
|
||||
#define GR06 0x06
|
||||
#define GR07 0x07
|
||||
#define GR08 0x08
|
||||
|
||||
/* Attribute Controller Registers */
|
||||
#define ATTR_WRITE 0x3C0
|
||||
#define ATTR_READ 0x3C1
|
||||
|
||||
/* VGA Color Palette Registers */
|
||||
|
||||
/* CLUT */
|
||||
#define CLUT_DATA 0x3C9 /* DACDATA */
|
||||
#define CLUT_INDEX_READ 0x3C7 /* DACRX */
|
||||
#define CLUT_INDEX_WRITE 0x3C8 /* DACWX */
|
||||
#define DACMASK 0x3C6
|
||||
|
||||
/* CRT Controller Registers */
|
||||
#define CR00 0x00
|
||||
#define CR01 0x01
|
||||
#define CR02 0x02
|
||||
#define CR03 0x03
|
||||
#define CR04 0x04
|
||||
#define CR05 0x05
|
||||
#define CR06 0x06
|
||||
#define CR07 0x07
|
||||
#define CR08 0x08
|
||||
#define CR09 0x09
|
||||
#define CR0A 0x0A
|
||||
#define CR0B 0x0B
|
||||
#define CR0C 0x0C
|
||||
#define CR0D 0x0D
|
||||
#define CR0E 0x0E
|
||||
#define CR0F 0x0F
|
||||
#define CR10 0x10
|
||||
#define CR11 0x11
|
||||
#define CR12 0x12
|
||||
#define CR13 0x13
|
||||
#define CR14 0x14
|
||||
#define CR15 0x15
|
||||
#define CR16 0x16
|
||||
#define CR17 0x17
|
||||
#define CR18 0x18
|
||||
|
||||
#endif /* __I810_REGS_H__ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue