mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 16:18:51 +01:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
3
drivers/video/fbdev/mbx/Makefile
Normal file
3
drivers/video/fbdev/mbx/Makefile
Normal file
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@ -0,0 +1,3 @@
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# Makefile for the 2700G controller driver.
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obj-y += mbxfb.o
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251
drivers/video/fbdev/mbx/mbxdebugfs.c
Normal file
251
drivers/video/fbdev/mbx/mbxdebugfs.c
Normal file
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@ -0,0 +1,251 @@
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#include <linux/debugfs.h>
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#include <linux/slab.h>
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#define BIG_BUFFER_SIZE (1024)
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static char big_buffer[BIG_BUFFER_SIZE];
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struct mbxfb_debugfs_data {
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struct dentry *dir;
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struct dentry *sysconf;
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struct dentry *clock;
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struct dentry *display;
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struct dentry *gsctl;
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struct dentry *sdram;
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struct dentry *misc;
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};
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static int open_file_generic(struct inode *inode, struct file *file)
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{
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file->private_data = inode->i_private;
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return 0;
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}
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static ssize_t write_file_dummy(struct file *file, const char __user *buf,
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size_t count, loff_t *ppos)
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{
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return count;
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}
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static ssize_t sysconf_read_file(struct file *file, char __user *userbuf,
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size_t count, loff_t *ppos)
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{
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char * s = big_buffer;
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s += sprintf(s, "SYSCFG = %08x\n", readl(SYSCFG));
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s += sprintf(s, "PFBASE = %08x\n", readl(PFBASE));
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s += sprintf(s, "PFCEIL = %08x\n", readl(PFCEIL));
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s += sprintf(s, "POLLFLAG = %08x\n", readl(POLLFLAG));
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s += sprintf(s, "SYSRST = %08x\n", readl(SYSRST));
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return simple_read_from_buffer(userbuf, count, ppos,
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big_buffer, s-big_buffer);
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}
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static ssize_t gsctl_read_file(struct file *file, char __user *userbuf,
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size_t count, loff_t *ppos)
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{
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char * s = big_buffer;
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s += sprintf(s, "GSCTRL = %08x\n", readl(GSCTRL));
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s += sprintf(s, "VSCTRL = %08x\n", readl(VSCTRL));
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s += sprintf(s, "GBBASE = %08x\n", readl(GBBASE));
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s += sprintf(s, "VBBASE = %08x\n", readl(VBBASE));
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s += sprintf(s, "GDRCTRL = %08x\n", readl(GDRCTRL));
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s += sprintf(s, "VCMSK = %08x\n", readl(VCMSK));
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s += sprintf(s, "GSCADR = %08x\n", readl(GSCADR));
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s += sprintf(s, "VSCADR = %08x\n", readl(VSCADR));
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s += sprintf(s, "VUBASE = %08x\n", readl(VUBASE));
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s += sprintf(s, "VVBASE = %08x\n", readl(VVBASE));
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s += sprintf(s, "GSADR = %08x\n", readl(GSADR));
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s += sprintf(s, "VSADR = %08x\n", readl(VSADR));
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s += sprintf(s, "HCCTRL = %08x\n", readl(HCCTRL));
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s += sprintf(s, "HCSIZE = %08x\n", readl(HCSIZE));
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s += sprintf(s, "HCPOS = %08x\n", readl(HCPOS));
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s += sprintf(s, "HCBADR = %08x\n", readl(HCBADR));
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s += sprintf(s, "HCCKMSK = %08x\n", readl(HCCKMSK));
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s += sprintf(s, "GPLUT = %08x\n", readl(GPLUT));
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return simple_read_from_buffer(userbuf, count, ppos,
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big_buffer, s-big_buffer);
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}
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static ssize_t display_read_file(struct file *file, char __user *userbuf,
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size_t count, loff_t *ppos)
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{
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char * s = big_buffer;
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s += sprintf(s, "DSCTRL = %08x\n", readl(DSCTRL));
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s += sprintf(s, "DHT01 = %08x\n", readl(DHT01));
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s += sprintf(s, "DHT02 = %08x\n", readl(DHT02));
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s += sprintf(s, "DHT03 = %08x\n", readl(DHT03));
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s += sprintf(s, "DVT01 = %08x\n", readl(DVT01));
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s += sprintf(s, "DVT02 = %08x\n", readl(DVT02));
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s += sprintf(s, "DVT03 = %08x\n", readl(DVT03));
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s += sprintf(s, "DBCOL = %08x\n", readl(DBCOL));
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s += sprintf(s, "BGCOLOR = %08x\n", readl(BGCOLOR));
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s += sprintf(s, "DINTRS = %08x\n", readl(DINTRS));
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s += sprintf(s, "DINTRE = %08x\n", readl(DINTRE));
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s += sprintf(s, "DINTRCNT = %08x\n", readl(DINTRCNT));
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s += sprintf(s, "DSIG = %08x\n", readl(DSIG));
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s += sprintf(s, "DMCTRL = %08x\n", readl(DMCTRL));
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s += sprintf(s, "CLIPCTRL = %08x\n", readl(CLIPCTRL));
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s += sprintf(s, "SPOCTRL = %08x\n", readl(SPOCTRL));
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s += sprintf(s, "SVCTRL = %08x\n", readl(SVCTRL));
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s += sprintf(s, "DLSTS = %08x\n", readl(DLSTS));
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s += sprintf(s, "DLLCTRL = %08x\n", readl(DLLCTRL));
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s += sprintf(s, "DVLNUM = %08x\n", readl(DVLNUM));
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s += sprintf(s, "DUCTRL = %08x\n", readl(DUCTRL));
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s += sprintf(s, "DVECTRL = %08x\n", readl(DVECTRL));
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s += sprintf(s, "DHDET = %08x\n", readl(DHDET));
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s += sprintf(s, "DVDET = %08x\n", readl(DVDET));
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s += sprintf(s, "DODMSK = %08x\n", readl(DODMSK));
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s += sprintf(s, "CSC01 = %08x\n", readl(CSC01));
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s += sprintf(s, "CSC02 = %08x\n", readl(CSC02));
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s += sprintf(s, "CSC03 = %08x\n", readl(CSC03));
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s += sprintf(s, "CSC04 = %08x\n", readl(CSC04));
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s += sprintf(s, "CSC05 = %08x\n", readl(CSC05));
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return simple_read_from_buffer(userbuf, count, ppos,
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big_buffer, s-big_buffer);
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}
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static ssize_t clock_read_file(struct file *file, char __user *userbuf,
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size_t count, loff_t *ppos)
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{
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char * s = big_buffer;
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s += sprintf(s, "SYSCLKSRC = %08x\n", readl(SYSCLKSRC));
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s += sprintf(s, "PIXCLKSRC = %08x\n", readl(PIXCLKSRC));
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s += sprintf(s, "CLKSLEEP = %08x\n", readl(CLKSLEEP));
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s += sprintf(s, "COREPLL = %08x\n", readl(COREPLL));
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s += sprintf(s, "DISPPLL = %08x\n", readl(DISPPLL));
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s += sprintf(s, "PLLSTAT = %08x\n", readl(PLLSTAT));
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s += sprintf(s, "VOVRCLK = %08x\n", readl(VOVRCLK));
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s += sprintf(s, "PIXCLK = %08x\n", readl(PIXCLK));
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s += sprintf(s, "MEMCLK = %08x\n", readl(MEMCLK));
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s += sprintf(s, "M24CLK = %08x\n", readl(M24CLK));
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s += sprintf(s, "MBXCLK = %08x\n", readl(MBXCLK));
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s += sprintf(s, "SDCLK = %08x\n", readl(SDCLK));
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s += sprintf(s, "PIXCLKDIV = %08x\n", readl(PIXCLKDIV));
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return simple_read_from_buffer(userbuf, count, ppos,
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big_buffer, s-big_buffer);
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}
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static ssize_t sdram_read_file(struct file *file, char __user *userbuf,
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size_t count, loff_t *ppos)
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{
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char * s = big_buffer;
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s += sprintf(s, "LMRST = %08x\n", readl(LMRST));
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s += sprintf(s, "LMCFG = %08x\n", readl(LMCFG));
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s += sprintf(s, "LMPWR = %08x\n", readl(LMPWR));
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s += sprintf(s, "LMPWRSTAT = %08x\n", readl(LMPWRSTAT));
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s += sprintf(s, "LMCEMR = %08x\n", readl(LMCEMR));
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s += sprintf(s, "LMTYPE = %08x\n", readl(LMTYPE));
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s += sprintf(s, "LMTIM = %08x\n", readl(LMTIM));
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s += sprintf(s, "LMREFRESH = %08x\n", readl(LMREFRESH));
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s += sprintf(s, "LMPROTMIN = %08x\n", readl(LMPROTMIN));
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s += sprintf(s, "LMPROTMAX = %08x\n", readl(LMPROTMAX));
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s += sprintf(s, "LMPROTCFG = %08x\n", readl(LMPROTCFG));
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s += sprintf(s, "LMPROTERR = %08x\n", readl(LMPROTERR));
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return simple_read_from_buffer(userbuf, count, ppos,
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big_buffer, s-big_buffer);
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}
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static ssize_t misc_read_file(struct file *file, char __user *userbuf,
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size_t count, loff_t *ppos)
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{
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char * s = big_buffer;
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s += sprintf(s, "LCD_CONFIG = %08x\n", readl(LCD_CONFIG));
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s += sprintf(s, "ODFBPWR = %08x\n", readl(ODFBPWR));
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s += sprintf(s, "ODFBSTAT = %08x\n", readl(ODFBSTAT));
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s += sprintf(s, "ID = %08x\n", readl(ID));
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return simple_read_from_buffer(userbuf, count, ppos,
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big_buffer, s-big_buffer);
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}
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static const struct file_operations sysconf_fops = {
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.read = sysconf_read_file,
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.write = write_file_dummy,
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.open = open_file_generic,
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.llseek = default_llseek,
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};
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static const struct file_operations clock_fops = {
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.read = clock_read_file,
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.write = write_file_dummy,
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.open = open_file_generic,
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.llseek = default_llseek,
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};
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static const struct file_operations display_fops = {
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.read = display_read_file,
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.write = write_file_dummy,
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.open = open_file_generic,
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.llseek = default_llseek,
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};
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static const struct file_operations gsctl_fops = {
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.read = gsctl_read_file,
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.write = write_file_dummy,
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.open = open_file_generic,
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.llseek = default_llseek,
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};
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static const struct file_operations sdram_fops = {
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.read = sdram_read_file,
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.write = write_file_dummy,
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.open = open_file_generic,
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.llseek = default_llseek,
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};
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static const struct file_operations misc_fops = {
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.read = misc_read_file,
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.write = write_file_dummy,
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.open = open_file_generic,
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.llseek = default_llseek,
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};
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static void mbxfb_debugfs_init(struct fb_info *fbi)
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{
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struct mbxfb_info *mfbi = fbi->par;
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struct mbxfb_debugfs_data *dbg;
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dbg = kzalloc(sizeof(struct mbxfb_debugfs_data), GFP_KERNEL);
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mfbi->debugfs_data = dbg;
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dbg->dir = debugfs_create_dir("mbxfb", NULL);
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dbg->sysconf = debugfs_create_file("sysconf", 0444, dbg->dir,
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fbi, &sysconf_fops);
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dbg->clock = debugfs_create_file("clock", 0444, dbg->dir,
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fbi, &clock_fops);
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dbg->display = debugfs_create_file("display", 0444, dbg->dir,
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fbi, &display_fops);
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dbg->gsctl = debugfs_create_file("gsctl", 0444, dbg->dir,
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fbi, &gsctl_fops);
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dbg->sdram = debugfs_create_file("sdram", 0444, dbg->dir,
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fbi, &sdram_fops);
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dbg->misc = debugfs_create_file("misc", 0444, dbg->dir,
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fbi, &misc_fops);
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}
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static void mbxfb_debugfs_remove(struct fb_info *fbi)
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{
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struct mbxfb_info *mfbi = fbi->par;
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struct mbxfb_debugfs_data *dbg = mfbi->debugfs_data;
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debugfs_remove(dbg->misc);
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debugfs_remove(dbg->sdram);
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debugfs_remove(dbg->gsctl);
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debugfs_remove(dbg->display);
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debugfs_remove(dbg->clock);
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debugfs_remove(dbg->sysconf);
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debugfs_remove(dbg->dir);
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}
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1055
drivers/video/fbdev/mbx/mbxfb.c
Normal file
1055
drivers/video/fbdev/mbx/mbxfb.c
Normal file
File diff suppressed because it is too large
Load diff
613
drivers/video/fbdev/mbx/reg_bits.h
Normal file
613
drivers/video/fbdev/mbx/reg_bits.h
Normal file
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@ -0,0 +1,613 @@
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|||
#ifndef __REG_BITS_2700G_
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#define __REG_BITS_2700G_
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/* use defines from asm-arm/arch-pxa/bitfields.h for bit fields access */
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#define UData(Data) ((unsigned long) (Data))
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#define Fld(Size, Shft) (((Size) << 16) + (Shft))
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#define FSize(Field) ((Field) >> 16)
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#define FShft(Field) ((Field) & 0x0000FFFF)
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#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
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#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
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#define F1stBit(Field) (UData (1) << FShft (Field))
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#define SYSRST_RST (1 << 0)
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/* SYSCLKSRC - SYSCLK Source Control Register */
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#define SYSCLKSRC_SEL Fld(2,0)
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#define SYSCLKSRC_REF ((0x0) << FShft(SYSCLKSRC_SEL))
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#define SYSCLKSRC_PLL_1 ((0x1) << FShft(SYSCLKSRC_SEL))
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#define SYSCLKSRC_PLL_2 ((0x2) << FShft(SYSCLKSRC_SEL))
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/* PIXCLKSRC - PIXCLK Source Control Register */
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#define PIXCLKSRC_SEL Fld(2,0)
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#define PIXCLKSRC_REF ((0x0) << FShft(PIXCLKSRC_SEL))
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#define PIXCLKSRC_PLL_1 ((0x1) << FShft(PIXCLKSRC_SEL))
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#define PIXCLKSRC_PLL_2 ((0x2) << FShft(PIXCLKSRC_SEL))
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/* Clock Disable Register */
|
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#define CLKSLEEP_SLP (1 << 0)
|
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|
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/* Core PLL Control Register */
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#define CORE_PLL_M Fld(6,7)
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#define Core_Pll_M(x) ((x) << FShft(CORE_PLL_M))
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#define CORE_PLL_N Fld(3,4)
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#define Core_Pll_N(x) ((x) << FShft(CORE_PLL_N))
|
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#define CORE_PLL_P Fld(3,1)
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#define Core_Pll_P(x) ((x) << FShft(CORE_PLL_P))
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#define CORE_PLL_EN (1 << 0)
|
||||
|
||||
/* Display PLL Control Register */
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#define DISP_PLL_M Fld(6,7)
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#define Disp_Pll_M(x) ((x) << FShft(DISP_PLL_M))
|
||||
#define DISP_PLL_N Fld(3,4)
|
||||
#define Disp_Pll_N(x) ((x) << FShft(DISP_PLL_N))
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||||
#define DISP_PLL_P Fld(3,1)
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||||
#define Disp_Pll_P(x) ((x) << FShft(DISP_PLL_P))
|
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#define DISP_PLL_EN (1 << 0)
|
||||
|
||||
/* PLL status register */
|
||||
#define PLLSTAT_CORE_PLL_LOST_L (1 << 3)
|
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#define PLLSTAT_CORE_PLL_LSTS (1 << 2)
|
||||
#define PLLSTAT_DISP_PLL_LOST_L (1 << 1)
|
||||
#define PLLSTAT_DISP_PLL_LSTS (1 << 0)
|
||||
|
||||
/* Video and scale clock control register */
|
||||
#define VOVRCLK_EN (1 << 0)
|
||||
|
||||
/* Pixel clock control register */
|
||||
#define PIXCLK_EN (1 << 0)
|
||||
|
||||
/* Memory clock control register */
|
||||
#define MEMCLK_EN (1 << 0)
|
||||
|
||||
/* MBX clock control register */
|
||||
#define MBXCLK_DIV Fld(2,2)
|
||||
#define MBXCLK_DIV_1 ((0x0) << FShft(MBXCLK_DIV))
|
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#define MBXCLK_DIV_2 ((0x1) << FShft(MBXCLK_DIV))
|
||||
#define MBXCLK_DIV_3 ((0x2) << FShft(MBXCLK_DIV))
|
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#define MBXCLK_DIV_4 ((0x3) << FShft(MBXCLK_DIV))
|
||||
#define MBXCLK_EN Fld(2,0)
|
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#define MBXCLK_EN_NONE ((0x0) << FShft(MBXCLK_EN))
|
||||
#define MBXCLK_EN_2D ((0x1) << FShft(MBXCLK_EN))
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#define MBXCLK_EN_BOTH ((0x2) << FShft(MBXCLK_EN))
|
||||
|
||||
/* M24 clock control register */
|
||||
#define M24CLK_DIV Fld(2,1)
|
||||
#define M24CLK_DIV_1 ((0x0) << FShft(M24CLK_DIV))
|
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#define M24CLK_DIV_2 ((0x1) << FShft(M24CLK_DIV))
|
||||
#define M24CLK_DIV_3 ((0x2) << FShft(M24CLK_DIV))
|
||||
#define M24CLK_DIV_4 ((0x3) << FShft(M24CLK_DIV))
|
||||
#define M24CLK_EN (1 << 0)
|
||||
|
||||
/* SDRAM clock control register */
|
||||
#define SDCLK_EN (1 << 0)
|
||||
|
||||
/* PixClk Divisor Register */
|
||||
#define PIXCLKDIV_PD Fld(9,0)
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||||
#define Pixclkdiv_Pd(x) ((x) << FShft(PIXCLKDIV_PD))
|
||||
|
||||
/* LCD Config control register */
|
||||
#define LCDCFG_IN_FMT Fld(3,28)
|
||||
#define Lcdcfg_In_Fmt(x) ((x) << FShft(LCDCFG_IN_FMT))
|
||||
#define LCDCFG_LCD1DEN_POL (1 << 27)
|
||||
#define LCDCFG_LCD1FCLK_POL (1 << 26)
|
||||
#define LCDCFG_LCD1LCLK_POL (1 << 25)
|
||||
#define LCDCFG_LCD1D_POL (1 << 24)
|
||||
#define LCDCFG_LCD2DEN_POL (1 << 23)
|
||||
#define LCDCFG_LCD2FCLK_POL (1 << 22)
|
||||
#define LCDCFG_LCD2LCLK_POL (1 << 21)
|
||||
#define LCDCFG_LCD2D_POL (1 << 20)
|
||||
#define LCDCFG_LCD1_TS (1 << 19)
|
||||
#define LCDCFG_LCD1D_DS (1 << 18)
|
||||
#define LCDCFG_LCD1C_DS (1 << 17)
|
||||
#define LCDCFG_LCD1_IS_IN (1 << 16)
|
||||
#define LCDCFG_LCD2_TS (1 << 3)
|
||||
#define LCDCFG_LCD2D_DS (1 << 2)
|
||||
#define LCDCFG_LCD2C_DS (1 << 1)
|
||||
#define LCDCFG_LCD2_IS_IN (1 << 0)
|
||||
|
||||
/* On-Die Frame Buffer Power Control Register */
|
||||
#define ODFBPWR_SLOW (1 << 2)
|
||||
#define ODFBPWR_MODE Fld(2,0)
|
||||
#define ODFBPWR_MODE_ACT ((0x0) << FShft(ODFBPWR_MODE))
|
||||
#define ODFBPWR_MODE_ACT_LP ((0x1) << FShft(ODFBPWR_MODE))
|
||||
#define ODFBPWR_MODE_SLEEP ((0x2) << FShft(ODFBPWR_MODE))
|
||||
#define ODFBPWR_MODE_SHUTD ((0x3) << FShft(ODFBPWR_MODE))
|
||||
|
||||
/* On-Die Frame Buffer Power State Status Register */
|
||||
#define ODFBSTAT_ACT (1 << 2)
|
||||
#define ODFBSTAT_SLP (1 << 1)
|
||||
#define ODFBSTAT_SDN (1 << 0)
|
||||
|
||||
/* LMRST - Local Memory (SDRAM) Reset */
|
||||
#define LMRST_MC_RST (1 << 0)
|
||||
|
||||
/* LMCFG - Local Memory (SDRAM) Configuration Register */
|
||||
#define LMCFG_LMC_DS (1 << 5)
|
||||
#define LMCFG_LMD_DS (1 << 4)
|
||||
#define LMCFG_LMA_DS (1 << 3)
|
||||
#define LMCFG_LMC_TS (1 << 2)
|
||||
#define LMCFG_LMD_TS (1 << 1)
|
||||
#define LMCFG_LMA_TS (1 << 0)
|
||||
|
||||
/* LMPWR - Local Memory (SDRAM) Power Control Register */
|
||||
#define LMPWR_MC_PWR_CNT Fld(2,0)
|
||||
#define LMPWR_MC_PWR_ACT ((0x0) << FShft(LMPWR_MC_PWR_CNT)) /* Active */
|
||||
#define LMPWR_MC_PWR_SRM ((0x1) << FShft(LMPWR_MC_PWR_CNT)) /* Self-refresh */
|
||||
#define LMPWR_MC_PWR_DPD ((0x3) << FShft(LMPWR_MC_PWR_CNT)) /* deep power down */
|
||||
|
||||
/* LMPWRSTAT - Local Memory (SDRAM) Power Status Register */
|
||||
#define LMPWRSTAT_MC_PWR_CNT Fld(2,0)
|
||||
#define LMPWRSTAT_MC_PWR_ACT ((0x0) << FShft(LMPWRSTAT_MC_PWR_CNT)) /* Active */
|
||||
#define LMPWRSTAT_MC_PWR_SRM ((0x1) << FShft(LMPWRSTAT_MC_PWR_CNT)) /* Self-refresh */
|
||||
#define LMPWRSTAT_MC_PWR_DPD ((0x3) << FShft(LMPWRSTAT_MC_PWR_CNT)) /* deep power down */
|
||||
|
||||
/* LMTYPE - Local Memory (SDRAM) Type Register */
|
||||
#define LMTYPE_CASLAT Fld(3,10)
|
||||
#define LMTYPE_CASLAT_1 ((0x1) << FShft(LMTYPE_CASLAT))
|
||||
#define LMTYPE_CASLAT_2 ((0x2) << FShft(LMTYPE_CASLAT))
|
||||
#define LMTYPE_CASLAT_3 ((0x3) << FShft(LMTYPE_CASLAT))
|
||||
#define LMTYPE_BKSZ Fld(2,8)
|
||||
#define LMTYPE_BKSZ_1 ((0x1) << FShft(LMTYPE_BKSZ))
|
||||
#define LMTYPE_BKSZ_2 ((0x2) << FShft(LMTYPE_BKSZ))
|
||||
#define LMTYPE_ROWSZ Fld(4,4)
|
||||
#define LMTYPE_ROWSZ_11 ((0xb) << FShft(LMTYPE_ROWSZ))
|
||||
#define LMTYPE_ROWSZ_12 ((0xc) << FShft(LMTYPE_ROWSZ))
|
||||
#define LMTYPE_ROWSZ_13 ((0xd) << FShft(LMTYPE_ROWSZ))
|
||||
#define LMTYPE_COLSZ Fld(4,0)
|
||||
#define LMTYPE_COLSZ_7 ((0x7) << FShft(LMTYPE_COLSZ))
|
||||
#define LMTYPE_COLSZ_8 ((0x8) << FShft(LMTYPE_COLSZ))
|
||||
#define LMTYPE_COLSZ_9 ((0x9) << FShft(LMTYPE_COLSZ))
|
||||
#define LMTYPE_COLSZ_10 ((0xa) << FShft(LMTYPE_COLSZ))
|
||||
#define LMTYPE_COLSZ_11 ((0xb) << FShft(LMTYPE_COLSZ))
|
||||
#define LMTYPE_COLSZ_12 ((0xc) << FShft(LMTYPE_COLSZ))
|
||||
|
||||
/* LMTIM - Local Memory (SDRAM) Timing Register */
|
||||
#define LMTIM_TRAS Fld(4,16)
|
||||
#define Lmtim_Tras(x) ((x) << FShft(LMTIM_TRAS))
|
||||
#define LMTIM_TRP Fld(4,12)
|
||||
#define Lmtim_Trp(x) ((x) << FShft(LMTIM_TRP))
|
||||
#define LMTIM_TRCD Fld(4,8)
|
||||
#define Lmtim_Trcd(x) ((x) << FShft(LMTIM_TRCD))
|
||||
#define LMTIM_TRC Fld(4,4)
|
||||
#define Lmtim_Trc(x) ((x) << FShft(LMTIM_TRC))
|
||||
#define LMTIM_TDPL Fld(4,0)
|
||||
#define Lmtim_Tdpl(x) ((x) << FShft(LMTIM_TDPL))
|
||||
|
||||
/* LMREFRESH - Local Memory (SDRAM) tREF Control Register */
|
||||
#define LMREFRESH_TREF Fld(2,0)
|
||||
#define Lmrefresh_Tref(x) ((x) << FShft(LMREFRESH_TREF))
|
||||
|
||||
/* GSCTRL - Graphics surface control register */
|
||||
#define GSCTRL_LUT_EN (1 << 31)
|
||||
#define GSCTRL_GPIXFMT Fld(4,27)
|
||||
#define GSCTRL_GPIXFMT_INDEXED ((0x0) << FShft(GSCTRL_GPIXFMT))
|
||||
#define GSCTRL_GPIXFMT_ARGB4444 ((0x4) << FShft(GSCTRL_GPIXFMT))
|
||||
#define GSCTRL_GPIXFMT_ARGB1555 ((0x5) << FShft(GSCTRL_GPIXFMT))
|
||||
#define GSCTRL_GPIXFMT_RGB888 ((0x6) << FShft(GSCTRL_GPIXFMT))
|
||||
#define GSCTRL_GPIXFMT_RGB565 ((0x7) << FShft(GSCTRL_GPIXFMT))
|
||||
#define GSCTRL_GPIXFMT_ARGB8888 ((0x8) << FShft(GSCTRL_GPIXFMT))
|
||||
#define GSCTRL_GAMMA_EN (1 << 26)
|
||||
|
||||
#define GSCTRL_GSWIDTH Fld(11,11)
|
||||
#define Gsctrl_Width(Pixel) /* Display Width [1..2048 pix.] */ \
|
||||
(((Pixel) - 1) << FShft(GSCTRL_GSWIDTH))
|
||||
|
||||
#define GSCTRL_GSHEIGHT Fld(11,0)
|
||||
#define Gsctrl_Height(Pixel) /* Display Height [1..2048 pix.] */ \
|
||||
(((Pixel) - 1) << FShft(GSCTRL_GSHEIGHT))
|
||||
|
||||
/* GBBASE fileds */
|
||||
#define GBBASE_GLALPHA Fld(8,24)
|
||||
#define Gbbase_Glalpha(x) ((x) << FShft(GBBASE_GLALPHA))
|
||||
|
||||
#define GBBASE_COLKEY Fld(24,0)
|
||||
#define Gbbase_Colkey(x) ((x) << FShft(GBBASE_COLKEY))
|
||||
|
||||
/* GDRCTRL fields */
|
||||
#define GDRCTRL_PIXDBL (1 << 31)
|
||||
#define GDRCTRL_PIXHLV (1 << 30)
|
||||
#define GDRCTRL_LNDBL (1 << 29)
|
||||
#define GDRCTRL_LNHLV (1 << 28)
|
||||
#define GDRCTRL_COLKEYM Fld(24,0)
|
||||
#define Gdrctrl_Colkeym(x) ((x) << FShft(GDRCTRL_COLKEYM))
|
||||
|
||||
/* GSCADR graphics stream control address register fields */
|
||||
#define GSCADR_STR_EN (1 << 31)
|
||||
#define GSCADR_COLKEY_EN (1 << 30)
|
||||
#define GSCADR_COLKEYSRC (1 << 29)
|
||||
#define GSCADR_BLEND_M Fld(2,27)
|
||||
#define GSCADR_BLEND_NONE ((0x0) << FShft(GSCADR_BLEND_M))
|
||||
#define GSCADR_BLEND_INV ((0x1) << FShft(GSCADR_BLEND_M))
|
||||
#define GSCADR_BLEND_GLOB ((0x2) << FShft(GSCADR_BLEND_M))
|
||||
#define GSCADR_BLEND_PIX ((0x3) << FShft(GSCADR_BLEND_M))
|
||||
#define GSCADR_BLEND_POS Fld(2,24)
|
||||
#define GSCADR_BLEND_GFX ((0x0) << FShft(GSCADR_BLEND_POS))
|
||||
#define GSCADR_BLEND_VID ((0x1) << FShft(GSCADR_BLEND_POS))
|
||||
#define GSCADR_BLEND_CUR ((0x2) << FShft(GSCADR_BLEND_POS))
|
||||
#define GSCADR_GBASE_ADR Fld(23,0)
|
||||
#define Gscadr_Gbase_Adr(x) ((x) << FShft(GSCADR_GBASE_ADR))
|
||||
|
||||
/* GSADR graphics stride address register fields */
|
||||
#define GSADR_SRCSTRIDE Fld(10,22)
|
||||
#define Gsadr_Srcstride(x) ((x) << FShft(GSADR_SRCSTRIDE))
|
||||
#define GSADR_XSTART Fld(11,11)
|
||||
#define Gsadr_Xstart(x) ((x) << FShft(GSADR_XSTART))
|
||||
#define GSADR_YSTART Fld(11,0)
|
||||
#define Gsadr_Ystart(y) ((y) << FShft(GSADR_YSTART))
|
||||
|
||||
/* GPLUT graphics palette register fields */
|
||||
#define GPLUT_LUTADR Fld(8,24)
|
||||
#define Gplut_Lutadr(x) ((x) << FShft(GPLUT_LUTADR))
|
||||
#define GPLUT_LUTDATA Fld(24,0)
|
||||
#define Gplut_Lutdata(x) ((x) << FShft(GPLUT_LUTDATA))
|
||||
|
||||
/* VSCTRL - Video Surface Control Register */
|
||||
#define VSCTRL_VPIXFMT Fld(4,27)
|
||||
#define VSCTRL_VPIXFMT_YUV12 ((0x9) << FShft(VSCTRL_VPIXFMT))
|
||||
#define VSCTRL_VPIXFMT_UY0VY1 ((0xc) << FShft(VSCTRL_VPIXFMT))
|
||||
#define VSCTRL_VPIXFMT_VY0UY1 ((0xd) << FShft(VSCTRL_VPIXFMT))
|
||||
#define VSCTRL_VPIXFMT_Y0UY1V ((0xe) << FShft(VSCTRL_VPIXFMT))
|
||||
#define VSCTRL_VPIXFMT_Y0VY1U ((0xf) << FShft(VSCTRL_VPIXFMT))
|
||||
#define VSCTRL_GAMMA_EN (1 << 26)
|
||||
#define VSCTRL_CSC_EN (1 << 25)
|
||||
#define VSCTRL_COSITED (1 << 22)
|
||||
#define VSCTRL_VSWIDTH Fld(11,11)
|
||||
#define Vsctrl_Width(Pixels) /* Video Width [1-2048] */ \
|
||||
(((Pixels) - 1) << FShft(VSCTRL_VSWIDTH))
|
||||
#define VSCTRL_VSHEIGHT Fld(11,0)
|
||||
#define Vsctrl_Height(Pixels) /* Video Height [1-2048] */ \
|
||||
(((Pixels) - 1) << FShft(VSCTRL_VSHEIGHT))
|
||||
|
||||
/* VBBASE - Video Blending Base Register */
|
||||
#define VBBASE_GLALPHA Fld(8,24)
|
||||
#define Vbbase_Glalpha(x) ((x) << FShft(VBBASE_GLALPHA))
|
||||
|
||||
#define VBBASE_COLKEY Fld(24,0)
|
||||
#define Vbbase_Colkey(x) ((x) << FShft(VBBASE_COLKEY))
|
||||
|
||||
/* VCMSK - Video Color Key Mask Register */
|
||||
#define VCMSK_COLKEY_M Fld(24,0)
|
||||
#define Vcmsk_colkey_m(x) ((x) << FShft(VCMSK_COLKEY_M))
|
||||
|
||||
/* VSCADR - Video Stream Control Rddress Register */
|
||||
#define VSCADR_STR_EN (1 << 31)
|
||||
#define VSCADR_COLKEY_EN (1 << 30)
|
||||
#define VSCADR_COLKEYSRC (1 << 29)
|
||||
#define VSCADR_BLEND_M Fld(2,27)
|
||||
#define VSCADR_BLEND_NONE ((0x0) << FShft(VSCADR_BLEND_M))
|
||||
#define VSCADR_BLEND_INV ((0x1) << FShft(VSCADR_BLEND_M))
|
||||
#define VSCADR_BLEND_GLOB ((0x2) << FShft(VSCADR_BLEND_M))
|
||||
#define VSCADR_BLEND_PIX ((0x3) << FShft(VSCADR_BLEND_M))
|
||||
#define VSCADR_BLEND_POS Fld(2,24)
|
||||
#define VSCADR_BLEND_GFX ((0x0) << FShft(VSCADR_BLEND_POS))
|
||||
#define VSCADR_BLEND_VID ((0x1) << FShft(VSCADR_BLEND_POS))
|
||||
#define VSCADR_BLEND_CUR ((0x2) << FShft(VSCADR_BLEND_POS))
|
||||
#define VSCADR_VBASE_ADR Fld(23,0)
|
||||
#define Vscadr_Vbase_Adr(x) ((x) << FShft(VSCADR_VBASE_ADR))
|
||||
|
||||
/* VUBASE - Video U Base Register */
|
||||
#define VUBASE_UVHALFSTR (1 << 31)
|
||||
#define VUBASE_UBASE_ADR Fld(24,0)
|
||||
#define Vubase_Ubase_Adr(x) ((x) << FShft(VUBASE_UBASE_ADR))
|
||||
|
||||
/* VVBASE - Video V Base Register */
|
||||
#define VVBASE_VBASE_ADR Fld(24,0)
|
||||
#define Vvbase_Vbase_Adr(x) ((x) << FShft(VVBASE_VBASE_ADR))
|
||||
|
||||
/* VSADR - Video Stride Address Register */
|
||||
#define VSADR_SRCSTRIDE Fld(10,22)
|
||||
#define Vsadr_Srcstride(x) ((x) << FShft(VSADR_SRCSTRIDE))
|
||||
#define VSADR_XSTART Fld(11,11)
|
||||
#define Vsadr_Xstart(x) ((x) << FShft(VSADR_XSTART))
|
||||
#define VSADR_YSTART Fld(11,0)
|
||||
#define Vsadr_Ystart(x) ((x) << FShft(VSADR_YSTART))
|
||||
|
||||
/* VSCTRL - Video Surface Control Register */
|
||||
#define VSCTRL_VPIXFMT Fld(4,27)
|
||||
#define VSCTRL_VPIXFMT_YUV12 ((0x9) << FShft(VSCTRL_VPIXFMT))
|
||||
#define VSCTRL_VPIXFMT_UY0VY1 ((0xc) << FShft(VSCTRL_VPIXFMT))
|
||||
#define VSCTRL_VPIXFMT_VY0UY1 ((0xd) << FShft(VSCTRL_VPIXFMT))
|
||||
#define VSCTRL_VPIXFMT_Y0UY1V ((0xe) << FShft(VSCTRL_VPIXFMT))
|
||||
#define VSCTRL_VPIXFMT_Y0VY1U ((0xf) << FShft(VSCTRL_VPIXFMT))
|
||||
#define VSCTRL_GAMMA_EN (1 << 26)
|
||||
#define VSCTRL_CSC_EN (1 << 25)
|
||||
#define VSCTRL_COSITED (1 << 22)
|
||||
#define VSCTRL_VSWIDTH Fld(11,11)
|
||||
#define Vsctrl_Width(Pixels) /* Video Width [1-2048] */ \
|
||||
(((Pixels) - 1) << FShft(VSCTRL_VSWIDTH))
|
||||
#define VSCTRL_VSHEIGHT Fld(11,0)
|
||||
#define Vsctrl_Height(Pixels) /* Video Height [1-2048] */ \
|
||||
(((Pixels) - 1) << FShft(VSCTRL_VSHEIGHT))
|
||||
|
||||
/* VBBASE - Video Blending Base Register */
|
||||
#define VBBASE_GLALPHA Fld(8,24)
|
||||
#define Vbbase_Glalpha(x) ((x) << FShft(VBBASE_GLALPHA))
|
||||
|
||||
#define VBBASE_COLKEY Fld(24,0)
|
||||
#define Vbbase_Colkey(x) ((x) << FShft(VBBASE_COLKEY))
|
||||
|
||||
/* VCMSK - Video Color Key Mask Register */
|
||||
#define VCMSK_COLKEY_M Fld(24,0)
|
||||
#define Vcmsk_colkey_m(x) ((x) << FShft(VCMSK_COLKEY_M))
|
||||
|
||||
/* VSCADR - Video Stream Control Rddress Register */
|
||||
#define VSCADR_STR_EN (1 << 31)
|
||||
#define VSCADR_COLKEY_EN (1 << 30)
|
||||
#define VSCADR_COLKEYSRC (1 << 29)
|
||||
#define VSCADR_BLEND_M Fld(2,27)
|
||||
#define VSCADR_BLEND_NONE ((0x0) << FShft(VSCADR_BLEND_M))
|
||||
#define VSCADR_BLEND_INV ((0x1) << FShft(VSCADR_BLEND_M))
|
||||
#define VSCADR_BLEND_GLOB ((0x2) << FShft(VSCADR_BLEND_M))
|
||||
#define VSCADR_BLEND_PIX ((0x3) << FShft(VSCADR_BLEND_M))
|
||||
#define VSCADR_BLEND_POS Fld(2,24)
|
||||
#define VSCADR_BLEND_GFX ((0x0) << FShft(VSCADR_BLEND_POS))
|
||||
#define VSCADR_BLEND_VID ((0x1) << FShft(VSCADR_BLEND_POS))
|
||||
#define VSCADR_BLEND_CUR ((0x2) << FShft(VSCADR_BLEND_POS))
|
||||
#define VSCADR_VBASE_ADR Fld(23,0)
|
||||
#define Vscadr_Vbase_Adr(x) ((x) << FShft(VSCADR_VBASE_ADR))
|
||||
|
||||
/* VUBASE - Video U Base Register */
|
||||
#define VUBASE_UVHALFSTR (1 << 31)
|
||||
#define VUBASE_UBASE_ADR Fld(24,0)
|
||||
#define Vubase_Ubase_Adr(x) ((x) << FShft(VUBASE_UBASE_ADR))
|
||||
|
||||
/* VVBASE - Video V Base Register */
|
||||
#define VVBASE_VBASE_ADR Fld(24,0)
|
||||
#define Vvbase_Vbase_Adr(x) ((x) << FShft(VVBASE_VBASE_ADR))
|
||||
|
||||
/* VSADR - Video Stride Address Register */
|
||||
#define VSADR_SRCSTRIDE Fld(10,22)
|
||||
#define Vsadr_Srcstride(x) ((x) << FShft(VSADR_SRCSTRIDE))
|
||||
#define VSADR_XSTART Fld(11,11)
|
||||
#define Vsadr_Xstart(x) ((x) << FShft(VSADR_XSTART))
|
||||
#define VSADR_YSTART Fld(11,0)
|
||||
#define Vsadr_Ystart(x) ((x) << FShft(VSADR_YSTART))
|
||||
|
||||
/* HCCTRL - Hardware Cursor Register fields */
|
||||
#define HCCTRL_CUR_EN (1 << 31)
|
||||
#define HCCTRL_COLKEY_EN (1 << 29)
|
||||
#define HCCTRL_COLKEYSRC (1 << 28)
|
||||
#define HCCTRL_BLEND_M Fld(2,26)
|
||||
#define HCCTRL_BLEND_NONE ((0x0) << FShft(HCCTRL_BLEND_M))
|
||||
#define HCCTRL_BLEND_INV ((0x1) << FShft(HCCTRL_BLEND_M))
|
||||
#define HCCTRL_BLEND_GLOB ((0x2) << FShft(HCCTRL_BLEND_M))
|
||||
#define HCCTRL_BLEND_PIX ((0x3) << FShft(HCCTRL_BLEND_M))
|
||||
#define HCCTRL_CPIXFMT Fld(3,23)
|
||||
#define HCCTRL_CPIXFMT_RGB332 ((0x3) << FShft(HCCTRL_CPIXFMT))
|
||||
#define HCCTRL_CPIXFMT_ARGB4444 ((0x4) << FShft(HCCTRL_CPIXFMT))
|
||||
#define HCCTRL_CPIXFMT_ARGB1555 ((0x5) << FShft(HCCTRL_CPIXFMT))
|
||||
#define HCCTRL_CBASE_ADR Fld(23,0)
|
||||
#define Hcctrl_Cbase_Adr(x) ((x) << FShft(HCCTRL_CBASE_ADR))
|
||||
|
||||
/* HCSIZE Hardware Cursor Size Register fields */
|
||||
#define HCSIZE_BLEND_POS Fld(2,29)
|
||||
#define HCSIZE_BLEND_GFX ((0x0) << FShft(HCSIZE_BLEND_POS))
|
||||
#define HCSIZE_BLEND_VID ((0x1) << FShft(HCSIZE_BLEND_POS))
|
||||
#define HCSIZE_BLEND_CUR ((0x2) << FShft(HCSIZE_BLEND_POS))
|
||||
#define HCSIZE_CWIDTH Fld(3,16)
|
||||
#define Hcsize_Cwidth(x) ((x) << FShft(HCSIZE_CWIDTH))
|
||||
#define HCSIZE_CHEIGHT Fld(3,0)
|
||||
#define Hcsize_Cheight(x) ((x) << FShft(HCSIZE_CHEIGHT))
|
||||
|
||||
/* HCPOS Hardware Cursor Position Register fields */
|
||||
#define HCPOS_SWITCHSRC (1 << 30)
|
||||
#define HCPOS_CURBLINK Fld(6,24)
|
||||
#define Hcpos_Curblink(x) ((x) << FShft(HCPOS_CURBLINK))
|
||||
#define HCPOS_XSTART Fld(12,12)
|
||||
#define Hcpos_Xstart(x) ((x) << FShft(HCPOS_XSTART))
|
||||
#define HCPOS_YSTART Fld(12,0)
|
||||
#define Hcpos_Ystart(y) ((y) << FShft(HCPOS_YSTART))
|
||||
|
||||
/* HCBADR Hardware Cursor Blend Address Register */
|
||||
#define HCBADR_GLALPHA Fld(8,24)
|
||||
#define Hcbadr_Glalpha(x) ((x) << FShft(HCBADR_GLALPHA))
|
||||
#define HCBADR_COLKEY Fld(24,0)
|
||||
#define Hcbadr_Colkey(x) ((x) << FShft(HCBADR_COLKEY))
|
||||
|
||||
/* HCCKMSK - Hardware Cursor Color Key Mask Register */
|
||||
#define HCCKMSK_COLKEY_M Fld(24,0)
|
||||
#define Hcckmsk_Colkey_M(x) ((x) << FShft(HCCKMSK_COLKEY_M))
|
||||
|
||||
/* DSCTRL - Display sync control register */
|
||||
#define DSCTRL_SYNCGEN_EN (1 << 31)
|
||||
#define DSCTRL_DPL_RST (1 << 29)
|
||||
#define DSCTRL_PWRDN_M (1 << 28)
|
||||
#define DSCTRL_UPDSYNCCNT (1 << 26)
|
||||
#define DSCTRL_UPDINTCNT (1 << 25)
|
||||
#define DSCTRL_UPDCNT (1 << 24)
|
||||
#define DSCTRL_UPDWAIT Fld(4,16)
|
||||
#define Dsctrl_Updwait(x) ((x) << FShft(DSCTRL_UPDWAIT))
|
||||
#define DSCTRL_CLKPOL (1 << 11)
|
||||
#define DSCTRL_CSYNC_EN (1 << 10)
|
||||
#define DSCTRL_VS_SLAVE (1 << 7)
|
||||
#define DSCTRL_HS_SLAVE (1 << 6)
|
||||
#define DSCTRL_BLNK_POL (1 << 5)
|
||||
#define DSCTRL_BLNK_DIS (1 << 4)
|
||||
#define DSCTRL_VS_POL (1 << 3)
|
||||
#define DSCTRL_VS_DIS (1 << 2)
|
||||
#define DSCTRL_HS_POL (1 << 1)
|
||||
#define DSCTRL_HS_DIS (1 << 0)
|
||||
|
||||
/* DHT01 - Display horizontal timing register 01 */
|
||||
#define DHT01_HBPS Fld(12,16)
|
||||
#define Dht01_Hbps(x) ((x) << FShft(DHT01_HBPS))
|
||||
#define DHT01_HT Fld(12,0)
|
||||
#define Dht01_Ht(x) ((x) << FShft(DHT01_HT))
|
||||
|
||||
/* DHT02 - Display horizontal timing register 02 */
|
||||
#define DHT02_HAS Fld(12,16)
|
||||
#define Dht02_Has(x) ((x) << FShft(DHT02_HAS))
|
||||
#define DHT02_HLBS Fld(12,0)
|
||||
#define Dht02_Hlbs(x) ((x) << FShft(DHT02_HLBS))
|
||||
|
||||
/* DHT03 - Display horizontal timing register 03 */
|
||||
#define DHT03_HFPS Fld(12,16)
|
||||
#define Dht03_Hfps(x) ((x) << FShft(DHT03_HFPS))
|
||||
#define DHT03_HRBS Fld(12,0)
|
||||
#define Dht03_Hrbs(x) ((x) << FShft(DHT03_HRBS))
|
||||
|
||||
/* DVT01 - Display vertical timing register 01 */
|
||||
#define DVT01_VBPS Fld(12,16)
|
||||
#define Dvt01_Vbps(x) ((x) << FShft(DVT01_VBPS))
|
||||
#define DVT01_VT Fld(12,0)
|
||||
#define Dvt01_Vt(x) ((x) << FShft(DVT01_VT))
|
||||
|
||||
/* DVT02 - Display vertical timing register 02 */
|
||||
#define DVT02_VAS Fld(12,16)
|
||||
#define Dvt02_Vas(x) ((x) << FShft(DVT02_VAS))
|
||||
#define DVT02_VTBS Fld(12,0)
|
||||
#define Dvt02_Vtbs(x) ((x) << FShft(DVT02_VTBS))
|
||||
|
||||
/* DVT03 - Display vertical timing register 03 */
|
||||
#define DVT03_VFPS Fld(12,16)
|
||||
#define Dvt03_Vfps(x) ((x) << FShft(DVT03_VFPS))
|
||||
#define DVT03_VBBS Fld(12,0)
|
||||
#define Dvt03_Vbbs(x) ((x) << FShft(DVT03_VBBS))
|
||||
|
||||
/* DVECTRL - display vertical event control register */
|
||||
#define DVECTRL_VEVENT Fld(12,16)
|
||||
#define Dvectrl_Vevent(x) ((x) << FShft(DVECTRL_VEVENT))
|
||||
#define DVECTRL_VFETCH Fld(12,0)
|
||||
#define Dvectrl_Vfetch(x) ((x) << FShft(DVECTRL_VFETCH))
|
||||
|
||||
/* DHDET - display horizontal DE timing register */
|
||||
#define DHDET_HDES Fld(12,16)
|
||||
#define Dhdet_Hdes(x) ((x) << FShft(DHDET_HDES))
|
||||
#define DHDET_HDEF Fld(12,0)
|
||||
#define Dhdet_Hdef(x) ((x) << FShft(DHDET_HDEF))
|
||||
|
||||
/* DVDET - display vertical DE timing register */
|
||||
#define DVDET_VDES Fld(12,16)
|
||||
#define Dvdet_Vdes(x) ((x) << FShft(DVDET_VDES))
|
||||
#define DVDET_VDEF Fld(12,0)
|
||||
#define Dvdet_Vdef(x) ((x) << FShft(DVDET_VDEF))
|
||||
|
||||
/* DODMSK - display output data mask register */
|
||||
#define DODMSK_MASK_LVL (1 << 31)
|
||||
#define DODMSK_BLNK_LVL (1 << 30)
|
||||
#define DODMSK_MASK_B Fld(8,16)
|
||||
#define Dodmsk_Mask_B(x) ((x) << FShft(DODMSK_MASK_B))
|
||||
#define DODMSK_MASK_G Fld(8,8)
|
||||
#define Dodmsk_Mask_G(x) ((x) << FShft(DODMSK_MASK_G))
|
||||
#define DODMSK_MASK_R Fld(8,0)
|
||||
#define Dodmsk_Mask_R(x) ((x) << FShft(DODMSK_MASK_R))
|
||||
|
||||
/* DBCOL - display border color control register */
|
||||
#define DBCOL_BORDCOL Fld(24,0)
|
||||
#define Dbcol_Bordcol(x) ((x) << FShft(DBCOL_BORDCOL))
|
||||
|
||||
/* DVLNUM - display vertical line number register */
|
||||
#define DVLNUM_VLINE Fld(12,0)
|
||||
#define Dvlnum_Vline(x) ((x) << FShft(DVLNUM_VLINE))
|
||||
|
||||
/* DMCTRL - Display Memory Control Register */
|
||||
#define DMCTRL_MEM_REF Fld(2,30)
|
||||
#define DMCTRL_MEM_REF_ACT ((0x0) << FShft(DMCTRL_MEM_REF))
|
||||
#define DMCTRL_MEM_REF_HB ((0x1) << FShft(DMCTRL_MEM_REF))
|
||||
#define DMCTRL_MEM_REF_VB ((0x2) << FShft(DMCTRL_MEM_REF))
|
||||
#define DMCTRL_MEM_REF_BOTH ((0x3) << FShft(DMCTRL_MEM_REF))
|
||||
#define DMCTRL_UV_THRHLD Fld(6,24)
|
||||
#define Dmctrl_Uv_Thrhld(x) ((x) << FShft(DMCTRL_UV_THRHLD))
|
||||
#define DMCTRL_V_THRHLD Fld(7,16)
|
||||
#define Dmctrl_V_Thrhld(x) ((x) << FShft(DMCTRL_V_THRHLD))
|
||||
#define DMCTRL_D_THRHLD Fld(7,8)
|
||||
#define Dmctrl_D_Thrhld(x) ((x) << FShft(DMCTRL_D_THRHLD))
|
||||
#define DMCTRL_BURSTLEN Fld(6,0)
|
||||
#define Dmctrl_Burstlen(x) ((x) << FShft(DMCTRL_BURSTLEN))
|
||||
|
||||
/* DINTRS - Display Interrupt Status Register */
|
||||
#define DINTRS_CUR_OR_S (1 << 18)
|
||||
#define DINTRS_STR2_OR_S (1 << 17)
|
||||
#define DINTRS_STR1_OR_S (1 << 16)
|
||||
#define DINTRS_CUR_UR_S (1 << 6)
|
||||
#define DINTRS_STR2_UR_S (1 << 5)
|
||||
#define DINTRS_STR1_UR_S (1 << 4)
|
||||
#define DINTRS_VEVENT1_S (1 << 3)
|
||||
#define DINTRS_VEVENT0_S (1 << 2)
|
||||
#define DINTRS_HBLNK1_S (1 << 1)
|
||||
#define DINTRS_HBLNK0_S (1 << 0)
|
||||
|
||||
/* DINTRE - Display Interrupt Enable Register */
|
||||
#define DINTRE_CUR_OR_EN (1 << 18)
|
||||
#define DINTRE_STR2_OR_EN (1 << 17)
|
||||
#define DINTRE_STR1_OR_EN (1 << 16)
|
||||
#define DINTRE_CUR_UR_EN (1 << 6)
|
||||
#define DINTRE_STR2_UR_EN (1 << 5)
|
||||
#define DINTRE_STR1_UR_EN (1 << 4)
|
||||
#define DINTRE_VEVENT1_EN (1 << 3)
|
||||
#define DINTRE_VEVENT0_EN (1 << 2)
|
||||
#define DINTRE_HBLNK1_EN (1 << 1)
|
||||
#define DINTRE_HBLNK0_EN (1 << 0)
|
||||
|
||||
/* DINTRS - Display Interrupt Status Register */
|
||||
#define DINTRS_CUR_OR_S (1 << 18)
|
||||
#define DINTRS_STR2_OR_S (1 << 17)
|
||||
#define DINTRS_STR1_OR_S (1 << 16)
|
||||
#define DINTRS_CUR_UR_S (1 << 6)
|
||||
#define DINTRS_STR2_UR_S (1 << 5)
|
||||
#define DINTRS_STR1_UR_S (1 << 4)
|
||||
#define DINTRS_VEVENT1_S (1 << 3)
|
||||
#define DINTRS_VEVENT0_S (1 << 2)
|
||||
#define DINTRS_HBLNK1_S (1 << 1)
|
||||
#define DINTRS_HBLNK0_S (1 << 0)
|
||||
|
||||
/* DINTRE - Display Interrupt Enable Register */
|
||||
#define DINTRE_CUR_OR_EN (1 << 18)
|
||||
#define DINTRE_STR2_OR_EN (1 << 17)
|
||||
#define DINTRE_STR1_OR_EN (1 << 16)
|
||||
#define DINTRE_CUR_UR_EN (1 << 6)
|
||||
#define DINTRE_STR2_UR_EN (1 << 5)
|
||||
#define DINTRE_STR1_UR_EN (1 << 4)
|
||||
#define DINTRE_VEVENT1_EN (1 << 3)
|
||||
#define DINTRE_VEVENT0_EN (1 << 2)
|
||||
#define DINTRE_HBLNK1_EN (1 << 1)
|
||||
#define DINTRE_HBLNK0_EN (1 << 0)
|
||||
|
||||
|
||||
/* DLSTS - display load status register */
|
||||
#define DLSTS_RLD_ADONE (1 << 23)
|
||||
/* #define DLSTS_RLD_ADOUT Fld(23,0) */
|
||||
|
||||
/* DLLCTRL - display list load control register */
|
||||
#define DLLCTRL_RLD_ADRLN Fld(8,24)
|
||||
#define Dllctrl_Rld_Adrln(x) ((x) << FShft(DLLCTRL_RLD_ADRLN))
|
||||
|
||||
/* CLIPCTRL - Clipping Control Register */
|
||||
#define CLIPCTRL_HSKIP Fld(11,16)
|
||||
#define Clipctrl_Hskip ((x) << FShft(CLIPCTRL_HSKIP))
|
||||
#define CLIPCTRL_VSKIP Fld(11,0)
|
||||
#define Clipctrl_Vskip ((x) << FShft(CLIPCTRL_VSKIP))
|
||||
|
||||
/* SPOCTRL - Scale Pitch/Order Control Register */
|
||||
#define SPOCTRL_H_SC_BP (1 << 31)
|
||||
#define SPOCTRL_V_SC_BP (1 << 30)
|
||||
#define SPOCTRL_HV_SC_OR (1 << 29)
|
||||
#define SPOCTRL_VS_UR_C (1 << 27)
|
||||
#define SPOCTRL_VORDER Fld(2,16)
|
||||
#define SPOCTRL_VORDER_1TAP ((0x0) << FShft(SPOCTRL_VORDER))
|
||||
#define SPOCTRL_VORDER_2TAP ((0x1) << FShft(SPOCTRL_VORDER))
|
||||
#define SPOCTRL_VORDER_4TAP ((0x3) << FShft(SPOCTRL_VORDER))
|
||||
#define SPOCTRL_VPITCH Fld(16,0)
|
||||
#define Spoctrl_Vpitch(x) ((x) << FShft(SPOCTRL_VPITCH))
|
||||
|
||||
/* SVCTRL - Scale Vertical Control Register */
|
||||
#define SVCTRL_INITIAL1 Fld(16,16)
|
||||
#define Svctrl_Initial1(x) ((x) << FShft(SVCTRL_INITIAL1))
|
||||
#define SVCTRL_INITIAL2 Fld(16,0)
|
||||
#define Svctrl_Initial2(x) ((x) << FShft(SVCTRL_INITIAL2))
|
||||
|
||||
/* SHCTRL - Scale Horizontal Control Register */
|
||||
#define SHCTRL_HINITIAL Fld(16,16)
|
||||
#define Shctrl_Hinitial(x) ((x) << FShft(SHCTRL_HINITIAL))
|
||||
#define SHCTRL_HDECIM (1 << 15)
|
||||
#define SHCTRL_HPITCH Fld(15,0)
|
||||
#define Shctrl_Hpitch(x) ((x) << FShft(SHCTRL_HPITCH))
|
||||
|
||||
/* SSSIZE - Scale Surface Size Register */
|
||||
#define SSSIZE_SC_WIDTH Fld(11,16)
|
||||
#define Sssize_Sc_Width(x) ((x) << FShft(SSSIZE_SC_WIDTH))
|
||||
#define SSSIZE_SC_HEIGHT Fld(11,0)
|
||||
#define Sssize_Sc_Height(x) ((x) << FShft(SSSIZE_SC_HEIGHT))
|
||||
|
||||
#endif /* __REG_BITS_2700G_ */
|
||||
195
drivers/video/fbdev/mbx/regs.h
Normal file
195
drivers/video/fbdev/mbx/regs.h
Normal file
|
|
@ -0,0 +1,195 @@
|
|||
#ifndef __REGS_2700G_
|
||||
#define __REGS_2700G_
|
||||
|
||||
/* extern unsigned long virt_base_2700; */
|
||||
/* #define __REG_2700G(x) (*(volatile unsigned long*)((x)+virt_base_2700)) */
|
||||
#define __REG_2700G(x) ((x)+virt_base_2700)
|
||||
|
||||
/* System Configuration Registers (0x0000_0000 0x0000_0010) */
|
||||
#define SYSCFG __REG_2700G(0x00000000)
|
||||
#define PFBASE __REG_2700G(0x00000004)
|
||||
#define PFCEIL __REG_2700G(0x00000008)
|
||||
#define POLLFLAG __REG_2700G(0x0000000c)
|
||||
#define SYSRST __REG_2700G(0x00000010)
|
||||
|
||||
/* Interrupt Control Registers (0x0000_0014 0x0000_002F) */
|
||||
#define NINTPW __REG_2700G(0x00000014)
|
||||
#define MINTENABLE __REG_2700G(0x00000018)
|
||||
#define MINTSTAT __REG_2700G(0x0000001c)
|
||||
#define SINTENABLE __REG_2700G(0x00000020)
|
||||
#define SINTSTAT __REG_2700G(0x00000024)
|
||||
#define SINTCLR __REG_2700G(0x00000028)
|
||||
|
||||
/* Clock Control Registers (0x0000_002C 0x0000_005F) */
|
||||
#define SYSCLKSRC __REG_2700G(0x0000002c)
|
||||
#define PIXCLKSRC __REG_2700G(0x00000030)
|
||||
#define CLKSLEEP __REG_2700G(0x00000034)
|
||||
#define COREPLL __REG_2700G(0x00000038)
|
||||
#define DISPPLL __REG_2700G(0x0000003c)
|
||||
#define PLLSTAT __REG_2700G(0x00000040)
|
||||
#define VOVRCLK __REG_2700G(0x00000044)
|
||||
#define PIXCLK __REG_2700G(0x00000048)
|
||||
#define MEMCLK __REG_2700G(0x0000004c)
|
||||
#define M24CLK __REG_2700G(0x00000050)
|
||||
#define MBXCLK __REG_2700G(0x00000054)
|
||||
#define SDCLK __REG_2700G(0x00000058)
|
||||
#define PIXCLKDIV __REG_2700G(0x0000005c)
|
||||
|
||||
/* LCD Port Control Register (0x0000_0060 0x0000_006F) */
|
||||
#define LCD_CONFIG __REG_2700G(0x00000060)
|
||||
|
||||
/* On-Die Frame Buffer Registers (0x0000_0064 0x0000_006B) */
|
||||
#define ODFBPWR __REG_2700G(0x00000064)
|
||||
#define ODFBSTAT __REG_2700G(0x00000068)
|
||||
|
||||
/* GPIO Registers (0x0000_006C 0x0000_007F) */
|
||||
#define GPIOCGF __REG_2700G(0x0000006c)
|
||||
#define GPIOHI __REG_2700G(0x00000070)
|
||||
#define GPIOLO __REG_2700G(0x00000074)
|
||||
#define GPIOSTAT __REG_2700G(0x00000078)
|
||||
|
||||
/* Pulse Width Modulator (PWM) Registers (0x0000_0200 0x0000_02FF) */
|
||||
#define PWMRST __REG_2700G(0x00000200)
|
||||
#define PWMCFG __REG_2700G(0x00000204)
|
||||
#define PWM0DIV __REG_2700G(0x00000210)
|
||||
#define PWM0DUTY __REG_2700G(0x00000214)
|
||||
#define PWM0PER __REG_2700G(0x00000218)
|
||||
#define PWM1DIV __REG_2700G(0x00000220)
|
||||
#define PWM1DUTY __REG_2700G(0x00000224)
|
||||
#define PWM1PER __REG_2700G(0x00000228)
|
||||
|
||||
/* Identification (ID) Registers (0x0000_0300 0x0000_0FFF) */
|
||||
#define ID __REG_2700G(0x00000FF0)
|
||||
|
||||
/* Local Memory (SDRAM) Interface Registers (0x0000_1000 0x0000_1FFF) */
|
||||
#define LMRST __REG_2700G(0x00001000)
|
||||
#define LMCFG __REG_2700G(0x00001004)
|
||||
#define LMPWR __REG_2700G(0x00001008)
|
||||
#define LMPWRSTAT __REG_2700G(0x0000100c)
|
||||
#define LMCEMR __REG_2700G(0x00001010)
|
||||
#define LMTYPE __REG_2700G(0x00001014)
|
||||
#define LMTIM __REG_2700G(0x00001018)
|
||||
#define LMREFRESH __REG_2700G(0x0000101c)
|
||||
#define LMPROTMIN __REG_2700G(0x00001020)
|
||||
#define LMPROTMAX __REG_2700G(0x00001024)
|
||||
#define LMPROTCFG __REG_2700G(0x00001028)
|
||||
#define LMPROTERR __REG_2700G(0x0000102c)
|
||||
|
||||
/* Plane Controller Registers (0x0000_2000 0x0000_2FFF) */
|
||||
#define GSCTRL __REG_2700G(0x00002000)
|
||||
#define VSCTRL __REG_2700G(0x00002004)
|
||||
#define GBBASE __REG_2700G(0x00002020)
|
||||
#define VBBASE __REG_2700G(0x00002024)
|
||||
#define GDRCTRL __REG_2700G(0x00002040)
|
||||
#define VCMSK __REG_2700G(0x00002044)
|
||||
#define GSCADR __REG_2700G(0x00002060)
|
||||
#define VSCADR __REG_2700G(0x00002064)
|
||||
#define VUBASE __REG_2700G(0x00002084)
|
||||
#define VVBASE __REG_2700G(0x000020a4)
|
||||
#define GSADR __REG_2700G(0x000020c0)
|
||||
#define VSADR __REG_2700G(0x000020c4)
|
||||
#define HCCTRL __REG_2700G(0x00002100)
|
||||
#define HCSIZE __REG_2700G(0x00002110)
|
||||
#define HCPOS __REG_2700G(0x00002120)
|
||||
#define HCBADR __REG_2700G(0x00002130)
|
||||
#define HCCKMSK __REG_2700G(0x00002140)
|
||||
#define GPLUT __REG_2700G(0x00002150)
|
||||
#define DSCTRL __REG_2700G(0x00002154)
|
||||
#define DHT01 __REG_2700G(0x00002158)
|
||||
#define DHT02 __REG_2700G(0x0000215c)
|
||||
#define DHT03 __REG_2700G(0x00002160)
|
||||
#define DVT01 __REG_2700G(0x00002164)
|
||||
#define DVT02 __REG_2700G(0x00002168)
|
||||
#define DVT03 __REG_2700G(0x0000216c)
|
||||
#define DBCOL __REG_2700G(0x00002170)
|
||||
#define BGCOLOR __REG_2700G(0x00002174)
|
||||
#define DINTRS __REG_2700G(0x00002178)
|
||||
#define DINTRE __REG_2700G(0x0000217c)
|
||||
#define DINTRCNT __REG_2700G(0x00002180)
|
||||
#define DSIG __REG_2700G(0x00002184)
|
||||
#define DMCTRL __REG_2700G(0x00002188)
|
||||
#define CLIPCTRL __REG_2700G(0x0000218c)
|
||||
#define SPOCTRL __REG_2700G(0x00002190)
|
||||
#define SVCTRL __REG_2700G(0x00002194)
|
||||
|
||||
/* 0x0000_2198 */
|
||||
/* 0x0000_21A8 VSCOEFF[0:4] Video Scalar Vertical Coefficient [0:4] 4.14.5 */
|
||||
#define VSCOEFF0 __REG_2700G(0x00002198)
|
||||
#define VSCOEFF1 __REG_2700G(0x0000219c)
|
||||
#define VSCOEFF2 __REG_2700G(0x000021a0)
|
||||
#define VSCOEFF3 __REG_2700G(0x000021a4)
|
||||
#define VSCOEFF4 __REG_2700G(0x000021a8)
|
||||
|
||||
#define SHCTRL __REG_2700G(0x000021b0)
|
||||
|
||||
/* 0x0000_21B4 */
|
||||
/* 0x0000_21D4 HSCOEFF[0:8] Video Scalar Horizontal Coefficient [0:8] 4.14.7 */
|
||||
#define HSCOEFF0 __REG_2700G(0x000021b4)
|
||||
#define HSCOEFF1 __REG_2700G(0x000021b8)
|
||||
#define HSCOEFF2 __REG_2700G(0x000021bc)
|
||||
#define HSCOEFF3 __REG_2700G(0x000021c0)
|
||||
#define HSCOEFF4 __REG_2700G(0x000021c4)
|
||||
#define HSCOEFF5 __REG_2700G(0x000021c8)
|
||||
#define HSCOEFF6 __REG_2700G(0x000021cc)
|
||||
#define HSCOEFF7 __REG_2700G(0x000021d0)
|
||||
#define HSCOEFF8 __REG_2700G(0x000021d4)
|
||||
|
||||
#define SSSIZE __REG_2700G(0x000021D8)
|
||||
|
||||
/* 0x0000_2200 */
|
||||
/* 0x0000_2240 VIDGAM[0:16] Video Gamma LUT Index [0:16] 4.15.2 */
|
||||
#define VIDGAM0 __REG_2700G(0x00002200)
|
||||
#define VIDGAM1 __REG_2700G(0x00002204)
|
||||
#define VIDGAM2 __REG_2700G(0x00002208)
|
||||
#define VIDGAM3 __REG_2700G(0x0000220c)
|
||||
#define VIDGAM4 __REG_2700G(0x00002210)
|
||||
#define VIDGAM5 __REG_2700G(0x00002214)
|
||||
#define VIDGAM6 __REG_2700G(0x00002218)
|
||||
#define VIDGAM7 __REG_2700G(0x0000221c)
|
||||
#define VIDGAM8 __REG_2700G(0x00002220)
|
||||
#define VIDGAM9 __REG_2700G(0x00002224)
|
||||
#define VIDGAM10 __REG_2700G(0x00002228)
|
||||
#define VIDGAM11 __REG_2700G(0x0000222c)
|
||||
#define VIDGAM12 __REG_2700G(0x00002230)
|
||||
#define VIDGAM13 __REG_2700G(0x00002234)
|
||||
#define VIDGAM14 __REG_2700G(0x00002238)
|
||||
#define VIDGAM15 __REG_2700G(0x0000223c)
|
||||
#define VIDGAM16 __REG_2700G(0x00002240)
|
||||
|
||||
/* 0x0000_2250 */
|
||||
/* 0x0000_2290 GFXGAM[0:16] Graphics Gamma LUT Index [0:16] 4.15.3 */
|
||||
#define GFXGAM0 __REG_2700G(0x00002250)
|
||||
#define GFXGAM1 __REG_2700G(0x00002254)
|
||||
#define GFXGAM2 __REG_2700G(0x00002258)
|
||||
#define GFXGAM3 __REG_2700G(0x0000225c)
|
||||
#define GFXGAM4 __REG_2700G(0x00002260)
|
||||
#define GFXGAM5 __REG_2700G(0x00002264)
|
||||
#define GFXGAM6 __REG_2700G(0x00002268)
|
||||
#define GFXGAM7 __REG_2700G(0x0000226c)
|
||||
#define GFXGAM8 __REG_2700G(0x00002270)
|
||||
#define GFXGAM9 __REG_2700G(0x00002274)
|
||||
#define GFXGAM10 __REG_2700G(0x00002278)
|
||||
#define GFXGAM11 __REG_2700G(0x0000227c)
|
||||
#define GFXGAM12 __REG_2700G(0x00002280)
|
||||
#define GFXGAM13 __REG_2700G(0x00002284)
|
||||
#define GFXGAM14 __REG_2700G(0x00002288)
|
||||
#define GFXGAM15 __REG_2700G(0x0000228c)
|
||||
#define GFXGAM16 __REG_2700G(0x00002290)
|
||||
|
||||
#define DLSTS __REG_2700G(0x00002300)
|
||||
#define DLLCTRL __REG_2700G(0x00002304)
|
||||
#define DVLNUM __REG_2700G(0x00002308)
|
||||
#define DUCTRL __REG_2700G(0x0000230c)
|
||||
#define DVECTRL __REG_2700G(0x00002310)
|
||||
#define DHDET __REG_2700G(0x00002314)
|
||||
#define DVDET __REG_2700G(0x00002318)
|
||||
#define DODMSK __REG_2700G(0x0000231c)
|
||||
#define CSC01 __REG_2700G(0x00002330)
|
||||
#define CSC02 __REG_2700G(0x00002334)
|
||||
#define CSC03 __REG_2700G(0x00002338)
|
||||
#define CSC04 __REG_2700G(0x0000233c)
|
||||
#define CSC05 __REG_2700G(0x00002340)
|
||||
|
||||
#define FB_MEMORY_START __REG_2700G(0x00060000)
|
||||
|
||||
#endif /* __REGS_2700G_ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue