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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
commit f6dfaef42e
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13
drivers/video/fbdev/nvidia/Makefile Normal file
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#
# Makefile for the nVidia framebuffer driver
#
obj-$(CONFIG_FB_NVIDIA) += nvidiafb.o
nvidiafb-y := nvidia.o nv_hw.o nv_setup.o \
nv_accel.o
nvidiafb-$(CONFIG_FB_NVIDIA_I2C) += nv_i2c.o
nvidiafb-$(CONFIG_FB_NVIDIA_BACKLIGHT) += nv_backlight.o
nvidiafb-$(CONFIG_PPC_OF) += nv_of.o
nvidiafb-objs := $(nvidiafb-y)

416
drivers/video/fbdev/nvidia/nv_accel.c Normal file
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/***************************************************************************\
|* *|
|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
|* *|
|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
|* international laws. Users and possessors of this source code are *|
|* hereby granted a nonexclusive, royalty-free copyright license to *|
|* use this code in individual and commercial software. *|
|* *|
|* Any use of this source code must include, in the user documenta- *|
|* tion and internal comments to the code, notices to the end user *|
|* as follows: *|
|* *|
|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
|* *|
|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
|* *|
|* U.S. Government End Users. This source code is a "commercial *|
|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
|* consisting of "commercial computer software" and "commercial *|
|* computer software documentation," as such terms are used in *|
|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
|* all U.S. Government End Users acquire the source code with only *|
|* those rights set forth herein. *|
|* *|
\***************************************************************************/
/*
* GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
* XFree86 'nv' driver, this source code is provided under MIT-style licensing
* where the source code is provided "as is" without warranty of any kind.
* The only usage restriction is for the copyright notices to be retained
* whenever code is used.
*
* Antonino Daplas <adaplas@pol.net> 2005-03-11
*/
#include <linux/fb.h>
#include "nv_type.h"
#include "nv_proto.h"
#include "nv_dma.h"
#include "nv_local.h"
/* There is a HW race condition with videoram command buffers.
You can't jump to the location of your put offset. We write put
at the jump offset + SKIPS dwords with noop padding in between
to solve this problem */
#define SKIPS 8
static const int NVCopyROP[16] = {
0xCC, /* copy */
0x55 /* invert */
};
static const int NVCopyROP_PM[16] = {
0xCA, /* copy */
0x5A, /* invert */
};
static inline void nvidiafb_safe_mode(struct fb_info *info)
{
struct nvidia_par *par = info->par;
touch_softlockup_watchdog();
info->pixmap.scan_align = 1;
par->lockup = 1;
}
static inline void NVFlush(struct fb_info *info)
{
struct nvidia_par *par = info->par;
int count = 1000000000;
while (--count && READ_GET(par) != par->dmaPut) ;
if (!count) {
printk("nvidiafb: DMA Flush lockup\n");
nvidiafb_safe_mode(info);
}
}
static inline void NVSync(struct fb_info *info)
{
struct nvidia_par *par = info->par;
int count = 1000000000;
while (--count && NV_RD32(par->PGRAPH, 0x0700)) ;
if (!count) {
printk("nvidiafb: DMA Sync lockup\n");
nvidiafb_safe_mode(info);
}
}
static void NVDmaKickoff(struct nvidia_par *par)
{
if (par->dmaCurrent != par->dmaPut) {
par->dmaPut = par->dmaCurrent;
WRITE_PUT(par, par->dmaPut);
}
}
static void NVDmaWait(struct fb_info *info, int size)
{
struct nvidia_par *par = info->par;
int dmaGet;
int count = 1000000000, cnt;
size++;
while (par->dmaFree < size && --count && !par->lockup) {
dmaGet = READ_GET(par);
if (par->dmaPut >= dmaGet) {
par->dmaFree = par->dmaMax - par->dmaCurrent;
if (par->dmaFree < size) {
NVDmaNext(par, 0x20000000);
if (dmaGet <= SKIPS) {
if (par->dmaPut <= SKIPS)
WRITE_PUT(par, SKIPS + 1);
cnt = 1000000000;
do {
dmaGet = READ_GET(par);
} while (--cnt && dmaGet <= SKIPS);
if (!cnt) {
printk("DMA Get lockup\n");
par->lockup = 1;
}
}
WRITE_PUT(par, SKIPS);
par->dmaCurrent = par->dmaPut = SKIPS;
par->dmaFree = dmaGet - (SKIPS + 1);
}
} else
par->dmaFree = dmaGet - par->dmaCurrent - 1;
}
if (!count) {
printk("nvidiafb: DMA Wait Lockup\n");
nvidiafb_safe_mode(info);
}
}
static void NVSetPattern(struct fb_info *info, u32 clr0, u32 clr1,
u32 pat0, u32 pat1)
{
struct nvidia_par *par = info->par;
NVDmaStart(info, par, PATTERN_COLOR_0, 4);
NVDmaNext(par, clr0);
NVDmaNext(par, clr1);
NVDmaNext(par, pat0);
NVDmaNext(par, pat1);
}
static void NVSetRopSolid(struct fb_info *info, u32 rop, u32 planemask)
{
struct nvidia_par *par = info->par;
if (planemask != ~0) {
NVSetPattern(info, 0, planemask, ~0, ~0);
if (par->currentRop != (rop + 32)) {
NVDmaStart(info, par, ROP_SET, 1);
NVDmaNext(par, NVCopyROP_PM[rop]);
par->currentRop = rop + 32;
}
} else if (par->currentRop != rop) {
if (par->currentRop >= 16)
NVSetPattern(info, ~0, ~0, ~0, ~0);
NVDmaStart(info, par, ROP_SET, 1);
NVDmaNext(par, NVCopyROP[rop]);
par->currentRop = rop;
}
}
static void NVSetClippingRectangle(struct fb_info *info, int x1, int y1,
int x2, int y2)
{
struct nvidia_par *par = info->par;
int h = y2 - y1 + 1;
int w = x2 - x1 + 1;
NVDmaStart(info, par, CLIP_POINT, 2);
NVDmaNext(par, (y1 << 16) | x1);
NVDmaNext(par, (h << 16) | w);
}
void NVResetGraphics(struct fb_info *info)
{
struct nvidia_par *par = info->par;
u32 surfaceFormat, patternFormat, rectFormat, lineFormat;
int pitch, i;
pitch = info->fix.line_length;
par->dmaBase = (u32 __iomem *) (&par->FbStart[par->FbUsableSize]);
for (i = 0; i < SKIPS; i++)
NV_WR32(&par->dmaBase[i], 0, 0x00000000);
NV_WR32(&par->dmaBase[0x0 + SKIPS], 0, 0x00040000);
NV_WR32(&par->dmaBase[0x1 + SKIPS], 0, 0x80000010);
NV_WR32(&par->dmaBase[0x2 + SKIPS], 0, 0x00042000);
NV_WR32(&par->dmaBase[0x3 + SKIPS], 0, 0x80000011);
NV_WR32(&par->dmaBase[0x4 + SKIPS], 0, 0x00044000);
NV_WR32(&par->dmaBase[0x5 + SKIPS], 0, 0x80000012);
NV_WR32(&par->dmaBase[0x6 + SKIPS], 0, 0x00046000);
NV_WR32(&par->dmaBase[0x7 + SKIPS], 0, 0x80000013);
NV_WR32(&par->dmaBase[0x8 + SKIPS], 0, 0x00048000);
NV_WR32(&par->dmaBase[0x9 + SKIPS], 0, 0x80000014);
NV_WR32(&par->dmaBase[0xA + SKIPS], 0, 0x0004A000);
NV_WR32(&par->dmaBase[0xB + SKIPS], 0, 0x80000015);
NV_WR32(&par->dmaBase[0xC + SKIPS], 0, 0x0004C000);
NV_WR32(&par->dmaBase[0xD + SKIPS], 0, 0x80000016);
NV_WR32(&par->dmaBase[0xE + SKIPS], 0, 0x0004E000);
NV_WR32(&par->dmaBase[0xF + SKIPS], 0, 0x80000017);
par->dmaPut = 0;
par->dmaCurrent = 16 + SKIPS;
par->dmaMax = 8191;
par->dmaFree = par->dmaMax - par->dmaCurrent;
switch (info->var.bits_per_pixel) {
case 32:
case 24:
surfaceFormat = SURFACE_FORMAT_DEPTH24;
patternFormat = PATTERN_FORMAT_DEPTH24;
rectFormat = RECT_FORMAT_DEPTH24;
lineFormat = LINE_FORMAT_DEPTH24;
break;
case 16:
surfaceFormat = SURFACE_FORMAT_DEPTH16;
patternFormat = PATTERN_FORMAT_DEPTH16;
rectFormat = RECT_FORMAT_DEPTH16;
lineFormat = LINE_FORMAT_DEPTH16;
break;
default:
surfaceFormat = SURFACE_FORMAT_DEPTH8;
patternFormat = PATTERN_FORMAT_DEPTH8;
rectFormat = RECT_FORMAT_DEPTH8;
lineFormat = LINE_FORMAT_DEPTH8;
break;
}
NVDmaStart(info, par, SURFACE_FORMAT, 4);
NVDmaNext(par, surfaceFormat);
NVDmaNext(par, pitch | (pitch << 16));
NVDmaNext(par, 0);
NVDmaNext(par, 0);
NVDmaStart(info, par, PATTERN_FORMAT, 1);
NVDmaNext(par, patternFormat);
NVDmaStart(info, par, RECT_FORMAT, 1);
NVDmaNext(par, rectFormat);
NVDmaStart(info, par, LINE_FORMAT, 1);
NVDmaNext(par, lineFormat);
par->currentRop = ~0; /* set to something invalid */
NVSetRopSolid(info, ROP_COPY, ~0);
NVSetClippingRectangle(info, 0, 0, info->var.xres_virtual,
info->var.yres_virtual);
NVDmaKickoff(par);
}
int nvidiafb_sync(struct fb_info *info)
{
struct nvidia_par *par = info->par;
if (info->state != FBINFO_STATE_RUNNING)
return 0;
if (!par->lockup)
NVFlush(info);
if (!par->lockup)
NVSync(info);
return 0;
}
void nvidiafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
{
struct nvidia_par *par = info->par;
if (info->state != FBINFO_STATE_RUNNING)
return;
if (par->lockup) {
cfb_copyarea(info, region);
return;
}
NVDmaStart(info, par, BLIT_POINT_SRC, 3);
NVDmaNext(par, (region->sy << 16) | region->sx);
NVDmaNext(par, (region->dy << 16) | region->dx);
NVDmaNext(par, (region->height << 16) | region->width);
NVDmaKickoff(par);
}
void nvidiafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
{
struct nvidia_par *par = info->par;
u32 color;
if (info->state != FBINFO_STATE_RUNNING)
return;
if (par->lockup) {
cfb_fillrect(info, rect);
return;
}
if (info->var.bits_per_pixel == 8)
color = rect->color;
else
color = ((u32 *) info->pseudo_palette)[rect->color];
if (rect->rop != ROP_COPY)
NVSetRopSolid(info, rect->rop, ~0);
NVDmaStart(info, par, RECT_SOLID_COLOR, 1);
NVDmaNext(par, color);
NVDmaStart(info, par, RECT_SOLID_RECTS(0), 2);
NVDmaNext(par, (rect->dx << 16) | rect->dy);
NVDmaNext(par, (rect->width << 16) | rect->height);
NVDmaKickoff(par);
if (rect->rop != ROP_COPY)
NVSetRopSolid(info, ROP_COPY, ~0);
}
static void nvidiafb_mono_color_expand(struct fb_info *info,
const struct fb_image *image)
{
struct nvidia_par *par = info->par;
u32 fg, bg, mask = ~(~0 >> (32 - info->var.bits_per_pixel));
u32 dsize, width, *data = (u32 *) image->data, tmp;
int j, k = 0;
width = (image->width + 31) & ~31;
dsize = (width * image->height) >> 5;
if (info->var.bits_per_pixel == 8) {
fg = image->fg_color | mask;
bg = image->bg_color | mask;
} else {
fg = ((u32 *) info->pseudo_palette)[image->fg_color] | mask;
bg = ((u32 *) info->pseudo_palette)[image->bg_color] | mask;
}
NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_CLIP, 7);
NVDmaNext(par, (image->dy << 16) | (image->dx & 0xffff));
NVDmaNext(par, ((image->dy + image->height) << 16) |
((image->dx + image->width) & 0xffff));
NVDmaNext(par, bg);
NVDmaNext(par, fg);
NVDmaNext(par, (image->height << 16) | width);
NVDmaNext(par, (image->height << 16) | width);
NVDmaNext(par, (image->dy << 16) | (image->dx & 0xffff));
while (dsize >= RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS) {
NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_DATA(0),
RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS);
for (j = RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS; j--;) {
tmp = data[k++];
reverse_order(&tmp);
NVDmaNext(par, tmp);
}
dsize -= RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS;
}
if (dsize) {
NVDmaStart(info, par, RECT_EXPAND_TWO_COLOR_DATA(0), dsize);
for (j = dsize; j--;) {
tmp = data[k++];
reverse_order(&tmp);
NVDmaNext(par, tmp);
}
}
NVDmaKickoff(par);
}
void nvidiafb_imageblit(struct fb_info *info, const struct fb_image *image)
{
struct nvidia_par *par = info->par;
if (info->state != FBINFO_STATE_RUNNING)
return;
if (image->depth == 1 && !par->lockup)
nvidiafb_mono_color_expand(info, image);
else
cfb_imageblit(info, image);
}

142
drivers/video/fbdev/nvidia/nv_backlight.c Normal file
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/*
* Backlight code for nVidia based graphic cards
*
* Copyright 2004 Antonino Daplas <adaplas@pol.net>
* Copyright (c) 2006 Michael Hanselmann <linux-kernel@hansmi.ch>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/backlight.h>
#include <linux/fb.h>
#include <linux/pci.h>
#ifdef CONFIG_PMAC_BACKLIGHT
#include <asm/backlight.h>
#endif
#include "nv_local.h"
#include "nv_type.h"
#include "nv_proto.h"
/* We do not have any information about which values are allowed, thus
* we used safe values.
*/
#define MIN_LEVEL 0x158
#define MAX_LEVEL 0x534
#define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX)
static int nvidia_bl_get_level_brightness(struct nvidia_par *par,
int level)
{
struct fb_info *info = pci_get_drvdata(par->pci_dev);
int nlevel;
/* Get and convert the value */
/* No locking of bl_curve since we read a single value */
nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP;
if (nlevel < 0)
nlevel = 0;
else if (nlevel < MIN_LEVEL)
nlevel = MIN_LEVEL;
else if (nlevel > MAX_LEVEL)
nlevel = MAX_LEVEL;
return nlevel;
}
static int nvidia_bl_update_status(struct backlight_device *bd)
{
struct nvidia_par *par = bl_get_data(bd);
u32 tmp_pcrt, tmp_pmc, fpcontrol;
int level;
if (!par->FlatPanel)
return 0;
if (bd->props.power != FB_BLANK_UNBLANK ||
bd->props.fb_blank != FB_BLANK_UNBLANK)
level = 0;
else
level = bd->props.brightness;
tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF;
tmp_pcrt = NV_RD32(par->PCRTC0, 0x081C) & 0xFFFFFFFC;
fpcontrol = NV_RD32(par->PRAMDAC, 0x0848) & 0xCFFFFFCC;
if (level > 0) {
tmp_pcrt |= 0x1;
tmp_pmc |= (1 << 31); /* backlight bit */
tmp_pmc |= nvidia_bl_get_level_brightness(par, level) << 16;
fpcontrol |= par->fpSyncs;
} else
fpcontrol |= 0x20000022;
NV_WR32(par->PCRTC0, 0x081C, tmp_pcrt);
NV_WR32(par->PMC, 0x10F0, tmp_pmc);
NV_WR32(par->PRAMDAC, 0x848, fpcontrol);
return 0;
}
static const struct backlight_ops nvidia_bl_ops = {
.update_status = nvidia_bl_update_status,
};
void nvidia_bl_init(struct nvidia_par *par)
{
struct backlight_properties props;
struct fb_info *info = pci_get_drvdata(par->pci_dev);
struct backlight_device *bd;
char name[12];
if (!par->FlatPanel)
return;
#ifdef CONFIG_PMAC_BACKLIGHT
if (!machine_is(powermac) ||
!pmac_has_backlight_type("mnca"))
return;
#endif
snprintf(name, sizeof(name), "nvidiabl%d", info->node);
memset(&props, 0, sizeof(struct backlight_properties));
props.type = BACKLIGHT_RAW;
props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
bd = backlight_device_register(name, info->dev, par, &nvidia_bl_ops,
&props);
if (IS_ERR(bd)) {
info->bl_dev = NULL;
printk(KERN_WARNING "nvidia: Backlight registration failed\n");
goto error;
}
info->bl_dev = bd;
fb_bl_default_curve(info, 0,
0x158 * FB_BACKLIGHT_MAX / MAX_LEVEL,
0x534 * FB_BACKLIGHT_MAX / MAX_LEVEL);
bd->props.brightness = bd->props.max_brightness;
bd->props.power = FB_BLANK_UNBLANK;
backlight_update_status(bd);
printk("nvidia: Backlight initialized (%s)\n", name);
return;
error:
return;
}
void nvidia_bl_exit(struct nvidia_par *par)
{
struct fb_info *info = pci_get_drvdata(par->pci_dev);
struct backlight_device *bd = info->bl_dev;
backlight_device_unregister(bd);
printk("nvidia: Backlight unloaded\n");
}

188
drivers/video/fbdev/nvidia/nv_dma.h Normal file
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/***************************************************************************\
|* *|
|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
|* *|
|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
|* international laws. Users and possessors of this source code are *|
|* hereby granted a nonexclusive, royalty-free copyright license to *|
|* use this code in individual and commercial software. *|
|* *|
|* Any use of this source code must include, in the user documenta- *|
|* tion and internal comments to the code, notices to the end user *|
|* as follows: *|
|* *|
|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
|* *|
|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
|* *|
|* U.S. Government End Users. This source code is a "commercial *|
|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
|* consisting of "commercial computer software" and "commercial *|
|* computer software documentation," as such terms are used in *|
|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
|* all U.S. Government End Users acquire the source code with only *|
|* those rights set forth herein. *|
|* *|
\***************************************************************************/
/*
* GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
* XFree86 'nv' driver, this source code is provided under MIT-style licensing
* where the source code is provided "as is" without warranty of any kind.
* The only usage restriction is for the copyright notices to be retained
* whenever code is used.
*
* Antonino Daplas <adaplas@pol.net> 2005-03-11
*/
#define SURFACE_FORMAT 0x00000300
#define SURFACE_FORMAT_DEPTH8 0x00000001
#define SURFACE_FORMAT_DEPTH15 0x00000002
#define SURFACE_FORMAT_DEPTH16 0x00000004
#define SURFACE_FORMAT_DEPTH24 0x00000006
#define SURFACE_PITCH 0x00000304
#define SURFACE_PITCH_SRC 15:0
#define SURFACE_PITCH_DST 31:16
#define SURFACE_OFFSET_SRC 0x00000308
#define SURFACE_OFFSET_DST 0x0000030C
#define ROP_SET 0x00002300
#define PATTERN_FORMAT 0x00004300
#define PATTERN_FORMAT_DEPTH8 0x00000003
#define PATTERN_FORMAT_DEPTH16 0x00000001
#define PATTERN_FORMAT_DEPTH24 0x00000003
#define PATTERN_COLOR_0 0x00004310
#define PATTERN_COLOR_1 0x00004314
#define PATTERN_PATTERN_0 0x00004318
#define PATTERN_PATTERN_1 0x0000431C
#define CLIP_POINT 0x00006300
#define CLIP_POINT_X 15:0
#define CLIP_POINT_Y 31:16
#define CLIP_SIZE 0x00006304
#define CLIP_SIZE_WIDTH 15:0
#define CLIP_SIZE_HEIGHT 31:16
#define LINE_FORMAT 0x00008300
#define LINE_FORMAT_DEPTH8 0x00000003
#define LINE_FORMAT_DEPTH16 0x00000001
#define LINE_FORMAT_DEPTH24 0x00000003
#define LINE_COLOR 0x00008304
#define LINE_MAX_LINES 16
#define LINE_LINES(i) 0x00008400\
+(i)*8
#define LINE_LINES_POINT0_X 15:0
#define LINE_LINES_POINT0_Y 31:16
#define LINE_LINES_POINT1_X 47:32
#define LINE_LINES_POINT1_Y 63:48
#define BLIT_POINT_SRC 0x0000A300
#define BLIT_POINT_SRC_X 15:0
#define BLIT_POINT_SRC_Y 31:16
#define BLIT_POINT_DST 0x0000A304
#define BLIT_POINT_DST_X 15:0
#define BLIT_POINT_DST_Y 31:16
#define BLIT_SIZE 0x0000A308
#define BLIT_SIZE_WIDTH 15:0
#define BLIT_SIZE_HEIGHT 31:16
#define RECT_FORMAT 0x0000C300
#define RECT_FORMAT_DEPTH8 0x00000003
#define RECT_FORMAT_DEPTH16 0x00000001
#define RECT_FORMAT_DEPTH24 0x00000003
#define RECT_SOLID_COLOR 0x0000C3FC
#define RECT_SOLID_RECTS_MAX_RECTS 32
#define RECT_SOLID_RECTS(i) 0x0000C400\
+(i)*8
#define RECT_SOLID_RECTS_Y 15:0
#define RECT_SOLID_RECTS_X 31:16
#define RECT_SOLID_RECTS_HEIGHT 47:32
#define RECT_SOLID_RECTS_WIDTH 63:48
#define RECT_EXPAND_ONE_COLOR_CLIP 0x0000C7EC
#define RECT_EXPAND_ONE_COLOR_CLIP_POINT0_X 15:0
#define RECT_EXPAND_ONE_COLOR_CLIP_POINT0_Y 31:16
#define RECT_EXPAND_ONE_COLOR_CLIP_POINT1_X 47:32
#define RECT_EXPAND_ONE_COLOR_CLIP_POINT1_Y 63:48
#define RECT_EXPAND_ONE_COLOR_COLOR 0x0000C7F4
#define RECT_EXPAND_ONE_COLOR_SIZE 0x0000C7F8
#define RECT_EXPAND_ONE_COLOR_SIZE_WIDTH 15:0
#define RECT_EXPAND_ONE_COLOR_SIZE_HEIGHT 31:16
#define RECT_EXPAND_ONE_COLOR_POINT 0x0000C7FC
#define RECT_EXPAND_ONE_COLOR_POINT_X 15:0
#define RECT_EXPAND_ONE_COLOR_POINT_Y 31:16
#define RECT_EXPAND_ONE_COLOR_DATA_MAX_DWORDS 128
#define RECT_EXPAND_ONE_COLOR_DATA(i) 0x0000C800\
+(i)*4
#define RECT_EXPAND_TWO_COLOR_CLIP 0x0000CBE4
#define RECT_EXPAND_TWO_COLOR_CLIP_POINT0_X 15:0
#define RECT_EXPAND_TWO_COLOR_CLIP_POINT0_Y 31:16
#define RECT_EXPAND_TWO_COLOR_CLIP_POINT1_X 47:32
#define RECT_EXPAND_TWO_COLOR_CLIP_POINT1_Y 63:48
#define RECT_EXPAND_TWO_COLOR_COLOR_0 0x0000CBEC
#define RECT_EXPAND_TWO_COLOR_COLOR_1 0x0000CBF0
#define RECT_EXPAND_TWO_COLOR_SIZE_IN 0x0000CBF4
#define RECT_EXPAND_TWO_COLOR_SIZE_IN_WIDTH 15:0
#define RECT_EXPAND_TWO_COLOR_SIZE_IN_HEIGHT 31:16
#define RECT_EXPAND_TWO_COLOR_SIZE_OUT 0x0000CBF8
#define RECT_EXPAND_TWO_COLOR_SIZE_OUT_WIDTH 15:0
#define RECT_EXPAND_TWO_COLOR_SIZE_OUT_HEIGHT 31:16
#define RECT_EXPAND_TWO_COLOR_POINT 0x0000CBFC
#define RECT_EXPAND_TWO_COLOR_POINT_X 15:0
#define RECT_EXPAND_TWO_COLOR_POINT_Y 31:16
#define RECT_EXPAND_TWO_COLOR_DATA_MAX_DWORDS 128
#define RECT_EXPAND_TWO_COLOR_DATA(i) 0x0000CC00\
+(i)*4
#define STRETCH_BLIT_FORMAT 0x0000E300
#define STRETCH_BLIT_FORMAT_DEPTH8 0x00000004
#define STRETCH_BLIT_FORMAT_DEPTH16 0x00000007
#define STRETCH_BLIT_FORMAT_DEPTH24 0x00000004
#define STRETCH_BLIT_FORMAT_X8R8G8B8 0x00000004
#define STRETCH_BLIT_FORMAT_YUYV 0x00000005
#define STRETCH_BLIT_FORMAT_UYVY 0x00000006
#define STRETCH_BLIT_CLIP_POINT 0x0000E308
#define STRETCH_BLIT_CLIP_POINT_X 15:0
#define STRETCH_BLIT_CLIP_POINT_Y 31:16
#define STRETCH_BLIT_CLIP_POINT 0x0000E308
#define STRETCH_BLIT_CLIP_SIZE 0x0000E30C
#define STRETCH_BLIT_CLIP_SIZE_WIDTH 15:0
#define STRETCH_BLIT_CLIP_SIZE_HEIGHT 31:16
#define STRETCH_BLIT_DST_POINT 0x0000E310
#define STRETCH_BLIT_DST_POINT_X 15:0
#define STRETCH_BLIT_DST_POINT_Y 31:16
#define STRETCH_BLIT_DST_SIZE 0x0000E314
#define STRETCH_BLIT_DST_SIZE_WIDTH 15:0
#define STRETCH_BLIT_DST_SIZE_HEIGHT 31:16
#define STRETCH_BLIT_DU_DX 0x0000E318
#define STRETCH_BLIT_DV_DY 0x0000E31C
#define STRETCH_BLIT_SRC_SIZE 0x0000E400
#define STRETCH_BLIT_SRC_SIZE_WIDTH 15:0
#define STRETCH_BLIT_SRC_SIZE_HEIGHT 31:16
#define STRETCH_BLIT_SRC_FORMAT 0x0000E404
#define STRETCH_BLIT_SRC_FORMAT_PITCH 15:0
#define STRETCH_BLIT_SRC_FORMAT_ORIGIN 23:16
#define STRETCH_BLIT_SRC_FORMAT_ORIGIN_CENTER 0x00000001
#define STRETCH_BLIT_SRC_FORMAT_ORIGIN_CORNER 0x00000002
#define STRETCH_BLIT_SRC_FORMAT_FILTER 31:24
#define STRETCH_BLIT_SRC_FORMAT_FILTER_POINT_SAMPLE 0x00000000
#define STRETCH_BLIT_SRC_FORMAT_FILTER_BILINEAR 0x00000001
#define STRETCH_BLIT_SRC_OFFSET 0x0000E408
#define STRETCH_BLIT_SRC_POINT 0x0000E40C
#define STRETCH_BLIT_SRC_POINT_U 15:0
#define STRETCH_BLIT_SRC_POINT_V 31:16

1687
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/*
* linux/drivers/video/nvidia/nvidia-i2c.c - nVidia i2c
*
* Copyright 2004 Antonino A. Daplas <adaplas @pol.net>
*
* Based on rivafb-i2c.c
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/gfp.h>
#include <linux/pci.h>
#include <linux/fb.h>
#include <asm/io.h>
#include "nv_type.h"
#include "nv_local.h"
#include "nv_proto.h"
#include "../edid.h"
static void nvidia_gpio_setscl(void *data, int state)
{
struct nvidia_i2c_chan *chan = data;
struct nvidia_par *par = chan->par;
u32 val;
val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0;
if (state)
val |= 0x20;
else
val &= ~0x20;
NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01);
}
static void nvidia_gpio_setsda(void *data, int state)
{
struct nvidia_i2c_chan *chan = data;
struct nvidia_par *par = chan->par;
u32 val;
val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0;
if (state)
val |= 0x10;
else
val &= ~0x10;
NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01);
}
static int nvidia_gpio_getscl(void *data)
{
struct nvidia_i2c_chan *chan = data;
struct nvidia_par *par = chan->par;
u32 val = 0;
if (NVReadCrtc(par, chan->ddc_base) & 0x04)
val = 1;
return val;
}
static int nvidia_gpio_getsda(void *data)
{
struct nvidia_i2c_chan *chan = data;
struct nvidia_par *par = chan->par;
u32 val = 0;
if (NVReadCrtc(par, chan->ddc_base) & 0x08)
val = 1;
return val;
}
static int nvidia_setup_i2c_bus(struct nvidia_i2c_chan *chan, const char *name,
unsigned int i2c_class)
{
int rc;
strcpy(chan->adapter.name, name);
chan->adapter.owner = THIS_MODULE;
chan->adapter.class = i2c_class;
chan->adapter.algo_data = &chan->algo;
chan->adapter.dev.parent = &chan->par->pci_dev->dev;
chan->algo.setsda = nvidia_gpio_setsda;
chan->algo.setscl = nvidia_gpio_setscl;
chan->algo.getsda = nvidia_gpio_getsda;
chan->algo.getscl = nvidia_gpio_getscl;
chan->algo.udelay = 40;
chan->algo.timeout = msecs_to_jiffies(2);
chan->algo.data = chan;
i2c_set_adapdata(&chan->adapter, chan);
/* Raise SCL and SDA */
nvidia_gpio_setsda(chan, 1);
nvidia_gpio_setscl(chan, 1);
udelay(20);
rc = i2c_bit_add_bus(&chan->adapter);
if (rc == 0)
dev_dbg(&chan->par->pci_dev->dev,
"I2C bus %s registered.\n", name);
else {
dev_warn(&chan->par->pci_dev->dev,
"Failed to register I2C bus %s.\n", name);
chan->par = NULL;
}
return rc;
}
void nvidia_create_i2c_busses(struct nvidia_par *par)
{
par->chan[0].par = par;
par->chan[1].par = par;
par->chan[2].par = par;
par->chan[0].ddc_base = (par->reverse_i2c) ? 0x36 : 0x3e;
nvidia_setup_i2c_bus(&par->chan[0], "nvidia #0",
(par->reverse_i2c) ? I2C_CLASS_HWMON : 0);
par->chan[1].ddc_base = (par->reverse_i2c) ? 0x3e : 0x36;
nvidia_setup_i2c_bus(&par->chan[1], "nvidia #1",
(par->reverse_i2c) ? 0 : I2C_CLASS_HWMON);
par->chan[2].ddc_base = 0x50;
nvidia_setup_i2c_bus(&par->chan[2], "nvidia #2", 0);
}
void nvidia_delete_i2c_busses(struct nvidia_par *par)
{
int i;
for (i = 0; i < 3; i++) {
if (!par->chan[i].par)
continue;
i2c_del_adapter(&par->chan[i].adapter);
par->chan[i].par = NULL;
}
}
int nvidia_probe_i2c_connector(struct fb_info *info, int conn, u8 **out_edid)
{
struct nvidia_par *par = info->par;
u8 *edid = NULL;
if (par->chan[conn - 1].par)
edid = fb_ddc_read(&par->chan[conn - 1].adapter);
if (!edid && conn == 1) {
/* try to get from firmware */
const u8 *e = fb_firmware_edid(info->device);
if (e != NULL)
edid = kmemdup(e, EDID_LENGTH, GFP_KERNEL);
}
*out_edid = edid;
return (edid) ? 0 : 1;
}

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/***************************************************************************\
|* *|
|* Copyright 1993-2003 NVIDIA, Corporation. All rights reserved. *|
|* *|
|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
|* international laws. Users and possessors of this source code are *|
|* hereby granted a nonexclusive, royalty-free copyright license to *|
|* use this code in individual and commercial software. *|
|* *|
|* Any use of this source code must include, in the user documenta- *|
|* tion and internal comments to the code, notices to the end user *|
|* as follows: *|
|* *|
|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
|* *|
|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
|* *|
|* U.S. Government End Users. This source code is a "commercial *|
|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
|* consisting of "commercial computer software" and "commercial *|
|* computer software documentation," as such terms are used in *|
|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
|* all U.S. Government End Users acquire the source code with only *|
|* those rights set forth herein. *|
|* *|
\***************************************************************************/
/*
* GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
* XFree86 'nv' driver, this source code is provided under MIT-style licensing
* where the source code is provided "as is" without warranty of any kind.
* The only usage restriction is for the copyright notices to be retained
* whenever code is used.
*
* Antonino Daplas <adaplas@pol.net> 2005-03-11
*/
#ifndef __NV_LOCAL_H__
#define __NV_LOCAL_H__
/*
* This file includes any environment or machine specific values to access the
* HW. Put all affected includes, typdefs, etc. here so the riva_hw.* files
* can stay generic in nature.
*/
/*
* HW access macros. These assume memory-mapped I/O, and not normal I/O space.
*/
#define NV_WR08(p,i,d) (__raw_writeb((d), (void __iomem *)(p) + (i)))
#define NV_RD08(p,i) (__raw_readb((void __iomem *)(p) + (i)))
#define NV_WR16(p,i,d) (__raw_writew((d), (void __iomem *)(p) + (i)))
#define NV_RD16(p,i) (__raw_readw((void __iomem *)(p) + (i)))
#define NV_WR32(p,i,d) (__raw_writel((d), (void __iomem *)(p) + (i)))
#define NV_RD32(p,i) (__raw_readl((void __iomem *)(p) + (i)))
/* VGA I/O is now always done through MMIO */
#define VGA_WR08(p,i,d) (writeb((d), (void __iomem *)(p) + (i)))
#define VGA_RD08(p,i) (readb((void __iomem *)(p) + (i)))
#define NVDmaNext(par, data) \
NV_WR32(&(par)->dmaBase[(par)->dmaCurrent++], 0, (data))
#define NVDmaStart(info, par, tag, size) { \
if((par)->dmaFree <= (size)) \
NVDmaWait(info, size); \
NVDmaNext(par, ((size) << 18) | (tag)); \
(par)->dmaFree -= ((size) + 1); \
}
#if defined(__i386__)
#define _NV_FENCE() outb(0, 0x3D0);
#else
#define _NV_FENCE() mb();
#endif
#define WRITE_PUT(par, data) { \
_NV_FENCE() \
NV_RD08((par)->FbStart, 0); \
NV_WR32(&(par)->FIFO[0x0010], 0, (data) << 2); \
mb(); \
}
#define READ_GET(par) (NV_RD32(&(par)->FIFO[0x0011], 0) >> 2)
#ifdef __LITTLE_ENDIAN
#include <linux/bitrev.h>
#define reverse_order(l) \
do { \
u8 *a = (u8 *)(l); \
a[0] = bitrev8(a[0]); \
a[1] = bitrev8(a[1]); \
a[2] = bitrev8(a[2]); \
a[3] = bitrev8(a[3]); \
} while(0)
#else
#define reverse_order(l) do { } while(0)
#endif /* __LITTLE_ENDIAN */
#endif /* __NV_LOCAL_H__ */

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/*
* linux/drivers/video/nvidia/nv_of.c
*
* Copyright 2004 Antonino A. Daplas <adaplas @pol.net>
*
* Based on rivafb-i2c.c
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/gfp.h>
#include <linux/pci.h>
#include <linux/fb.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#include "nv_type.h"
#include "nv_local.h"
#include "nv_proto.h"
#include "../edid.h"
int nvidia_probe_of_connector(struct fb_info *info, int conn, u8 **out_edid)
{
struct nvidia_par *par = info->par;
struct device_node *parent, *dp;
const unsigned char *pedid = NULL;
static char *propnames[] = {
"DFP,EDID", "LCD,EDID", "EDID", "EDID1",
"EDID,B", "EDID,A", NULL };
int i;
parent = pci_device_to_OF_node(par->pci_dev);
if (parent == NULL)
return -1;
if (par->twoHeads) {
const char *pname;
int len;
for (dp = NULL;
(dp = of_get_next_child(parent, dp)) != NULL;) {
pname = of_get_property(dp, "name", NULL);
if (!pname)
continue;
len = strlen(pname);
if ((pname[len-1] == 'A' && conn == 1) ||
(pname[len-1] == 'B' && conn == 2)) {
for (i = 0; propnames[i] != NULL; ++i) {
pedid = of_get_property(dp,
propnames[i], NULL);
if (pedid != NULL)
break;
}
of_node_put(dp);
break;
}
}
}
if (pedid == NULL) {
for (i = 0; propnames[i] != NULL; ++i) {
pedid = of_get_property(parent, propnames[i], NULL);
if (pedid != NULL)
break;
}
}
if (pedid) {
*out_edid = kmemdup(pedid, EDID_LENGTH, GFP_KERNEL);
if (*out_edid == NULL)
return -1;
printk(KERN_DEBUG "nvidiafb: Found OF EDID for head %d\n", conn);
return 0;
}
return -1;
}

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/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_proto.h,v 1.10 2003/07/31 20:24:29 mvojkovi Exp $ */
#ifndef __NV_PROTO_H__
#define __NV_PROTO_H__
/* in nv_setup.c */
int NVCommonSetup(struct fb_info *info);
void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value);
u8 NVReadCrtc(struct nvidia_par *par, u8 index);
void NVWriteGr(struct nvidia_par *par, u8 index, u8 value);
u8 NVReadGr(struct nvidia_par *par, u8 index);
void NVWriteSeq(struct nvidia_par *par, u8 index, u8 value);
u8 NVReadSeq(struct nvidia_par *par, u8 index);
void NVWriteAttr(struct nvidia_par *par, u8 index, u8 value);
u8 NVReadAttr(struct nvidia_par *par, u8 index);
void NVWriteMiscOut(struct nvidia_par *par, u8 value);
u8 NVReadMiscOut(struct nvidia_par *par);
void NVWriteDacMask(struct nvidia_par *par, u8 value);
void NVWriteDacReadAddr(struct nvidia_par *par, u8 value);
void NVWriteDacWriteAddr(struct nvidia_par *par, u8 value);
void NVWriteDacData(struct nvidia_par *par, u8 value);
u8 NVReadDacData(struct nvidia_par *par);
/* in nv_hw.c */
void NVCalcStateExt(struct nvidia_par *par, struct _riva_hw_state *,
int, int, int, int, int, int);
void NVLoadStateExt(struct nvidia_par *par, struct _riva_hw_state *);
void NVUnloadStateExt(struct nvidia_par *par, struct _riva_hw_state *);
void NVSetStartAddress(struct nvidia_par *par, u32);
int NVShowHideCursor(struct nvidia_par *par, int);
void NVLockUnlock(struct nvidia_par *par, int);
/* in nvidia-i2c.c */
#ifdef CONFIG_FB_NVIDIA_I2C
void nvidia_create_i2c_busses(struct nvidia_par *par);
void nvidia_delete_i2c_busses(struct nvidia_par *par);
int nvidia_probe_i2c_connector(struct fb_info *info, int conn,
u8 ** out_edid);
#else
#define nvidia_create_i2c_busses(...)
#define nvidia_delete_i2c_busses(...)
#define nvidia_probe_i2c_connector(p, c, edid) (-1)
#endif
#ifdef CONFIG_PPC_OF
int nvidia_probe_of_connector(struct fb_info *info, int conn,
u8 ** out_edid);
#else
static inline int nvidia_probe_of_connector(struct fb_info *info, int conn,
u8 ** out_edid)
{
return -1;
}
#endif
/* in nv_accel.c */
extern void NVResetGraphics(struct fb_info *info);
extern void nvidiafb_copyarea(struct fb_info *info,
const struct fb_copyarea *region);
extern void nvidiafb_fillrect(struct fb_info *info,
const struct fb_fillrect *rect);
extern void nvidiafb_imageblit(struct fb_info *info,
const struct fb_image *image);
extern int nvidiafb_sync(struct fb_info *info);
/* in nv_backlight.h */
#ifdef CONFIG_FB_NVIDIA_BACKLIGHT
extern void nvidia_bl_init(struct nvidia_par *par);
extern void nvidia_bl_exit(struct nvidia_par *par);
#else
static inline void nvidia_bl_init(struct nvidia_par *par) {}
static inline void nvidia_bl_exit(struct nvidia_par *par) {}
#endif
#endif /* __NV_PROTO_H__ */

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/***************************************************************************\
|* *|
|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
|* *|
|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
|* international laws. Users and possessors of this source code are *|
|* hereby granted a nonexclusive, royalty-free copyright license to *|
|* use this code in individual and commercial software. *|
|* *|
|* Any use of this source code must include, in the user documenta- *|
|* tion and internal comments to the code, notices to the end user *|
|* as follows: *|
|* *|
|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
|* *|
|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
|* *|
|* U.S. Government End Users. This source code is a "commercial *|
|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
|* consisting of "commercial computer software" and "commercial *|
|* computer software documentation," as such terms are used in *|
|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
|* all U.S. Government End Users acquire the source code with only *|
|* those rights set forth herein. *|
|* *|
\***************************************************************************/
/*
* GPL Licensing Note - According to Mark Vojkovich, author of the Xorg/
* XFree86 'nv' driver, this source code is provided under MIT-style licensing
* where the source code is provided "as is" without warranty of any kind.
* The only usage restriction is for the copyright notices to be retained
* whenever code is used.
*
* Antonino Daplas <adaplas@pol.net> 2005-03-11
*/
#include <video/vga.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include "nv_type.h"
#include "nv_local.h"
#include "nv_proto.h"
/*
* Override VGA I/O routines.
*/
void NVWriteCrtc(struct nvidia_par *par, u8 index, u8 value)
{
VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
VGA_WR08(par->PCIO, par->IOBase + 0x05, value);
}
u8 NVReadCrtc(struct nvidia_par *par, u8 index)
{
VGA_WR08(par->PCIO, par->IOBase + 0x04, index);
return (VGA_RD08(par->PCIO, par->IOBase + 0x05));
}
void NVWriteGr(struct nvidia_par *par, u8 index, u8 value)
{
VGA_WR08(par->PVIO, VGA_GFX_I, index);
VGA_WR08(par->PVIO, VGA_GFX_D, value);
}
u8 NVReadGr(struct nvidia_par *par, u8 index)
{
VGA_WR08(par->PVIO, VGA_GFX_I, index);
return (VGA_RD08(par->PVIO, VGA_GFX_D));
}
void NVWriteSeq(struct nvidia_par *par, u8 index, u8 value)
{
VGA_WR08(par->PVIO, VGA_SEQ_I, index);
VGA_WR08(par->PVIO, VGA_SEQ_D, value);
}
u8 NVReadSeq(struct nvidia_par *par, u8 index)
{
VGA_WR08(par->PVIO, VGA_SEQ_I, index);
return (VGA_RD08(par->PVIO, VGA_SEQ_D));
}
void NVWriteAttr(struct nvidia_par *par, u8 index, u8 value)
{
volatile u8 tmp;
tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
if (par->paletteEnabled)
index &= ~0x20;
else
index |= 0x20;
VGA_WR08(par->PCIO, VGA_ATT_IW, index);
VGA_WR08(par->PCIO, VGA_ATT_W, value);
}
u8 NVReadAttr(struct nvidia_par *par, u8 index)
{
volatile u8 tmp;
tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
if (par->paletteEnabled)
index &= ~0x20;
else
index |= 0x20;
VGA_WR08(par->PCIO, VGA_ATT_IW, index);
return (VGA_RD08(par->PCIO, VGA_ATT_R));
}
void NVWriteMiscOut(struct nvidia_par *par, u8 value)
{
VGA_WR08(par->PVIO, VGA_MIS_W, value);
}
u8 NVReadMiscOut(struct nvidia_par *par)
{
return (VGA_RD08(par->PVIO, VGA_MIS_R));
}
#if 0
void NVEnablePalette(struct nvidia_par *par)
{
volatile u8 tmp;
tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
VGA_WR08(par->PCIO, VGA_ATT_IW, 0x00);
par->paletteEnabled = 1;
}
void NVDisablePalette(struct nvidia_par *par)
{
volatile u8 tmp;
tmp = VGA_RD08(par->PCIO, par->IOBase + 0x0a);
VGA_WR08(par->PCIO, VGA_ATT_IW, 0x20);
par->paletteEnabled = 0;
}
#endif /* 0 */
void NVWriteDacMask(struct nvidia_par *par, u8 value)
{
VGA_WR08(par->PDIO, VGA_PEL_MSK, value);
}
#if 0
u8 NVReadDacMask(struct nvidia_par *par)
{
return (VGA_RD08(par->PDIO, VGA_PEL_MSK));
}
#endif /* 0 */
void NVWriteDacReadAddr(struct nvidia_par *par, u8 value)
{
VGA_WR08(par->PDIO, VGA_PEL_IR, value);
}
void NVWriteDacWriteAddr(struct nvidia_par *par, u8 value)
{
VGA_WR08(par->PDIO, VGA_PEL_IW, value);
}
void NVWriteDacData(struct nvidia_par *par, u8 value)
{
VGA_WR08(par->PDIO, VGA_PEL_D, value);
}
u8 NVReadDacData(struct nvidia_par *par)
{
return (VGA_RD08(par->PDIO, VGA_PEL_D));
}
static int NVIsConnected(struct nvidia_par *par, int output)
{
volatile u32 __iomem *PRAMDAC = par->PRAMDAC0;
u32 reg52C, reg608, dac0_reg608 = 0;
int present;
if (output) {
dac0_reg608 = NV_RD32(PRAMDAC, 0x0608);
PRAMDAC += 0x800;
}
reg52C = NV_RD32(PRAMDAC, 0x052C);
reg608 = NV_RD32(PRAMDAC, 0x0608);
NV_WR32(PRAMDAC, 0x0608, reg608 & ~0x00010000);
NV_WR32(PRAMDAC, 0x052C, reg52C & 0x0000FEEE);
msleep(1);
NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1);
NV_WR32(par->PRAMDAC0, 0x0610, 0x94050140);
NV_WR32(par->PRAMDAC0, 0x0608, NV_RD32(par->PRAMDAC0, 0x0608) |
0x00001000);
msleep(1);
present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? 1 : 0;
if (present)
printk("nvidiafb: CRTC%i analog found\n", output);
else
printk("nvidiafb: CRTC%i analog not found\n", output);
if (output)
NV_WR32(par->PRAMDAC0, 0x0608, dac0_reg608);
NV_WR32(PRAMDAC, 0x052C, reg52C);
NV_WR32(PRAMDAC, 0x0608, reg608);
return present;
}
static void NVSelectHeadRegisters(struct nvidia_par *par, int head)
{
if (head) {
par->PCIO = par->PCIO0 + 0x2000;
par->PCRTC = par->PCRTC0 + 0x800;
par->PRAMDAC = par->PRAMDAC0 + 0x800;
par->PDIO = par->PDIO0 + 0x2000;
} else {
par->PCIO = par->PCIO0;
par->PCRTC = par->PCRTC0;
par->PRAMDAC = par->PRAMDAC0;
par->PDIO = par->PDIO0;
}
}
static void nv4GetConfig(struct nvidia_par *par)
{
if (NV_RD32(par->PFB, 0x0000) & 0x00000100) {
par->RamAmountKBytes =
((NV_RD32(par->PFB, 0x0000) >> 12) & 0x0F) * 1024 * 2 +
1024 * 2;
} else {
switch (NV_RD32(par->PFB, 0x0000) & 0x00000003) {
case 0:
par->RamAmountKBytes = 1024 * 32;
break;
case 1:
par->RamAmountKBytes = 1024 * 4;
break;
case 2:
par->RamAmountKBytes = 1024 * 8;
break;
case 3:
default:
par->RamAmountKBytes = 1024 * 16;
break;
}
}
par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & 0x00000040) ?
14318 : 13500;
par->CURSOR = &par->PRAMIN[0x1E00];
par->MinVClockFreqKHz = 12000;
par->MaxVClockFreqKHz = 350000;
}
static void nv10GetConfig(struct nvidia_par *par)
{
struct pci_dev *dev;
u32 implementation = par->Chipset & 0x0ff0;
#ifdef __BIG_ENDIAN
/* turn on big endian register access */
if (!(NV_RD32(par->PMC, 0x0004) & 0x01000001)) {
NV_WR32(par->PMC, 0x0004, 0x01000001);
mb();
}
#endif
dev = pci_get_bus_and_slot(0, 1);
if ((par->Chipset & 0xffff) == 0x01a0) {
u32 amt;
pci_read_config_dword(dev, 0x7c, &amt);
par->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024;
} else if ((par->Chipset & 0xffff) == 0x01f0) {
u32 amt;
pci_read_config_dword(dev, 0x84, &amt);
par->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024;
} else {
par->RamAmountKBytes =
(NV_RD32(par->PFB, 0x020C) & 0xFFF00000) >> 10;
}
pci_dev_put(dev);
par->CrystalFreqKHz = (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 6)) ?
14318 : 13500;
if (par->twoHeads && (implementation != 0x0110)) {
if (NV_RD32(par->PEXTDEV, 0x0000) & (1 << 22))
par->CrystalFreqKHz = 27000;
}
par->CURSOR = NULL; /* can't set this here */
par->MinVClockFreqKHz = 12000;
par->MaxVClockFreqKHz = par->twoStagePLL ? 400000 : 350000;
}
int NVCommonSetup(struct fb_info *info)
{
struct nvidia_par *par = info->par;
struct fb_var_screeninfo *var;
u16 implementation = par->Chipset & 0x0ff0;
u8 *edidA = NULL, *edidB = NULL;
struct fb_monspecs *monitorA, *monitorB;
struct fb_monspecs *monA = NULL, *monB = NULL;
int mobile = 0;
int tvA = 0;
int tvB = 0;
int FlatPanel = -1; /* really means the CRTC is slaved */
int Television = 0;
int err = 0;
var = kzalloc(sizeof(struct fb_var_screeninfo), GFP_KERNEL);
monitorA = kzalloc(sizeof(struct fb_monspecs), GFP_KERNEL);
monitorB = kzalloc(sizeof(struct fb_monspecs), GFP_KERNEL);
if (!var || !monitorA || !monitorB) {
err = -ENOMEM;
goto done;
}
par->PRAMIN = par->REGS + (0x00710000 / 4);
par->PCRTC0 = par->REGS + (0x00600000 / 4);
par->PRAMDAC0 = par->REGS + (0x00680000 / 4);
par->PFB = par->REGS + (0x00100000 / 4);
par->PFIFO = par->REGS + (0x00002000 / 4);
par->PGRAPH = par->REGS + (0x00400000 / 4);
par->PEXTDEV = par->REGS + (0x00101000 / 4);
par->PTIMER = par->REGS + (0x00009000 / 4);
par->PMC = par->REGS + (0x00000000 / 4);
par->FIFO = par->REGS + (0x00800000 / 4);
/* 8 bit registers */
par->PCIO0 = (u8 __iomem *) par->REGS + 0x00601000;
par->PDIO0 = (u8 __iomem *) par->REGS + 0x00681000;
par->PVIO = (u8 __iomem *) par->REGS + 0x000C0000;
par->twoHeads = (par->Architecture >= NV_ARCH_10) &&
(implementation != 0x0100) &&
(implementation != 0x0150) &&
(implementation != 0x01A0) && (implementation != 0x0200);
par->fpScaler = (par->FpScale && par->twoHeads &&
(implementation != 0x0110));
par->twoStagePLL = (implementation == 0x0310) ||
(implementation == 0x0340) || (par->Architecture >= NV_ARCH_40);
par->WaitVSyncPossible = (par->Architecture >= NV_ARCH_10) &&
(implementation != 0x0100);
par->BlendingPossible = ((par->Chipset & 0xffff) != 0x0020);
/* look for known laptop chips */
switch (par->Chipset & 0xffff) {
case 0x0112:
case 0x0174:
case 0x0175:
case 0x0176:
case 0x0177:
case 0x0179:
case 0x017C:
case 0x017D:
case 0x0186:
case 0x0187:
case 0x018D:
case 0x01D7:
case 0x0228:
case 0x0286:
case 0x028C:
case 0x0316:
case 0x0317:
case 0x031A:
case 0x031B:
case 0x031C:
case 0x031D:
case 0x031E:
case 0x031F:
case 0x0324:
case 0x0325:
case 0x0328:
case 0x0329:
case 0x032C:
case 0x032D:
case 0x0347:
case 0x0348:
case 0x0349:
case 0x034B:
case 0x034C:
case 0x0160:
case 0x0166:
case 0x0169:
case 0x016B:
case 0x016C:
case 0x016D:
case 0x00C8:
case 0x00CC:
case 0x0144:
case 0x0146:
case 0x0147:
case 0x0148:
case 0x0098:
case 0x0099:
mobile = 1;
break;
default:
break;
}
if (par->Architecture == NV_ARCH_04)
nv4GetConfig(par);
else
nv10GetConfig(par);
NVSelectHeadRegisters(par, 0);
NVLockUnlock(par, 0);
par->IOBase = (NVReadMiscOut(par) & 0x01) ? 0x3d0 : 0x3b0;
par->Television = 0;
nvidia_create_i2c_busses(par);
if (!par->twoHeads) {
par->CRTCnumber = 0;
if (nvidia_probe_i2c_connector(info, 1, &edidA))
nvidia_probe_of_connector(info, 1, &edidA);
if (edidA && !fb_parse_edid(edidA, var)) {
printk("nvidiafb: EDID found from BUS1\n");
monA = monitorA;
fb_edid_to_monspecs(edidA, monA);
FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0;
/* NV4 doesn't support FlatPanels */
if ((par->Chipset & 0x0fff) <= 0x0020)
FlatPanel = 0;
} else {
VGA_WR08(par->PCIO, 0x03D4, 0x28);
if (VGA_RD08(par->PCIO, 0x03D5) & 0x80) {
VGA_WR08(par->PCIO, 0x03D4, 0x33);
if (!(VGA_RD08(par->PCIO, 0x03D5) & 0x01))
Television = 1;
FlatPanel = 1;
} else {
FlatPanel = 0;
}
printk("nvidiafb: HW is currently programmed for %s\n",
FlatPanel ? (Television ? "TV" : "DFP") :
"CRT");
}
if (par->FlatPanel == -1) {
par->FlatPanel = FlatPanel;
par->Television = Television;
} else {
printk("nvidiafb: Forcing display type to %s as "
"specified\n", par->FlatPanel ? "DFP" : "CRT");
}
} else {
u8 outputAfromCRTC, outputBfromCRTC;
int CRTCnumber = -1;
u8 slaved_on_A, slaved_on_B;
int analog_on_A, analog_on_B;
u32 oldhead;
u8 cr44;
if (implementation != 0x0110) {
if (NV_RD32(par->PRAMDAC0, 0x0000052C) & 0x100)
outputAfromCRTC = 1;
else
outputAfromCRTC = 0;
if (NV_RD32(par->PRAMDAC0, 0x0000252C) & 0x100)
outputBfromCRTC = 1;
else
outputBfromCRTC = 0;
analog_on_A = NVIsConnected(par, 0);
analog_on_B = NVIsConnected(par, 1);
} else {
outputAfromCRTC = 0;
outputBfromCRTC = 1;
analog_on_A = 0;
analog_on_B = 0;
}
VGA_WR08(par->PCIO, 0x03D4, 0x44);
cr44 = VGA_RD08(par->PCIO, 0x03D5);
VGA_WR08(par->PCIO, 0x03D5, 3);
NVSelectHeadRegisters(par, 1);
NVLockUnlock(par, 0);
VGA_WR08(par->PCIO, 0x03D4, 0x28);
slaved_on_B = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
if (slaved_on_B) {
VGA_WR08(par->PCIO, 0x03D4, 0x33);
tvB = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
}
VGA_WR08(par->PCIO, 0x03D4, 0x44);
VGA_WR08(par->PCIO, 0x03D5, 0);
NVSelectHeadRegisters(par, 0);
NVLockUnlock(par, 0);
VGA_WR08(par->PCIO, 0x03D4, 0x28);
slaved_on_A = VGA_RD08(par->PCIO, 0x03D5) & 0x80;
if (slaved_on_A) {
VGA_WR08(par->PCIO, 0x03D4, 0x33);
tvA = !(VGA_RD08(par->PCIO, 0x03D5) & 0x01);
}
oldhead = NV_RD32(par->PCRTC0, 0x00000860);
NV_WR32(par->PCRTC0, 0x00000860, oldhead | 0x00000010);
if (nvidia_probe_i2c_connector(info, 1, &edidA))
nvidia_probe_of_connector(info, 1, &edidA);
if (edidA && !fb_parse_edid(edidA, var)) {
printk("nvidiafb: EDID found from BUS1\n");
monA = monitorA;
fb_edid_to_monspecs(edidA, monA);
}
if (nvidia_probe_i2c_connector(info, 2, &edidB))
nvidia_probe_of_connector(info, 2, &edidB);
if (edidB && !fb_parse_edid(edidB, var)) {
printk("nvidiafb: EDID found from BUS2\n");
monB = monitorB;
fb_edid_to_monspecs(edidB, monB);
}
if (slaved_on_A && !tvA) {
CRTCnumber = 0;
FlatPanel = 1;
printk("nvidiafb: CRTC 0 is currently programmed for "
"DFP\n");
} else if (slaved_on_B && !tvB) {
CRTCnumber = 1;
FlatPanel = 1;
printk("nvidiafb: CRTC 1 is currently programmed "
"for DFP\n");
} else if (analog_on_A) {
CRTCnumber = outputAfromCRTC;
FlatPanel = 0;
printk("nvidiafb: CRTC %i appears to have a "
"CRT attached\n", CRTCnumber);
} else if (analog_on_B) {
CRTCnumber = outputBfromCRTC;
FlatPanel = 0;
printk("nvidiafb: CRTC %i appears to have a "
"CRT attached\n", CRTCnumber);
} else if (slaved_on_A) {
CRTCnumber = 0;
FlatPanel = 1;
Television = 1;
printk("nvidiafb: CRTC 0 is currently programmed "
"for TV\n");
} else if (slaved_on_B) {
CRTCnumber = 1;
FlatPanel = 1;
Television = 1;
printk("nvidiafb: CRTC 1 is currently programmed for "
"TV\n");
} else if (monA) {
FlatPanel = (monA->input & FB_DISP_DDI) ? 1 : 0;
} else if (monB) {
FlatPanel = (monB->input & FB_DISP_DDI) ? 1 : 0;
}
if (par->FlatPanel == -1) {
if (FlatPanel != -1) {
par->FlatPanel = FlatPanel;
par->Television = Television;
} else {
printk("nvidiafb: Unable to detect display "
"type...\n");
if (mobile) {
printk("...On a laptop, assuming "
"DFP\n");
par->FlatPanel = 1;
} else {
printk("...Using default of CRT\n");
par->FlatPanel = 0;
}
}
} else {
printk("nvidiafb: Forcing display type to %s as "
"specified\n", par->FlatPanel ? "DFP" : "CRT");
}
if (par->CRTCnumber == -1) {
if (CRTCnumber != -1)
par->CRTCnumber = CRTCnumber;
else {
printk("nvidiafb: Unable to detect which "
"CRTCNumber...\n");
if (par->FlatPanel)
par->CRTCnumber = 1;
else
par->CRTCnumber = 0;
printk("...Defaulting to CRTCNumber %i\n",
par->CRTCnumber);
}
} else {
printk("nvidiafb: Forcing CRTCNumber %i as "
"specified\n", par->CRTCnumber);
}
if (monA) {
if (((monA->input & FB_DISP_DDI) &&
par->FlatPanel) ||
((!(monA->input & FB_DISP_DDI)) &&
!par->FlatPanel)) {
if (monB) {
fb_destroy_modedb(monB->modedb);
monB = NULL;
}
} else {
fb_destroy_modedb(monA->modedb);
monA = NULL;
}
}
if (monB) {
if (((monB->input & FB_DISP_DDI) &&
!par->FlatPanel) ||
((!(monB->input & FB_DISP_DDI)) &&
par->FlatPanel)) {
fb_destroy_modedb(monB->modedb);
monB = NULL;
} else
monA = monB;
}
if (implementation == 0x0110)
cr44 = par->CRTCnumber * 0x3;
NV_WR32(par->PCRTC0, 0x00000860, oldhead);
VGA_WR08(par->PCIO, 0x03D4, 0x44);
VGA_WR08(par->PCIO, 0x03D5, cr44);
NVSelectHeadRegisters(par, par->CRTCnumber);
}
printk("nvidiafb: Using %s on CRTC %i\n",
par->FlatPanel ? (par->Television ? "TV" : "DFP") : "CRT",
par->CRTCnumber);
if (par->FlatPanel && !par->Television) {
par->fpWidth = NV_RD32(par->PRAMDAC, 0x0820) + 1;
par->fpHeight = NV_RD32(par->PRAMDAC, 0x0800) + 1;
par->fpSyncs = NV_RD32(par->PRAMDAC, 0x0848) & 0x30000033;
printk("nvidiafb: Panel size is %i x %i\n", par->fpWidth, par->fpHeight);
}
if (monA)
info->monspecs = *monA;
if (!par->FlatPanel || !par->twoHeads)
par->FPDither = 0;
par->LVDS = 0;
if (par->FlatPanel && par->twoHeads) {
NV_WR32(par->PRAMDAC0, 0x08B0, 0x00010004);
if (NV_RD32(par->PRAMDAC0, 0x08b4) & 1)
par->LVDS = 1;
printk("nvidiafb: Panel is %s\n", par->LVDS ? "LVDS" : "TMDS");
}
kfree(edidA);
kfree(edidB);
done:
kfree(var);
kfree(monitorA);
kfree(monitorB);
return err;
}

180
drivers/video/fbdev/nvidia/nv_type.h Normal file
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@ -0,0 +1,180 @@
#ifndef __NV_TYPE_H__
#define __NV_TYPE_H__
#include <linux/fb.h>
#include <linux/types.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <video/vga.h>
#define NV_ARCH_04 0x04
#define NV_ARCH_10 0x10
#define NV_ARCH_20 0x20
#define NV_ARCH_30 0x30
#define NV_ARCH_40 0x40
#define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))
#define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
#define SetBF(mask,value) ((value) << (0?mask))
#define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
#define SetBitField(value,from,to) SetBF(to, GetBF(value,from))
#define SetBit(n) (1<<(n))
#define Set8Bits(value) ((value)&0xff)
#define V_DBLSCAN 1
typedef struct {
int bitsPerPixel;
int depth;
int displayWidth;
int weight;
} NVFBLayout;
#define NUM_SEQ_REGS 0x05
#define NUM_CRT_REGS 0x41
#define NUM_GRC_REGS 0x09
#define NUM_ATC_REGS 0x15
struct nvidia_par;
struct nvidia_i2c_chan {
struct nvidia_par *par;
unsigned long ddc_base;
struct i2c_adapter adapter;
struct i2c_algo_bit_data algo;
};
typedef struct _riva_hw_state {
u8 attr[NUM_ATC_REGS];
u8 crtc[NUM_CRT_REGS];
u8 gra[NUM_GRC_REGS];
u8 seq[NUM_SEQ_REGS];
u8 misc_output;
u32 bpp;
u32 width;
u32 height;
u32 interlace;
u32 repaint0;
u32 repaint1;
u32 screen;
u32 scale;
u32 dither;
u32 extra;
u32 fifo;
u32 pixel;
u32 horiz;
u32 arbitration0;
u32 arbitration1;
u32 pll;
u32 pllB;
u32 vpll;
u32 vpll2;
u32 vpllB;
u32 vpll2B;
u32 pllsel;
u32 general;
u32 crtcOwner;
u32 head;
u32 head2;
u32 config;
u32 cursorConfig;
u32 cursor0;
u32 cursor1;
u32 cursor2;
u32 timingH;
u32 timingV;
u32 displayV;
u32 crtcSync;
u32 control;
} RIVA_HW_STATE;
struct riva_regs {
RIVA_HW_STATE ext;
};
struct nvidia_par {
RIVA_HW_STATE SavedReg;
RIVA_HW_STATE ModeReg;
RIVA_HW_STATE initial_state;
RIVA_HW_STATE *CurrentState;
struct vgastate vgastate;
u32 pseudo_palette[16];
struct pci_dev *pci_dev;
u32 Architecture;
u32 CursorStart;
int Chipset;
unsigned long FbAddress;
u8 __iomem *FbStart;
u32 FbMapSize;
u32 FbUsableSize;
u32 ScratchBufferSize;
u32 ScratchBufferStart;
int FpScale;
u32 MinVClockFreqKHz;
u32 MaxVClockFreqKHz;
u32 CrystalFreqKHz;
u32 RamAmountKBytes;
u32 IOBase;
NVFBLayout CurrentLayout;
int cursor_reset;
int lockup;
int videoKey;
int FlatPanel;
int FPDither;
int Television;
int CRTCnumber;
int alphaCursor;
int twoHeads;
int twoStagePLL;
int fpScaler;
int fpWidth;
int fpHeight;
int PanelTweak;
int paneltweak;
int LVDS;
int pm_state;
int reverse_i2c;
u32 crtcSync_read;
u32 fpSyncs;
u32 dmaPut;
u32 dmaCurrent;
u32 dmaFree;
u32 dmaMax;
u32 __iomem *dmaBase;
u32 currentRop;
int WaitVSyncPossible;
int BlendingPossible;
u32 paletteEnabled;
u32 forceCRTC;
u32 open_count;
u8 DDCBase;
#ifdef CONFIG_MTRR
struct {
int vram;
int vram_valid;
} mtrr;
#endif
struct nvidia_i2c_chan chan[3];
volatile u32 __iomem *REGS;
volatile u32 __iomem *PCRTC0;
volatile u32 __iomem *PCRTC;
volatile u32 __iomem *PRAMDAC0;
volatile u32 __iomem *PFB;
volatile u32 __iomem *PFIFO;
volatile u32 __iomem *PGRAPH;
volatile u32 __iomem *PEXTDEV;
volatile u32 __iomem *PTIMER;
volatile u32 __iomem *PMC;
volatile u32 __iomem *PRAMIN;
volatile u32 __iomem *FIFO;
volatile u32 __iomem *CURSOR;
volatile u8 __iomem *PCIO0;
volatile u8 __iomem *PCIO;
volatile u8 __iomem *PVIO;
volatile u8 __iomem *PDIO0;
volatile u8 __iomem *PDIO;
volatile u32 __iomem *PRAMDAC;
};
#endif /* __NV_TYPE_H__ */

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drivers/video/fbdev/nvidia/nvidia.c Normal file
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