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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
commit f6dfaef42e
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11
drivers/video/fbdev/riva/Makefile Normal file
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#
# Makefile for the Riva framebuffer driver
#
obj-$(CONFIG_FB_RIVA) += rivafb.o
rivafb-objs := fbdev.o riva_hw.o nv_driver.o
ifdef CONFIG_FB_RIVA_I2C
rivafb-objs += rivafb-i2c.o
endif

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drivers/video/fbdev/riva/fbdev.c Normal file
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drivers/video/fbdev/riva/nv_driver.c Normal file
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/* $XConsortium: nv_driver.c /main/3 1996/10/28 05:13:37 kaleb $ */
/*
* Copyright 1996-1997 David J. McKay
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
/*
* GPL licensing note -- nVidia is allowing a liberal interpretation of
* the documentation restriction above, to merely say that this nVidia's
* copyright and disclaimer should be included with all code derived
* from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
*/
/* Hacked together from mga driver and 3.3.4 NVIDIA driver by Jarno Paananen
<jpaana@s2.org> */
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_setup.c,v 1.18 2002/08/0
5 20:47:06 mvojkovi Exp $ */
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include "nv_type.h"
#include "rivafb.h"
#include "nvreg.h"
#define PFX "rivafb: "
static inline unsigned char MISCin(struct riva_par *par)
{
return (VGA_RD08(par->riva.PVIO, 0x3cc));
}
static Bool
riva_is_connected(struct riva_par *par, Bool second)
{
volatile U032 __iomem *PRAMDAC = par->riva.PRAMDAC0;
U032 reg52C, reg608;
Bool present;
if(second) PRAMDAC += 0x800;
reg52C = NV_RD32(PRAMDAC, 0x052C);
reg608 = NV_RD32(PRAMDAC, 0x0608);
NV_WR32(PRAMDAC, 0x0608, reg608 & ~0x00010000);
NV_WR32(PRAMDAC, 0x052C, reg52C & 0x0000FEEE);
mdelay(1);
NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1);
NV_WR32(par->riva.PRAMDAC0, 0x0610, 0x94050140);
NV_WR32(par->riva.PRAMDAC0, 0x0608, 0x00001000);
mdelay(1);
present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? TRUE : FALSE;
NV_WR32(par->riva.PRAMDAC0, 0x0608,
NV_RD32(par->riva.PRAMDAC0, 0x0608) & 0x0000EFFF);
NV_WR32(PRAMDAC, 0x052C, reg52C);
NV_WR32(PRAMDAC, 0x0608, reg608);
return present;
}
static void
riva_override_CRTC(struct riva_par *par)
{
printk(KERN_INFO PFX
"Detected CRTC controller %i being used\n",
par->SecondCRTC ? 1 : 0);
if(par->forceCRTC != -1) {
printk(KERN_INFO PFX
"Forcing usage of CRTC %i\n", par->forceCRTC);
par->SecondCRTC = par->forceCRTC;
}
}
static void
riva_is_second(struct riva_par *par)
{
if (par->FlatPanel == 1) {
switch(par->Chipset & 0xffff) {
case 0x0174:
case 0x0175:
case 0x0176:
case 0x0177:
case 0x0179:
case 0x017C:
case 0x017D:
case 0x0186:
case 0x0187:
/* this might not be a good default for the chips below */
case 0x0286:
case 0x028C:
case 0x0316:
case 0x0317:
case 0x031A:
case 0x031B:
case 0x031C:
case 0x031D:
case 0x031E:
case 0x031F:
case 0x0324:
case 0x0325:
case 0x0328:
case 0x0329:
case 0x032C:
case 0x032D:
par->SecondCRTC = TRUE;
break;
default:
par->SecondCRTC = FALSE;
break;
}
} else {
if(riva_is_connected(par, 0)) {
if (NV_RD32(par->riva.PRAMDAC0, 0x0000052C) & 0x100)
par->SecondCRTC = TRUE;
else
par->SecondCRTC = FALSE;
} else
if (riva_is_connected(par, 1)) {
if(NV_RD32(par->riva.PRAMDAC0, 0x0000252C) & 0x100)
par->SecondCRTC = TRUE;
else
par->SecondCRTC = FALSE;
} else /* default */
par->SecondCRTC = FALSE;
}
riva_override_CRTC(par);
}
unsigned long riva_get_memlen(struct riva_par *par)
{
RIVA_HW_INST *chip = &par->riva;
unsigned long memlen = 0;
unsigned int chipset = par->Chipset;
struct pci_dev* dev;
u32 amt;
switch (chip->Architecture) {
case NV_ARCH_03:
if (NV_RD32(chip->PFB, 0x00000000) & 0x00000020) {
if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20)
&& ((NV_RD32(chip->PMC, 0x00000000)&0x0F)>=0x02)) {
/*
* SDRAM 128 ZX.
*/
switch (NV_RD32(chip->PFB,0x00000000) & 0x03) {
case 2:
memlen = 1024 * 4;
break;
case 1:
memlen = 1024 * 2;
break;
default:
memlen = 1024 * 8;
break;
}
} else {
memlen = 1024 * 8;
}
} else {
/*
* SGRAM 128.
*/
switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) {
case 0:
memlen = 1024 * 8;
break;
case 2:
memlen = 1024 * 4;
break;
default:
memlen = 1024 * 2;
break;
}
}
break;
case NV_ARCH_04:
if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100) {
memlen = ((NV_RD32(chip->PFB, 0x00000000)>>12)&0x0F) *
1024 * 2 + 1024 * 2;
} else {
switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) {
case 0:
memlen = 1024 * 32;
break;
case 1:
memlen = 1024 * 4;
break;
case 2:
memlen = 1024 * 8;
break;
case 3:
default:
memlen = 1024 * 16;
break;
}
}
break;
case NV_ARCH_10:
case NV_ARCH_20:
case NV_ARCH_30:
if(chipset == NV_CHIP_IGEFORCE2) {
dev = pci_get_bus_and_slot(0, 1);
pci_read_config_dword(dev, 0x7C, &amt);
pci_dev_put(dev);
memlen = (((amt >> 6) & 31) + 1) * 1024;
} else if (chipset == NV_CHIP_0x01F0) {
dev = pci_get_bus_and_slot(0, 1);
pci_read_config_dword(dev, 0x84, &amt);
pci_dev_put(dev);
memlen = (((amt >> 4) & 127) + 1) * 1024;
} else {
switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) &
0x000000FF){
case 0x02:
memlen = 1024 * 2;
break;
case 0x04:
memlen = 1024 * 4;
break;
case 0x08:
memlen = 1024 * 8;
break;
case 0x10:
memlen = 1024 * 16;
break;
case 0x20:
memlen = 1024 * 32;
break;
case 0x40:
memlen = 1024 * 64;
break;
case 0x80:
memlen = 1024 * 128;
break;
default:
memlen = 1024 * 16;
break;
}
}
break;
}
return memlen;
}
unsigned long riva_get_maxdclk(struct riva_par *par)
{
RIVA_HW_INST *chip = &par->riva;
unsigned long dclk = 0;
switch (chip->Architecture) {
case NV_ARCH_03:
if (NV_RD32(chip->PFB, 0x00000000) & 0x00000020) {
if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20)
&& ((NV_RD32(chip->PMC,0x00000000)&0x0F) >= 0x02)) {
/*
* SDRAM 128 ZX.
*/
dclk = 800000;
} else {
dclk = 1000000;
}
} else {
/*
* SGRAM 128.
*/
dclk = 1000000;
}
break;
case NV_ARCH_04:
case NV_ARCH_10:
case NV_ARCH_20:
case NV_ARCH_30:
switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) {
case 3:
dclk = 800000;
break;
default:
dclk = 1000000;
break;
}
break;
}
return dclk;
}
void
riva_common_setup(struct riva_par *par)
{
par->riva.EnableIRQ = 0;
par->riva.PRAMDAC0 =
(volatile U032 __iomem *)(par->ctrl_base + 0x00680000);
par->riva.PFB =
(volatile U032 __iomem *)(par->ctrl_base + 0x00100000);
par->riva.PFIFO =
(volatile U032 __iomem *)(par->ctrl_base + 0x00002000);
par->riva.PGRAPH =
(volatile U032 __iomem *)(par->ctrl_base + 0x00400000);
par->riva.PEXTDEV =
(volatile U032 __iomem *)(par->ctrl_base + 0x00101000);
par->riva.PTIMER =
(volatile U032 __iomem *)(par->ctrl_base + 0x00009000);
par->riva.PMC =
(volatile U032 __iomem *)(par->ctrl_base + 0x00000000);
par->riva.FIFO =
(volatile U032 __iomem *)(par->ctrl_base + 0x00800000);
par->riva.PCIO0 = par->ctrl_base + 0x00601000;
par->riva.PDIO0 = par->ctrl_base + 0x00681000;
par->riva.PVIO = par->ctrl_base + 0x000C0000;
par->riva.IO = (MISCin(par) & 0x01) ? 0x3D0 : 0x3B0;
if (par->FlatPanel == -1) {
switch (par->Chipset & 0xffff) {
case 0x0112: /* known laptop chips */
case 0x0174:
case 0x0175:
case 0x0176:
case 0x0177:
case 0x0179:
case 0x017C:
case 0x017D:
case 0x0186:
case 0x0187:
case 0x0286:
case 0x028C:
case 0x0316:
case 0x0317:
case 0x031A:
case 0x031B:
case 0x031C:
case 0x031D:
case 0x031E:
case 0x031F:
case 0x0324:
case 0x0325:
case 0x0328:
case 0x0329:
case 0x032C:
case 0x032D:
printk(KERN_INFO PFX
"On a laptop. Assuming Digital Flat Panel\n");
par->FlatPanel = 1;
break;
default:
break;
}
}
switch (par->Chipset & 0x0ff0) {
case 0x0110:
if (par->Chipset == NV_CHIP_GEFORCE2_GO)
par->SecondCRTC = TRUE;
#if defined(__powerpc__)
if (par->FlatPanel == 1)
par->SecondCRTC = TRUE;
#endif
riva_override_CRTC(par);
break;
case 0x0170:
case 0x0180:
case 0x01F0:
case 0x0250:
case 0x0280:
case 0x0300:
case 0x0310:
case 0x0320:
case 0x0330:
case 0x0340:
riva_is_second(par);
break;
default:
break;
}
if (par->SecondCRTC) {
par->riva.PCIO = par->riva.PCIO0 + 0x2000;
par->riva.PCRTC = par->riva.PCRTC0 + 0x800;
par->riva.PRAMDAC = par->riva.PRAMDAC0 + 0x800;
par->riva.PDIO = par->riva.PDIO0 + 0x2000;
} else {
par->riva.PCIO = par->riva.PCIO0;
par->riva.PCRTC = par->riva.PCRTC0;
par->riva.PRAMDAC = par->riva.PRAMDAC0;
par->riva.PDIO = par->riva.PDIO0;
}
if (par->FlatPanel == -1) {
/* Fix me, need x86 DDC code */
par->FlatPanel = 0;
}
par->riva.flatPanel = (par->FlatPanel > 0) ? TRUE : FALSE;
RivaGetConfig(&par->riva, par->Chipset);
}

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drivers/video/fbdev/riva/nv_type.h Normal file
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/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h,v 1.35 2002/08/05 20:47:06 mvojkovi Exp $ */
#ifndef __NV_STRUCT_H__
#define __NV_STRUCT_H__
#define NV_CHIP_RIVA_128 ((PCI_VENDOR_ID_NVIDIA_SGS << 16)| PCI_DEVICE_ID_NVIDIA_RIVA128)
#define NV_CHIP_TNT ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_TNT)
#define NV_CHIP_TNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_TNT2)
#define NV_CHIP_UTNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_UTNT2)
#define NV_CHIP_VTNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_VTNT2)
#define NV_CHIP_UVTNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_UVTNT2)
#define NV_CHIP_ITNT2 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_ITNT2)
#define NV_CHIP_GEFORCE_256 ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_GEFORCE_256)
#define NV_CHIP_GEFORCE_DDR ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR)
#define NV_CHIP_QUADRO ((PCI_VENDOR_ID_NVIDIA << 16)| PCI_DEVICE_ID_NVIDIA_QUADRO)
#define NV_CHIP_GEFORCE2_MX ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX)
#define NV_CHIP_GEFORCE2_MX_100 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX_100)
#define NV_CHIP_QUADRO2_MXR ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR)
#define NV_CHIP_GEFORCE2_GO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO)
#define NV_CHIP_GEFORCE2_GTS ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS)
#define NV_CHIP_GEFORCE2_TI ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_TI)
#define NV_CHIP_GEFORCE2_ULTRA ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA)
#define NV_CHIP_QUADRO2_PRO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO)
#define NV_CHIP_GEFORCE4_MX_460 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460)
#define NV_CHIP_GEFORCE4_MX_440 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440)
#define NV_CHIP_GEFORCE4_MX_420 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420)
#define NV_CHIP_GEFORCE4_440_GO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO)
#define NV_CHIP_GEFORCE4_420_GO ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO)
#define NV_CHIP_GEFORCE4_420_GO_M32 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32)
#define NV_CHIP_QUADRO4_500XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL)
#define NV_CHIP_GEFORCE4_440_GO_M64 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64)
#define NV_CHIP_QUADRO4_200 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_200)
#define NV_CHIP_QUADRO4_550XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL)
#define NV_CHIP_QUADRO4_500_GOGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL)
#define NV_CHIP_0x0180 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0180)
#define NV_CHIP_0x0181 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0181)
#define NV_CHIP_0x0182 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0182)
#define NV_CHIP_0x0188 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0188)
#define NV_CHIP_0x018A ((PCI_VENDOR_ID_NVIDIA << 16) | 0x018A)
#define NV_CHIP_0x018B ((PCI_VENDOR_ID_NVIDIA << 16) | 0x018B)
#define NV_CHIP_IGEFORCE2 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_IGEFORCE2)
#define NV_CHIP_0x01F0 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x01F0)
#define NV_CHIP_GEFORCE3 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE3)
#define NV_CHIP_GEFORCE3_TI_200 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI_200)
#define NV_CHIP_GEFORCE3_TI_500 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE3_TI_500)
#define NV_CHIP_QUADRO_DCC ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO_DCC)
#define NV_CHIP_GEFORCE4_TI_4600 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600)
#define NV_CHIP_GEFORCE4_TI_4400 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400)
#define NV_CHIP_GEFORCE4_TI_4200 ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200)
#define NV_CHIP_QUADRO4_900XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL)
#define NV_CHIP_QUADRO4_750XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL)
#define NV_CHIP_QUADRO4_700XGL ((PCI_VENDOR_ID_NVIDIA << 16) | PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL)
#define NV_CHIP_0x0280 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0280)
#define NV_CHIP_0x0281 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0281)
#define NV_CHIP_0x0288 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0288)
#define NV_CHIP_0x0289 ((PCI_VENDOR_ID_NVIDIA << 16) | 0x0289)
#endif /* __NV_STRUCT_H__ */

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drivers/video/fbdev/riva/nvreg.h Normal file
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/* $XConsortium: nvreg.h /main/2 1996/10/28 05:13:41 kaleb $ */
/*
* Copyright 1996-1997 David J. McKay
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
/* $XFree86: xc/programs/Xserver/hw/xfree86/vga256/drivers/nv/nvreg.h,v 3.2.2.1 1998/01/18 10:35:36 hohndel Exp $ */
#ifndef __NVREG_H_
#define __NVREG_H_
/* Little macro to construct bitmask for contiguous ranges of bits */
#define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))
#define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
/* Macro to set specific bitfields (mask has to be a macro x:y) ! */
#define SetBF(mask,value) ((value) << (0?mask))
#define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) )
#define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \
| SetBF(mask,value)))
#define DEVICE_BASE(device) (0?NV##_##device)
#define DEVICE_SIZE(device) ((1?NV##_##device) - DEVICE_BASE(device)+1)
/* This is where we will have to have conditional compilation */
#define DEVICE_ACCESS(device,reg) \
nvCONTROL[(NV_##device##_##reg)/4]
#define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value)
#define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg)
#define DEVICE_PRINT(device,reg) \
ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg))
#define DEVICE_DEF(device,mask,value) \
SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value)
#define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value)
#define DEVICE_MASK(device,mask) MASKEXPAND(NV_##device##_##mask)
#define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value)
#define PDAC_Read(reg) DEVICE_READ(PDAC,reg)
#define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg)
#define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value)
#define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value)
#define PDAC_Mask(mask) DEVICE_MASK(PDAC,mask)
#define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value)
#define PFB_Read(reg) DEVICE_READ(PFB,reg)
#define PFB_Print(reg) DEVICE_PRINT(PFB,reg)
#define PFB_Def(mask,value) DEVICE_DEF(PFB,mask,value)
#define PFB_Val(mask,value) DEVICE_VALUE(PFB,mask,value)
#define PFB_Mask(mask) DEVICE_MASK(PFB,mask)
#define PRM_Write(reg,value) DEVICE_WRITE(PRM,reg,value)
#define PRM_Read(reg) DEVICE_READ(PRM,reg)
#define PRM_Print(reg) DEVICE_PRINT(PRM,reg)
#define PRM_Def(mask,value) DEVICE_DEF(PRM,mask,value)
#define PRM_Val(mask,value) DEVICE_VALUE(PRM,mask,value)
#define PRM_Mask(mask) DEVICE_MASK(PRM,mask)
#define PGRAPH_Write(reg,value) DEVICE_WRITE(PGRAPH,reg,value)
#define PGRAPH_Read(reg) DEVICE_READ(PGRAPH,reg)
#define PGRAPH_Print(reg) DEVICE_PRINT(PGRAPH,reg)
#define PGRAPH_Def(mask,value) DEVICE_DEF(PGRAPH,mask,value)
#define PGRAPH_Val(mask,value) DEVICE_VALUE(PGRAPH,mask,value)
#define PGRAPH_Mask(mask) DEVICE_MASK(PGRAPH,mask)
#define PDMA_Write(reg,value) DEVICE_WRITE(PDMA,reg,value)
#define PDMA_Read(reg) DEVICE_READ(PDMA,reg)
#define PDMA_Print(reg) DEVICE_PRINT(PDMA,reg)
#define PDMA_Def(mask,value) DEVICE_DEF(PDMA,mask,value)
#define PDMA_Val(mask,value) DEVICE_VALUE(PDMA,mask,value)
#define PDMA_Mask(mask) DEVICE_MASK(PDMA,mask)
#define PTIMER_Write(reg,value) DEVICE_WRITE(PTIMER,reg,value)
#define PTIMER_Read(reg) DEVICE_READ(PTIMER,reg)
#define PTIMER_Print(reg) DEVICE_PRINT(PTIMER,reg)
#define PTIMER_Def(mask,value) DEVICE_DEF(PTIMER,mask,value)
#define PTIMER_Val(mask,value) DEVICE_VALUE(PTIEMR,mask,value)
#define PTIMER_Mask(mask) DEVICE_MASK(PTIMER,mask)
#define PEXTDEV_Write(reg,value) DEVICE_WRITE(PEXTDEV,reg,value)
#define PEXTDEV_Read(reg) DEVICE_READ(PEXTDEV,reg)
#define PEXTDEV_Print(reg) DEVICE_PRINT(PEXTDEV,reg)
#define PEXTDEV_Def(mask,value) DEVICE_DEF(PEXTDEV,mask,value)
#define PEXTDEV_Val(mask,value) DEVICE_VALUE(PEXTDEV,mask,value)
#define PEXTDEV_Mask(mask) DEVICE_MASK(PEXTDEV,mask)
#define PFIFO_Write(reg,value) DEVICE_WRITE(PFIFO,reg,value)
#define PFIFO_Read(reg) DEVICE_READ(PFIFO,reg)
#define PFIFO_Print(reg) DEVICE_PRINT(PFIFO,reg)
#define PFIFO_Def(mask,value) DEVICE_DEF(PFIFO,mask,value)
#define PFIFO_Val(mask,value) DEVICE_VALUE(PFIFO,mask,value)
#define PFIFO_Mask(mask) DEVICE_MASK(PFIFO,mask)
#define PRAM_Write(reg,value) DEVICE_WRITE(PRAM,reg,value)
#define PRAM_Read(reg) DEVICE_READ(PRAM,reg)
#define PRAM_Print(reg) DEVICE_PRINT(PRAM,reg)
#define PRAM_Def(mask,value) DEVICE_DEF(PRAM,mask,value)
#define PRAM_Val(mask,value) DEVICE_VALUE(PRAM,mask,value)
#define PRAM_Mask(mask) DEVICE_MASK(PRAM,mask)
#define PRAMFC_Write(reg,value) DEVICE_WRITE(PRAMFC,reg,value)
#define PRAMFC_Read(reg) DEVICE_READ(PRAMFC,reg)
#define PRAMFC_Print(reg) DEVICE_PRINT(PRAMFC,reg)
#define PRAMFC_Def(mask,value) DEVICE_DEF(PRAMFC,mask,value)
#define PRAMFC_Val(mask,value) DEVICE_VALUE(PRAMFC,mask,value)
#define PRAMFC_Mask(mask) DEVICE_MASK(PRAMFC,mask)
#define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
#define PMC_Read(reg) DEVICE_READ(PMC,reg)
#define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
#define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
#define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)
#define PMC_Mask(mask) DEVICE_MASK(PMC,mask)
#define PMC_Write(reg,value) DEVICE_WRITE(PMC,reg,value)
#define PMC_Read(reg) DEVICE_READ(PMC,reg)
#define PMC_Print(reg) DEVICE_PRINT(PMC,reg)
#define PMC_Def(mask,value) DEVICE_DEF(PMC,mask,value)
#define PMC_Val(mask,value) DEVICE_VALUE(PMC,mask,value)
#define PMC_Mask(mask) DEVICE_MASK(PMC,mask)
#define PBUS_Write(reg,value) DEVICE_WRITE(PBUS,reg,value)
#define PBUS_Read(reg) DEVICE_READ(PBUS,reg)
#define PBUS_Print(reg) DEVICE_PRINT(PBUS,reg)
#define PBUS_Def(mask,value) DEVICE_DEF(PBUS,mask,value)
#define PBUS_Val(mask,value) DEVICE_VALUE(PBUS,mask,value)
#define PBUS_Mask(mask) DEVICE_MASK(PBUS,mask)
#define PRAMDAC_Write(reg,value) DEVICE_WRITE(PRAMDAC,reg,value)
#define PRAMDAC_Read(reg) DEVICE_READ(PRAMDAC,reg)
#define PRAMDAC_Print(reg) DEVICE_PRINT(PRAMDAC,reg)
#define PRAMDAC_Def(mask,value) DEVICE_DEF(PRAMDAC,mask,value)
#define PRAMDAC_Val(mask,value) DEVICE_VALUE(PRAMDAC,mask,value)
#define PRAMDAC_Mask(mask) DEVICE_MASK(PRAMDAC,mask)
#define PDAC_ReadExt(reg) \
((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\
(PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\
(PDAC_Read(INDEX_DATA)))
#define PDAC_WriteExt(reg,value)\
((PDAC_Write(INDEX_LO,(NV_PDAC_EXT_##reg) & 0xff)),\
(PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\
(PDAC_Write(INDEX_DATA,(value))))
#define CRTC_Write(index,value) outb((index), 0x3d4); outb(value, 0x3d5)
#define CRTC_Read(index) (outb(index, 0x3d4),inb(0x3d5))
#define PCRTC_Write(index,value) CRTC_Write(NV_PCRTC_##index,value)
#define PCRTC_Read(index) CRTC_Read(NV_PCRTC_##index)
#define PCRTC_Def(mask,value) DEVICE_DEF(PCRTC,mask,value)
#define PCRTC_Val(mask,value) DEVICE_VALUE(PCRTC,mask,value)
#define PCRTC_Mask(mask) DEVICE_MASK(PCRTC,mask)
#define SR_Write(index,value) outb(0x3c4,(index));outb(0x3c5,value)
#define SR_Read(index) (outb(0x3c4,index),inb(0x3c5))
extern volatile unsigned *nvCONTROL;
typedef enum {NV1,NV3,NV4,NumNVChips} NVChipType;
NVChipType GetChipType(void);
#endif

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/***************************************************************************\
|* *|
|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
|* *|
|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
|* international laws. Users and possessors of this source code are *|
|* hereby granted a nonexclusive, royalty-free copyright license to *|
|* use this code in individual and commercial software. *|
|* *|
|* Any use of this source code must include, in the user documenta- *|
|* tion and internal comments to the code, notices to the end user *|
|* as follows: *|
|* *|
|* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
|* *|
|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
|* *|
|* U.S. Government End Users. This source code is a "commercial *|
|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
|* consisting of "commercial computer software" and "commercial *|
|* computer software documentation," as such terms are used in *|
|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
|* all U.S. Government End Users acquire the source code with only *|
|* those rights set forth herein. *|
|* *|
\***************************************************************************/
/*
* GPL licensing note -- nVidia is allowing a liberal interpretation of
* the documentation restriction above, to merely say that this nVidia's
* copyright and disclaimer should be included with all code derived
* from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
*/
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.h,v 1.21 2002/10/14 18:22:46 mvojkovi Exp $ */
#ifndef __RIVA_HW_H__
#define __RIVA_HW_H__
#define RIVA_SW_VERSION 0x00010003
#ifndef Bool
typedef int Bool;
#endif
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#ifndef NULL
#define NULL 0
#endif
/*
* Typedefs to force certain sized values.
*/
typedef unsigned char U008;
typedef unsigned short U016;
typedef unsigned int U032;
/*
* HW access macros.
*/
#include <asm/io.h>
#define NV_WR08(p,i,d) (__raw_writeb((d), (void __iomem *)(p) + (i)))
#define NV_RD08(p,i) (__raw_readb((void __iomem *)(p) + (i)))
#define NV_WR16(p,i,d) (__raw_writew((d), (void __iomem *)(p) + (i)))
#define NV_RD16(p,i) (__raw_readw((void __iomem *)(p) + (i)))
#define NV_WR32(p,i,d) (__raw_writel((d), (void __iomem *)(p) + (i)))
#define NV_RD32(p,i) (__raw_readl((void __iomem *)(p) + (i)))
#define VGA_WR08(p,i,d) (writeb((d), (void __iomem *)(p) + (i)))
#define VGA_RD08(p,i) (readb((void __iomem *)(p) + (i)))
/*
* Define different architectures.
*/
#define NV_ARCH_03 0x03
#define NV_ARCH_04 0x04
#define NV_ARCH_10 0x10
#define NV_ARCH_20 0x20
#define NV_ARCH_30 0x30
#define NV_ARCH_40 0x40
/***************************************************************************\
* *
* FIFO registers. *
* *
\***************************************************************************/
/*
* Raster OPeration. Windows style ROP3.
*/
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BB];
U032 Rop3;
} RivaRop;
/*
* 8X8 Monochrome pattern.
*/
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BD];
U032 Shape;
U032 reserved03[0x001];
U032 Color0;
U032 Color1;
U032 Monochrome[2];
} RivaPattern;
/*
* Scissor clip rectangle.
*/
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BB];
U032 TopLeft;
U032 WidthHeight;
} RivaClip;
/*
* 2D filled rectangle.
*/
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop[1];
#endif
U032 reserved01[0x0BC];
U032 Color;
U032 reserved03[0x03E];
U032 TopLeft;
U032 WidthHeight;
} RivaRectangle;
/*
* 2D screen-screen BLT.
*/
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BB];
U032 TopLeftSrc;
U032 TopLeftDst;
U032 WidthHeight;
} RivaScreenBlt;
/*
* 2D pixel BLT.
*/
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop[1];
#endif
U032 reserved01[0x0BC];
U032 TopLeft;
U032 WidthHeight;
U032 WidthHeightIn;
U032 reserved02[0x03C];
U032 Pixels;
} RivaPixmap;
/*
* Filled rectangle combined with monochrome expand. Useful for glyphs.
*/
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BB];
U032 reserved03[(0x040)-1];
U032 Color1A;
struct
{
U032 TopLeft;
U032 WidthHeight;
} UnclippedRectangle[64];
U032 reserved04[(0x080)-3];
struct
{
U032 TopLeft;
U032 BottomRight;
} ClipB;
U032 Color1B;
struct
{
U032 TopLeft;
U032 BottomRight;
} ClippedRectangle[64];
U032 reserved05[(0x080)-5];
struct
{
U032 TopLeft;
U032 BottomRight;
} ClipC;
U032 Color1C;
U032 WidthHeightC;
U032 PointC;
U032 MonochromeData1C;
U032 reserved06[(0x080)+121];
struct
{
U032 TopLeft;
U032 BottomRight;
} ClipD;
U032 Color1D;
U032 WidthHeightInD;
U032 WidthHeightOutD;
U032 PointD;
U032 MonochromeData1D;
U032 reserved07[(0x080)+120];
struct
{
U032 TopLeft;
U032 BottomRight;
} ClipE;
U032 Color0E;
U032 Color1E;
U032 WidthHeightInE;
U032 WidthHeightOutE;
U032 PointE;
U032 MonochromeData01E;
} RivaBitmap;
/*
* 3D textured, Z buffered triangle.
*/
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BC];
U032 TextureOffset;
U032 TextureFormat;
U032 TextureFilter;
U032 FogColor;
/* This is a problem on LynxOS */
#ifdef Control
#undef Control
#endif
U032 Control;
U032 AlphaTest;
U032 reserved02[0x339];
U032 FogAndIndex;
U032 Color;
float ScreenX;
float ScreenY;
float ScreenZ;
float EyeM;
float TextureS;
float TextureT;
} RivaTexturedTriangle03;
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BB];
U032 ColorKey;
U032 TextureOffset;
U032 TextureFormat;
U032 TextureFilter;
U032 Blend;
/* This is a problem on LynxOS */
#ifdef Control
#undef Control
#endif
U032 Control;
U032 FogColor;
U032 reserved02[0x39];
struct
{
float ScreenX;
float ScreenY;
float ScreenZ;
float EyeM;
U032 Color;
U032 Specular;
float TextureS;
float TextureT;
} Vertex[16];
U032 DrawTriangle3D;
} RivaTexturedTriangle05;
/*
* 2D line.
*/
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop[1];
#endif
U032 reserved01[0x0BC];
U032 Color; /* source color 0304-0307*/
U032 Reserved02[0x03e];
struct { /* start aliased methods in array 0400- */
U032 point0; /* y_x S16_S16 in pixels 0- 3*/
U032 point1; /* y_x S16_S16 in pixels 4- 7*/
} Lin[16]; /* end of aliased methods in array -047f*/
struct { /* start aliased methods in array 0480- */
U032 point0X; /* in pixels, 0 at left 0- 3*/
U032 point0Y; /* in pixels, 0 at top 4- 7*/
U032 point1X; /* in pixels, 0 at left 8- b*/
U032 point1Y; /* in pixels, 0 at top c- f*/
} Lin32[8]; /* end of aliased methods in array -04ff*/
U032 PolyLin[32]; /* y_x S16_S16 in pixels 0500-057f*/
struct { /* start aliased methods in array 0580- */
U032 x; /* in pixels, 0 at left 0- 3*/
U032 y; /* in pixels, 0 at top 4- 7*/
} PolyLin32[16]; /* end of aliased methods in array -05ff*/
struct { /* start aliased methods in array 0600- */
U032 color; /* source color 0- 3*/
U032 point; /* y_x S16_S16 in pixels 4- 7*/
} ColorPolyLin[16]; /* end of aliased methods in array -067f*/
} RivaLine;
/*
* 2D/3D surfaces
*/
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BE];
U032 Offset;
} RivaSurface;
typedef volatile struct
{
U032 reserved00[4];
#ifdef __BIG_ENDIAN
U032 FifoFree;
#else
U016 FifoFree;
U016 Nop;
#endif
U032 reserved01[0x0BD];
U032 Pitch;
U032 RenderBufferOffset;
U032 ZBufferOffset;
} RivaSurface3D;
/***************************************************************************\
* *
* Virtualized RIVA H/W interface. *
* *
\***************************************************************************/
#define FP_ENABLE 1
#define FP_DITHER 2
struct _riva_hw_inst;
struct _riva_hw_state;
/*
* Virtialized chip interface. Makes RIVA 128 and TNT look alike.
*/
typedef struct _riva_hw_inst
{
/*
* Chip specific settings.
*/
U032 Architecture;
U032 Version;
U032 Chipset;
U032 CrystalFreqKHz;
U032 RamAmountKBytes;
U032 MaxVClockFreqKHz;
U032 RamBandwidthKBytesPerSec;
U032 EnableIRQ;
U032 IO;
U032 VBlankBit;
U032 FifoFreeCount;
U032 FifoEmptyCount;
U032 CursorStart;
U032 flatPanel;
Bool twoHeads;
/*
* Non-FIFO registers.
*/
volatile U032 __iomem *PCRTC0;
volatile U032 __iomem *PCRTC;
volatile U032 __iomem *PRAMDAC0;
volatile U032 __iomem *PFB;
volatile U032 __iomem *PFIFO;
volatile U032 __iomem *PGRAPH;
volatile U032 __iomem *PEXTDEV;
volatile U032 __iomem *PTIMER;
volatile U032 __iomem *PMC;
volatile U032 __iomem *PRAMIN;
volatile U032 __iomem *FIFO;
volatile U032 __iomem *CURSOR;
volatile U008 __iomem *PCIO0;
volatile U008 __iomem *PCIO;
volatile U008 __iomem *PVIO;
volatile U008 __iomem *PDIO0;
volatile U008 __iomem *PDIO;
volatile U032 __iomem *PRAMDAC;
/*
* Common chip functions.
*/
int (*Busy)(struct _riva_hw_inst *);
void (*LoadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
void (*UnloadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
void (*SetStartAddress)(struct _riva_hw_inst *,U032);
void (*SetSurfaces2D)(struct _riva_hw_inst *,U032,U032);
void (*SetSurfaces3D)(struct _riva_hw_inst *,U032,U032);
int (*ShowHideCursor)(struct _riva_hw_inst *,int);
void (*LockUnlock)(struct _riva_hw_inst *, int);
/*
* Current extended mode settings.
*/
struct _riva_hw_state *CurrentState;
/*
* FIFO registers.
*/
RivaRop __iomem *Rop;
RivaPattern __iomem *Patt;
RivaClip __iomem *Clip;
RivaPixmap __iomem *Pixmap;
RivaScreenBlt __iomem *Blt;
RivaBitmap __iomem *Bitmap;
RivaLine __iomem *Line;
RivaTexturedTriangle03 __iomem *Tri03;
RivaTexturedTriangle05 __iomem *Tri05;
} RIVA_HW_INST;
/*
* Extended mode state information.
*/
typedef struct _riva_hw_state
{
U032 bpp;
U032 width;
U032 height;
U032 interlace;
U032 repaint0;
U032 repaint1;
U032 screen;
U032 scale;
U032 dither;
U032 extra;
U032 pixel;
U032 horiz;
U032 arbitration0;
U032 arbitration1;
U032 vpll;
U032 vpll2;
U032 pllsel;
U032 general;
U032 crtcOwner;
U032 head;
U032 head2;
U032 config;
U032 cursorConfig;
U032 cursor0;
U032 cursor1;
U032 cursor2;
U032 offset0;
U032 offset1;
U032 offset2;
U032 offset3;
U032 pitch0;
U032 pitch1;
U032 pitch2;
U032 pitch3;
} RIVA_HW_STATE;
/*
* function prototypes
*/
extern int CalcStateExt
(
RIVA_HW_INST *chip,
RIVA_HW_STATE *state,
int bpp,
int width,
int hDisplaySize,
int height,
int dotClock
);
/*
* External routines.
*/
int RivaGetConfig(RIVA_HW_INST *, unsigned int);
/*
* FIFO Free Count. Should attempt to yield processor if RIVA is busy.
*/
#define RIVA_FIFO_FREE(hwinst,hwptr,cnt) \
{ \
while ((hwinst).FifoFreeCount < (cnt)) { \
mb();mb(); \
(hwinst).FifoFreeCount = NV_RD32(&(hwinst).hwptr->FifoFree, 0) >> 2; \
} \
(hwinst).FifoFreeCount -= (cnt); \
}
#endif /* __RIVA_HW_H__ */

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/*
* linux/drivers/video/riva/fbdev-i2c.c - nVidia i2c
*
* Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
*
* Copyright 2004 Antonino A. Daplas <adaplas @pol.net>
*
* Based on radeonfb-i2c.c
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/fb.h>
#include <linux/jiffies.h>
#include <asm/io.h>
#include "rivafb.h"
#include "../edid.h"
static void riva_gpio_setscl(void* data, int state)
{
struct riva_i2c_chan *chan = data;
struct riva_par *par = chan->par;
u32 val;
VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0;
if (state)
val |= 0x20;
else
val &= ~0x20;
VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1);
}
static void riva_gpio_setsda(void* data, int state)
{
struct riva_i2c_chan *chan = data;
struct riva_par *par = chan->par;
u32 val;
VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
val = VGA_RD08(par->riva.PCIO, 0x3d5) & 0xf0;
if (state)
val |= 0x10;
else
val &= ~0x10;
VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base + 1);
VGA_WR08(par->riva.PCIO, 0x3d5, val | 0x1);
}
static int riva_gpio_getscl(void* data)
{
struct riva_i2c_chan *chan = data;
struct riva_par *par = chan->par;
u32 val = 0;
VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base);
if (VGA_RD08(par->riva.PCIO, 0x3d5) & 0x04)
val = 1;
return val;
}
static int riva_gpio_getsda(void* data)
{
struct riva_i2c_chan *chan = data;
struct riva_par *par = chan->par;
u32 val = 0;
VGA_WR08(par->riva.PCIO, 0x3d4, chan->ddc_base);
if (VGA_RD08(par->riva.PCIO, 0x3d5) & 0x08)
val = 1;
return val;
}
static int riva_setup_i2c_bus(struct riva_i2c_chan *chan, const char *name,
unsigned int i2c_class)
{
int rc;
strcpy(chan->adapter.name, name);
chan->adapter.owner = THIS_MODULE;
chan->adapter.class = i2c_class;
chan->adapter.algo_data = &chan->algo;
chan->adapter.dev.parent = &chan->par->pdev->dev;
chan->algo.setsda = riva_gpio_setsda;
chan->algo.setscl = riva_gpio_setscl;
chan->algo.getsda = riva_gpio_getsda;
chan->algo.getscl = riva_gpio_getscl;
chan->algo.udelay = 40;
chan->algo.timeout = msecs_to_jiffies(2);
chan->algo.data = chan;
i2c_set_adapdata(&chan->adapter, chan);
/* Raise SCL and SDA */
riva_gpio_setsda(chan, 1);
riva_gpio_setscl(chan, 1);
udelay(20);
rc = i2c_bit_add_bus(&chan->adapter);
if (rc == 0)
dev_dbg(&chan->par->pdev->dev, "I2C bus %s registered.\n", name);
else {
dev_warn(&chan->par->pdev->dev,
"Failed to register I2C bus %s.\n", name);
chan->par = NULL;
}
return rc;
}
void riva_create_i2c_busses(struct riva_par *par)
{
par->chan[0].par = par;
par->chan[1].par = par;
par->chan[2].par = par;
par->chan[0].ddc_base = 0x36;
par->chan[1].ddc_base = 0x3e;
par->chan[2].ddc_base = 0x50;
riva_setup_i2c_bus(&par->chan[0], "BUS1", I2C_CLASS_HWMON);
riva_setup_i2c_bus(&par->chan[1], "BUS2", 0);
riva_setup_i2c_bus(&par->chan[2], "BUS3", 0);
}
void riva_delete_i2c_busses(struct riva_par *par)
{
int i;
for (i = 0; i < 3; i++) {
if (!par->chan[i].par)
continue;
i2c_del_adapter(&par->chan[i].adapter);
par->chan[i].par = NULL;
}
}
int riva_probe_i2c_connector(struct riva_par *par, int conn, u8 **out_edid)
{
u8 *edid = NULL;
if (par->chan[conn].par)
edid = fb_ddc_read(&par->chan[conn].adapter);
if (out_edid)
*out_edid = edid;
if (!edid)
return 1;
return 0;
}

77
drivers/video/fbdev/riva/rivafb.h Normal file
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#ifndef __RIVAFB_H
#define __RIVAFB_H
#include <linux/fb.h>
#include <video/vga.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include "riva_hw.h"
/* GGI compatibility macros */
#define NUM_SEQ_REGS 0x05
#define NUM_CRT_REGS 0x41
#define NUM_GRC_REGS 0x09
#define NUM_ATC_REGS 0x15
/* I2C */
#define DDC_SCL_READ_MASK (1 << 2)
#define DDC_SCL_WRITE_MASK (1 << 5)
#define DDC_SDA_READ_MASK (1 << 3)
#define DDC_SDA_WRITE_MASK (1 << 4)
/* holds the state of the VGA core and extended Riva hw state from riva_hw.c.
* From KGI originally. */
struct riva_regs {
u8 attr[NUM_ATC_REGS];
u8 crtc[NUM_CRT_REGS];
u8 gra[NUM_GRC_REGS];
u8 seq[NUM_SEQ_REGS];
u8 misc_output;
RIVA_HW_STATE ext;
};
struct riva_par;
struct riva_i2c_chan {
struct riva_par *par;
unsigned long ddc_base;
struct i2c_adapter adapter;
struct i2c_algo_bit_data algo;
};
struct riva_par {
RIVA_HW_INST riva; /* interface to riva_hw.c */
u32 pseudo_palette[16]; /* default palette */
u32 palette[16]; /* for Riva128 */
u8 __iomem *ctrl_base; /* virtual control register base addr */
unsigned dclk_max; /* max DCLK */
struct riva_regs initial_state; /* initial startup video mode */
struct riva_regs current_state;
#ifdef CONFIG_X86
struct vgastate state;
#endif
struct mutex open_lock;
unsigned int ref_count;
unsigned char *EDID;
unsigned int Chipset;
int forceCRTC;
Bool SecondCRTC;
int FlatPanel;
struct pci_dev *pdev;
int cursor_reset;
#ifdef CONFIG_MTRR
struct { int vram; int vram_valid; } mtrr;
#endif
struct riva_i2c_chan chan[3];
};
void riva_common_setup(struct riva_par *);
unsigned long riva_get_memlen(struct riva_par *);
unsigned long riva_get_maxdclk(struct riva_par *);
void riva_delete_i2c_busses(struct riva_par *par);
void riva_create_i2c_busses(struct riva_par *par);
int riva_probe_i2c_connector(struct riva_par *par, int conn, u8 **out_edid);
#endif /* __RIVAFB_H */