mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-10 01:12:45 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
422
drivers/video/fbdev/riva/nv_driver.c
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422
drivers/video/fbdev/riva/nv_driver.c
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@ -0,0 +1,422 @@
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/* $XConsortium: nv_driver.c /main/3 1996/10/28 05:13:37 kaleb $ */
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/*
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* Copyright 1996-1997 David J. McKay
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* DAVID J. MCKAY BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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/*
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* GPL licensing note -- nVidia is allowing a liberal interpretation of
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* the documentation restriction above, to merely say that this nVidia's
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* copyright and disclaimer should be included with all code derived
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* from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
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*/
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/* Hacked together from mga driver and 3.3.4 NVIDIA driver by Jarno Paananen
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<jpaana@s2.org> */
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/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_setup.c,v 1.18 2002/08/0
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5 20:47:06 mvojkovi Exp $ */
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include "nv_type.h"
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#include "rivafb.h"
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#include "nvreg.h"
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#define PFX "rivafb: "
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static inline unsigned char MISCin(struct riva_par *par)
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{
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return (VGA_RD08(par->riva.PVIO, 0x3cc));
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}
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static Bool
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riva_is_connected(struct riva_par *par, Bool second)
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{
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volatile U032 __iomem *PRAMDAC = par->riva.PRAMDAC0;
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U032 reg52C, reg608;
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Bool present;
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if(second) PRAMDAC += 0x800;
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reg52C = NV_RD32(PRAMDAC, 0x052C);
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reg608 = NV_RD32(PRAMDAC, 0x0608);
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NV_WR32(PRAMDAC, 0x0608, reg608 & ~0x00010000);
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NV_WR32(PRAMDAC, 0x052C, reg52C & 0x0000FEEE);
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mdelay(1);
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NV_WR32(PRAMDAC, 0x052C, NV_RD32(PRAMDAC, 0x052C) | 1);
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NV_WR32(par->riva.PRAMDAC0, 0x0610, 0x94050140);
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NV_WR32(par->riva.PRAMDAC0, 0x0608, 0x00001000);
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mdelay(1);
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present = (NV_RD32(PRAMDAC, 0x0608) & (1 << 28)) ? TRUE : FALSE;
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NV_WR32(par->riva.PRAMDAC0, 0x0608,
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NV_RD32(par->riva.PRAMDAC0, 0x0608) & 0x0000EFFF);
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NV_WR32(PRAMDAC, 0x052C, reg52C);
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NV_WR32(PRAMDAC, 0x0608, reg608);
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return present;
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}
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static void
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riva_override_CRTC(struct riva_par *par)
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{
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printk(KERN_INFO PFX
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"Detected CRTC controller %i being used\n",
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par->SecondCRTC ? 1 : 0);
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if(par->forceCRTC != -1) {
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printk(KERN_INFO PFX
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"Forcing usage of CRTC %i\n", par->forceCRTC);
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par->SecondCRTC = par->forceCRTC;
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}
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}
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static void
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riva_is_second(struct riva_par *par)
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{
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if (par->FlatPanel == 1) {
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switch(par->Chipset & 0xffff) {
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case 0x0174:
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case 0x0175:
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case 0x0176:
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case 0x0177:
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case 0x0179:
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case 0x017C:
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case 0x017D:
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case 0x0186:
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case 0x0187:
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/* this might not be a good default for the chips below */
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case 0x0286:
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case 0x028C:
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case 0x0316:
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case 0x0317:
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case 0x031A:
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case 0x031B:
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case 0x031C:
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case 0x031D:
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case 0x031E:
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case 0x031F:
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case 0x0324:
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case 0x0325:
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case 0x0328:
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case 0x0329:
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case 0x032C:
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case 0x032D:
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par->SecondCRTC = TRUE;
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break;
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default:
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par->SecondCRTC = FALSE;
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break;
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}
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} else {
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if(riva_is_connected(par, 0)) {
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if (NV_RD32(par->riva.PRAMDAC0, 0x0000052C) & 0x100)
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par->SecondCRTC = TRUE;
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else
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par->SecondCRTC = FALSE;
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} else
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if (riva_is_connected(par, 1)) {
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if(NV_RD32(par->riva.PRAMDAC0, 0x0000252C) & 0x100)
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par->SecondCRTC = TRUE;
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else
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par->SecondCRTC = FALSE;
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} else /* default */
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par->SecondCRTC = FALSE;
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}
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riva_override_CRTC(par);
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}
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unsigned long riva_get_memlen(struct riva_par *par)
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{
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RIVA_HW_INST *chip = &par->riva;
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unsigned long memlen = 0;
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unsigned int chipset = par->Chipset;
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struct pci_dev* dev;
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u32 amt;
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switch (chip->Architecture) {
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case NV_ARCH_03:
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if (NV_RD32(chip->PFB, 0x00000000) & 0x00000020) {
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if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20)
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&& ((NV_RD32(chip->PMC, 0x00000000)&0x0F)>=0x02)) {
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/*
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* SDRAM 128 ZX.
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*/
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switch (NV_RD32(chip->PFB,0x00000000) & 0x03) {
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case 2:
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memlen = 1024 * 4;
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break;
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case 1:
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memlen = 1024 * 2;
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break;
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default:
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memlen = 1024 * 8;
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break;
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}
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} else {
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memlen = 1024 * 8;
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}
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} else {
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/*
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* SGRAM 128.
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*/
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switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) {
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case 0:
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memlen = 1024 * 8;
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break;
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case 2:
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memlen = 1024 * 4;
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break;
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default:
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memlen = 1024 * 2;
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break;
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}
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}
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break;
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case NV_ARCH_04:
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if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100) {
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memlen = ((NV_RD32(chip->PFB, 0x00000000)>>12)&0x0F) *
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1024 * 2 + 1024 * 2;
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} else {
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switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) {
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case 0:
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memlen = 1024 * 32;
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break;
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case 1:
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memlen = 1024 * 4;
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break;
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case 2:
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memlen = 1024 * 8;
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break;
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case 3:
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default:
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memlen = 1024 * 16;
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break;
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}
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}
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break;
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case NV_ARCH_10:
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case NV_ARCH_20:
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case NV_ARCH_30:
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if(chipset == NV_CHIP_IGEFORCE2) {
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dev = pci_get_bus_and_slot(0, 1);
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pci_read_config_dword(dev, 0x7C, &amt);
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pci_dev_put(dev);
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memlen = (((amt >> 6) & 31) + 1) * 1024;
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} else if (chipset == NV_CHIP_0x01F0) {
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dev = pci_get_bus_and_slot(0, 1);
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pci_read_config_dword(dev, 0x84, &amt);
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pci_dev_put(dev);
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memlen = (((amt >> 4) & 127) + 1) * 1024;
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} else {
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switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) &
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0x000000FF){
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case 0x02:
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memlen = 1024 * 2;
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break;
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case 0x04:
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memlen = 1024 * 4;
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break;
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case 0x08:
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memlen = 1024 * 8;
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break;
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case 0x10:
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memlen = 1024 * 16;
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break;
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case 0x20:
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memlen = 1024 * 32;
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break;
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case 0x40:
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memlen = 1024 * 64;
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break;
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case 0x80:
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memlen = 1024 * 128;
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break;
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default:
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memlen = 1024 * 16;
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break;
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}
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}
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break;
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}
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return memlen;
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}
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unsigned long riva_get_maxdclk(struct riva_par *par)
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{
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RIVA_HW_INST *chip = &par->riva;
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unsigned long dclk = 0;
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switch (chip->Architecture) {
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case NV_ARCH_03:
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if (NV_RD32(chip->PFB, 0x00000000) & 0x00000020) {
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if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20)
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&& ((NV_RD32(chip->PMC,0x00000000)&0x0F) >= 0x02)) {
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/*
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* SDRAM 128 ZX.
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*/
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dclk = 800000;
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} else {
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dclk = 1000000;
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}
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} else {
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/*
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* SGRAM 128.
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*/
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dclk = 1000000;
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}
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break;
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case NV_ARCH_04:
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case NV_ARCH_10:
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case NV_ARCH_20:
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case NV_ARCH_30:
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switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) {
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case 3:
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dclk = 800000;
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break;
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default:
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dclk = 1000000;
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break;
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}
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break;
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}
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return dclk;
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}
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void
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riva_common_setup(struct riva_par *par)
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{
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par->riva.EnableIRQ = 0;
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par->riva.PRAMDAC0 =
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(volatile U032 __iomem *)(par->ctrl_base + 0x00680000);
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par->riva.PFB =
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(volatile U032 __iomem *)(par->ctrl_base + 0x00100000);
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par->riva.PFIFO =
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(volatile U032 __iomem *)(par->ctrl_base + 0x00002000);
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par->riva.PGRAPH =
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(volatile U032 __iomem *)(par->ctrl_base + 0x00400000);
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par->riva.PEXTDEV =
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(volatile U032 __iomem *)(par->ctrl_base + 0x00101000);
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par->riva.PTIMER =
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(volatile U032 __iomem *)(par->ctrl_base + 0x00009000);
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par->riva.PMC =
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(volatile U032 __iomem *)(par->ctrl_base + 0x00000000);
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par->riva.FIFO =
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(volatile U032 __iomem *)(par->ctrl_base + 0x00800000);
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par->riva.PCIO0 = par->ctrl_base + 0x00601000;
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par->riva.PDIO0 = par->ctrl_base + 0x00681000;
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par->riva.PVIO = par->ctrl_base + 0x000C0000;
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par->riva.IO = (MISCin(par) & 0x01) ? 0x3D0 : 0x3B0;
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if (par->FlatPanel == -1) {
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switch (par->Chipset & 0xffff) {
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case 0x0112: /* known laptop chips */
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case 0x0174:
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case 0x0175:
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case 0x0176:
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case 0x0177:
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case 0x0179:
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case 0x017C:
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case 0x017D:
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case 0x0186:
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case 0x0187:
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case 0x0286:
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case 0x028C:
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case 0x0316:
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case 0x0317:
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case 0x031A:
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case 0x031B:
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case 0x031C:
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case 0x031D:
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case 0x031E:
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case 0x031F:
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case 0x0324:
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case 0x0325:
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case 0x0328:
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case 0x0329:
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case 0x032C:
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case 0x032D:
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printk(KERN_INFO PFX
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"On a laptop. Assuming Digital Flat Panel\n");
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par->FlatPanel = 1;
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break;
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default:
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break;
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}
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}
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switch (par->Chipset & 0x0ff0) {
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case 0x0110:
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if (par->Chipset == NV_CHIP_GEFORCE2_GO)
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par->SecondCRTC = TRUE;
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#if defined(__powerpc__)
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if (par->FlatPanel == 1)
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par->SecondCRTC = TRUE;
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#endif
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riva_override_CRTC(par);
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break;
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case 0x0170:
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case 0x0180:
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case 0x01F0:
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case 0x0250:
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case 0x0280:
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case 0x0300:
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case 0x0310:
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case 0x0320:
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case 0x0330:
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case 0x0340:
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riva_is_second(par);
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break;
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default:
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break;
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}
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if (par->SecondCRTC) {
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par->riva.PCIO = par->riva.PCIO0 + 0x2000;
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par->riva.PCRTC = par->riva.PCRTC0 + 0x800;
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par->riva.PRAMDAC = par->riva.PRAMDAC0 + 0x800;
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par->riva.PDIO = par->riva.PDIO0 + 0x2000;
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} else {
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par->riva.PCIO = par->riva.PCIO0;
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par->riva.PCRTC = par->riva.PCRTC0;
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par->riva.PRAMDAC = par->riva.PRAMDAC0;
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par->riva.PDIO = par->riva.PDIO0;
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}
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if (par->FlatPanel == -1) {
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/* Fix me, need x86 DDC code */
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par->FlatPanel = 0;
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}
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par->riva.flatPanel = (par->FlatPanel > 0) ? TRUE : FALSE;
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RivaGetConfig(&par->riva, par->Chipset);
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}
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|
||||
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