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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
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233
include/linux/mfd/arizona/core.h Normal file
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/*
* Arizona MFD internals
*
* Copyright 2014 CirrusLogic, Inc.
* Copyright 2012 Wolfson Microelectronics plc
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _WM_ARIZONA_CORE_H
#define _WM_ARIZONA_CORE_H
#include <linux/interrupt.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/notifier.h>
#include <linux/mfd/arizona/pdata.h>
#define ARIZONA_MAX_CORE_SUPPLIES 2
enum arizona_type {
WM5102 = 1,
WM5110 = 2,
WM8997 = 3,
WM8280 = 4,
WM8998 = 5,
WM1814 = 6,
WM8285 = 7,
WM1840 = 8,
WM1831 = 9,
CS47L24 = 10,
CS47L35 = 11,
CS47L90 = 12,
CS47L91 = 13,
};
#define ARIZONA_IRQ_GP1 0
#define ARIZONA_IRQ_GP2 1
#define ARIZONA_IRQ_GP3 2
#define ARIZONA_IRQ_GP4 3
#define ARIZONA_IRQ_GP5 4
#define ARIZONA_IRQ_GP6 5
#define ARIZONA_IRQ_GP7 6
#define ARIZONA_IRQ_GP8 7
#define ARIZONA_IRQ_GP5_FALL 8
#define ARIZONA_IRQ_GP5_RISE 9
#define ARIZONA_IRQ_JD_FALL 10
#define ARIZONA_IRQ_JD_RISE 11
#define ARIZONA_IRQ_DSP1_RAM_RDY 12
#define ARIZONA_IRQ_DSP2_RAM_RDY 13
#define ARIZONA_IRQ_DSP3_RAM_RDY 14
#define ARIZONA_IRQ_DSP4_RAM_RDY 15
#define ARIZONA_IRQ_DSP_IRQ1 16
#define ARIZONA_IRQ_DSP_IRQ2 17
#define ARIZONA_IRQ_DSP_IRQ3 18
#define ARIZONA_IRQ_DSP_IRQ4 19
#define ARIZONA_IRQ_DSP_IRQ5 20
#define ARIZONA_IRQ_DSP_IRQ6 21
#define ARIZONA_IRQ_DSP_IRQ7 22
#define ARIZONA_IRQ_DSP_IRQ8 23
#define ARIZONA_IRQ_SPK_OVERHEAT_WARN 24
#define ARIZONA_IRQ_SPK_OVERHEAT 25
#define ARIZONA_IRQ_MICDET 26
#define ARIZONA_IRQ_HPDET 27
#define ARIZONA_IRQ_WSEQ_DONE 28
#define ARIZONA_IRQ_DRC2_SIG_DET 29
#define ARIZONA_IRQ_DRC1_SIG_DET 30
#define ARIZONA_IRQ_ASRC2_LOCK 31
#define ARIZONA_IRQ_ASRC1_LOCK 32
#define ARIZONA_IRQ_UNDERCLOCKED 33
#define ARIZONA_IRQ_OVERCLOCKED 34
#define ARIZONA_IRQ_FLL2_LOCK 35
#define ARIZONA_IRQ_FLL1_LOCK 36
#define ARIZONA_IRQ_CLKGEN_ERR 37
#define ARIZONA_IRQ_CLKGEN_ERR_ASYNC 38
#define ARIZONA_IRQ_ASRC_CFG_ERR 39
#define ARIZONA_IRQ_AIF3_ERR 40
#define ARIZONA_IRQ_AIF2_ERR 41
#define ARIZONA_IRQ_AIF1_ERR 42
#define ARIZONA_IRQ_CTRLIF_ERR 43
#define ARIZONA_IRQ_MIXER_DROPPED_SAMPLES 44
#define ARIZONA_IRQ_ASYNC_CLK_ENA_LOW 45
#define ARIZONA_IRQ_SYSCLK_ENA_LOW 46
#define ARIZONA_IRQ_ISRC1_CFG_ERR 47
#define ARIZONA_IRQ_ISRC2_CFG_ERR 48
#define ARIZONA_IRQ_BOOT_DONE 49
#define ARIZONA_IRQ_DCS_DAC_DONE 50
#define ARIZONA_IRQ_DCS_HP_DONE 51
#define ARIZONA_IRQ_FLL2_CLOCK_OK 52
#define ARIZONA_IRQ_FLL1_CLOCK_OK 53
#define ARIZONA_IRQ_MICD_CLAMP_RISE 54
#define ARIZONA_IRQ_MICD_CLAMP_FALL 55
#define ARIZONA_IRQ_HP3R_DONE 56
#define ARIZONA_IRQ_HP3L_DONE 57
#define ARIZONA_IRQ_HP2R_DONE 58
#define ARIZONA_IRQ_HP2L_DONE 59
#define ARIZONA_IRQ_HP1R_DONE 60
#define ARIZONA_IRQ_HP1L_DONE 61
#define ARIZONA_IRQ_ISRC3_CFG_ERR 62
#define ARIZONA_IRQ_DSP_SHARED_WR_COLL 63
#define ARIZONA_IRQ_SPK_SHUTDOWN 64
#define ARIZONA_IRQ_SPK1R_SHORT 65
#define ARIZONA_IRQ_SPK1L_SHORT 66
#define ARIZONA_IRQ_HP3R_SC_NEG 67
#define ARIZONA_IRQ_HP3R_SC_POS 68
#define ARIZONA_IRQ_HP3L_SC_NEG 69
#define ARIZONA_IRQ_HP3L_SC_POS 70
#define ARIZONA_IRQ_HP2R_SC_NEG 71
#define ARIZONA_IRQ_HP2R_SC_POS 72
#define ARIZONA_IRQ_HP2L_SC_NEG 73
#define ARIZONA_IRQ_HP2L_SC_POS 74
#define ARIZONA_IRQ_HP1R_SC_NEG 75
#define ARIZONA_IRQ_HP1R_SC_POS 76
#define ARIZONA_IRQ_HP1L_SC_NEG 77
#define ARIZONA_IRQ_HP1L_SC_POS 78
#define ARIZONA_IRQ_FLL3_LOCK 79
#define ARIZONA_IRQ_FLL3_CLOCK_OK 80
#define MOON_IRQ_FLLAO_CLOCK_OK 81
#define MOON_IRQ_MICDET2 82
#define MOON_IRQ_DSP1_BUS_ERROR 83
#define MOON_IRQ_DSP2_BUS_ERROR 84
#define MOON_IRQ_DSP3_BUS_ERROR 85
#define MOON_IRQ_DSP4_BUS_ERROR 86
#define MOON_IRQ_DSP5_BUS_ERROR 87
#define MOON_IRQ_DSP6_BUS_ERROR 88
#define MOON_IRQ_DSP7_BUS_ERROR 89
#define ARIZONA_NUM_IRQ 90
#define ARIZONA_HP_SHORT_IMPEDANCE 4
struct snd_soc_dapm_context;
struct arizona_extcon_info;
struct arizona {
struct regmap *regmap;
struct regmap *regmap_32bit;
struct device *dev;
enum arizona_type type;
unsigned int rev;
int num_core_supplies;
struct regulator_bulk_data core_supplies[ARIZONA_MAX_CORE_SUPPLIES];
struct regulator *dcvdd;
struct notifier_block dcvdd_notifier;
struct arizona_pdata pdata;
unsigned int external_dcvdd:1;
unsigned int irq_sem;
int irq;
struct irq_domain *virq;
struct regmap_irq_chip_data *aod_irq_chip;
struct regmap_irq_chip_data *irq_chip;
bool hpdet_clamp;
unsigned int hp_ena;
unsigned int hp_impedance;
struct arizona_extcon_info *extcon_info;
struct mutex clk_lock;
int clk32k_ref;
bool ctrlif_error;
struct snd_soc_dapm_context *dapm;
int tdm_width[ARIZONA_MAX_AIF];
int tdm_slots[ARIZONA_MAX_AIF];
uint16_t dac_comp_coeff;
uint8_t dac_comp_enabled;
struct mutex reg_setting_lock;
bool micvdd_regulated;
struct mutex rate_lock;
struct mutex dspclk_ena_lock;
};
int arizona_clk32k_enable(struct arizona *arizona);
int arizona_clk32k_disable(struct arizona *arizona);
int arizona_request_irq(struct arizona *arizona, int irq, const char *name,
irq_handler_t handler, void *data);
void arizona_free_irq(struct arizona *arizona, int irq, void *data);
int arizona_set_irq_wake(struct arizona *arizona, int irq, int on);
int arizona_map_irq(struct arizona *arizona, int irq);
#ifdef CONFIG_MFD_WM5102
int wm5102_patch(struct arizona *arizona);
#else
static inline int wm5102_patch(struct arizona *arizona)
{
return 0;
}
#endif
int florida_patch(struct arizona *arizona);
int wm8997_patch(struct arizona *arizona);
int vegas_patch(struct arizona *arizona);
int clearwater_patch(struct arizona *arizona);
int largo_patch(struct arizona *arizona);
int marley_patch(struct arizona *arizona);
int moon_patch(struct arizona *arizona);
extern int arizona_of_get_named_gpio(struct arizona *arizona, const char *prop,
bool mandatory);
extern int arizona_of_read_u32_array(struct arizona *arizona, const char *prop,
bool mandatory, u32 *data, size_t num);
extern int arizona_of_read_u32(struct arizona *arizona, const char* prop,
bool mandatory, u32 *data);
extern void arizona_florida_mute_analog(struct arizona* arizona,
unsigned int mute);
extern void arizona_florida_clear_input(struct arizona *arizona);
extern int arizona_get_num_micbias(struct arizona *arizona,
unsigned int *micbiases, unsigned int *child_micbiases);
static inline int arizona_of_read_s32(struct arizona *arizona, const char *prop,
bool mandatory, s32 *data)
{
return arizona_of_read_u32(arizona, prop, mandatory, (u32 *)data);
}
#endif

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include/linux/mfd/arizona/gpio.h Normal file
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/*
* GPIO configuration for Arizona devices
*
* Copyright 2013 Wolfson Microelectronics. PLC.
*
* Author: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _ARIZONA_GPIO_H
#define _ARIZONA_GPIO_H
#define ARIZONA_GP_FN_TXLRCLK 0x00
#define ARIZONA_GP_FN_GPIO 0x01
#define ARIZONA_GP_FN_IRQ1 0x02
#define ARIZONA_GP_FN_IRQ2 0x03
#define ARIZONA_GP_FN_OPCLK 0x04
#define ARIZONA_GP_FN_FLL1_OUT 0x05
#define ARIZONA_GP_FN_FLL2_OUT 0x06
#define ARIZONA_GP_FN_PWM1 0x08
#define ARIZONA_GP_FN_PWM2 0x09
#define ARIZONA_GP_FN_SYSCLK_UNDERCLOCKED 0x0A
#define ARIZONA_GP_FN_ASYNCCLK_UNDERCLOCKED 0x0B
#define ARIZONA_GP_FN_FLL1_LOCK 0x0C
#define ARIZONA_GP_FN_FLL2_LOCK 0x0D
#define ARIZONA_GP_FN_FLL1_CLOCK_OK 0x0F
#define ARIZONA_GP_FN_FLL2_CLOCK_OK 0x10
#define ARIZONA_GP_FN_HEADPHONE_DET 0x12
#define ARIZONA_GP_FN_MIC_DET 0x13
#define ARIZONA_GP_FN_WSEQ_STATUS 0x15
#define ARIZONA_GP_FN_CIF_ADDRESS_ERROR 0x16
#define ARIZONA_GP_FN_ASRC1_LOCK 0x1A
#define ARIZONA_GP_FN_ASRC2_LOCK 0x1B
#define ARIZONA_GP_FN_ASRC_CONFIG_ERROR 0x1C
#define ARIZONA_GP_FN_DRC1_SIGNAL_DETECT 0x1D
#define ARIZONA_GP_FN_DRC1_ANTICLIP 0x1E
#define ARIZONA_GP_FN_DRC1_DECAY 0x1F
#define ARIZONA_GP_FN_DRC1_NOISE 0x20
#define ARIZONA_GP_FN_DRC1_QUICK_RELEASE 0x21
#define ARIZONA_GP_FN_DRC2_SIGNAL_DETECT 0x22
#define ARIZONA_GP_FN_DRC2_ANTICLIP 0x23
#define ARIZONA_GP_FN_DRC2_DECAY 0x24
#define ARIZONA_GP_FN_DRC2_NOISE 0x25
#define ARIZONA_GP_FN_DRC2_QUICK_RELEASE 0x26
#define ARIZONA_GP_FN_MIXER_DROPPED_SAMPLE 0x27
#define ARIZONA_GP_FN_AIF1_CONFIG_ERROR 0x28
#define ARIZONA_GP_FN_AIF2_CONFIG_ERROR 0x29
#define ARIZONA_GP_FN_AIF3_CONFIG_ERROR 0x2A
#define ARIZONA_GP_FN_SPK_TEMP_SHUTDOWN 0x2B
#define ARIZONA_GP_FN_SPK_TEMP_WARNING 0x2C
#define ARIZONA_GP_FN_UNDERCLOCKED 0x2D
#define ARIZONA_GP_FN_OVERCLOCKED 0x2E
#define ARIZONA_GP_FN_DSP_IRQ1 0x35
#define ARIZONA_GP_FN_DSP_IRQ2 0x36
#define ARIZONA_GP_FN_ASYNC_OPCLK 0x3D
#define ARIZONA_GP_FN_BOOT_DONE 0x44
#define ARIZONA_GP_FN_DSP1_RAM_READY 0x45
#define ARIZONA_GP_FN_SYSCLK_ENA_STATUS 0x4B
#define ARIZONA_GP_FN_ASYNCCLK_ENA_STATUS 0x4C
#define ARIZONA_GPN_DIR 0x8000 /* GPN_DIR */
#define ARIZONA_GPN_DIR_MASK 0x8000 /* GPN_DIR */
#define ARIZONA_GPN_DIR_SHIFT 15 /* GPN_DIR */
#define ARIZONA_GPN_DIR_WIDTH 1 /* GPN_DIR */
#define ARIZONA_GPN_PU 0x4000 /* GPN_PU */
#define ARIZONA_GPN_PU_MASK 0x4000 /* GPN_PU */
#define ARIZONA_GPN_PU_SHIFT 14 /* GPN_PU */
#define ARIZONA_GPN_PU_WIDTH 1 /* GPN_PU */
#define ARIZONA_GPN_PD 0x2000 /* GPN_PD */
#define ARIZONA_GPN_PD_MASK 0x2000 /* GPN_PD */
#define ARIZONA_GPN_PD_SHIFT 13 /* GPN_PD */
#define ARIZONA_GPN_PD_WIDTH 1 /* GPN_PD */
#define ARIZONA_GPN_LVL 0x0800 /* GPN_LVL */
#define ARIZONA_GPN_LVL_MASK 0x0800 /* GPN_LVL */
#define ARIZONA_GPN_LVL_SHIFT 11 /* GPN_LVL */
#define ARIZONA_GPN_LVL_WIDTH 1 /* GPN_LVL */
#define ARIZONA_GPN_POL 0x0400 /* GPN_POL */
#define ARIZONA_GPN_POL_MASK 0x0400 /* GPN_POL */
#define ARIZONA_GPN_POL_SHIFT 10 /* GPN_POL */
#define ARIZONA_GPN_POL_WIDTH 1 /* GPN_POL */
#define ARIZONA_GPN_OP_CFG 0x0200 /* GPN_OP_CFG */
#define ARIZONA_GPN_OP_CFG_MASK 0x0200 /* GPN_OP_CFG */
#define ARIZONA_GPN_OP_CFG_SHIFT 9 /* GPN_OP_CFG */
#define ARIZONA_GPN_OP_CFG_WIDTH 1 /* GPN_OP_CFG */
#define ARIZONA_GPN_DB 0x0100 /* GPN_DB */
#define ARIZONA_GPN_DB_MASK 0x0100 /* GPN_DB */
#define ARIZONA_GPN_DB_SHIFT 8 /* GPN_DB */
#define ARIZONA_GPN_DB_WIDTH 1 /* GPN_DB */
#define ARIZONA_GPN_FN_MASK 0x007F /* GPN_DB */
#define ARIZONA_GPN_FN_SHIFT 0 /* GPN_DB */
#define ARIZONA_GPN_FN_WIDTH 7 /* GPN_DB */
#endif

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include/linux/mfd/arizona/pdata.h Normal file
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/*
* Platform data for Arizona devices
*
* Copyright 2012 Wolfson Microelectronics. PLC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#ifndef _ARIZONA_PDATA_H
#define _ARIZONA_PDATA_H
#include <dt-bindings/mfd/arizona.h>
#define ARIZONA_GPN_DIR_MASK 0x8000 /* GPN_DIR */
#define ARIZONA_GPN_DIR_SHIFT 15 /* GPN_DIR */
#define ARIZONA_GPN_DIR_WIDTH 1 /* GPN_DIR */
#define ARIZONA_GPN_PU_MASK 0x4000 /* GPN_PU */
#define ARIZONA_GPN_PU_SHIFT 14 /* GPN_PU */
#define ARIZONA_GPN_PU_WIDTH 1 /* GPN_PU */
#define ARIZONA_GPN_PD_MASK 0x2000 /* GPN_PD */
#define ARIZONA_GPN_PD_SHIFT 13 /* GPN_PD */
#define ARIZONA_GPN_PD_WIDTH 1 /* GPN_PD */
#define ARIZONA_GPN_LVL_MASK 0x0800 /* GPN_LVL */
#define ARIZONA_GPN_LVL_SHIFT 11 /* GPN_LVL */
#define ARIZONA_GPN_LVL_WIDTH 1 /* GPN_LVL */
#define ARIZONA_GPN_POL_MASK 0x0400 /* GPN_POL */
#define ARIZONA_GPN_POL_SHIFT 10 /* GPN_POL */
#define ARIZONA_GPN_POL_WIDTH 1 /* GPN_POL */
#define ARIZONA_GPN_OP_CFG_MASK 0x0200 /* GPN_OP_CFG */
#define ARIZONA_GPN_OP_CFG_SHIFT 9 /* GPN_OP_CFG */
#define ARIZONA_GPN_OP_CFG_WIDTH 1 /* GPN_OP_CFG */
#define ARIZONA_GPN_DB_MASK 0x0100 /* GPN_DB */
#define ARIZONA_GPN_DB_SHIFT 8 /* GPN_DB */
#define ARIZONA_GPN_DB_WIDTH 1 /* GPN_DB */
#define ARIZONA_GPN_FN_MASK 0x007F /* GPN_FN - [6:0] */
#define ARIZONA_GPN_FN_SHIFT 0 /* GPN_FN - [6:0] */
#define ARIZONA_GPN_FN_WIDTH 7 /* GPN_FN - [6:0] */
#define CLEARWATER_GPN_LVL 0x8000 /* GPN_LVL */
#define CLEARWATER_GPN_LVL_MASK 0x8000 /* GPN_LVL */
#define CLEARWATER_GPN_LVL_SHIFT 15 /* GPN_LVL */
#define CLEARWATER_GPN_LVL_WIDTH 1 /* GPN_LVL */
#define ARIZONA_MAX_GPIO_REGS 5
#define CLEARWATER_MAX_GPIO_REGS 80
#define CLEARWATER_NUM_GPIOS 40
#define MARLEY_NUM_GPIOS 16
#define MOON_NUM_GPIOS 38
#define ARIZONA_MAX_INPUT 12
#define ARIZONA_MAX_MICBIAS 4
#define ARIZONA_MAX_CHILD_MICBIAS 4
#define WM5102_NUM_MICBIAS 3
#define CLEARWATER_NUM_MICBIAS 4
#define LARGO_NUM_MICBIAS 2
#define MARLEY_NUM_MICBIAS 2
#define MARLEY_NUM_CHILD_MICBIAS 2
#define MOON_NUM_MICBIAS 2
#define MOON_NUM_CHILD_MICBIAS 4
#define ARIZONA_MAX_OUTPUT 6
#define ARIZONA_MAX_AIF 4
#define ARIZONA_HAP_ACT_ERM 0
#define ARIZONA_HAP_ACT_LRA 2
#define ARIZONA_MAX_PDM_SPK 2
/* Treat INT_MAX impedance as open circuit */
#define ARIZONA_HP_Z_OPEN INT_MAX
#define ARIZONA_MAX_DSP 7
struct regulator_init_data;
struct arizona_jd_state;
struct arizona_micbias {
int mV; /** Regulated voltage */
unsigned int ext_cap:1; /** External capacitor fitted */
/** Actively discharge */
unsigned int discharge[ARIZONA_MAX_CHILD_MICBIAS];
unsigned int soft_start:1; /** Disable aggressive startup ramp rate */
unsigned int bypass:1; /** Use bypass mode */
};
struct arizona_micd_config {
unsigned int src;
unsigned int gnd;
unsigned int bias;
bool gpio;
};
struct arizona_micd_range {
int max; /** Ohms */
int key; /** Key to report to input layer */
};
struct arizona_hpd_pins {
unsigned int clamp_pin;
unsigned int impd_pin;
};
struct arizona_pdata {
int reset; /** GPIO controlling /RESET, if any */
int ldoena; /** GPIO controlling LODENA, if any */
/** Regulator configuration for MICVDD */
struct regulator_init_data *micvdd;
/** Regulator configuration for LDO1 */
struct regulator_init_data *ldo1;
/** If a direct 32kHz clock is provided on an MCLK specify it here */
int clk32k_src;
/** Mode for primary IRQ (defaults to active low) */
unsigned int irq_flags;
/* Base GPIO */
int gpio_base;
/** Pin state for GPIO pins
* Defines default pin function and state for each GPIO
*
* 0 = leave at chip default
* values 0x1..0xffff = set to this value
* >0xffff = set to 0
*/
unsigned int gpio_defaults[CLEARWATER_MAX_GPIO_REGS];
/**
* Maximum number of channels clocks will be generated for,
* useful for systems where and I2S bus with multiple data
* lines is mastered.
*/
int max_channels_clocked[ARIZONA_MAX_AIF];
/** Time in milliseconds to keep wake lock during jack detection */
int jd_wake_time;
/** GPIO5 is used for jack detection */
bool jd_gpio5;
/** Internal pull on GPIO5 is disabled when used for jack detection */
bool jd_gpio5_nopull;
/** set to true if jackdet contact opens on insert */
bool jd_invert;
/** If non-zero don't run headphone detection, report this value */
int fixed_hpdet_imp;
/** Use the headphone detect circuit to identify the accessory */
bool hpdet_acc_id;
/** Check for line output with HPDET method */
bool hpdet_acc_id_line;
/** GPIO used for mic isolation with HPDET */
int hpdet_id_gpio;
/** Callback notifying HPDET result */
void (*hpdet_cb)(unsigned int measurement);
/** Callback notifying mic presence */
void (*micd_cb)(bool mic);
/** If non-zero, specifies the maximum impedance in ohms
* that will be considered as a short circuit.
*/
int hpdet_short_circuit_imp;
/**
* Channel to use for headphone detection, valid values are 0 for
* left and 1 for right
*/
int hpdet_channel;
/** Use software comparison to determine mic presence */
bool micd_software_compare;
/** Extra debounce timeout used during initial mic detection (ms) */
int micd_detect_debounce;
/** Extra software debounces during button detection */
int micd_manual_debounce;
/** GPIO for mic detection polarity */
int micd_pol_gpio;
/** Mic detect ramp rate */
int micd_bias_start_time;
/** Mic detect sample rate */
int micd_rate;
/** Mic detect debounce level */
int micd_dbtime;
/** Mic detect timeout (ms) */
int micd_timeout;
/** Force MICBIAS on for mic detect */
bool micd_force_micbias;
/** Force MICBIAS on for initial mic detect only, not button detect */
bool micd_force_micbias_initial;
/** Declare an open circuit as a 4 pole jack */
bool micd_open_circuit_declare;
/** Delay between jack detection and MICBIAS ramp */
int init_mic_delay;
/** Mic detect level parameters */
const struct arizona_micd_range *micd_ranges;
int num_micd_ranges;
/** Mic detect clamp function */
unsigned int micd_clamp_mode;
/** Headset polarity configurations */
struct arizona_micd_config *micd_configs;
int num_micd_configs;
/**
* [clamp_pin, impedance_measurement_pin] for HPL
* of 3.5mm Jack
*/
struct arizona_hpd_pins hpd_l_pins;
/**
* [clamp_pin, impedance_measurement_pin] for HPR
* of 3.5mm Jack
*/
struct arizona_hpd_pins hpd_r_pins;
/** Reference voltage for DMIC inputs */
int dmic_ref[ARIZONA_MAX_INPUT];
/** Clock Source for DMIC's */
int dmic_clksrc[ARIZONA_MAX_INPUT];
/** MICBIAS configurations */
struct arizona_micbias micbias[ARIZONA_MAX_MICBIAS];
/**
* Mode of input structures
* One of the ARIZONA_INMODE_xxx values
* For most codecs the entries are [0]=IN1 [1]=IN2 [2]=IN3 [3]=IN4
* wm8998: [0]=IN1A [1]=IN2A [2]=IN1B [3]=IN2B
* cs47l85, wm8285: [0]=IN1L [1]=IN1R [2]=IN2L [3]=IN2R [4]=IN3L [5]=IN3R
*/
int inmode[ARIZONA_MAX_INPUT];
/** Mode for outputs */
bool out_mono[ARIZONA_MAX_OUTPUT];
/** Provide improved ultrasonic frequency response */
bool ultrasonic_response;
/** PDM speaker mute setting */
unsigned int spk_mute[ARIZONA_MAX_PDM_SPK];
/** PDM speaker format */
unsigned int spk_fmt[ARIZONA_MAX_PDM_SPK];
/** Haptic actuator type */
unsigned int hap_act;
/** GPIO for primary IRQ (used for edge triggered emulation) */
int irq_gpio;
/** General purpose switch control */
unsigned int gpsw;
/** Callback which is called when the trigger phrase is detected */
void (*ez2ctrl_trigger)(void);
/** wm5102t output power */
unsigned int wm5102t_output_pwr;
/** Override the normal jack detection */
const struct arizona_jd_state *custom_jd;
struct wm_adsp_fw_defs *fw_defs[ARIZONA_MAX_DSP];
int num_fw_defs[ARIZONA_MAX_DSP];
/** Some platforms add a series resistor for hpdet to suppress pops */
int hpdet_ext_res;
/** Load firmwares for specific chip revisions */
bool rev_specific_fw;
/**
* Specify an input to mute during headset button presses and jack
* removal: 1 - IN1L, 2 - IN1R, ..., n - IN[n]R
*/
unsigned int hs_mic;
/* If lrclk_adv is set then in dsp-a mode,
fsync is shifted left by half bclk */
int lrclk_adv[ARIZONA_MAX_AIF];
};
#endif

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