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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
commit f6dfaef42e
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241
include/linux/mfd/samsung/core.h Normal file
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/*
* core.h
*
* copyright (c) 2011 Samsung Electronics Co., Ltd
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_SEC_CORE_H
#define __LINUX_MFD_SEC_CORE_H
#define NUM_IRQ_REGS 4
#define SEC_PMIC_REV(iodev) (iodev)->rev_num
enum sec_device_type {
S5M8751X,
S5M8763X,
S5M8767X,
S2MPS11X,
S2MPS13X,
S2MPS15X,
S2MPU03X,
S2MPS16X,
S2MPU05X,
};
/**
* struct sec_pmic_dev - s5m87xx master device for sub-drivers
* @dev: master device of the chip (can be used to access platform data)
* @pdata: pointer to private data used to pass platform data to child
* @i2c: i2c client private data for regulator
* @rtc: i2c client private data for rtc
* @iolock: mutex for serializing io access
* @irqlock: mutex for buslock
* @irq_base: base IRQ number for sec-pmic, required for IRQs
* @irq: generic IRQ number for s5m87xx
* @ono: power onoff IRQ number for s5m87xx
* @irq_masks_cur: currently active value
* @irq_masks_cache: cached hardware value
* @type: indicate which s5m87xx "variant" is used
*/
struct sec_pmic_dev {
struct device *dev;
struct sec_platform_data *pdata;
struct regmap *regmap;
struct regmap *rtc_regmap;
struct i2c_client *i2c;
struct i2c_client *rtc;
struct mutex sec_lock;
struct mutex iolock;
struct mutex irqlock;
struct apm_ops *ops;
int device_type;
int rev_num;
int irq_base;
int irq;
struct regmap_irq_chip_data *irq_data;
int ono;
u8 irq_masks_cur[NUM_IRQ_REGS];
u8 irq_masks_cache[NUM_IRQ_REGS];
int type;
bool wakeup;
bool adc_en;
};
/**
* struct sec_wtsr_smpl - settings for WTSR/SMPL
* @wtsr_en: WTSR Function Enable Control
* @smpl_en: SMPL Function Enable Control
* @wtsr_timer_val: Set the WTSR timer Threshold
* @smpl_timer_val: Set the SMPL timer Threshold
* @check_jigon: if this value is true, do not enable SMPL function when
* JIGONB is low(JIG cable is attached)
*/
struct sec_wtsr_smpl {
bool wtsr_en;
bool smpl_en;
int wtsr_timer_val;
int smpl_timer_val;
bool check_jigon;
};
struct sec_platform_data {
struct sec_regulator_data *regulators;
struct sec_opmode_data *opmode;
int device_type;
int num_regulators;
int irq_base;
int (*cfg_pmic_irq)(void);
int ono;
bool wakeup;
bool buck_voltage_lock;
int buck_gpios[3];
int buck_ds[3];
unsigned int buck2_voltage[8];
bool buck2_gpiodvs;
unsigned int buck3_voltage[8];
bool buck3_gpiodvs;
unsigned int buck4_voltage[8];
bool buck4_gpiodvs;
int buck_set1;
int buck_set2;
int buck_set3;
int buck2_enable;
int buck3_enable;
int buck4_enable;
int buck_default_idx;
int buck2_default_idx;
int buck3_default_idx;
int buck4_default_idx;
int buck_ramp_delay;
int buck2_ramp_delay;
int buck3_ramp_delay;
int buck4_ramp_delay;
int buck6_ramp_delay;
int buck710_ramp_delay;
int buck89_ramp_delay;
int buck15_ramp_delay;
int buck34_ramp_delay;
int buck5_ramp_delay;
int buck16_ramp_delay;
int buck7810_ramp_delay;
int buck9_ramp_delay;
int bb1_ramp_delay;
bool buck2_ramp_enable;
bool buck3_ramp_enable;
bool buck4_ramp_enable;
bool buck6_ramp_enable;
int buck2_init;
int buck3_init;
int buck4_init;
int smpl_warn;
int g3d_pin;
int dvs_pin;
bool g3d_en;
bool cache_data;
bool smpl_warn_en;
bool dvs_en;
bool buck_dvs_on;
bool adc_en;
bool ap_buck_avp_en;
bool sub_buck_avp_en;
unsigned int smpl_warn_vth;
unsigned int smpl_warn_hys;
unsigned int ldo8_7_seq;
unsigned int ldo10_9_seq;
bool ten_bit_address;
/* ---- RTC ---- */
struct sec_wtsr_smpl *wtsr_smpl;
struct rtc_time *init_time;
};
int sec_irq_init(struct sec_pmic_dev *sec_pmic);
void sec_irq_exit(struct sec_pmic_dev *sec_pmic);
int sec_irq_resume(struct sec_pmic_dev *sec_pmic);
extern int sec_reg_read(struct sec_pmic_dev *sec_pmic, u32 reg, void *dest);
extern int sec_bulk_read(struct sec_pmic_dev *sec_pmic, u32 reg, int count, u8 *buf);
extern int sec_reg_write(struct sec_pmic_dev *sec_pmic, u32 reg, u32 value);
extern int sec_bulk_write(struct sec_pmic_dev *sec_pmic, u32 reg, int count, u8 *buf);
extern int sec_reg_update(struct sec_pmic_dev *sec_pmic, u32 reg, u32 val, u32 mask);
extern int sec_rtc_read(struct sec_pmic_dev *sec_pmic, u32 reg, void *dest);
extern int sec_rtc_bulk_read(struct sec_pmic_dev *sec_pmic, u32 reg, int count,
u8 *buf);
extern int sec_rtc_write(struct sec_pmic_dev *sec_pmic, u32 reg, u32 value);
extern int sec_rtc_bulk_write(struct sec_pmic_dev *sec_pmic, u32 reg, int count,
u8 *buf);
extern int sec_rtc_update(struct sec_pmic_dev *sec_pmic, u32 reg, u32 val,
u32 mask);
extern void s2m_init_dvs(void);
extern int s2m_get_dvs_is_enable(void);
extern int s2m_get_dvs_is_on(void);
extern int s2m_set_dvs_pin(bool gpio_val);
extern int s2m_set_g3d_pin(bool gpio_val);
extern void sec_core_lock(void);
extern void sec_core_unlock(void);
void g3d_pin_config_set(void);
/**
* sec_regulator_data - regulator data
* @id: regulator id
* @initdata: regulator init data (contraints, supplies, ...)
*/
struct sec_regulator_data {
int id;
struct regulator_init_data *initdata;
struct device_node *reg_node;
};
/*
* sec_opmode_data - regulator operation mode data
* @id: regulator id
* @mode: regulator operation mode
*/
struct sec_opmode_data {
int id;
unsigned int mode;
};
/*
* samsung regulator operation mode
* SEC_OPMODE_OFF Regulator always OFF
* SEC_OPMODE_ON Regulator always ON
* SEC_OPMODE_LOWPOWER Regulator is on in low-power mode
* SEC_OPMODE_SUSPEND Regulator is changed by PWREN pin
* If PWREN is high, regulator is on
* If PWREN is low, regulator is off
*/
enum sec_opmode {
SEC_OPMODE_OFF,
SEC_OPMODE_SUSPEND,
SEC_OPMODE_LOWPOWER,
SEC_OPMODE_ON,
SEC_OPMODE_MIF = 0x2,
SEC_OPMODE_TCXO = 0x2,
};
#endif /* __LINUX_MFD_SEC_CORE_H */

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include/linux/mfd/samsung/irq.h Normal file
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/* irq.h
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_SEC_IRQ_H
#define __LINUX_MFD_SEC_IRQ_H
enum s2mpu05_irq {
S2MPU05_IRQ_PWRONF,
S2MPU05_IRQ_PWRONR,
S2MPU05_IRQ_JIGONBF,
S2MPU05_IRQ_JIGONBR,
S2MPU05_IRQ_ACOKF,
S2MPU05_IRQ_ACOKR,
S2MPU05_IRQ_PWRON1S,
S2MPU05_IRQ_MRB,
S2MPU05_IRQ_RTC60S,
S2MPU05_IRQ_RTCA1,
S2MPU05_IRQ_RTCA0,
S2MPU05_IRQ_SMPL,
S2MPU05_IRQ_RTC1S,
S2MPU05_IRQ_WTSR,
S2MPU05_IRQ_INT120C,
S2MPU05_IRQ_INT140C,
S2MPU05_IRQ_TSD,
S2MPU05_IRQ_NR,
};
#define S2MPU05_IRQ_PWRONF_MASK (1 << 0)
#define S2MPU05_IRQ_PWRONR_MASK (1 << 1)
#define S2MPU05_IRQ_JIGONBF_MASK (1 << 2)
#define S2MPU05_IRQ_JIGONBR_MASK (1 << 3)
#define S2MPU05_IRQ_ACOKF_MASK (1 << 4)
#define S2MPU05_IRQ_ACOKR_MASK (1 << 5)
#define S2MPU05_IRQ_PWRON1S_MASK (1 << 6)
#define S2MPU05_IRQ_MRB_MASK (1 << 7)
#define S2MPU05_IRQ_RTC60S_MASK (1 << 0)
#define S2MPU05_IRQ_RTCA1_MASK (1 << 1)
#define S2MPU05_IRQ_RTCA0_MASK (1 << 2)
#define S2MPU05_IRQ_SMPL_MASK (1 << 3)
#define S2MPU05_IRQ_RTC1S_MASK (1 << 4)
#define S2MPU05_IRQ_WTSR_MASK (1 << 5)
#define S2MPU05_IRQ_INT120C_MASK (1 << 0)
#define S2MPU05_IRQ_INT140C_MASK (1 << 1)
#define S2MPU05_IRQ_TSD_MASK (1 << 2)
enum s2mpu03_irq {
S2MPU03_IRQ_PWRONF,
S2MPU03_IRQ_PWRONR,
S2MPU03_IRQ_JIGONBF,
S2MPU03_IRQ_JIGONBR,
S2MPU03_IRQ_ACOKF,
S2MPU03_IRQ_ACOKR,
S2MPU03_IRQ_PWRON1S,
S2MPU03_IRQ_MRB,
S2MPU03_IRQ_RTC60S,
S2MPU03_IRQ_RTCA1,
S2MPU03_IRQ_RTCA0,
S2MPU03_IRQ_SMPL,
S2MPU03_IRQ_RTC1S,
S2MPU03_IRQ_WTSR,
S2MPU03_IRQ_INT120C,
S2MPU03_IRQ_INT140C,
S2MPU03_IRQ_TSD,
S2MPU03_IRQ_NR,
};
#define S2MPU03_IRQ_PWRONF_MASK (1 << 0)
#define S2MPU03_IRQ_PWRONR_MASK (1 << 1)
#define S2MPU03_IRQ_JIGONBF_MASK (1 << 2)
#define S2MPU03_IRQ_JIGONBR_MASK (1 << 3)
#define S2MPU03_IRQ_ACOKF_MASK (1 << 4)
#define S2MPU03_IRQ_ACOKR_MASK (1 << 5)
#define S2MPU03_IRQ_PWRON1S_MASK (1 << 6)
#define S2MPU03_IRQ_MRB_MASK (1 << 7)
#define S2MPU03_IRQ_RTC60S_MASK (1 << 0)
#define S2MPU03_IRQ_RTCA1_MASK (1 << 1)
#define S2MPU03_IRQ_RTCA0_MASK (1 << 2)
#define S2MPU03_IRQ_SMPL_MASK (1 << 3)
#define S2MPU03_IRQ_RTC1S_MASK (1 << 4)
#define S2MPU03_IRQ_WTSR_MASK (1 << 5)
#define S2MPU03_IRQ_INT120C_MASK (1 << 0)
#define S2MPU03_IRQ_INT140C_MASK (1 << 1)
#define S2MPU03_IRQ_TSD_MASK (1 << 2)
enum s2mps16_irq {
S2MPS16_IRQ_PWRONF,
S2MPS16_IRQ_PWRONR,
S2MPS16_IRQ_JIGONBF,
S2MPS16_IRQ_JIGONBR,
S2MPS16_IRQ_ACOKBF,
S2MPS16_IRQ_ACOKBR,
S2MPS16_IRQ_PWRON1S,
S2MPS16_IRQ_MRB,
S2MPS16_IRQ_RTC60S,
S2MPS16_IRQ_RTCA1,
S2MPS16_IRQ_RTCA0,
S2MPS16_IRQ_SMPL,
S2MPS16_IRQ_RTC1S,
S2MPS16_IRQ_WTSR,
S2MPS16_IRQ_WRSTB,
S2MPS16_IRQ_INT120C,
S2MPS16_IRQ_INT140C,
S2MPS16_IRQ_TSD,
S2MPS16_IRQ_ADCDONE,
S2MPS16_IRQ_OC0,
S2MPS16_IRQ_OC1,
S2MPS16_IRQ_OC2,
S2MPS16_IRQ_OC3,
S2MPS16_IRQ_OC4,
S2MPS16_IRQ_OC5,
S2MPS16_IRQ_OC6,
S2MPS16_IRQ_OC7,
S2MPS16_IRQ_NR,
};
#define S2MPS16_IRQ_PWRONF_MASK (1 << 0)
#define S2MPS16_IRQ_PWRONR_MASK (1 << 1)
#define S2MPS16_IRQ_JIGONBF_MASK (1 << 2)
#define S2MPS16_IRQ_JIGONBR_MASK (1 << 3)
#define S2MPS16_IRQ_ACOKBF_MASK (1 << 4)
#define S2MPS16_IRQ_ACOKBR_MASK (1 << 5)
#define S2MPS16_IRQ_PWRON1S_MASK (1 << 6)
#define S2MPS16_IRQ_MRB_MASK (1 << 7)
#define S2MPS16_IRQ_RTC60S_MASK (1 << 0)
#define S2MPS16_IRQ_RTCA1_MASK (1 << 1)
#define S2MPS16_IRQ_RTCA0_MASK (1 << 2)
#define S2MPS16_IRQ_SMPL_MASK (1 << 3)
#define S2MPS16_IRQ_RTC1S_MASK (1 << 4)
#define S2MPS16_IRQ_WTSR_MASK (1 << 5)
#define S2MPS16_IRQ_WRSTB_MASK (1 << 7)
#define S2MPS16_IRQ_INT120C_MASK (1 << 0)
#define S2MPS16_IRQ_INT140C_MASK (1 << 1)
#define S2MPS16_IRQ_TSD_MASK (1 << 2)
#define S2MPS16_IRQ_ADCDONE_MASK (1 << 7)
#define S2MPS16_IRQ_OC0_MASK (1 << 0)
#define S2MPS16_IRQ_OC1_MASK (1 << 1)
#define S2MPS16_IRQ_OC2_MASK (1 << 2)
#define S2MPS16_IRQ_OC3_MASK (1 << 3)
#define S2MPS16_IRQ_OC4_MASK (1 << 4)
#define S2MPS16_IRQ_OC5_MASK (1 << 5)
#define S2MPS16_IRQ_OC6_MASK (1 << 6)
#define S2MPS16_IRQ_OC7_MASK (1 << 7)
enum s2mps15_irq {
S2MPS15_IRQ_PWRONF,
S2MPS15_IRQ_PWRONR,
S2MPS15_IRQ_JIGONBF,
S2MPS15_IRQ_JIGONBR,
S2MPS15_IRQ_ACOKBF,
S2MPS15_IRQ_ACOKBR,
S2MPS15_IRQ_PWRON1S,
S2MPS15_IRQ_MRB,
S2MPS15_IRQ_RTC60S,
S2MPS15_IRQ_RTCA1,
S2MPS15_IRQ_RTCA0,
S2MPS15_IRQ_SMPL,
S2MPS15_IRQ_RTC1S,
S2MPS15_IRQ_WTSR,
S2MPS15_IRQ_WRSTB,
S2MPS15_IRQ_INT120C,
S2MPS15_IRQ_INT140C,
S2MPS15_IRQ_TSD,
S2MPS15_IRQ_OC0,
S2MPS15_IRQ_OC1,
S2MPS15_IRQ_OC2,
S2MPS15_IRQ_OC3,
S2MPS15_IRQ_ADCDONE,
S2MPS15_IRQ_NR,
};
#define S2MPS15_IRQ_PWRONF_MASK (1 << 0)
#define S2MPS15_IRQ_PWRONR_MASK (1 << 1)
#define S2MPS15_IRQ_JIGONBF_MASK (1 << 2)
#define S2MPS15_IRQ_JIGONBR_MASK (1 << 3)
#define S2MPS15_IRQ_ACOKBF_MASK (1 << 4)
#define S2MPS15_IRQ_ACOKBR_MASK (1 << 5)
#define S2MPS15_IRQ_PWRON1S_MASK (1 << 6)
#define S2MPS15_IRQ_MRB_MASK (1 << 7)
#define S2MPS15_IRQ_RTC60S_MASK (1 << 0)
#define S2MPS15_IRQ_RTCA1_MASK (1 << 1)
#define S2MPS15_IRQ_RTCA0_MASK (1 << 2)
#define S2MPS15_IRQ_SMPL_MASK (1 << 3)
#define S2MPS15_IRQ_RTC1S_MASK (1 << 4)
#define S2MPS15_IRQ_WTSR_MASK (1 << 5)
#define S2MPS15_IRQ_WRSTB_MASK (1 << 7)
#define S2MPS15_IRQ_INT120C_MASK (1 << 0)
#define S2MPS15_IRQ_INT140C_MASK (1 << 1)
#define S2MPS15_IRQ_TSD_MASK (1 << 2)
#define S2MPS15_IRQ_OC0_MASK (1 << 3)
#define S2MPS15_IRQ_OC1_MASK (1 << 4)
#define S2MPS15_IRQ_OC2_MASK (1 << 5)
#define S2MPS15_IRQ_OC3_MASK (1 << 6)
#define S2MPS15_IRQ_ADCDONE_MASK (1 << 7)
enum s2mps13_irq {
S2MPS13_IRQ_PWRONF,
S2MPS13_IRQ_PWRONR,
S2MPS13_IRQ_JIGONBF,
S2MPS13_IRQ_JIGONBR,
S2MPS13_IRQ_ACOKBF,
S2MPS13_IRQ_ACOKBR,
S2MPS13_IRQ_PWRON1S,
S2MPS13_IRQ_MRB,
S2MPS13_IRQ_RTC60S,
S2MPS13_IRQ_RTCA1,
S2MPS13_IRQ_RTCA0,
S2MPS13_IRQ_SMPL,
S2MPS13_IRQ_RTC1S,
S2MPS13_IRQ_WTSR,
S2MPS13_IRQ_INT120C,
S2MPS13_IRQ_INT140C,
S2MPS13_IRQ_TSD,
S2MPS13_IRQ_NR,
};
#define S2MPS13_IRQ_PWRONF_MASK (1 << 0)
#define S2MPS13_IRQ_PWRONR_MASK (1 << 1)
#define S2MPS13_IRQ_JIGONBF_MASK (1 << 2)
#define S2MPS13_IRQ_JIGONBR_MASK (1 << 3)
#define S2MPS13_IRQ_ACOKBF_MASK (1 << 4)
#define S2MPS13_IRQ_ACOKBR_MASK (1 << 5)
#define S2MPS13_IRQ_PWRON1S_MASK (1 << 6)
#define S2MPS13_IRQ_MRB_MASK (1 << 7)
#define S2MPS13_IRQ_RTC60S_MASK (1 << 0)
#define S2MPS13_IRQ_RTCA1_MASK (1 << 1)
#define S2MPS13_IRQ_RTCA0_MASK (1 << 2)
#define S2MPS13_IRQ_SMPL_MASK (1 << 3)
#define S2MPS13_IRQ_RTC1S_MASK (1 << 4)
#define S2MPS13_IRQ_WTSR_MASK (1 << 5)
#define S2MPS13_IRQ_INT120C_MASK (1 << 0)
#define S2MPS13_IRQ_INT140C_MASK (1 << 1)
#define S2MPS13_IRQ_TSD_MASK (1 << 2)
enum s2mps11_irq {
S2MPS11_IRQ_PWRONF,
S2MPS11_IRQ_PWRONR,
S2MPS11_IRQ_JIGONBF,
S2MPS11_IRQ_JIGONBR,
S2MPS11_IRQ_ACOKBF,
S2MPS11_IRQ_ACOKBR,
S2MPS11_IRQ_PWRON1S,
S2MPS11_IRQ_MRB,
S2MPS11_IRQ_RTC60S,
S2MPS11_IRQ_RTCA1,
S2MPS11_IRQ_RTCA0,
S2MPS11_IRQ_SMPL,
S2MPS11_IRQ_RTC1S,
S2MPS11_IRQ_WTSR,
S2MPS11_IRQ_INT120C,
S2MPS11_IRQ_INT140C,
S2MPS11_IRQ_NR,
};
#define S2MPS11_IRQ_PWRONF_MASK (1 << 0)
#define S2MPS11_IRQ_PWRONR_MASK (1 << 1)
#define S2MPS11_IRQ_JIGONBF_MASK (1 << 2)
#define S2MPS11_IRQ_JIGONBR_MASK (1 << 3)
#define S2MPS11_IRQ_ACOKBF_MASK (1 << 4)
#define S2MPS11_IRQ_ACOKBR_MASK (1 << 5)
#define S2MPS11_IRQ_PWRON1S_MASK (1 << 6)
#define S2MPS11_IRQ_MRB_MASK (1 << 7)
#define S2MPS11_IRQ_RTC60S_MASK (1 << 0)
#define S2MPS11_IRQ_RTCA1_MASK (1 << 1)
#define S2MPS11_IRQ_RTCA0_MASK (1 << 2)
#define S2MPS11_IRQ_SMPL_MASK (1 << 3)
#define S2MPS11_IRQ_RTC1S_MASK (1 << 4)
#define S2MPS11_IRQ_WTSR_MASK (1 << 5)
#define S2MPS11_IRQ_INT120C_MASK (1 << 0)
#define S2MPS11_IRQ_INT140C_MASK (1 << 1)
enum s5m8767_irq {
S5M8767_IRQ_PWRR,
S5M8767_IRQ_PWRF,
S5M8767_IRQ_PWR1S,
S5M8767_IRQ_JIGR,
S5M8767_IRQ_JIGF,
S5M8767_IRQ_LOWBAT2,
S5M8767_IRQ_LOWBAT1,
S5M8767_IRQ_MRB,
S5M8767_IRQ_DVSOK2,
S5M8767_IRQ_DVSOK3,
S5M8767_IRQ_DVSOK4,
S5M8767_IRQ_RTC60S,
S5M8767_IRQ_RTCA1,
S5M8767_IRQ_RTCA2,
S5M8767_IRQ_SMPL,
S5M8767_IRQ_RTC1S,
S5M8767_IRQ_WTSR,
S5M8767_IRQ_NR,
};
#define S5M8767_IRQ_PWRR_MASK (1 << 0)
#define S5M8767_IRQ_PWRF_MASK (1 << 1)
#define S5M8767_IRQ_PWR1S_MASK (1 << 3)
#define S5M8767_IRQ_JIGR_MASK (1 << 4)
#define S5M8767_IRQ_JIGF_MASK (1 << 5)
#define S5M8767_IRQ_LOWBAT2_MASK (1 << 6)
#define S5M8767_IRQ_LOWBAT1_MASK (1 << 7)
#define S5M8767_IRQ_MRB_MASK (1 << 2)
#define S5M8767_IRQ_DVSOK2_MASK (1 << 3)
#define S5M8767_IRQ_DVSOK3_MASK (1 << 4)
#define S5M8767_IRQ_DVSOK4_MASK (1 << 5)
#define S5M8767_IRQ_RTC60S_MASK (1 << 0)
#define S5M8767_IRQ_RTCA1_MASK (1 << 1)
#define S5M8767_IRQ_RTCA2_MASK (1 << 2)
#define S5M8767_IRQ_SMPL_MASK (1 << 3)
#define S5M8767_IRQ_RTC1S_MASK (1 << 4)
#define S5M8767_IRQ_WTSR_MASK (1 << 5)
enum s5m8763_irq {
S5M8763_IRQ_DCINF,
S5M8763_IRQ_DCINR,
S5M8763_IRQ_JIGF,
S5M8763_IRQ_JIGR,
S5M8763_IRQ_PWRONF,
S5M8763_IRQ_PWRONR,
S5M8763_IRQ_WTSREVNT,
S5M8763_IRQ_SMPLEVNT,
S5M8763_IRQ_ALARM1,
S5M8763_IRQ_ALARM0,
S5M8763_IRQ_ONKEY1S,
S5M8763_IRQ_TOPOFFR,
S5M8763_IRQ_DCINOVPR,
S5M8763_IRQ_CHGRSTF,
S5M8763_IRQ_DONER,
S5M8763_IRQ_CHGFAULT,
S5M8763_IRQ_LOBAT1,
S5M8763_IRQ_LOBAT2,
S5M8763_IRQ_NR,
};
#define S5M8763_IRQ_DCINF_MASK (1 << 2)
#define S5M8763_IRQ_DCINR_MASK (1 << 3)
#define S5M8763_IRQ_JIGF_MASK (1 << 4)
#define S5M8763_IRQ_JIGR_MASK (1 << 5)
#define S5M8763_IRQ_PWRONF_MASK (1 << 6)
#define S5M8763_IRQ_PWRONR_MASK (1 << 7)
#define S5M8763_IRQ_WTSREVNT_MASK (1 << 0)
#define S5M8763_IRQ_SMPLEVNT_MASK (1 << 1)
#define S5M8763_IRQ_ALARM1_MASK (1 << 2)
#define S5M8763_IRQ_ALARM0_MASK (1 << 3)
#define S5M8763_IRQ_ONKEY1S_MASK (1 << 0)
#define S5M8763_IRQ_TOPOFFR_MASK (1 << 2)
#define S5M8763_IRQ_DCINOVPR_MASK (1 << 3)
#define S5M8763_IRQ_CHGRSTF_MASK (1 << 4)
#define S5M8763_IRQ_DONER_MASK (1 << 5)
#define S5M8763_IRQ_CHGFAULT_MASK (1 << 7)
#define S5M8763_IRQ_LOBAT1_MASK (1 << 0)
#define S5M8763_IRQ_LOBAT2_MASK (1 << 1)
#define S5M8763_ENRAMP (1 << 4)
#endif /* __LINUX_MFD_SEC_IRQ_H */

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/* rtc-s2mp.h
*
* Copyright (c) 2015 Samsung Electronics Co., Ltd
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_SEC_RTC_H
#define __LINUX_MFD_SEC_RTC_H
/* Slave addr = 0x0C */
/* RTC Registers */
#define S2MP_RTC_REG_CTRL 0x00
#define S2MP_RTC_REG_WTSR_SMPL 0x01
#define S2MP_RTC_REG_UPDATE 0x02
#define S2MP_RTC_REG_CAPSEL 0x03
#define S2MP_RTC_REG_SEC 0x04
#define S2MP_RTC_REG_MIN 0x05
#define S2MP_RTC_REG_HOUR 0x06
#define S2MP_RTC_REG_WEEK 0x07
#define S2MP_RTC_REG_DAY 0x08
#define S2MP_RTC_REG_MON 0x09
#define S2MP_RTC_REG_YEAR 0x0A
#define S2MP_RTC_REG_A0SEC 0x0B
#define S2MP_RTC_REG_A0MIN 0x0C
#define S2MP_RTC_REG_A0HOUR 0x0D
#define S2MP_RTC_REG_A0WEEK 0x0E
#define S2MP_RTC_REG_A0DAY 0x0F
#define S2MP_RTC_REG_A0MON 0x10
#define S2MP_RTC_REG_A0YEAR 0x11
#define S2MP_RTC_REG_A1SEC 0x12
#define S2MP_RTC_REG_A1MIN 0x13
#define S2MP_RTC_REG_A1HOUR 0x14
#define S2MP_RTC_REG_A1WEEK 0x15
#define S2MP_RTC_REG_A1DAY 0x16
#define S2MP_RTC_REG_A1MON 0x17
#define S2MP_RTC_REG_A1YEAR 0x18
/* RTC Control Register */
#define BCD_EN_SHIFT 0
#define BCD_EN_MASK (1 << BCD_EN_SHIFT)
#define MODEL24_SHIFT 1
#define MODEL24_MASK (1 << MODEL24_SHIFT)
/* WTSR and SMPL Register */
#define WTSRT_SHIFT 0
#define SMPLT_SHIFT 3
#define WTSRT_MASK (7 << WTSRT_SHIFT)
#define SMPLT_MASK (7 << SMPLT_SHIFT)
#define WTSR_EN_SHIFT 6
#define SMPL_EN_SHIFT 7
#define WTSR_EN_MASK (1 << WTSR_EN_SHIFT)
#define SMPL_EN_MASK (1 << SMPL_EN_SHIFT)
/* RTC Update Register */
#define RTC_RUDR_SHIFT 0
#define RTC_RUDR_MASK (1 << RTC_RUDR_SHIFT)
#define RTC_AUDR_SHIFT_REV 4
#define RTC_AUDR_MASK_REV (1 << RTC_AUDR_SHIFT_REV)
#define RTC_FREEZE_SHIFT 2
#define RTC_FREEZE_MASK (1 << RTC_FREEZE_SHIFT)
#define RTC_WUDR_SHIFT_REV 1
#define RTC_WUDR_MASK_REV (1 << RTC_WUDR_SHIFT_REV)
/* RTC HOUR Register */
#define HOUR_PM_SHIFT 6
#define HOUR_PM_MASK (1 << HOUR_PM_SHIFT)
/* RTC Alarm Enable */
#define ALARM_ENABLE_SHIFT 7
#define ALARM_ENABLE_MASK (1 << ALARM_ENABLE_SHIFT)
/* PMIC STATUS2 Register */
#define RTCA0E (1<<2)
#define RTCA1E (1<<1)
#define WTSR_TIMER_BITS(v) (((v) << WTSRT_SHIFT) & WTSRT_MASK)
#define SMPL_TIMER_BITS(v) (((v) << SMPLT_SHIFT) & SMPLT_MASK)
/* RTC Counter Register offsets */
enum {
RTC_SEC = 0,
RTC_MIN,
RTC_HOUR,
RTC_WEEKDAY,
RTC_DATE,
RTC_MONTH,
RTC_YEAR,
NR_RTC_CNT_REGS,
};
#endif /* __LINUX_MFD_SEC_RTC_H */

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/* rtc.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_SEC_RTC_H
#define __LINUX_MFD_SEC_RTC_H
enum s2m_rtc_reg {
S2M_RTC_CTRL,
S2M_RTC_WTSR_SMPL,
S2M_RTC_UPDATE,
S2M_CAP_SEL,
S2M_RTC_SEC,
S2M_RTC_MIN,
S2M_RTC_HOUR,
S2M_RTC_WEEK,
S2M_RTC_DAY,
S2M_RTC_MON,
S2M_RTC_YEAR,
S2M_ALARM0_SEC,
S2M_ALARM0_MIN,
S2M_ALARM0_HOUR,
S2M_ALARM0_WEEK,
S2M_ALARM0_DAY,
S2M_ALARM0_MON,
S2M_ALARM0_YEAR,
S2M_ALARM1_SEC,
S2M_ALARM1_MIN,
S2M_ALARM1_HOUR,
S2M_ALARM1_WEEK,
S2M_ALARM1_DAY,
S2M_ALARM1_MON,
S2M_ALARM1_YEAR,
};
#define RTC_I2C_ADDR (0x0C >> 1)
/* RTC Control Register */
#define BCD_EN_SHIFT 0
#define BCD_EN_MASK (1 << BCD_EN_SHIFT)
#define MODEL24_SHIFT 1
#define MODEL24_MASK (1 << MODEL24_SHIFT)
/* WTSR and SMPL Register */
#if defined(CONFIG_REGULATOR_S2MPS11)
#define WTSRT_SHIFT 0
#define SMPLT_SHIFT 2
#define WTSRT_MASK (3 << WTSRT_SHIFT)
#define SMPLT_MASK (3 << SMPLT_SHIFT)
#else
#define WTSRT_SHIFT 0
#define SMPLT_SHIFT 3
#define WTSRT_MASK (7 << WTSRT_SHIFT)
#define SMPLT_MASK (7 << SMPLT_SHIFT)
#endif
#define WTSR_EN_SHIFT 6
#define SMPL_EN_SHIFT 7
#define WTSR_EN_MASK (1 << WTSR_EN_SHIFT)
#define SMPL_EN_MASK (1 << SMPL_EN_SHIFT)
/* RTC Update Register */
#define RTC_RUDR_SHIFT 0
#define RTC_RUDR_MASK (1 << RTC_RUDR_SHIFT)
#define RTC_AUDR_SHIFT 1
#define RTC_AUDR_MASK (1 << RTC_AUDR_SHIFT)
#define RTC_AUDR_SHIFT_REV 4
#define RTC_AUDR_MASK_REV (1 << RTC_AUDR_SHIFT_REV)
#define RTC_FREEZE_SHIFT 2
#define RTC_FREEZE_MASK (1 << RTC_FREEZE_SHIFT)
#define RTC_WUDR_SHIFT 4
#define RTC_WUDR_MASK (1 << RTC_WUDR_SHIFT)
#define RTC_WUDR_SHIFT_REV 1
#define RTC_WUDR_MASK_REV (1 << RTC_WUDR_SHIFT_REV)
/* RTC HOUR Register */
#define HOUR_PM_SHIFT 6
#define HOUR_PM_MASK (1 << HOUR_PM_SHIFT)
/* RTC Alarm Enable */
#define ALARM_ENABLE_SHIFT 7
#define ALARM_ENABLE_MASK (1 << ALARM_ENABLE_SHIFT)
/* PMIC STATUS2 Register */
#define RTCA0E (1<<2)
#define RTCA1E (1<<1)
#define WTSR_TIMER_BITS(v) (((v) << WTSRT_SHIFT) & WTSRT_MASK)
#define SMPL_TIMER_BITS(v) (((v) << SMPLT_SHIFT) & SMPLT_MASK)
/* RTC Counter Register offsets */
enum {
RTC_SEC = 0,
RTC_MIN,
RTC_HOUR,
RTC_WEEKDAY,
RTC_DATE,
RTC_MONTH,
RTC_YEAR,
NR_RTC_CNT_REGS,
};
#endif /* __LINUX_MFD_SEC_RTC_H */

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/*
* Copyright (c) 2013 Samsung Electronics Co., Ltd
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_S2MPA01_H
#define __LINUX_MFD_S2MPA01_H
/* S2MPA01 registers */
enum s2mpa01_reg {
S2MPA01_REG_ID,
S2MPA01_REG_INT1,
S2MPA01_REG_INT2,
S2MPA01_REG_INT3,
S2MPA01_REG_INT1M,
S2MPA01_REG_INT2M,
S2MPA01_REG_INT3M,
S2MPA01_REG_ST1,
S2MPA01_REG_ST2,
S2MPA01_REG_PWRONSRC,
S2MPA01_REG_OFFSRC,
S2MPA01_REG_RTC_BUF,
S2MPA01_REG_CTRL1,
S2MPA01_REG_ETC_TEST,
S2MPA01_REG_RSVD1,
S2MPA01_REG_BU_CHG,
S2MPA01_REG_RAMP1,
S2MPA01_REG_RAMP2,
S2MPA01_REG_LDO_DSCH1,
S2MPA01_REG_LDO_DSCH2,
S2MPA01_REG_LDO_DSCH3,
S2MPA01_REG_LDO_DSCH4,
S2MPA01_REG_OTP_ADRL,
S2MPA01_REG_OTP_ADRH,
S2MPA01_REG_OTP_DATA,
S2MPA01_REG_MON1SEL,
S2MPA01_REG_MON2SEL,
S2MPA01_REG_LEE,
S2MPA01_REG_RSVD2,
S2MPA01_REG_RSVD3,
S2MPA01_REG_RSVD4,
S2MPA01_REG_RSVD5,
S2MPA01_REG_RSVD6,
S2MPA01_REG_TOP_RSVD,
S2MPA01_REG_DVS_SEL,
S2MPA01_REG_DVS_PTR,
S2MPA01_REG_DVS_DATA,
S2MPA01_REG_RSVD_NO,
S2MPA01_REG_UVLO,
S2MPA01_REG_LEE_NO,
S2MPA01_REG_B1CTRL1,
S2MPA01_REG_B1CTRL2,
S2MPA01_REG_B2CTRL1,
S2MPA01_REG_B2CTRL2,
S2MPA01_REG_B3CTRL1,
S2MPA01_REG_B3CTRL2,
S2MPA01_REG_B4CTRL1,
S2MPA01_REG_B4CTRL2,
S2MPA01_REG_B5CTRL1,
S2MPA01_REG_B5CTRL2,
S2MPA01_REG_B5CTRL3,
S2MPA01_REG_B5CTRL4,
S2MPA01_REG_B5CTRL5,
S2MPA01_REG_B5CTRL6,
S2MPA01_REG_B6CTRL1,
S2MPA01_REG_B6CTRL2,
S2MPA01_REG_B7CTRL1,
S2MPA01_REG_B7CTRL2,
S2MPA01_REG_B8CTRL1,
S2MPA01_REG_B8CTRL2,
S2MPA01_REG_B9CTRL1,
S2MPA01_REG_B9CTRL2,
S2MPA01_REG_B10CTRL1,
S2MPA01_REG_B10CTRL2,
S2MPA01_REG_L1CTRL,
S2MPA01_REG_L2CTRL,
S2MPA01_REG_L3CTRL,
S2MPA01_REG_L4CTRL,
S2MPA01_REG_L5CTRL,
S2MPA01_REG_L6CTRL,
S2MPA01_REG_L7CTRL,
S2MPA01_REG_L8CTRL,
S2MPA01_REG_L9CTRL,
S2MPA01_REG_L10CTRL,
S2MPA01_REG_L11CTRL,
S2MPA01_REG_L12CTRL,
S2MPA01_REG_L13CTRL,
S2MPA01_REG_L14CTRL,
S2MPA01_REG_L15CTRL,
S2MPA01_REG_L16CTRL,
S2MPA01_REG_L17CTRL,
S2MPA01_REG_L18CTRL,
S2MPA01_REG_L19CTRL,
S2MPA01_REG_L20CTRL,
S2MPA01_REG_L21CTRL,
S2MPA01_REG_L22CTRL,
S2MPA01_REG_L23CTRL,
S2MPA01_REG_L24CTRL,
S2MPA01_REG_L25CTRL,
S2MPA01_REG_L26CTRL,
S2MPA01_REG_LDO_OVCB1,
S2MPA01_REG_LDO_OVCB2,
S2MPA01_REG_LDO_OVCB3,
S2MPA01_REG_LDO_OVCB4,
};
/* S2MPA01 regulator ids */
enum s2mpa01_regulators {
S2MPA01_LDO1,
S2MPA01_LDO2,
S2MPA01_LDO3,
S2MPA01_LDO4,
S2MPA01_LDO5,
S2MPA01_LDO6,
S2MPA01_LDO7,
S2MPA01_LDO8,
S2MPA01_LDO9,
S2MPA01_LDO10,
S2MPA01_LDO11,
S2MPA01_LDO12,
S2MPA01_LDO13,
S2MPA01_LDO14,
S2MPA01_LDO15,
S2MPA01_LDO16,
S2MPA01_LDO17,
S2MPA01_LDO18,
S2MPA01_LDO19,
S2MPA01_LDO20,
S2MPA01_LDO21,
S2MPA01_LDO22,
S2MPA01_LDO23,
S2MPA01_LDO24,
S2MPA01_LDO25,
S2MPA01_LDO26,
S2MPA01_BUCK1,
S2MPA01_BUCK2,
S2MPA01_BUCK3,
S2MPA01_BUCK4,
S2MPA01_BUCK5,
S2MPA01_BUCK6,
S2MPA01_BUCK7,
S2MPA01_BUCK8,
S2MPA01_BUCK9,
S2MPA01_BUCK10,
S2MPA01_REGULATOR_MAX,
};
#define S2MPA01_LDO_VSEL_MASK 0x3F
#define S2MPA01_BUCK_VSEL_MASK 0xFF
#define S2MPA01_ENABLE_MASK (0x03 << S2MPA01_ENABLE_SHIFT)
#define S2MPA01_ENABLE_SHIFT 0x06
#define S2MPA01_LDO_N_VOLTAGES (S2MPA01_LDO_VSEL_MASK + 1)
#define S2MPA01_BUCK_N_VOLTAGES (S2MPA01_BUCK_VSEL_MASK + 1)
#define S2MPA01_RAMP_DELAY 12500 /* uV/us */
#define S2MPA01_BUCK16_RAMP_SHIFT 4
#define S2MPA01_BUCK24_RAMP_SHIFT 6
#define S2MPA01_BUCK3_RAMP_SHIFT 4
#define S2MPA01_BUCK5_RAMP_SHIFT 6
#define S2MPA01_BUCK7_RAMP_SHIFT 2
#define S2MPA01_BUCK8910_RAMP_SHIFT 0
#define S2MPA01_BUCK1_RAMP_EN_SHIFT 3
#define S2MPA01_BUCK2_RAMP_EN_SHIFT 2
#define S2MPA01_BUCK3_RAMP_EN_SHIFT 1
#define S2MPA01_BUCK4_RAMP_EN_SHIFT 0
#define S2MPA01_PMIC_EN_SHIFT 6
#endif /*__LINUX_MFD_S2MPA01_H */

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/*
* s2mps11.h
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_S2MPS11_H
#define __LINUX_MFD_S2MPS11_H
/* S2MPS11 Revision Number */
enum s2mps11_revision_number {
S2MPS11_REV_82 = 0x82,
S2MPS11_REV_83 = 0x83,
};
/* S2MPS11 registers */
enum s2mps11_reg {
S2MPS11_REG_ID,
S2MPS11_REG_INT1,
S2MPS11_REG_INT2,
S2MPS11_REG_INT3,
S2MPS11_REG_INT1M,
S2MPS11_REG_INT2M,
S2MPS11_REG_INT3M,
S2MPS11_REG_ST1,
S2MPS11_REG_ST2,
S2MPS11_REG_OFFSRC,
S2MPS11_REG_PWRONSRC,
S2MPS11_REG_RTC_CTRL,
S2MPS11_REG_CTRL1,
S2MPS11_REG_ETC_TEST,
S2MPS11_REG_RSVD3,
S2MPS11_REG_BU_CHG,
S2MPS11_REG_RAMP,
S2MPS11_REG_RAMP_BUCK,
S2MPS11_REG_LDO1_8,
S2MPS11_REG_LDO9_16,
S2MPS11_REG_LDO17_24,
S2MPS11_REG_LDO25_32,
S2MPS11_REG_LDO33_38,
S2MPS11_REG_LDO1_8_1,
S2MPS11_REG_LDO9_16_1,
S2MPS11_REG_LDO17_24_1,
S2MPS11_REG_LDO25_32_1,
S2MPS11_REG_LDO33_38_1,
S2MPS11_REG_OTP_ADRL,
S2MPS11_REG_OTP_ADRH,
S2MPS11_REG_OTP_DATA,
S2MPS11_REG_MON1SEL,
S2MPS11_REG_MON2SEL,
S2MPS11_REG_LEE,
S2MPS11_REG_RSVD_NO,
S2MPS11_REG_UVLO,
S2MPS11_REG_LEE_NO,
S2MPS11_REG_B1CTRL1,
S2MPS11_REG_B1CTRL2,
S2MPS11_REG_B2CTRL1,
S2MPS11_REG_B2CTRL2,
S2MPS11_REG_B3CTRL1,
S2MPS11_REG_B3CTRL2,
S2MPS11_REG_B4CTRL1,
S2MPS11_REG_B4CTRL2,
S2MPS11_REG_B5CTRL1,
S2MPS11_REG_BUCK5_SW,
S2MPS11_REG_B5CTRL2,
S2MPS11_REG_B5CTRL3,
S2MPS11_REG_B5CTRL4,
S2MPS11_REG_B5CTRL5,
S2MPS11_REG_B6CTRL1,
S2MPS11_REG_B6CTRL2,
S2MPS11_REG_B7CTRL1,
S2MPS11_REG_B7CTRL2,
S2MPS11_REG_B8CTRL1,
S2MPS11_REG_B8CTRL2,
S2MPS11_REG_B9CTRL1,
S2MPS11_REG_B9CTRL2,
S2MPS11_REG_B10CTRL1,
S2MPS11_REG_B10CTRL2,
S2MPS11_REG_L1CTRL,
S2MPS11_REG_L2CTRL,
S2MPS11_REG_L3CTRL,
S2MPS11_REG_L4CTRL,
S2MPS11_REG_L5CTRL,
S2MPS11_REG_L6CTRL,
S2MPS11_REG_L7CTRL,
S2MPS11_REG_L8CTRL,
S2MPS11_REG_L9CTRL,
S2MPS11_REG_L10CTRL,
S2MPS11_REG_L11CTRL,
S2MPS11_REG_L12CTRL,
S2MPS11_REG_L13CTRL,
S2MPS11_REG_L14CTRL,
S2MPS11_REG_L15CTRL,
S2MPS11_REG_L16CTRL,
S2MPS11_REG_L17CTRL,
S2MPS11_REG_L18CTRL,
S2MPS11_REG_L19CTRL,
S2MPS11_REG_L20CTRL,
S2MPS11_REG_L21CTRL,
S2MPS11_REG_L22CTRL,
S2MPS11_REG_L23CTRL,
S2MPS11_REG_L24CTRL,
S2MPS11_REG_L25CTRL,
S2MPS11_REG_L26CTRL,
S2MPS11_REG_L27CTRL,
S2MPS11_REG_L28CTRL,
S2MPS11_REG_L29CTRL,
S2MPS11_REG_L30CTRL,
S2MPS11_REG_L31CTRL,
S2MPS11_REG_L32CTRL,
S2MPS11_REG_L33CTRL,
S2MPS11_REG_L34CTRL,
S2MPS11_REG_L35CTRL,
S2MPS11_REG_L36CTRL,
S2MPS11_REG_L37CTRL,
S2MPS11_REG_L38CTRL,
};
/* S2MPS11 regulator ids */
enum s2mps11_regulators {
S2MPS11_LDO1,
S2MPS11_LDO2,
S2MPS11_LDO3,
S2MPS11_LDO4,
S2MPS11_LDO5,
S2MPS11_LDO6,
S2MPS11_LDO7,
S2MPS11_LDO8,
S2MPS11_LDO9,
S2MPS11_LDO10,
S2MPS11_LDO11,
S2MPS11_LDO12,
S2MPS11_LDO13,
S2MPS11_LDO14,
S2MPS11_LDO15,
S2MPS11_LDO16,
S2MPS11_LDO17,
S2MPS11_LDO18,
S2MPS11_LDO19,
S2MPS11_LDO20,
S2MPS11_LDO21,
S2MPS11_LDO22,
S2MPS11_LDO23,
S2MPS11_LDO24,
S2MPS11_LDO25,
S2MPS11_LDO26,
S2MPS11_LDO27,
S2MPS11_LDO28,
S2MPS11_LDO29,
S2MPS11_LDO30,
S2MPS11_LDO31,
S2MPS11_LDO32,
S2MPS11_LDO33,
S2MPS11_LDO34,
S2MPS11_LDO35,
S2MPS11_LDO36,
S2MPS11_LDO37,
S2MPS11_LDO38,
S2MPS11_BUCK1,
S2MPS11_BUCK2,
S2MPS11_BUCK3,
S2MPS11_BUCK4,
S2MPS11_BUCK5,
S2MPS11_BUCK6,
S2MPS11_BUCK7,
S2MPS11_BUCK8,
S2MPS11_BUCK9,
S2MPS11_BUCK10,
S2MPS11_AP_EN32KHZ,
S2MPS11_CP_EN32KHZ,
S2MPS11_BT_EN32KHZ,
S2MPS11_REG_MAX,
};
#define S2MPS11_BUCK_MIN1 600000
#define S2MPS11_BUCK_MIN2 750000
#define S2MPS11_BUCK_MIN3 1400000
#define S2MPS11_LDO_MIN1 800000
#define S2MPS11_BUCK_STEP1 6250
#define S2MPS11_BUCK_STEP2 12500
#define S2MPS11_BUCK_STEP3 25000
#define S2MPS11_LDO_STEP2 25000
#define S2MPS11_LDO_STEP1 50000
#define S2MPS11_LDO_VSEL_MASK 0x3F
#define S2MPS11_BUCK_VSEL_MASK 0xFF
#define S2MPS11_ENABLE_MASK (0x03 << S2MPS11_ENABLE_SHIFT)
#define S2MPS11_SW_ENABLE_MASK 0x03
#define S2MPS11_RAMP_DELAY 12000
#define S2MPS11_ENABLE_SHIFT 0x06
#define S2MPS11_LDO_N_VOLTAGES (S2MPS11_LDO_VSEL_MASK + 1)
#define S2MPS11_BUCK_N_VOLTAGES (S2MPS11_BUCK_VSEL_MASK + 1)
#define S2MPS11_PMIC_EN_SHIFT 6
#define S2MPS11_REGULATOR_MAX (S2MPS11_REG_MAX)
#endif /* __LINUX_MFD_S2MPS11_H */

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/*
* s2mps13.h
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_S2MPS13_H
#define __LINUX_MFD_S2MPS13_H
/* S2MPS13 Revision Number */
enum s2mps13_revision_number {
S2MPS13_REV_0 = 0x00,
S2MPS13_REV_1 = 0x01,
};
/* S2MPS13 registers */
enum S2MPS13_reg {
S2MPS13_REG_ID,
S2MPS13_REG_INT1,
S2MPS13_REG_INT2,
S2MPS13_REG_INT3,
S2MPS13_REG_INT1M,
S2MPS13_REG_INT2M,
S2MPS13_REG_INT3M,
S2MPS13_REG_ST1,
S2MPS13_REG_ST2,
S2MPS13_REG_PWRONSRC,
S2MPS13_REG_OFFSRC,
S2MPS13_REG_BU_CHG,
S2MPS13_REG_RTC_BUF,
S2MPS13_REG_CTRL1,
S2MPS13_REG_CTRL2,
S2MPS13_REG_ETC_TEST,
S2MPS13_REG_OTP_ADRL,
S2MPS13_REG_OTP_ADRH,
S2MPS13_REG_OTP_DATA,
S2MPS13_REG_MON1SEL,
S2MPS13_REG_MON2SEL,
S2MPS13_REG_CTRL3,
S2MPS13_REG_ETC_OTP,
S2MPS13_REG_UVLO_OTP,
S2MPS13_REG_LEE,
S2MPS13_REG_B1CTRL1,
S2MPS13_REG_B1CTRL2,
S2MPS13_REG_B2CTRL1,
S2MPS13_REG_B2CTRL2,
S2MPS13_REG_B3CTRL1,
S2MPS13_REG_B3CTRL2,
S2MPS13_REG_B4CTRL1,
S2MPS13_REG_B4CTRL2,
S2MPS13_REG_B5CTRL1,
S2MPS13_REG_B5CTRL2,
S2MPS13_REG_B6CTRL1,
S2MPS13_REG_B6CTRL2,
S2MPS13_REG_B7CTRL1,
S2MPS13_REG_B7CTRL_SW,
S2MPS13_REG_B7CTRL2,
S2MPS13_REG_B8CTRL1,
S2MPS13_REG_B8CTRL2,
S2MPS13_REG_B9CTRL1,
S2MPS13_REG_B9CTRL2,
S2MPS13_REG_B10CTRL1,
S2MPS13_REG_B10CTRL2,
S2MPS13_REG_BB1CTRL1,
S2MPS13_REG_BB1CTRL2,
S2MPS13_REG_BUCK_RAMP1,
S2MPS13_REG_BUCK_RAMP2,
S2MPS13_REG_LDO_DVS1,
S2MPS13_REG_LDO_DVS2,
S2MPS13_REG_LDO_DVS3,
S2MPS13_REG_B6CTRL3,
S2MPS13_REG_L1CTRL,
S2MPS13_REG_L2CTRL,
S2MPS13_REG_L3CTRL,
S2MPS13_REG_L4CTRL,
S2MPS13_REG_L5CTRL,
S2MPS13_REG_L6CTRL,
S2MPS13_REG_L7CTRL,
S2MPS13_REG_L8CTRL,
S2MPS13_REG_L9CTRL,
S2MPS13_REG_L10CTRL,
S2MPS13_REG_L11CTRL,
S2MPS13_REG_L12CTRL,
S2MPS13_REG_L13CTRL,
S2MPS13_REG_L14CTRL,
S2MPS13_REG_L15CTRL,
S2MPS13_REG_L16CTRL,
S2MPS13_REG_L17CTRL,
S2MPS13_REG_L18CTRL,
S2MPS13_REG_L19CTRL,
S2MPS13_REG_L20CTRL,
S2MPS13_REG_L21CTRL,
S2MPS13_REG_L22CTRL,
S2MPS13_REG_L23CTRL,
S2MPS13_REG_L24CTRL,
S2MPS13_REG_L25CTRL,
S2MPS13_REG_L26CTRL,
S2MPS13_REG_L27CTRL,
S2MPS13_REG_L28CTRL,
S2MPS13_REG_L29CTRL,
S2MPS13_REG_L30CTRL,
S2MPS13_REG_L31CTRL,
S2MPS13_REG_L32CTRL,
S2MPS13_REG_L33CTRL,
S2MPS13_REG_L34CTRL,
S2MPS13_REG_L35CTRL,
S2MPS13_REG_L36CTRL,
S2MPS13_REG_L37CTRL,
S2MPS13_REG_L38CTRL,
S2MPS13_REG_L39CTRL,
S2MPS13_REG_L40CTRL,
S2MPS13_REG_LDO_DSCH1,
S2MPS13_REG_LDO_DSCH2,
S2MPS13_REG_LDO_DSCH3,
S2MPS13_REG_LDO_DSCH4,
S2MPS13_REG_LDO_DSCH5,
};
/* S2MPS13 regulator ids */
enum S2MPS13_regulators {
S2MPS13_LDO1,
S2MPS13_LDO2,
S2MPS13_LDO3,
S2MPS13_LDO4,
S2MPS13_LDO5,
S2MPS13_LDO6,
S2MPS13_LDO7,
S2MPS13_LDO8,
S2MPS13_LDO9,
S2MPS13_LDO10,
S2MPS13_LDO11,
S2MPS13_LDO12,
S2MPS13_LDO13,
S2MPS13_LDO14,
S2MPS13_LDO15,
S2MPS13_LDO16,
S2MPS13_LDO17,
S2MPS13_LDO18,
S2MPS13_LDO19,
S2MPS13_LDO20,
S2MPS13_LDO21,
S2MPS13_LDO22,
S2MPS13_LDO23,
S2MPS13_LDO24,
S2MPS13_LDO25,
S2MPS13_LDO26,
S2MPS13_LDO27,
S2MPS13_LDO28,
S2MPS13_LDO29,
S2MPS13_LDO30,
S2MPS13_LDO31,
S2MPS13_LDO32,
S2MPS13_LDO33,
S2MPS13_LDO34,
S2MPS13_LDO35,
S2MPS13_LDO36,
S2MPS13_LDO37,
S2MPS13_LDO38,
S2MPS13_LDO39,
S2MPS13_LDO40,
S2MPS13_BUCK1,
S2MPS13_BUCK2,
S2MPS13_BUCK3,
S2MPS13_BUCK4,
S2MPS13_BUCK5,
S2MPS13_BUCK6,
S2MPS13_BUCK7,
S2MPS13_BUCK7_SW,
S2MPS13_BUCK8,
S2MPS13_BUCK9,
S2MPS13_BUCK10,
S2MPS13_BB1,
S2MPS13_AP_EN32KHZ,
S2MPS13_CP_EN32KHZ,
S2MPS13_BT_EN32KHZ,
S2MPS13_REG_MAX,
};
#define S2M_MODE_STANDBY 0x01
#define S2M_MODE_NORMAL 0x03
#define S2MPS13_BUCK_MIN1 600000
#define S2MPS13_BUCK_MIN1_REV0 600000
#define S2MPS13_BUCK_MIN1_REV1 400000
#define S2MPS13_BUCK_MIN2 2400000
#define S2MPS13_LDO_MIN1_REV0 600000
#define S2MPS13_LDO_MIN1_REV1 400000
#define S2MPS13_LDO_MIN2 800000
#define S2MPS13_BUCK_STEP1 6250
#define S2MPS13_BUCK_STEP2 12500
#define S2MPS13_LDO_STEP1 12500
#define S2MPS13_LDO_STEP2 25000
#define S2MPS13_LDO_STEP3 50000
#define S2MPS13_LDO_VSEL_MASK 0x3F
#define S2MPS13_BUCK_VSEL_MASK 0xFF
#define S2MPS13_ENABLE_MASK (0x03 << S2MPS13_ENABLE_SHIFT)
#define S2MPS13_SW_ENABLE_MASK 0x03
#define S2MPS13_RAMP_DELAY 12000
#define S2MPS13_ENABLE_TIME_LDO 128
#define S2MPS13_ENABLE_TIME_BUCK1 106
#define S2MPS13_ENABLE_TIME_BUCK2 95
#define S2MPS13_ENABLE_TIME_BUCK3 106
#define S2MPS13_ENABLE_TIME_BUCK4 95
#define S2MPS13_ENABLE_TIME_BUCK5 106
#define S2MPS13_ENABLE_TIME_BUCK6 128
#define S2MPS13_ENABLE_TIME_BUCK7 106
#define S2MPS13_ENABLE_TIME_BUCK8 106
#define S2MPS13_ENABLE_TIME_BUCK9 150
#define S2MPS13_ENABLE_TIME_BUCK10 106
#define S2MPS13_ENABLE_TIME_BB 217
#define S2MPS13_ENABLE_SHIFT 0x06
#define S2MPS13_LDO_N_VOLTAGES (S2MPS13_LDO_VSEL_MASK + 1)
#define S2MPS13_BUCK_N_VOLTAGES (S2MPS13_BUCK_VSEL_MASK + 1)
#define S2MPS13_PMIC_EN_SHIFT 6
#define S2MPS13_REGULATOR_MAX (S2MPS13_REG_MAX)
#endif /* __LINUX_MFD_S2MPS13_H */

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/*
* s2mps14.h
*
* Copyright (c) 2014 Samsung Electronics Co., Ltd
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __LINUX_MFD_S2MPS14_H
#define __LINUX_MFD_S2MPS14_H
/* S2MPS14 registers */
enum s2mps14_reg {
S2MPS14_REG_ID,
S2MPS14_REG_INT1,
S2MPS14_REG_INT2,
S2MPS14_REG_INT3,
S2MPS14_REG_INT1M,
S2MPS14_REG_INT2M,
S2MPS14_REG_INT3M,
S2MPS14_REG_ST1,
S2MPS14_REG_ST2,
S2MPS14_REG_PWRONSRC,
S2MPS14_REG_OFFSRC,
S2MPS14_REG_BU_CHG,
S2MPS14_REG_RTCCTRL,
S2MPS14_REG_CTRL1,
S2MPS14_REG_CTRL2,
S2MPS14_REG_RSVD1,
S2MPS14_REG_RSVD2,
S2MPS14_REG_RSVD3,
S2MPS14_REG_RSVD4,
S2MPS14_REG_RSVD5,
S2MPS14_REG_RSVD6,
S2MPS14_REG_CTRL3,
S2MPS14_REG_RSVD7,
S2MPS14_REG_RSVD8,
S2MPS14_REG_WRSTBI,
S2MPS14_REG_B1CTRL1,
S2MPS14_REG_B1CTRL2,
S2MPS14_REG_B2CTRL1,
S2MPS14_REG_B2CTRL2,
S2MPS14_REG_B3CTRL1,
S2MPS14_REG_B3CTRL2,
S2MPS14_REG_B4CTRL1,
S2MPS14_REG_B4CTRL2,
S2MPS14_REG_B5CTRL1,
S2MPS14_REG_B5CTRL2,
S2MPS14_REG_L1CTRL,
S2MPS14_REG_L2CTRL,
S2MPS14_REG_L3CTRL,
S2MPS14_REG_L4CTRL,
S2MPS14_REG_L5CTRL,
S2MPS14_REG_L6CTRL,
S2MPS14_REG_L7CTRL,
S2MPS14_REG_L8CTRL,
S2MPS14_REG_L9CTRL,
S2MPS14_REG_L10CTRL,
S2MPS14_REG_L11CTRL,
S2MPS14_REG_L12CTRL,
S2MPS14_REG_L13CTRL,
S2MPS14_REG_L14CTRL,
S2MPS14_REG_L15CTRL,
S2MPS14_REG_L16CTRL,
S2MPS14_REG_L17CTRL,
S2MPS14_REG_L18CTRL,
S2MPS14_REG_L19CTRL,
S2MPS14_REG_L20CTRL,
S2MPS14_REG_L21CTRL,
S2MPS14_REG_L22CTRL,
S2MPS14_REG_L23CTRL,
S2MPS14_REG_L24CTRL,
S2MPS14_REG_L25CTRL,
S2MPS14_REG_LDODSCH1,
S2MPS14_REG_LDODSCH2,
S2MPS14_REG_LDODSCH3,
};
/* S2MPS14 regulator ids */
enum s2mps14_regulators {
S2MPS14_LDO1,
S2MPS14_LDO2,
S2MPS14_LDO3,
S2MPS14_LDO4,
S2MPS14_LDO5,
S2MPS14_LDO6,
S2MPS14_LDO7,
S2MPS14_LDO8,
S2MPS14_LDO9,
S2MPS14_LDO10,
S2MPS14_LDO11,
S2MPS14_LDO12,
S2MPS14_LDO13,
S2MPS14_LDO14,
S2MPS14_LDO15,
S2MPS14_LDO16,
S2MPS14_LDO17,
S2MPS14_LDO18,
S2MPS14_LDO19,
S2MPS14_LDO20,
S2MPS14_LDO21,
S2MPS14_LDO22,
S2MPS14_LDO23,
S2MPS14_LDO24,
S2MPS14_LDO25,
S2MPS14_BUCK1,
S2MPS14_BUCK2,
S2MPS14_BUCK3,
S2MPS14_BUCK4,
S2MPS14_BUCK5,
S2MPS14_REGULATOR_MAX,
};
/* Regulator constraints for BUCKx */
#define S2MPS14_BUCK1235_START_SEL 0x20
#define S2MPS14_BUCK4_START_SEL 0x40
/*
* Default ramp delay in uv/us. Datasheet says that ramp delay can be
* controlled however it does not specify which register is used for that.
* Let's assume that default value will be set.
*/
#define S2MPS14_BUCK_RAMP_DELAY 12500
#define S2MPS14_LDO_VSEL_MASK 0x3F
#define S2MPS14_BUCK_VSEL_MASK 0xFF
#define S2MPS14_ENABLE_MASK (0x03 << S2MPS14_ENABLE_SHIFT)
#define S2MPS14_ENABLE_SHIFT 6
/* On/Off controlled by PWREN */
#define S2MPS14_ENABLE_SUSPEND (0x01 << S2MPS14_ENABLE_SHIFT)
/* On/Off controlled by LDO10EN or EMMCEN */
#define S2MPS14_ENABLE_EXT_CONTROL (0x00 << S2MPS14_ENABLE_SHIFT)
#define S2MPS14_LDO_N_VOLTAGES (S2MPS14_LDO_VSEL_MASK + 1)
#define S2MPS14_BUCK_N_VOLTAGES (S2MPS14_BUCK_VSEL_MASK + 1)
#endif /* __LINUX_MFD_S2MPS14_H */

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/*
* s2mps15.h
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_S2MPS15_H
#define __LINUX_MFD_S2MPS15_H
/* S2MPS15 Revision Number */
enum s2mps15_revision_number {
S2MPS15_REV_0 = 0x00,
S2MPS15_REV_1 = 0x01,
};
/* S2MPS15 registers */
enum S2MPS15_reg {
S2MPS15_REG_ID,
S2MPS15_REG_INT1,
S2MPS15_REG_INT2,
S2MPS15_REG_INT3,
S2MPS15_REG_INT1M,
S2MPS15_REG_INT2M,
S2MPS15_REG_INT3M,
S2MPS15_REG_ST1,
S2MPS15_REG_ST2,
S2MPS15_REG_PWRONSRC,
S2MPS15_REG_OFFSRC,
S2MPS15_REG_BU_CHG,
S2MPS15_REG_RTC_BUF,
S2MPS15_REG_CTRL1,
S2MPS15_REG_CTRL2,
S2MPS15_REG_ETC_TEST,
S2MPS15_REG_OTP_ADRL,
S2MPS15_REG_OTP_ADRH,
S2MPS15_REG_OTP_DATA,
S2MPS15_REG_MON1SEL,
S2MPS15_REG_MON2SEL,
S2MPS15_REG_CTRL3,
S2MPS15_REG_ETC_OTP,
S2MPS15_REG_UVLO_OTP,
S2MPS15_REG_LEE,
S2MPS15_REG_B1CTRL1,
S2MPS15_REG_B1CTRL2,
S2MPS15_REG_B2CTRL1,
S2MPS15_REG_B2CTRL2,
S2MPS15_REG_B3CTRL1,
S2MPS15_REG_B3CTRL2,
S2MPS15_REG_B4CTRL1,
S2MPS15_REG_B4CTRL2,
S2MPS15_REG_B5CTRL1,
S2MPS15_REG_B5CTRL2,
S2MPS15_REG_B6CTRL1,
S2MPS15_REG_B6CTRL2,
S2MPS15_REG_B7CTRL1,
S2MPS15_REG_B7CTRL2,
S2MPS15_REG_B8CTRL1,
S2MPS15_REG_B8CTRL2,
S2MPS15_REG_B9CTRL1,
S2MPS15_REG_B9CTRL2,
S2MPS15_REG_B10CTRL1,
S2MPS15_REG_B10CTRL2,
S2MPS15_REG_BB1CTRL1,
S2MPS15_REG_BB1CTRL2,
S2MPS15_REG_BUCK_RAMP1,
S2MPS15_REG_LDO_DVS1,
S2MPS15_REG_LDO_DVS2,
S2MPS15_REG_LDO_DVS3,
S2MPS15_REG_LDO_DVS4,
S2MPS15_REG_L1CTRL,
S2MPS15_REG_L2CTRL,
S2MPS15_REG_L3CTRL,
S2MPS15_REG_L4CTRL,
S2MPS15_REG_L5CTRL,
S2MPS15_REG_L6CTRL,
S2MPS15_REG_L7CTRL,
S2MPS15_REG_L8CTRL,
S2MPS15_REG_L9CTRL,
S2MPS15_REG_L10CTRL,
S2MPS15_REG_L11CTRL,
S2MPS15_REG_L12CTRL,
S2MPS15_REG_L13CTRL,
S2MPS15_REG_L14CTRL,
S2MPS15_REG_L15CTRL,
S2MPS15_REG_L16CTRL,
S2MPS15_REG_L17CTRL,
S2MPS15_REG_L18CTRL,
S2MPS15_REG_L19CTRL,
S2MPS15_REG_L20CTRL,
S2MPS15_REG_L21CTRL,
S2MPS15_REG_L22CTRL,
S2MPS15_REG_L23CTRL,
S2MPS15_REG_L24CTRL,
S2MPS15_REG_L25CTRL,
S2MPS15_REG_L26CTRL,
S2MPS15_REG_L27CTRL,
S2MPS15_REG_LDO_DSCH1,
S2MPS15_REG_LDO_DSCH2,
S2MPS15_REG_LDO_DSCH3,
S2MPS15_REG_LDO_DSCH4,
S2MPS15_REG_L26CTRL_REV1 = 0x4C,
S2MPS15_REG_L25CTRL_REV1 = 0x4D,
S2MPS15_REG_LDO_RSVD3 = 0x52,
S2MPS15_REG_B6CTRL3 = 0x57,
S2MPS15_REG_ADC_CTRL1 = 0x5B,
S2MPS15_REG_ADC_CTRL2 = 0x5C,
S2MPS15_REG_ADC_DATA = 0x5D,
};
/* S2MPS15 regulator ids */
enum S2MPS15_regulators {
S2MPS15_LDO1,
S2MPS15_LDO2,
S2MPS15_LDO3,
S2MPS15_LDO4,
S2MPS15_LDO5,
S2MPS15_LDO6,
S2MPS15_LDO7,
S2MPS15_LDO8,
S2MPS15_LDO9,
S2MPS15_LDO10,
S2MPS15_LDO11,
S2MPS15_LDO12,
S2MPS15_LDO13,
S2MPS15_LDO14,
S2MPS15_LDO15,
S2MPS15_LDO16,
S2MPS15_LDO17,
S2MPS15_LDO18,
S2MPS15_LDO19,
S2MPS15_LDO20,
S2MPS15_LDO21,
S2MPS15_LDO22,
S2MPS15_LDO23,
S2MPS15_LDO24,
S2MPS15_LDO25,
S2MPS15_LDO26,
S2MPS15_LDO27,
S2MPS15_BUCK1,
S2MPS15_BUCK2,
S2MPS15_BUCK3,
S2MPS15_BUCK4,
S2MPS15_BUCK5,
S2MPS15_BUCK6,
S2MPS15_BUCK7,
S2MPS15_BUCK8,
S2MPS15_BUCK9,
S2MPS15_BUCK10,
S2MPS15_BB1,
S2MPS15_AP_EN32KHZ,
S2MPS15_CP_EN32KHZ,
S2MPS15_BT_EN32KHZ,
S2MPS15_REG_MAX,
};
#define S2MPS15_BUCK_MIN1 400000
#define S2MPS15_BUCK_MIN1_REV1 300000
#define S2MPS15_BUCK_MIN2 600000
#define S2MPS15_BUCK_MIN3 2600000
#define S2MPS15_LDO_MIN1 400000
#define S2MPS15_LDO_MIN1_REV1 300000
#define S2MPS15_LDO_MIN2 500000
#define S2MPS15_LDO_MIN3 700000
#define S2MPS15_LDO_MIN4 1800000
#define S2MPS15_BUCK_STEP1 6250
#define S2MPS15_BUCK_STEP2 12500
#define S2MPS15_LDO_STEP1 12500
#define S2MPS15_LDO_STEP2 25000
#define S2MPS15_LDO_VSEL_MASK 0x3F
#define S2MPS15_BUCK_VSEL_MASK 0xFF
#define S2MPS15_ENABLE_MASK (0x03 << S2MPS15_ENABLE_SHIFT)
#define S2MPS15_SW_ENABLE_MASK 0x03
#define S2MPS15_RAMP_DELAY 12000
#define S2MPS15_ENABLE_TIME_LDO 115
#define S2MPS15_ENABLE_TIME_BUCK1 65
#define S2MPS15_ENABLE_TIME_BUCK2 65
#define S2MPS15_ENABLE_TIME_BUCK3 65
#define S2MPS15_ENABLE_TIME_BUCK4 65
#define S2MPS15_ENABLE_TIME_BUCK5 65
#define S2MPS15_ENABLE_TIME_BUCK6 65
#define S2MPS15_ENABLE_TIME_BUCK7 75
#define S2MPS15_ENABLE_TIME_BUCK8 90
#define S2MPS15_ENABLE_TIME_BUCK9 115
#define S2MPS15_ENABLE_TIME_BUCK10 75
#define S2MPS15_ENABLE_TIME_BB 171
#define S2MPS15_ENABLE_TIME_LDO_REV1 128
#define S2MPS15_ENABLE_TIME_BUCK1_REV1 95
#define S2MPS15_ENABLE_TIME_BUCK2_REV1 95
#define S2MPS15_ENABLE_TIME_BUCK3_REV1 95
#define S2MPS15_ENABLE_TIME_BUCK4_REV1 95
#define S2MPS15_ENABLE_TIME_BUCK5_REV1 95
#define S2MPS15_ENABLE_TIME_BUCK6_REV1 128
#define S2MPS15_ENABLE_TIME_BUCK7_REV1 95
#define S2MPS15_ENABLE_TIME_BUCK8_REV1 106
#define S2MPS15_ENABLE_TIME_BUCK9_REV1 150
#define S2MPS15_ENABLE_TIME_BUCK10_REV1 95
#define S2MPS15_ENABLE_TIME_BB_REV1 217
#define S2MPS15_ENABLE_SHIFT 0x06
#define S2MPS15_LDO_N_VOLTAGES (S2MPS15_LDO_VSEL_MASK + 1)
#define S2MPS15_BUCK_N_VOLTAGES (S2MPS15_BUCK_VSEL_MASK + 1)
#define S2MPS15_PMIC_EN_SHIFT 6
#define S2MPS15_REGULATOR_MAX (S2MPS15_REG_MAX)
#define S2MPS15_MAX_ADC_CHANNEL 4
#define S2MPS15_BUCK_MAX 11
#define S2MPS15_LDO_START 0x21
#define S2MPS15_LDO_END 0x3b
#define S2MPS15_BUCK_START 0x1
#define S2MPS15_BUCK_END 0xb
#define S2MPS15_ADC_SMP_NUM_MAX 0x3
#define S2MPS15_ADC_DIV_RATIO_MAX 0xf
#define S2MPS15_ADCEN_MASK 0x80
#define S2MPS15_SMP_NUM_MASK 0x30
#define S2MPS15_SMP_NUM_SHIFT 4
#define S2MPS15_DIV_RATIO_MASK 0x0F
#endif /* __LINUX_MFD_S2MPS15_H */

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/*
* s2mps16.h
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_S2MPS16_H
#define __LINUX_MFD_S2MPS16_H
/* S2MPS16 registers */
enum S2MPS16_reg {
S2MPS16_REG_ID,
S2MPS16_REG_INT1,
S2MPS16_REG_INT2,
S2MPS16_REG_INT3,
S2MPS16_REG_INT4,
S2MPS16_REG_INT1M,
S2MPS16_REG_INT2M,
S2MPS16_REG_INT3M,
S2MPS16_REG_INT4M,
S2MPS16_REG_ST1,
S2MPS16_REG_ST2,
S2MPS16_REG_PWRONSRC,
S2MPS16_REG_OFFSRC,
S2MPS16_REG_BU_CHG,
S2MPS16_REG_RTC_BUF,
S2MPS16_REG_CTRL1,
S2MPS16_REG_CTRL2,
S2MPS16_REG_ETC_TEST,
S2MPS16_REG_OTP_ADRL,
S2MPS16_REG_OTP_ADRH,
S2MPS16_REG_OTP_DATA,
S2MPS16_REG_CTRL3,
S2MPS16_REG_ETC_OTP,
S2MPS16_REG_UVLO_OTP,
S2MPS16_REG_CFG1,
S2MPS16_REG_CFG2,
S2MPS16_REG_B1CTRL1,
S2MPS16_REG_B1CTRL2,
S2MPS16_REG_B2CTRL1,
S2MPS16_REG_B2CTRL2,
S2MPS16_REG_B3CTRL1,
S2MPS16_REG_B3CTRL2,
S2MPS16_REG_B4CTRL1,
S2MPS16_REG_B4CTRL2,
S2MPS16_REG_B5CTRL1,
S2MPS16_REG_B5CTRL2,
S2MPS16_REG_B6CTRL1,
S2MPS16_REG_B6CTRL2,
S2MPS16_REG_B6CTRL3,
S2MPS16_REG_B7CTRL1,
S2MPS16_REG_B7CTRL2,
S2MPS16_REG_B8CTRL1,
S2MPS16_REG_B8CTRL2,
S2MPS16_REG_B9CTRL1,
S2MPS16_REG_B9CTRL2, /* Buck10 for CP */
S2MPS16_REG_B11CTRL1 = 0x30,
S2MPS16_REG_B11CTRL2,
S2MPS16_REG_BB1CTRL1,
S2MPS16_REG_BB1CTRL2,
S2MPS16_REG_BUCK_RAMP,
S2MPS16_REG_LDO7_DVS,
S2MPS16_REG_LDO8_DVS,
S2MPS16_REG_LDO9_DVS,
S2MPS16_REG_LDO10_DVS,
S2MPS16_REG_LDO11_DVS,
S2MPS16_REG_L1CTRL,
S2MPS16_REG_L2CTRL,
S2MPS16_REG_L3CTRL,
S2MPS16_REG_L4CTRL,
S2MPS16_REG_L5CTRL,
S2MPS16_REG_L6CTRL,
S2MPS16_REG_L7CTRL,
S2MPS16_REG_L8CTRL,
S2MPS16_REG_L9CTRL,
S2MPS16_REG_L10CTRL,
S2MPS16_REG_L11CTRL,
S2MPS16_REG_L12CTRL,
S2MPS16_REG_L13CTRL, /* LDO14~24 for CP */
S2MPS16_REG_L25CTRL = 0x55,
S2MPS16_REG_L26CTRL,
S2MPS16_REG_L27CTRL,
S2MPS16_REG_L28CTRL,
S2MPS16_REG_L29CTRL,
S2MPS16_REG_L30CTRL,
S2MPS16_REG_L31CTRL,
S2MPS16_REG_L32CTRL,
S2MPS16_REG_L33CTRL,
S2MPS16_REG_L34CTRL,
S2MPS16_REG_L35CTRL,
S2MPS16_REG_L36CTRL,
S2MPS16_REG_L37CTRL,
S2MPS16_REG_L38CTRL,
S2MPS16_REG_LDO_DSCH,
S2MPS16_REG_LDO_CTRL0,
S2MPS16_REG_LDO_CTRL1,
S2MPS16_REG_LDO_CTRL2,
S2MPS16_REG_LDO_OCP,
S2MPS16_REG_IOCONF,
S2MPS16_REG_AVP,
S2MPS16_REG_ADC_CTRL1,
S2MPS16_REG_ADC_CTRL2,
S2MPS16_REG_ADC_DATA,
S2MPS16_REG_TCXO_CTRL,
S2MPS16_REG_SELMIF,
S2MPS16_REG_SQE_CTRL,
};
/* S2MPS16 regulator ids */
enum S2MPS16_regulators {
S2MPS16_LDO1,
S2MPS16_LDO2,
S2MPS16_LDO3,
S2MPS16_LDO4,
S2MPS16_LDO5,
S2MPS16_LDO6,
S2MPS16_LDO7,
S2MPS16_LDO8,
S2MPS16_LDO9,
S2MPS16_LDO10,
S2MPS16_LDO11,
S2MPS16_LDO12,
S2MPS16_LDO13, /* LDO14~24 for CP */
S2MPS16_LDO25,
S2MPS16_LDO26,
S2MPS16_LDO27,
S2MPS16_LDO28,
S2MPS16_LDO29,
S2MPS16_LDO30,
S2MPS16_LDO31,
S2MPS16_LDO32,
S2MPS16_LDO33,
S2MPS16_LDO34,
S2MPS16_LDO35,
S2MPS16_LDO36,
S2MPS16_LDO37,
S2MPS16_LDO38,
S2MPS16_BUCK1,
S2MPS16_BUCK2,
S2MPS16_BUCK3,
S2MPS16_BUCK4,
S2MPS16_BUCK5,
S2MPS16_BUCK6,
S2MPS16_BUCK7,
S2MPS16_BUCK8,
S2MPS16_BUCK9, /* Buck10 for CP */
S2MPS16_BUCK11,
S2MPS16_BB1,
S2MPS16_AP_EN32KHZ,
S2MPS16_CP_EN32KHZ,
S2MPS16_BT_EN32KHZ,
S2MPS16_REG_MAX,
};
#define S2MPS16_BUCK_MIN1 300000
#define S2MPS16_BUCK_MIN2 600000
#define S2MPS16_BUCK_MIN3 2600000
#define S2MPS16_LDO_MIN1 300000
#define S2MPS16_LDO_MIN2 500000
#define S2MPS16_LDO_MIN3 700000
#define S2MPS16_LDO_MIN4 1800000
#define S2MPS16_BUCK_STEP1 6250
#define S2MPS16_BUCK_STEP2 12500
#define S2MPS16_LDO_STEP1 12500
#define S2MPS16_LDO_STEP2 25000
#define S2MPS16_LDO_VSEL_MASK 0x3F
#define S2MPS16_BUCK_VSEL_MASK 0xFF
#define S2MPS16_ENABLE_MASK (0x03 << S2MPS16_ENABLE_SHIFT)
#define S2MPS16_RAMP_DELAY 12000
#define S2MPS16_ENABLE_TIME_LDO 128
#define S2MPS16_ENABLE_TIME_BUCK1 95
#define S2MPS16_ENABLE_TIME_BUCK2 95
#define S2MPS16_ENABLE_TIME_BUCK3 95
#define S2MPS16_ENABLE_TIME_BUCK4 95
#define S2MPS16_ENABLE_TIME_BUCK5 95
#define S2MPS16_ENABLE_TIME_BUCK6 128
#define S2MPS16_ENABLE_TIME_BUCK7 95
#define S2MPS16_ENABLE_TIME_BUCK8 106
#define S2MPS16_ENABLE_TIME_BUCK9 150
#define S2MPS16_ENABLE_TIME_BUCK10 95
#define S2MPS16_ENABLE_TIME_BUCK11 95
#define S2MPS16_ENABLE_TIME_BB 217
#define S2MPS16_ENABLE_SHIFT 0x06
#define S2MPS16_LDO_N_VOLTAGES (S2MPS16_LDO_VSEL_MASK + 1)
#define S2MPS16_BUCK_N_VOLTAGES (S2MPS16_BUCK_VSEL_MASK + 1)
#define S2MPS16_PMIC_EN_SHIFT 6
#define S2MPS16_REGULATOR_MAX (S2MPS16_REG_MAX)
#define S2MPS16_MAX_ADC_CHANNEL 8
#define S2MPS16_BUCK_MAX 11
#define S2MPS16_LDO_START 0x41
#define S2MPS16_LDO_END 0x55
#define S2MPS16_BUCK_START 0x1
#define S2MPS16_BUCK_END 0xc
#define S2MPS16_ADC_SMP_NUM_MAX 0x8
#define S2MPS16_ADC_DIV_RATIO_MAX 0xf
#define S2MPS16_ADCEN_MASK 0x80
#define S2MPS16_SMP_NUM_MASK 0x0F
#define S2MPS16_SMP_NUM_SHIFT 0
#define S2MPS16_DIV_RATIO_MASK 0x0F
#define S2MPS16_BS 15625
#define S2MPS16_BD 31250
#define S2MPS16_BT 46875
#define S2MPS16_BV 15625
#define S2MPS16_BB 15625
#define S2MPS16_L150 1172
#define S2MPS16_L300 2344
#define S2MPS16_L450 3516
#define S2MPS16_L600 4687
#endif /* __LINUX_MFD_S2MPS16_H */

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/*
* s2mpu02.h
*
* Copyright (c) 2014 Samsung Electronics Co., Ltd
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __LINUX_MFD_S2MPU02_H
#define __LINUX_MFD_S2MPU02_H
/* S2MPU02 registers */
enum S2MPU02_reg {
S2MPU02_REG_ID,
S2MPU02_REG_INT1,
S2MPU02_REG_INT2,
S2MPU02_REG_INT3,
S2MPU02_REG_INT1M,
S2MPU02_REG_INT2M,
S2MPU02_REG_INT3M,
S2MPU02_REG_ST1,
S2MPU02_REG_ST2,
S2MPU02_REG_PWRONSRC,
S2MPU02_REG_OFFSRC,
S2MPU02_REG_BU_CHG,
S2MPU02_REG_RTCCTRL,
S2MPU02_REG_PMCTRL1,
S2MPU02_REG_RSVD1,
S2MPU02_REG_RSVD2,
S2MPU02_REG_RSVD3,
S2MPU02_REG_RSVD4,
S2MPU02_REG_RSVD5,
S2MPU02_REG_RSVD6,
S2MPU02_REG_RSVD7,
S2MPU02_REG_WRSTEN,
S2MPU02_REG_RSVD8,
S2MPU02_REG_RSVD9,
S2MPU02_REG_RSVD10,
S2MPU02_REG_B1CTRL1,
S2MPU02_REG_B1CTRL2,
S2MPU02_REG_B2CTRL1,
S2MPU02_REG_B2CTRL2,
S2MPU02_REG_B3CTRL1,
S2MPU02_REG_B3CTRL2,
S2MPU02_REG_B4CTRL1,
S2MPU02_REG_B4CTRL2,
S2MPU02_REG_B5CTRL1,
S2MPU02_REG_B5CTRL2,
S2MPU02_REG_B5CTRL3,
S2MPU02_REG_B5CTRL4,
S2MPU02_REG_B5CTRL5,
S2MPU02_REG_B6CTRL1,
S2MPU02_REG_B6CTRL2,
S2MPU02_REG_B7CTRL1,
S2MPU02_REG_B7CTRL2,
S2MPU02_REG_RAMP1,
S2MPU02_REG_RAMP2,
S2MPU02_REG_L1CTRL,
S2MPU02_REG_L2CTRL1,
S2MPU02_REG_L2CTRL2,
S2MPU02_REG_L2CTRL3,
S2MPU02_REG_L2CTRL4,
S2MPU02_REG_L3CTRL,
S2MPU02_REG_L4CTRL,
S2MPU02_REG_L5CTRL,
S2MPU02_REG_L6CTRL,
S2MPU02_REG_L7CTRL,
S2MPU02_REG_L8CTRL,
S2MPU02_REG_L9CTRL,
S2MPU02_REG_L10CTRL,
S2MPU02_REG_L11CTRL,
S2MPU02_REG_L12CTRL,
S2MPU02_REG_L13CTRL,
S2MPU02_REG_L14CTRL,
S2MPU02_REG_L15CTRL,
S2MPU02_REG_L16CTRL,
S2MPU02_REG_L17CTRL,
S2MPU02_REG_L18CTRL,
S2MPU02_REG_L19CTRL,
S2MPU02_REG_L20CTRL,
S2MPU02_REG_L21CTRL,
S2MPU02_REG_L22CTRL,
S2MPU02_REG_L23CTRL,
S2MPU02_REG_L24CTRL,
S2MPU02_REG_L25CTRL,
S2MPU02_REG_L26CTRL,
S2MPU02_REG_L27CTRL,
S2MPU02_REG_L28CTRL,
S2MPU02_REG_LDODSCH1,
S2MPU02_REG_LDODSCH2,
S2MPU02_REG_LDODSCH3,
S2MPU02_REG_LDODSCH4,
S2MPU02_REG_SELMIF,
S2MPU02_REG_RSVD11,
S2MPU02_REG_RSVD12,
S2MPU02_REG_RSVD13,
S2MPU02_REG_DVSSEL,
S2MPU02_REG_DVSPTR,
S2MPU02_REG_DVSDATA,
};
/* S2MPU02 regulator ids */
enum S2MPU02_regulators {
S2MPU02_LDO1,
S2MPU02_LDO2,
S2MPU02_LDO3,
S2MPU02_LDO4,
S2MPU02_LDO5,
S2MPU02_LDO6,
S2MPU02_LDO7,
S2MPU02_LDO8,
S2MPU02_LDO9,
S2MPU02_LDO10,
S2MPU02_LDO11,
S2MPU02_LDO12,
S2MPU02_LDO13,
S2MPU02_LDO14,
S2MPU02_LDO15,
S2MPU02_LDO16,
S2MPU02_LDO17,
S2MPU02_LDO18,
S2MPU02_LDO19,
S2MPU02_LDO20,
S2MPU02_LDO21,
S2MPU02_LDO22,
S2MPU02_LDO23,
S2MPU02_LDO24,
S2MPU02_LDO25,
S2MPU02_LDO26,
S2MPU02_LDO27,
S2MPU02_LDO28,
S2MPU02_BUCK1,
S2MPU02_BUCK2,
S2MPU02_BUCK3,
S2MPU02_BUCK4,
S2MPU02_BUCK5,
S2MPU02_BUCK6,
S2MPU02_BUCK7,
S2MPU02_REGULATOR_MAX,
};
/* Regulator constraints for BUCKx */
#define S2MPU02_BUCK1234_MIN_600MV 600000
#define S2MPU02_BUCK5_MIN_1081_25MV 1081250
#define S2MPU02_BUCK6_MIN_1700MV 1700000
#define S2MPU02_BUCK7_MIN_900MV 900000
#define S2MPU02_BUCK1234_STEP_6_25MV 6250
#define S2MPU02_BUCK5_STEP_6_25MV 6250
#define S2MPU02_BUCK6_STEP_2_50MV 2500
#define S2MPU02_BUCK7_STEP_6_25MV 6250
#define S2MPU02_BUCK1234_START_SEL 0x00
#define S2MPU02_BUCK5_START_SEL 0x4D
#define S2MPU02_BUCK6_START_SEL 0x28
#define S2MPU02_BUCK7_START_SEL 0x30
#define S2MPU02_BUCK_RAMP_DELAY 12500
/* Regulator constraints for different types of LDOx */
#define S2MPU02_LDO_MIN_900MV 900000
#define S2MPU02_LDO_MIN_1050MV 1050000
#define S2MPU02_LDO_MIN_1600MV 1600000
#define S2MPU02_LDO_STEP_12_5MV 12500
#define S2MPU02_LDO_STEP_25MV 25000
#define S2MPU02_LDO_STEP_50MV 50000
#define S2MPU02_LDO_GROUP1_START_SEL 0x8
#define S2MPU02_LDO_GROUP2_START_SEL 0xA
#define S2MPU02_LDO_GROUP3_START_SEL 0x10
#define S2MPU02_LDO_VSEL_MASK 0x3F
#define S2MPU02_BUCK_VSEL_MASK 0xFF
#define S2MPU02_ENABLE_MASK (0x03 << S2MPU02_ENABLE_SHIFT)
#define S2MPU02_ENABLE_SHIFT 6
/* On/Off controlled by PWREN */
#define S2MPU02_ENABLE_SUSPEND (0x01 << S2MPU02_ENABLE_SHIFT)
#define S2MPU02_DISABLE_SUSPEND (0x11 << S2MPU02_ENABLE_SHIFT)
#define S2MPU02_LDO_N_VOLTAGES (S2MPU02_LDO_VSEL_MASK + 1)
#define S2MPU02_BUCK_N_VOLTAGES (S2MPU02_BUCK_VSEL_MASK + 1)
/* RAMP delay for BUCK1234*/
#define S2MPU02_BUCK1_RAMP_SHIFT 6
#define S2MPU02_BUCK2_RAMP_SHIFT 4
#define S2MPU02_BUCK3_RAMP_SHIFT 2
#define S2MPU02_BUCK4_RAMP_SHIFT 0
#define S2MPU02_BUCK1234_RAMP_MASK 0x3
#endif /* __LINUX_MFD_S2MPU02_H */

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/*
* s2mpu03.h
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_S2MPU03_H
#define __LINUX_MFD_S2MPU03_H
/* S2MPU03 registers */
enum S2MPU03_reg {
S2MPU03_REG_ID,
S2MPU03_REG_INT1,
S2MPU03_REG_INT2,
S2MPU03_REG_INT3,
S2MPU03_REG_INT1M,
S2MPU03_REG_INT2M,
S2MPU03_REG_INT3M,
S2MPU03_REG_ST1,
S2MPU03_REG_ST2,
S2MPU03_REG_PWRONSRC,
S2MPU03_REG_OFFSRC,
S2MPU03_REG_BU_CHG,
S2MPU03_REG_RTC_BUF,
S2MPU03_REG_CTRL1,
S2MPU03_REG_CTRL2,
S2MPU03_REG_ETC_TEST,
S2MPU03_REG_OTP_ADRL,
S2MPU03_REG_OTP_ADRH,
S2MPU03_REG_OTP_DATA,
S2MPU03_REG_MON1SEL,
S2MPU03_REG_MON2SEL,
S2MPU03_REG_CTRL3,
S2MPU03_REG_ETC_OTP,
S2MPU03_REG_UVLO,
S2MPU03_REG_TIME_CTRL1,
S2MPU03_REG_TIME_CTRL2,
S2MPU03_REG_B1CTRL1,
S2MPU03_REG_B1CTRL2,
S2MPU03_REG_B2CTRL1,
S2MPU03_REG_B2CTRL2,
S2MPU03_REG_B3CTRL1,
S2MPU03_REG_B3CTRL2,
S2MPU03_REG_B4CTRL1,
S2MPU03_REG_B4CTRL2,
S2MPU03_REG_B5CTRL1,
S2MPU03_REG_B5CTRL2,
S2MPU03_REG_B6CTRL1,
S2MPU03_REG_B6CTRL2, /* BUCK7 for CP */
S2MPU03_REG_BUCK_RAMP = 0x29,
S2MPU03_REG_LDO_DVS10,
S2MPU03_REG_L1CTRL,
S2MPU03_REG_L2CTRL,
S2MPU03_REG_L3CTRL,
S2MPU03_REG_L4CTRL,
S2MPU03_REG_L5CTRL,
S2MPU03_REG_L6CTRL,
S2MPU03_REG_L7CTRL,
S2MPU03_REG_L8CTRL,
S2MPU03_REG_L9CTRL,
S2MPU03_REG_L10CTRL, /* LDO11~21 for CP */
S2MPU03_REG_L22CTRL = 0x43,
S2MPU03_REG_L23CTRL,
S2MPU03_REG_L24CTRL,
S2MPU03_REG_L25CTRL,
S2MPU03_REG_L26CTRL,
S2MPU03_REG_L27CTRL,
S2MPU03_REG_L28CTRL,
S2MPU03_REG_L29CTRL,
S2MPU03_REG_L30CTRL,
S2MPU03_REG_L31CTRL,
S2MPU03_REG_L32CTRL,
S2MPU03_REG_L33CTRL,
S2MPU03_REG_L34CTRL,
S2MPU03_REG_L35CTRL,
S2MPU03_REG_L36CTRL,
S2MPU03_REG_L37CTRL,
S2MPU03_REG_L38CTRL,
S2MPU03_REG_L39CTRL,
S2MPU03_REG_LDO_DSCH1,
S2MPU03_REG_LDO_DSCH2,
S2MPU03_REG_LDO_DSCH3,
S2MPU03_REG_LDO_DSCH4,
S2MPU03_REG_LDO_DSCH5,
S2MPU03_REG_LDO_BB,
S2MPU03_REG_LDO_EFUSE,
S2MPU03_REG_TCXO_CTRL,
S2MPU03_REG_SELMIF,
};
/* S2MPU03 regulator ids */
enum S2MPU03_regulators {
S2MPU03_LDO1,
S2MPU03_LDO2,
S2MPU03_LDO3,
S2MPU03_LDO4,
S2MPU03_LDO5,
S2MPU03_LDO6,
S2MPU03_LDO7,
S2MPU03_LDO8,
S2MPU03_LDO9,
S2MPU03_LDO10, /* LDO11~21 for CP */
S2MPU03_LDO22,
S2MPU03_LDO23,
S2MPU03_LDO24,
S2MPU03_LDO25,
S2MPU03_LDO26,
S2MPU03_LDO27,
S2MPU03_LDO28,
S2MPU03_LDO29,
S2MPU03_LDO30,
S2MPU03_LDO31,
S2MPU03_LDO32,
S2MPU03_LDO33,
S2MPU03_LDO34,
S2MPU03_LDO35,
S2MPU03_LDO36,
S2MPU03_LDO37,
S2MPU03_LDO38,
S2MPU03_LDO39,
S2MPU03_BUCK1,
S2MPU03_BUCK2,
S2MPU03_BUCK3,
S2MPU03_BUCK4,
S2MPU03_BUCK5,
S2MPU03_BUCK6, /* BUCK7 for CP */
S2MPU03_REG_MAX,
};
#define S2MPU03_BUCK_MIN1 400000
#define S2MPU03_BUCK_MIN2 600000
#define S2MPU03_LDO_MIN1 800000
#define S2MPU03_LDO_MIN2 1800000
#define S2MPU03_LDO_MIN3 400000
#define S2MPU03_BUCK_STEP1 6250
#define S2MPU03_BUCK_STEP2 12500
#define S2MPU03_LDO_STEP1 12500
#define S2MPU03_LDO_STEP2 25000
#define S2MPU03_LDO_VSEL_MASK 0x3F
#define S2MPU03_BUCK_VSEL_MASK 0xFF
#define S2MPU03_ENABLE_MASK (0x03 << S2MPU03_ENABLE_SHIFT)
#define S2MPU03_SW_ENABLE_MASK 0x03
#define S2MPU03_RAMP_DELAY 12000
#define S2MPU03_ENABLE_TIME_LDO 128
#define S2MPU03_ENABLE_TIME_BUCK1 95
#define S2MPU03_ENABLE_TIME_BUCK2 95
#define S2MPU03_ENABLE_TIME_BUCK3 95
#define S2MPU03_ENABLE_TIME_BUCK4 128
#define S2MPU03_ENABLE_TIME_BUCK5 150
#define S2MPU03_ENABLE_TIME_BUCK6 150
#define S2MPU03_ENABLE_SHIFT 0x06
#define S2MPU03_LDO_N_VOLTAGES (S2MPU03_LDO_VSEL_MASK + 1)
#define S2MPU03_BUCK_N_VOLTAGES (S2MPU03_BUCK_VSEL_MASK + 1)
#define S2MPU03_PMIC_EN_SHIFT 6
#define S2MPU03_REGULATOR_MAX (S2MPU03_REG_MAX)
#endif /* __LINUX_MFD_S2MPU03_H */

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/*
* s2mpu05.h
*
* Copyright (c) 2015 Samsung Electronics Co., Ltd
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_S2MPU05_H
#define __LINUX_MFD_S2MPU05_H
/* S2MPU05 registers */
enum S2MPU05_reg {
S2MPU05_REG_ID,
S2MPU05_REG_INT1,
S2MPU05_REG_INT2,
S2MPU05_REG_INT3,
S2MPU05_REG_INT1M,
S2MPU05_REG_INT2M,
S2MPU05_REG_INT3M,
S2MPU05_REG_ST1,
S2MPU05_REG_ST2,
S2MPU05_REG_PWRONSRC,
S2MPU05_REG_OFFSRC,
S2MPU05_REG_BU_CHG,
S2MPU05_REG_RTC_BUF,
S2MPU05_REG_CTRL1,
S2MPU05_REG_CTRL2,
S2MPU05_REG_ETC_TEST,
S2MPU05_REG_OTP_ADRL,
S2MPU05_REG_OTP_ADRH,
S2MPU05_REG_OTP_DATA,
S2MPU05_REG_MON1SEL,
S2MPU05_REG_MON2SEL,
S2MPU05_REG_CTRL3,
S2MPU05_REG_ETC_OTP,
S2MPU05_REG_UVLO,
S2MPU05_REG_TIME_CTRL1,
S2MPU05_REG_TIME_CTRL2,
S2MPU05_REG_B1CTRL1,
S2MPU05_REG_B1CTRL2,
S2MPU05_REG_B2CTRL1,
S2MPU05_REG_B2CTRL2,
S2MPU05_REG_B2CTRL3,
S2MPU05_REG_B2CTRL4,
S2MPU05_REG_B3CTRL1,
S2MPU05_REG_B3CTRL2,
S2MPU05_REG_B3CTRL3,
S2MPU05_REG_B4CTRL1,
S2MPU05_REG_B4CTRL2,
S2MPU05_REG_B5CTRL1,
S2MPU05_REG_B5CTRL2,
S2MPU05_REG_BUCK_RAMP,
S2MPU05_REG_LDO_DVS1,
S2MPU05_REG_LDO_DVS9,
S2MPU05_REG_LDO_DVS10,
S2MPU05_REG_L1CTRL,
S2MPU05_REG_L2CTRL,
S2MPU05_REG_L3CTRL,
S2MPU05_REG_L4CTRL,
S2MPU05_REG_L5CTRL,
S2MPU05_REG_L6CTRL,
S2MPU05_REG_L7CTRL,
S2MPU05_REG_L8CTRL,
S2MPU05_REG_L9CTRL1,
S2MPU05_REG_L9CTRL2,
S2MPU05_REG_L10CTRL, /* LDO11~24 for CP */
S2MPU05_REG_L25CTRL = 0x47,
S2MPU05_REG_L26CTRL,
S2MPU05_REG_L27CTRL,
S2MPU05_REG_L28CTRL,
S2MPU05_REG_L29CTRL,
S2MPU05_REG_L30CTRL,
S2MPU05_REG_L31CTRL,
S2MPU05_REG_L32CTRL,
S2MPU05_REG_L33CTRL,
S2MPU05_REG_L34CTRL,
S2MPU05_REG_L35CTRL,
S2MPU05_REG_LDO_DSCH1,
S2MPU05_REG_LDO_DSCH2,
S2MPU05_REG_LDO_DSCH3,
S2MPU05_REG_LDO_DSCH4,
S2MPU05_REG_LDO_DSCH5,
S2MPU05_REG_LDO_CTRL1,
S2MPU05_REG_LDO_CTRL2,
S2MPU05_REG_TCXO_CTRL,
S2MPU05_REG_SELMIF,
};
/* S2MPU05 regulator ids */
enum S2MPU05_regulators {
S2MPU05_LDO1,
S2MPU05_LDO2,
S2MPU05_LDO3,
S2MPU05_LDO4,
S2MPU05_LDO5,
S2MPU05_LDO6,
S2MPU05_LDO7,
S2MPU05_LDO8,
S2MPU05_LDO9,
S2MPU05_LDO10, /* LDO11~24 for CP */
S2MPU05_LDO25,
S2MPU05_LDO26,
S2MPU05_LDO27,
S2MPU05_LDO28,
S2MPU05_LDO29,
S2MPU05_LDO30,
S2MPU05_LDO31,
S2MPU05_LDO32,
S2MPU05_LDO33,
S2MPU05_LDO34,
S2MPU05_LDO35,
S2MPU05_BUCK1,
S2MPU05_BUCK2,
S2MPU05_BUCK3,
S2MPU05_BUCK4,
S2MPU05_BUCK5,
S2MPU05_REG_MAX,
};
#define S2MPU05_BUCK_MIN1 400000
#define S2MPU05_BUCK_MIN2 600000
#define S2MPU05_LDO_MIN1 800000
#define S2MPU05_LDO_MIN2 1800000
#define S2MPU05_LDO_MIN3 400000
#define S2MPU05_BUCK_STEP1 6250
#define S2MPU05_BUCK_STEP2 12500
#define S2MPU05_LDO_STEP1 12500
#define S2MPU05_LDO_STEP2 25000
#define S2MPU05_LDO_VSEL_MASK 0x3F
#define S2MPU05_BUCK_VSEL_MASK 0xFF
#define S2MPU05_ENABLE_MASK (0x03 << S2MPU05_ENABLE_SHIFT)
#define S2MPU05_SW_ENABLE_MASK 0x03
#define S2MPU05_RAMP_DELAY 12000
#define S2MPU05_ENABLE_TIME_LDO 128
#define S2MPU05_ENABLE_TIME_BUCK1 110
#define S2MPU05_ENABLE_TIME_BUCK2 110
#define S2MPU05_ENABLE_TIME_BUCK3 110
#define S2MPU05_ENABLE_TIME_BUCK4 150
#define S2MPU05_ENABLE_TIME_BUCK5 150
#define S2MPU05_ENABLE_SHIFT 0x06
#define S2MPU05_LDO_N_VOLTAGES (S2MPU05_LDO_VSEL_MASK + 1)
#define S2MPU05_BUCK_N_VOLTAGES (S2MPU05_BUCK_VSEL_MASK + 1)
#define S2MPU05_PMIC_EN_SHIFT 6
#define S2MPU05_REGULATOR_MAX (S2MPU05_REG_MAX)
#endif /* __LINUX_MFD_S2MPU05_H */

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/*
* s2mpu06-private.h - Voltage regulator driver for the s2mpu06
*
* Copyright (C) 2015 Samsung Electrnoics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __LINUX_MFD_S2MPU06_PRIV_H
#define __LINUX_MFD_S2MPU06_PRIV_H
#include <linux/i2c.h>
#define S2MPU06_REG_INVALID (0xff)
#define S2MPU06_IRQSRC_PMIC (1 << 0)
#define S2MPU06_IRQSRC_CHG (1 << 2)
#define S2MPU06_IRQSRC_FG (1 << 4)
#define S2MPU06_IRQSRC_CODEC (1 << 1)
/* Slave addr = 0x66 */
/* PMIC Top-Level Registers */
#define S2MPU06_PMIC_REG_PMICID 0x00
#define S2MPU06_PMIC_REG_INTSRC 0x05
#define S2MPU06_PMIC_REG_INTSRC_MASK 0x06
/* Slave addr = 0xCC */
/* PMIC Registers */
#define S2MPU06_PMIC_REG_INT1 0x00
#define S2MPU06_PMIC_REG_INT2 0x01
#define S2MPU06_PMIC_REG_INT3 0x02
#define S2MPU06_PMIC_REG_INT1M 0x03
#define S2MPU06_PMIC_REG_INT2M 0x04
#define S2MPU06_PMIC_REG_INT3M 0x05
#define S2MPU06_PMIC_REG_STATUS1 0x06
#define S2MPU06_PMIC_REG_STATUS2 0x07
#define S2MPU06_PMIC_REG_PWRONSRC 0x08
#define S2MPU06_PMIC_REG_OFFSRC 0x09
#define S2MPU06_PMIC_REG_RTCBUF 0x0B
#define S2MPU06_PMIC_REG_CTRL1 0x0C
#define S2MPU06_PMIC_REG_CTRL3 0x0E
#define S2MPU06_PMIC_REG_B1CTRL 0x13
#define S2MPU06_PMIC_REG_B1OUT1 0x14
#define S2MPU06_PMIC_REG_B1OUT2 0x15
#define S2MPU06_PMIC_REG_B1OUT3 0x16
#define S2MPU06_PMIC_REG_B2CTRL1 0x17
#define S2MPU06_PMIC_REG_B2CTRL2 0x18
#define S2MPU06_PMIC_REG_B3CTRL1 0x19
#define S2MPU06_PMIC_REG_B3CTRL2 0x1A
#define S2MPU06_PMIC_REG_RAMP 0x1B
#define S2MPU06_PMIC_REG_BSTCTRL 0x1C
#define S2MPU06_PMIC_REG_L6DVS 0x1D
#define S2MPU06_PMIC_REG_L1CTRL1 0x1E
#define S2MPU06_PMIC_REG_L1CTRL2 0x1F
#define S2MPU06_PMIC_REG_L2CTRL 0x20
#define S2MPU06_PMIC_REG_L3CTRL 0x21
#define S2MPU06_PMIC_REG_L4CTRL 0x22
#define S2MPU06_PMIC_REG_L5CTRL 0x23
#define S2MPU06_PMIC_REG_L6CTRL1 0x24
#define S2MPU06_PMIC_REG_L6CTRL2 0x25
#define S2MPU06_PMIC_REG_L7CTRL 0x26
#define S2MPU06_PMIC_REG_L8CTRL 0x27
#define S2MPU06_PMIC_REG_L9CTRL 0x28
#define S2MPU06_PMIC_REG_L10CTRL 0x29
#define S2MPU06_PMIC_REG_L11CTRL 0x2A
#define S2MPU06_PMIC_REG_L12CTRL 0x2B
#define S2MPU06_PMIC_REG_L13CTRL 0x2C
#define S2MPU06_PMIC_REG_L14CTRL 0x2D
#define S2MPU06_PMIC_REG_L15CTRL 0x2E
#define S2MPU06_PMIC_REG_L16CTRL 0x2F
#define S2MPU06_PMIC_REG_L17CTRL 0x30
#define S2MPU06_PMIC_REG_L18CTRL 0x31
#define S2MPU06_PMIC_REG_L19CTRL 0x32
#define S2MPU06_PMIC_REG_L20CTRL 0x33
#define S2MPU06_PMIC_REG_L21CTRL 0x34
#define S2MPU06_PMIC_REG_L22CTRL 0x35
#define S2MPU06_PMIC_REG_L23CTRL 0x36
#define S2MPU06_PMIC_REG_L24CTRL 0x37
#define S2MPU06_PMIC_REG_LDO_DSCH1 0x38
#define S2MPU06_PMIC_REG_LDO_DSCH2 0x39
#define S2MPU06_PMIC_REG_LDO_DSCH3 0x3A
#define S2MPU06_PMIC_REG_EXT_CTRL 0xFF
/* Charger INT register */
#define S2MPU06_CHG_REG_INT1 0x00
#define S2MPU06_CHG_REG_INT2 0x01
#define S2MPU06_CHG_REG_INT3 0x02
#define S2MPU06_CHG_REG_PMIC_INT 0x03
#define S2MPU06_CHG_REG_INT1M 0x04
#define S2MPU06_CHG_REG_INT2M 0x05
#define S2MPU06_CHG_REG_INT3M 0x06
#define S2MPU06_CHG_REG_PMIC_INTM 0x07
/* FG INT register */
#define S2MPU06_FG_REG_IRQ_INT 0x02
#define S2MPU06_FG_REG_IRQ_INTM 0x03
/* S2MPU06regulator ids */
enum S2MPU06_regulators {
S2MPU06_LDO1,
S2MPU06_LDO2,
S2MPU06_LDO3,
S2MPU06_LDO4,
S2MPU06_LDO5,
S2MPU06_LDO6,
S2MPU06_LDO7,
S2MPU06_LDO8,
S2MPU06_LDO13,
S2MPU06_LDO14,
S2MPU06_LDO15,
S2MPU06_LDO16,
S2MPU06_LDO17,
S2MPU06_LDO18,
S2MPU06_LDO19,
S2MPU06_LDO20,
S2MPU06_LDO21,
S2MPU06_LDO22,
S2MPU06_LDO23,
S2MPU06_LDO24,
S2MPU06_BUCK1,
S2MPU06_BUCK2,
S2MPU06_BUCK3,
S2MPU06_REG_MAX,
};
#define S2MPU06_BUCK_MIN1 400000
#define S2MPU06_BUCK_MIN2 800000
#define S2MPU06_LDO_MIN1 800000
#define S2MPU06_LDO_MIN2 1800000
#define S2MPU06_LDO_MIN3 400000
#define S2MPU06_BUCK_STEP1 6250
#define S2MPU06_BUCK_STEP2 25000
#define S2MPU06_LDO_STEP1 12500
#define S2MPU06_LDO_STEP2 25000
#define S2MPU06_LDO_VSEL_MASK 0x3F
#define S2MPU06_BUCK_VSEL_MASK 0xFF
#define S2MPU06_ENABLE_MASK (0x03 << S2MPU06_ENABLE_SHIFT)
#define S2MPU06_SW_ENABLE_MASK 0x03
#define S2MPU06_RAMP_DELAY 12000
#define S2MPU06_ENABLE_TIME_LDO 128
#define S2MPU06_ENABLE_TIME_BUCK1 95
#define S2MPU06_ENABLE_TIME_BUCK2 106
#define S2MPU06_ENABLE_TIME_BUCK3 150
#define S2MPU06_ENABLE_SHIFT 0x06
#define S2MPU06_LDO_N_VOLTAGES (S2MPU06_LDO_VSEL_MASK + 1)
#define S2MPU06_BUCK_N_VOLTAGES (S2MPU06_BUCK_VSEL_MASK + 1)
#define S2MPU06_PMIC_EN_SHIFT 6
#define S2MPU06_REGULATOR_MAX (S2MPU06_REG_MAX)
#define SEC_PMIC_REV(iodev) (iodev)->pmic_rev
/*
* sec_opmode_data - regulator operation mode data
* @id: regulator id
* @mode: regulator operation mode
*/
enum s2mpu06_irq_source {
PMIC_INT1 = 0,
PMIC_INT2,
PMIC_INT3,
CHG_INT1,
CHG_INT2,
CHG_INT3,
CHG_PMIC_INT,
FG_INT,
S2MPU06_IRQ_GROUP_NR,
};
#define S2MPU06_NUM_IRQ_PMIC_REGS 3
#define S2MPU06_NUM_IRQ_CHG_REGS 3
enum s2mpu06_irq {
/* PMIC */
S2MPU06_PMIC_IRQ_PWRONR_INT1,
S2MPU06_PMIC_IRQ_PWRONF_INT1,
S2MPU06_PMIC_IRQ_JIGONBF_INT1,
S2MPU06_PMIC_IRQ_JIGONBR_INT1,
S2MPU06_PMIC_IRQ_ACOKBF_INT1,
S2MPU06_PMIC_IRQ_ACOKBR_INT1,
S2MPU06_PMIC_IRQ_PWRON1S_INT1,
S2MPU06_PMIC_IRQ_MRB_INT1,
S2MPU06_PMIC_IRQ_RTC60S_INT2,
S2MPU06_PMIC_IRQ_RTCA1_INT2,
S2MPU06_PMIC_IRQ_RTCA0_INT2,
S2MPU06_PMIC_IRQ_SMPL_INT2,
S2MPU06_PMIC_IRQ_RTC1S_INT2,
S2MPU06_PMIC_IRQ_WTSR_INT2,
S2MPU06_PMIC_IRQ_WRSTB_INT2,
S2MPU06_PMIC_IRQ_120C_INT3,
S2MPU06_PMIC_IRQ_140C_INT3,
S2MPU06_PMIC_IRQ_TSD_INT3,
/* Charger */
S2MPU06_CHG_IRQ_EOC_INT1,
S2MPU06_CHG_IRQ_CINIR_INT1,
S2MPU06_CHG_IRQ_BATP_INT1,
S2MPU06_CHG_IRQ_BATLV_INT1,
S2MPU06_CHG_IRQ_TOPOFF_INT1,
S2MPU06_CHG_IRQ_CINOVP_INT1,
S2MPU06_CHG_IRQ_CHGTSD_INT1,
S2MPU06_CHG_IRQ_CHGVINVR_INT2,
S2MPU06_CHG_IRQ_CHGTR_INT2,
S2MPU06_CHG_IRQ_TMROUT_INT2,
S2MPU06_CHG_IRQ_RECHG_INT2,
S2MPU06_CHG_IRQ_CHGTERM_INT2,
S2MPU06_CHG_IRQ_BATOVP_INT2,
S2MPU06_CHG_IRQ_CHGVIN_INT2,
S2MPU06_CHG_IRQ_CIN2BAT_INT2,
S2MPU06_CHG_IRQ_CHGSTS_INT3,
S2MPU06_CHG_IRQ_OTGILIM_INT3,
S2MPU06_CHG_IRQ_BSTINLV_INT3,
S2MPU06_CHG_IRQ_BSTILIM_INT3,
S2MPU06_CHG_IRQ_VMIDOVP_INT3,
S2MPU06_CHG_IRQ_WDT_PM,
S2MPU06_CHG_IRQ_TSD_PM,
S2MPU06_CHG_IRQ_VDDALV_PM,
/* Fuelgauge */
S2MPU06_FG_IRQ_VBAT_L_INT,
S2MPU06_FG_IRQ_SOC_L_INT,
S2MPU06_FG_IRQ_IDLE_ST_INT,
S2MPU06_FG_IRQ_INIT_ST_INT,
S2MPU06_IRQ_NR,
};
enum sec_device_type {
S2MPU06X,
};
struct s2mpu06_dev {
struct device *dev;
struct i2c_client *i2c; /* 0x66; TOP */
struct i2c_client *pmic; /* 0xCC; Regulator */
struct i2c_client *rtc; /* 0x0C; RTC */
struct i2c_client *charger; /* 0x68; Charger */
struct i2c_client *fuelgauge; /* 0xCE; Fuelgauge */
struct i2c_client *codec;
struct mutex i2c_lock;
struct apm_ops *ops;
int type;
int device_type;
int irq;
int irq_base;
int irq_gpio;
bool wakeup;
struct mutex irqlock;
int irq_masks_cur[S2MPU06_IRQ_GROUP_NR];
int irq_masks_cache[S2MPU06_IRQ_GROUP_NR];
/* pmic VER/REV register */
u8 pmic_rev; /* pmic Rev */
u8 pmic_ver; /* pmic version */
struct s2mpu06_platform_data *pdata;
};
enum s2mpu06_types {
TYPE_S2MPU06,
};
extern int s2mpu06_irq_init(struct s2mpu06_dev *s2mpu06);
extern void s2mpu06_irq_exit(struct s2mpu06_dev *s2mpu06);
extern int s2mpu06_read_codec_reg(struct i2c_client *i2c, u8 reg, u8 *dest);
/* S2MPU06 shared i2c API function */
extern int s2mpu06_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest);
extern int s2mpu06_read_reg_non_mutex(struct i2c_client *i2c, u8 reg, u8 *dest);
extern int s2mpu06_bulk_read(struct i2c_client *i2c, u8 reg, int count,
u8 *buf);
extern int s2mpu06_write_reg(struct i2c_client *i2c, u8 reg, u8 value);
extern int s2mpu06_bulk_write(struct i2c_client *i2c, u8 reg, int count,
u8 *buf);
extern int s2mpu06_write_word(struct i2c_client *i2c, u8 reg, u16 value);
extern int s2mpu06_read_word(struct i2c_client *i2c, u8 reg);
extern int s2mpu06_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask);
extern bool s2mpu06_is_pwron(void);
#endif /* __LINUX_MFD_S2MPU06_PRIV_H */

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/*
* s2mpu06.h - Driver for the s2mpu06
*
* Copyright (C) 2015 Samsung Electrnoics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __S2MPU06_MFD_H__
#define __S2MPU06_MFD_H__
#include <linux/platform_device.h>
#include <linux/regmap.h>
#if defined(CONFIG_SEC_CHARGER_S2MU005)
#include <linux/power/sec_charging_common.h>
#else
#include <linux/battery/sec_charging_common.h>
#endif
#define MFD_DEV_NAME "s2mpu06"
#define M2SH(m) ((m) & 0x0F ? ((m) & 0x03 ? ((m) & 0x01 ? 0 : 1) : \
((m) & 0x04 ? 2 : 3)) : \
((m) & 0x30 ? ((m) & 0x10 ? 4 : 5) : ((m) & 0x40 ? 6 : 7)))
#if defined(CONFIG_SEC_CHARGER_S2MPU06) || defined(CONFIG_CHARGER_S2MPU06)
typedef struct s2mpu06_charger_platform_data {
struct sec_charging_current *charging_current;
int chg_float_voltage;
char *charger_name;
char *fuelgauge_name;
bool chg_eoc_dualpath;
uint32_t is_1MHz_switching:1;
/* 2nd full check */
sec_battery_full_charged_t full_check_type_2nd;
int battery_type;
} s2mpu06_charger_platform_data_t;
#endif
#if defined(CONFIG_SEC_FUELGAUGE_S2MPU06) || defined(CONFIG_FUELGAUGE_S2MPU06)
typedef struct s2mpu06_fuelgauge_platform_data {
int capacity_max;
int capacity_max_margin;
int capacity_min;
int capacity_calculation_type;
int fuel_alert_soc;
int fullsocthr;
int fg_irq;
char *fuelgauge_name;
bool repeated_fuelalert;
struct sec_charging_current *charging_current;
} s2mpu06_fuelgauge_platform_data_t;
#endif
/**
* sec_regulator_data - regulator data
* @id: regulator id
* @initdata: regulator init data (contraints, supplies, ...)
*/
struct s2mpu06_regulator_data {
int id;
struct regulator_init_data *initdata;
struct device_node *reg_node;
};
/*
* sec_opmode_data - regulator operation mode data
* @id: regulator id
* @mode: regulator operation mode
*/
struct sec_opmode_data {
int id;
unsigned int mode;
};
/*
* samsung regulator operation mode
* SEC_OPMODE_OFF Regulator always OFF
* SEC_OPMODE_ON Regulator always ON
* SEC_OPMODE_LOWPOWER Regulator is on in low-power mode
* SEC_OPMODE_SUSPEND Regulator is changed by PWREN pin
* If PWREN is high, regulator is on
* If PWREN is low, regulator is off
*/
enum sec_opmode {
SEC_OPMODE_OFF,
SEC_OPMODE_SUSPEND,
SEC_OPMODE_LOWPOWER,
SEC_OPMODE_ON,
SEC_OPMODE_TCXO = 0x2,
};
/**
* struct sec_wtsr_smpl - settings for WTSR/SMPL
* @wtsr_en: WTSR Function Enable Control
* @smpl_en: SMPL Function Enable Control
* @wtsr_timer_val: Set the WTSR timer Threshold
* @smpl_timer_val: Set the SMPL timer Threshold
* @check_jigon: if this value is true, do not enable SMPL function when
* JIGONB is low(JIG cable is attached)
*/
struct sec_wtsr_smpl {
bool wtsr_en;
bool smpl_en;
int wtsr_timer_val;
int smpl_timer_val;
bool check_jigon;
};
struct s2mpu06_platform_data {
/* IRQ */
int irq_base;
int irq_gpio;
bool wakeup;
#if defined(CONFIG_SEC_CHARGER_S2MPU06) || defined(CONFIG_CHARGER_S2MPU06)
s2mpu06_charger_platform_data_t *pdata;
#endif
#if defined(CONFIG_SEC_FUELGAUGE_S2MPU06) || defined(CONFIG_FUELGAUGE_S2MPU06)
s2mpu06_fuelgauge_platform_data_t *fuelgauge_pdata;
#endif
int num_regulators;
struct s2mpu06_regulator_data *regulators;
struct sec_opmode_data *opmode;
struct mfd_cell *sub_devices;
int num_subdevs;
int (*cfg_pmic_irq)(void);
int device_type;
int ono;
int buck_ramp_delay;
bool dvs_en;
/* ---- RTC ---- */
struct sec_wtsr_smpl *wtsr_smpl;
struct rtc_time *init_time;
bool use_i2c_speedy;
bool cache_data;
};
struct s2mpu06 {
struct regmap *regmap;
};
#endif /* __S2MPU06_MFD_H__ */

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/*
* s2mpw01-private.h - Voltage regulator driver for the s2mpw01
*
* Copyright (C) 2015 Samsung Electrnoics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __LINUX_MFD_S2MPW01_PRIV_H
#define __LINUX_MFD_S2MPW01_PRIV_H
#include <linux/i2c.h>
#define S2MPW01_I2C_ADDR (0x66)
#define S2MPW01_REG_INVALID (0xff)
#define S2MPW01_IRQSRC_PMIC (1 << 0)
#define S2MPW01_IRQSRC_CHG (1 << 1)
#define S2MPW01_IRQSRC_FG (1 << 2)
/* Slave addr = 0x66 */
/* PMIC Top-Level Registers */
#define S2MPW01_PMIC_REG_PMICID (0x00)
#define S2MPW01_PMIC_REG_INTSRC (0x05)
#define S2MPW01_PMIC_REG_INTSRC_MASK (0x06)
/* Slave addr = 0xCC */
/* PMIC Registers */
#define S2MPW01_PMIC_REG_INT1 (0x00)
#define S2MPW01_PMIC_REG_INT2 0x01
#define S2MPW01_PMIC_REG_INT3 0x02
#define S2MPW01_PMIC_REG_INT1M 0x03
#define S2MPW01_PMIC_REG_INT2M 0x04
#define S2MPW01_PMIC_REG_INT3M 0x05
#define S2MPW01_PMIC_REG_STATUS1 0x06
#define S2MPW01_PMIC_REG_STATUS2 0x07
#define S2MPW01_PMIC_REG_PWRONSRC 0x08
#define S2MPW01_PMIC_REG_OFFSRC 0x09
#define S2MPW01_PMIC_REG_RTCBUF 0x0B
#define S2MPW01_PMIC_REG_CTRL1 0x0C
#define S2MPW01_PMIC_REG_CTRL3 0x0E
#define S2MPW01_PMIC_REG_B1CTRL 0x13
#define S2MPW01_PMIC_REG_B1OUT1 0x14
#define S2MPW01_PMIC_REG_B1OUT2 0x15
#define S2MPW01_PMIC_REG_B1OUT3 0x16
#define S2MPW01_PMIC_REG_B2CTRL1 0x17
#define S2MPW01_PMIC_REG_B2CTRL2 0x18
#define S2MPW01_PMIC_REG_B3CTRL1 0x19
#define S2MPW01_PMIC_REG_B3CTRL2 0x1A
#define S2MPW01_PMIC_REG_B4CTRL1 0x1B
#define S2MPW01_PMIC_REG_B4CTRL2 0x1C
#define S2MPW01_PMIC_REG_RAMP 0x1D
#define S2MPW01_PMIC_REG_BSTCTRL 0x1E
#define S2MPW01_PMIC_REG_L1DVS 0x1F
#define S2MPW01_PMIC_REG_L1CTRL1 0x20
#define S2MPW01_PMIC_REG_L1CTRL2 0x21
#define S2MPW01_PMIC_REG_L2CTRL1 0x22
#define S2MPW01_PMIC_REG_L2CTRL2 0x23
#define S2MPW01_PMIC_REG_L3CTRL 0x24
#define S2MPW01_PMIC_REG_L4CTRL 0x25
#define S2MPW01_PMIC_REG_L5CTRL 0x26
#define S2MPW01_PMIC_REG_L6CTRL 0x27
#define S2MPW01_PMIC_REG_L7CTRL 0x28
#define S2MPW01_PMIC_REG_L8CTRL 0x29
#define S2MPW01_PMIC_REG_L9CTRL 0x2A
#define S2MPW01_PMIC_REG_L10CTRL 0x2B
#define S2MPW01_PMIC_REG_L11CTRL 0x2C
#define S2MPW01_PMIC_REG_L12CTRL 0x2D
#define S2MPW01_PMIC_REG_L13CTRL 0x2E
#define S2MPW01_PMIC_REG_L14CTRL 0x2F
#define S2MPW01_PMIC_REG_L15CTRL 0x30
#define S2MPW01_PMIC_REG_L16CTRL 0x31
#define S2MPW01_PMIC_REG_L17CTRL 0x32
#define S2MPW01_PMIC_REG_L18CTRL 0x33
#define S2MPW01_PMIC_REG_L19CTRL 0x34
#define S2MPW01_PMIC_REG_L20CTRL 0x35
#define S2MPW01_PMIC_REG_L21CTRL 0x36
#define S2MPW01_PMIC_REG_L22CTRL 0x37
#define S2MPW01_PMIC_REG_L23CTRL 0x38
#define S2MPW01_PMIC_REG_LDO_DSCH1 0x39
#define S2MPW01_PMIC_REG_LDO_DSCH2 0x3A
#define S2MPW01_PMIC_REG_LDO_DSCH3 0x3B
#define S2MPW01_PMIC_REG_EXT_CTRL 0xFF
/* status1 register fields */
#define S2MPW01_STATUS1_PWRON_M (0x1 << 0)
#define S2MPW01_STATUS1_JIGONB_M (0x1 << 1)
#define S2MPW01_STATUS1_ACOKB_M (0x1 << 2)
#define S2MPW01_STATUS1_MRB_M (0x1 << 4)
#define S2MPW01_STATUS1_PWRON1S_M (0x1 << 5)
#define S2MPW01_STATUS1_INT120CS_M (0x1 << 6)
#define S2MPW01_STATUS1_INT140CS_M (0x1 << 7)
/* S2MPW01regulator ids */
enum S2MPW01_regulators {
S2MPW01_LDO1,
S2MPW01_LDO2,
S2MPW01_LDO3,
S2MPW01_LDO4,
S2MPW01_LDO5,
S2MPW01_LDO6,
S2MPW01_LDO7,
S2MPW01_LDO8,
S2MPW01_LDO9,
S2MPW01_LDO10,
S2MPW01_LDO11,
S2MPW01_LDO12,
S2MPW01_LDO13,
S2MPW01_LDO14,
S2MPW01_LDO15,
S2MPW01_LDO16,
S2MPW01_LDO17,
S2MPW01_LDO18,
S2MPW01_LDO19,
S2MPW01_LDO20,
S2MPW01_LDO21,
S2MPW01_LDO22,
S2MPW01_LDO23,
S2MPW01_BUCK1,
S2MPW01_BUCK3,
S2MPW01_BUCK4,
S2MPW01_REG_MAX,
};
#define S2MPW01_BUCK_MIN1 400000
#define S2MPW01_BUCK_MIN2 600000
#define S2MPW01_LDO_MIN1 400000
#define S2MPW01_LDO_MIN2 800000
#define S2MPW01_LDO_MIN3 1800000
#define S2MPW01_BUCK_STEP1 6250
#define S2MPW01_BUCK_STEP2 12500
#define S2MPW01_LDO_STEP1 12500
#define S2MPW01_LDO_STEP2 25000
#define S2MPW01_LDO_VSEL_MASK 0x3F
#define S2MPW01_BUCK_VSEL_MASK 0xFF
#define S2MPW01_ENABLE_MASK (0x03 << S2MPW01_ENABLE_SHIFT)
#define S2MPW01_SW_ENABLE_MASK 0x03
#define S2MPW01_RAMP_DELAY 12000
#define S2MPW01_ENABLE_TIME_LDO 128
#define S2MPW01_ENABLE_TIME_BUCK1 95
#define S2MPW01_ENABLE_TIME_BUCK2 106
#define S2MPW01_ENABLE_TIME_BUCK3 150
#define S2MPW01_ENABLE_TIME_BUCK4 150
#define S2MPW01_ENABLE_SHIFT 0x06
#define S2MPW01_LDO_N_VOLTAGES (S2MPW01_LDO_VSEL_MASK + 1)
#define S2MPW01_BUCK_N_VOLTAGES (S2MPW01_BUCK_VSEL_MASK + 1)
#define S2MPW01_PMIC_EN_SHIFT 6
#define S2MPW01_REGULATOR_MAX (S2MPW01_REG_MAX)
#define SEC_PMIC_REV(iodev) ((iodev)->pmic_rev)
/*
* sec_opmode_data - regulator operation mode data
* @id: regulator id
* @mode: regulator operation mode
*/
enum s2mpw01_irq_source {
PMIC_INT1 = 0,
PMIC_INT2,
PMIC_INT3,
#if defined(CONFIG_SEC_CHARGER_S2MPW01)
CHG_INT1,
CHG_INT2,
CHG_INT3,
#endif
#if defined(CONFIG_SEC_FUELGAUGE_S2MPW01)
FG_INT,
#endif
S2MPW01_IRQ_GROUP_NR,
};
#define S2MPW01_NUM_IRQ_PMIC_REGS 3
#define S2MPW01_NUM_IRQ_CHG_REGS 3
#define S2MPW01_NUM_IRQ_FG_REGS 1
enum s2mpw01_irq {
/* PMIC */
S2MPW01_PMIC_IRQ_PWRONR_INT1,
S2MPW01_PMIC_IRQ_PWRONF_INT1,
S2MPW01_PMIC_IRQ_JIGONBF_INT1,
S2MPW01_PMIC_IRQ_JIGONBR_INT1,
S2MPW01_PMIC_IRQ_ACOKBF_INT1,
S2MPW01_PMIC_IRQ_ACOKBR_INT1,
S2MPW01_PMIC_IRQ_PWRON1S_INT1,
S2MPW01_PMIC_IRQ_MRB_INT1,
S2MPW01_PMIC_IRQ_RTC60S_INT2,
S2MPW01_PMIC_IRQ_RTCA1_INT2,
S2MPW01_PMIC_IRQ_RTCA0_INT2,
S2MPW01_PMIC_IRQ_SMPL_INT2,
S2MPW01_PMIC_IRQ_RTC1S_INT2,
S2MPW01_PMIC_IRQ_WTSR_INT2,
S2MPW01_PMIC_IRQ_WRSTB_INT2,
S2MPW01_PMIC_IRQ_120C_INT3,
S2MPW01_PMIC_IRQ_140C_INT3,
S2MPW01_PMIC_IRQ_TSD_INT3,
#ifdef CONFIG_SEC_CHARGER_S2MPW01
/* Charger */
S2MPW01_CHG_IRQ_RECHG_INT1,
S2MPW01_CHG_IRQ_CHGDONE_INT1,
S2MPW01_CHG_IRQ_TOPOFF_INT1,
S2MPW01_CHG_IRQ_PREECHG_INT1,
S2MPW01_CHG_IRQ_CHGSTS_INT1,
S2MPW01_CHG_IRQ_CIN2BAT_INT1,
S2MPW01_CHG_IRQ_CHGVINOVP_INT1,
S2MPW01_CHG_IRQ_CHGVIN_INT1,
S2MPW01_CHG_IRQ_ADPATH_INT2,
S2MPW01_CHG_IRQ_FCHG_INT2,
S2MPW01_CHG_IRQ_BATDET_INT2,
S2MPW01_CHG_IRQ_CVOK_INT3,
S2MPW01_CHG_IRQ_TMROUT_INT3,
S2MPW01_CHG_IRQ_CHGTSDINT3,
#endif
#ifdef CONFIG_SEC_FUELGAUGE_S2MPW01
/* Fuelgauge */
S2MPW01_FG_IRQ_VBAT_L_INT,
S2MPW01_FG_IRQ_SOC_L_INT,
S2MPW01_FG_IRQ_IDLE_ST_INT,
S2MPW01_FG_IRQ_INIT_ST_INT,
#endif
S2MPW01_IRQ_NR,
};
enum sec_device_type {
S2MPW01X,
};
struct s2mpw01_dev {
struct device *dev;
struct i2c_client *i2c; /* 0x66; TOP */
struct i2c_client *pmic; /* 0xCC; Regulator */
struct i2c_client *rtc; /* 0x0C; RTC */
struct i2c_client *charger; /* 0x68; Charger */
struct i2c_client *fuelgauge; /* 0xCE; Fuelgauge */
struct mutex i2c_lock;
struct apm_ops *ops;
int type;
int device_type;
int irq;
int irq_base;
int irq_gpio;
bool wakeup;
struct mutex irqlock;
int irq_masks_cur[S2MPW01_IRQ_GROUP_NR];
int irq_masks_cache[S2MPW01_IRQ_GROUP_NR];
/* pmic VER/REV register */
u8 pmic_rev; /* pmic Rev */
u8 pmic_ver; /* pmic version */
struct s2mpw01_platform_data *pdata;
};
enum s2mpw01_types {
TYPE_S2MPW01,
};
extern int s2mpw01_irq_init(struct s2mpw01_dev *s2mpw01);
extern void s2mpw01_irq_exit(struct s2mpw01_dev *s2mpw01);
/* S2MPW01 shared i2c API function */
extern int s2mpw01_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest);
extern int s2mpw01_bulk_read(struct i2c_client *i2c, u8 reg, int count,
u8 *buf);
extern int s2mpw01_write_reg(struct i2c_client *i2c, u8 reg, u8 value);
extern int s2mpw01_bulk_write(struct i2c_client *i2c, u8 reg, int count,
u8 *buf);
extern int s2mpw01_write_word(struct i2c_client *i2c, u8 reg, u16 value);
extern int s2mpw01_read_word(struct i2c_client *i2c, u8 reg);
extern int s2mpw01_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask);
#endif /* __LINUX_MFD_S2MPW01_PRIV_H */

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/*
* s2mpw01.h - Driver for the s2mpw01
*
* Copyright (C) 2015 Samsung Electrnoics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __S2MPW01_MFD_H__
#define __S2MPW01_MFD_H__
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/power/sec_charging_common.h>
#define MFD_DEV_NAME "s2mpw01"
#define M2SH(m) ((m) & 0x0F ? ((m) & 0x03 ? ((m) & 0x01 ? 0 : 1) : ((m) & 0x04 ? 2 : 3)) : \
((m) & 0x30 ? ((m) & 0x10 ? 4 : 5) : ((m) & 0x40 ? 6 : 7)))
#if defined(CONFIG_SEC_CHARGER_S2MPW01)
typedef struct s2mpw01_charger_platform_data {
sec_charging_current_t *charging_current_table;
int chg_float_voltage;
char *charger_name;
char *fuelgauge_name;
bool chg_eoc_dualpath;
uint32_t is_1MHz_switching:1;
/* 2nd full check */
sec_battery_full_charged_t full_check_type_2nd;
} s2mpw01_charger_platform_data_t;
#endif
/**
* sec_regulator_data - regulator data
* @id: regulator id
* @initdata: regulator init data (contraints, supplies, ...)
*/
struct s2mpw01_regulator_data {
int id;
struct regulator_init_data *initdata;
struct device_node *reg_node;
};
/*
* sec_opmode_data - regulator operation mode data
* @id: regulator id
* @mode: regulator operation mode
*/
struct sec_opmode_data {
int id;
unsigned int mode;
};
/*
* samsung regulator operation mode
* SEC_OPMODE_OFF Regulator always OFF
* SEC_OPMODE_ON Regulator always ON
* SEC_OPMODE_LOWPOWER Regulator is on in low-power mode
* SEC_OPMODE_SUSPEND Regulator is changed by PWREN pin
* If PWREN is high, regulator is on
* If PWREN is low, regulator is off
*/
enum sec_opmode {
SEC_OPMODE_OFF,
SEC_OPMODE_SUSPEND,
SEC_OPMODE_LOWPOWER,
SEC_OPMODE_ON,
};
/**
* struct sec_wtsr_smpl - settings for WTSR/SMPL
* @wtsr_en: WTSR Function Enable Control
* @smpl_en: SMPL Function Enable Control
* @wtsr_timer_val: Set the WTSR timer Threshold
* @smpl_timer_val: Set the SMPL timer Threshold
* @check_jigon: if this value is true, do not enable SMPL function when
* JIGONB is low(JIG cable is attached)
*/
struct sec_wtsr_smpl {
bool wtsr_en;
bool smpl_en;
int wtsr_timer_val;
int smpl_timer_val;
bool check_jigon;
};
struct s2mpw01_platform_data {
/* IRQ */
int irq_base;
int irq_gpio;
bool wakeup;
int num_regulators;
struct s2mpw01_regulator_data *regulators;
struct sec_opmode_data *opmode;
struct mfd_cell *sub_devices;
int num_subdevs;
int (*cfg_pmic_irq)(void);
int device_type;
int ono;
int buck_ramp_delay;
bool dvs_en;
/* ---- RTC ---- */
struct sec_wtsr_smpl *wtsr_smpl;
struct rtc_time *init_time;
bool use_i2c_speedy;
bool cache_data;
};
struct s2mpw01
{
struct regmap *regmap;
};
/* easier regulator block control : lock is aquired internally */
extern int swa_pmic_reg_read(u8 reg, void *dest);
extern int swa_pmic_reg_write(u8 reg, u8 value);
extern int swa_pmic_reg_update(u8 reg, u8 val, u8 mask);
/* easier rtc block control : lock is aquired internally */
extern int swa_pmic_rtc_read(u8 reg, void *dest);
extern int swa_pmic_rtc_write(u8 reg, u8 value);
extern int swa_pmic_rtc_update(u8 reg, u8 val, u8 mask);
#endif /* __S2MPW01_MFD_H__ */

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/*
* s2mu003-private.h - Voltage regulator driver for the Samsung s2mpb02
*
* Copyright (C) 2014 Samsung Electrnoics
* XXX <xxx@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __LINUX_MFD_S2MU003_PRIV_H
#define __LINUX_MFD_S2MU003_PRIV_H
/* S2MU003 registers */
enum s2mpu003_reg {
S2MU003_CHG_STATUS,
S2MU003_CHG_CTRL1,
S2MU003_CHG_CTRL2,
S2MU003_PMIC_ID,
S2MU003_CHG_CTRL3,
S2MU003_CHG_CTRL4,
S2MU003_CHG_CTRL5,
S2MU003_SoftRESET,
S2MU003_CHG_CTRL6,
S2MU003_CHG_CTRL7,
S2MU003_CHG_CTRL8,
S2MU003_CHG_STATUS2,
S2MU003_CHG_STATUS3,
S2MU003_CHG_STATUS4,
S2MU003_CHG_CTRL9,
S2MU003_FLED_CH1_CTRL0 = 0x20,
S2MU003_FLED_CH1_CTRL1,
S2MU003_FLED_CH1_CTRL2,
S2MU003_FLED_CH1_CTRL3,
S2MU003_FLED_CH1_CTRL4,
S2MU003_FLED_CH1_CTRL5,
S2MU003_FLED_CH2_CTRL0,
S2MU003_FLED_CH2_CTRL1,
S2MU003_FLED_CH2_CTRL2,
S2MU003_FLED_CH2_CTRL3,
S2MU003_FLED_CH2_CTRL4,
S2MU003_FLED_CH2_CTRL5,
S2MU003_FLED_CTRL0,
S2MU003_FLED_CTRL1,
S2MU003_FLED_CTRL2,
S2MU003_FLED_CTRL3,
S2MU003_Buck_LDO_CTRL = 0x41,
S2MU003_Buck_CTRL,
S2MU003_LDO_CTRL,
S2MU003_Buck_CTRL2 = 0x45,
S2MU003_MRSTB_CTRL = 0X47,
S2MU003_CHG_INT1 = 0X60,
S2MU003_CHG_INT2,
S2MU003_CHG_INT3,
S2MU003_CHG_INT1M,
S2MU003_CHG_INT2M,
S2MU003_CHG_INT3M,
S2MU003_FLED_INT,
S2MU003_FLED_INTM,
S2MU003_PMIC_INT,
S2MU003_PMIC_INTM,
S2MU003_SHUTDOWN_CTRL,
S2MU003_OFF_EVENT,
S2MU003_FLED_STATUS,
S2MU003_PMIC_STATUS,
};
/* S2MU003 regulator ids */
enum S2MU003_regulators {
S2MU003_CAMLDO,
S2MU003_BUCK,
S2MU003_REG_MAX,
};
#define S2MU003_BUCK_MIN1 600000
#define S2MU003_LDO_MIN1 800000
#define S2MU003_BUCK_STEP1 100000
#define S2MU003_LDO_STEP1 100000
#define S2MU003_CAMLDO_VSEL_MASK 0x1F
#define S2MU003_BUCK_VSEL_MASK 0x1F
#define S2MU003_BUCK_ENABLE_MASK 0x10
#define S2MU003_CAMLDO_ENABLE_MASK 0x20
#define S2MU003_RAMP_DELAY 12000
#define S2MU003_ENABLE_TIME_LDO 180
#define S2MU003_ENABLE_TIME_BUCK 100
#define S2MU003_BUCK_ENABLE_SHIFT 0x04
#define S2MU003_CAMLDO_ENABLE_SHIFT 0x06
#define S2MU003_CAMLDO_N_VOLTAGES (S2MU003_CAMLDO_VSEL_MASK + 1)
#define S2MU003_BUCK_N_VOLTAGES (S2MU003_BUCK_VSEL_MASK + 1)
#define S2MU003_REGULATOR_MAX (S2MU003_REG_MAX)
#endif /* __LINUX_MFD_S2MU003_PRIV_H */

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/*
* include/linux/mfd/s2mu003.h
*
* Driver to Richtek S2MU003
* Multi function device -- Charger / Battery Gauge /
* DCDC Converter / LED Flashlight
*
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com
* Author: Junhan Bae <junhan84.bae@samsung.com>
*
* Copyright (C) 2013 Richtek Technology Corp.
* Author: Patrick Chang <patrick_chang@richtek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*/
#ifndef S2MU003_H
#define S2MU003_H
/* delete below header caused it is only for this module*/
/*#include <linux/rtdefs.h> */
#include <linux/mutex.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/wakelock.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/workqueue.h>
#include <linux/slab.h>
#if defined(CONFIG_SEC_CHARGER_S2MU003)
#include <linux/power/sec_charging_common.h>
#else
#include <linux/battery/sec_charging_common.h>
#endif
#define S2MU003_DRV_VER "1.1.8_S"
#ifdef CONFIG_S2MU003_SADDR
#define S2MU003FG_SLAVE_ADDR_MSB (0x40)
#else
#define S2MU003FG_SLAVE_ADDR_MSB (0x00)
#endif
#define S2MU003FG_SLAVE_ADDR (0x35|S2MU003FG_SLAVE_ADDR_MSB)
#define S2MU003_SLAVE_ADDR (0x34|S2MU003FG_SLAVE_ADDR_MSB)
#define S2MU003_CHG_IRQ_REGS_NR 3
#define S2MU003_LED_IRQ_REGS_NR 1
#define S2MU003_PMIC_IRQ_REGS_NR 1
#define S2MU003_IRQ_REGS_NR \
(S2MU003_CHG_IRQ_REGS_NR + \
S2MU003_LED_IRQ_REGS_NR + \
S2MU003_PMIC_IRQ_REGS_NR)
#define S2MU003_DECLARE_IRQ(irq) { \
irq, irq, \
irq##_NAME, IORESOURCE_IRQ }
#define S2MU003_OF_COMPATIBLE_LDO_SAFE "samsung,s2mu003-safeldo"
#define S2MU003_OF_COMPATIBLE_LDO1 "samsung,s2mu003-ldo1"
#define S2MU003_OF_COMPATIBLE_DCDC1 "samsung,s2mu003-dcdc1"
enum {
S2MU003_ID_LDO_SAFE = 0,
S2MU003_ID_LDO1,
S2MU003_ID_DCDC1,
S2MU003_MAX_REGULATOR,
};
typedef union s2mu003_irq_status {
struct {
uint8_t chg_irq_status[S2MU003_CHG_IRQ_REGS_NR];
uint8_t fled_irq_status[S2MU003_LED_IRQ_REGS_NR];
uint8_t pmic_irq_status[S2MU003_PMIC_IRQ_REGS_NR];
};
struct {
uint8_t regs[S2MU003_IRQ_REGS_NR];
};
} s2mu003_irq_status_t;
typedef union s2mu003_pmic_shdn_ctrl {
struct {
uint8_t reserved:2;
uint8_t buck_ocp_enshdn:1;
uint8_t buck_lv_enshdn:1;
uint8_t sldo_lv_enshdn:1;
uint8_t ldo_lv_enshdn:1;
uint8_t ot_enshdn:1;
uint8_t vdda_uv_enshdn:1;
} shdn_ctrl1;
uint8_t shdn_ctrl[1];
} s2mu003_pmic_shdn_ctrl_t;
typedef struct s2mu003_regulator_platform_data {
int id;
struct regulator_init_data *initdata;
struct device_node *reg_node;
} s2mu003_regulator_platform_data_t;
struct s2mu003_fled_platform_data;
typedef struct s2mu003_charger_platform_data {
sec_charging_current_t *charging_current_table;
int chg_float_voltage;
char *charger_name;
#ifdef CONFIG_SEC_FUELGAUGE_S2MU003
char *fuelgauge_name;
#endif
uint32_t is_1MHz_switching:1;
uint32_t is_fixed_switching:1;
sec_bat_adc_table_data_t *temp_adc_table;
unsigned int temp_adc_table_size;
unsigned int temp_amb_adc_table_size;
unsigned int chg_temp_adc_table_size;
unsigned int inbat_adc_table_size;
sec_battery_thermal_source_t thermal_source;
} s2mu003_charger_platform_data_t;
struct s2mu003_mfd_platform_data {
s2mu003_regulator_platform_data_t *regulator_platform_data;
struct s2mu003_fled_platform_data *fled_platform_data;
int irq_gpio;
int irq_base;
int num_regulators;
int fuelgauge_reg;
s2mu003_regulator_platform_data_t *regulators;
#ifdef CONFIG_CHARGER_S2MU003
s2mu003_charger_platform_data_t *charger_platform_data;
#endif
};
#define s2mu003_mfd_platform_data_t \
struct s2mu003_mfd_platform_data
struct s2mu003_charger_data;
struct s2mu003_mfd_chip {
struct i2c_client *i2c_client;
struct i2c_client *fuelgauge_i2c;
struct device *dev;
s2mu003_mfd_platform_data_t *pdata;
int irq_base;
struct mutex io_lock;
struct mutex irq_lock;
struct wake_lock irq_wake_lock;
/* prev IRQ status and now IRQ_status*/
s2mu003_irq_status_t irq_status[2];
/* irq_status_index ^= 0x01; after access irq*/
int irq_status_index;
int irq;
uint8_t irq_masks_cache[S2MU003_IRQ_REGS_NR];
int suspend_flag;
struct s2mu003_charger_data *charger;
int dev_id;
#ifdef CONFIG_FLED_S2MU003
struct s2mu003_fled_info *fled_info;
#endif
#ifdef CONFIG_REGULATOR_S2MU003
struct s2mu003_regulator_info *regulator_info[S2MU003_MAX_REGULATOR];
#endif
};
#define s2mu003_mfd_chip_t \
struct s2mu003_mfd_chip
extern int s2mu003_block_read_device(struct i2c_client *i2c,
int reg, int bytes, void *dest);
extern int s2mu003_block_write_device(struct i2c_client *i2c,
int reg, int bytes, void *src);
extern int s2mu003_reg_read(struct i2c_client *i2c, int reg_addr);
extern int s2mu003_reg_write(struct i2c_client *i2c, int reg_addr, u8 data);
extern int s2mu003_assign_bits(struct i2c_client *i2c, int reg_addr, u8 mask,
u8 data);
extern int s2mu003_set_bits(struct i2c_client *i2c, int reg_addr, u8 mask);
extern int s2mu003_clr_bits(struct i2c_client *i2c, int reg_addr, u8 mask);
extern int charger_led_ctl(bool on);
typedef enum {
S2MU003_PREV_STATUS = 0,
S2MU003_NOW_STATUS } s2mu003_irq_status_sel_t;
extern s2mu003_irq_status_t *s2mu003_get_irq_status(
s2mu003_mfd_chip_t *mfd_chip, s2mu003_irq_status_sel_t sel);
extern int s2mu003_init_irq(s2mu003_mfd_chip_t *chip);
extern int s2mu003_exit_irq(s2mu003_mfd_chip_t *chip);
#endif /* S2MU003_H */

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#ifndef LINUX_MFD_S2MU003_IRQ_H
#define LINUX_MFD_S2MU003_IRQ_H
enum {
S2MU003_EOC_IRQ,
S2MU003_CINIR_IRQ,
S2MU003_BATP_IRQ,
S2MU003_BATLV_IRQ,
S2MU003_TOPOFF_IRQ,
S2MU003_CINOVP_IRQ,
S2MU003_CHGTSD_IRQ,
S2MU003_CHGVINVR_IRQ,
S2MU003_CHGTR_IRQ,
S2MU003_TMROUT_IRQ,
S2MU003_RECHG_IRQ,
S2MU003_CHGTERM_IRQ,
S2MU003_BATOVP_IRQ,
S2MU003_CHGVIN_IRQ,
S2MU003_CIN2VAT_IRQ,
S2MU003_CHGSTS_IRQ,
S2MU003_OTGILIM_IRQ,
S2MU003_BSTINLV_IRQ,
S2MU003_BSTILIM_IRQ,
S2MU003_VMIDOVP_IRQ,
S2MU003_LBPROT_IRQ,
S2MU003_OPEN_CH2_IRQ,
S2MU003_OPEN_CH1_IRQ,
S2MU003_SHORT_CH2_IRQ,
S2MU003_SHORT_CH1_IRQ,
S2MU003_WDT_IRQ,
S2MU003_TSD_IRQ,
S2MU003_CPWRLV_IRQ,
S2MU003_IRQS_NR,
};
#define S2MU003_EOC_IRQ_NAME "chg_eoc"
#define S2MU003_CINIR_IRQ_NAME "chg_cinir"
#define S2MU003_BATP_IRQ_NAME "chg_batp"
#define S2MU003_BATLV_IRQ_NAME "chg_batlv"
#define S2MU003_TOPOFF_IRQ_NAME "chg_topoff"
#define S2MU003_CINOVP_IRQ_NAME "chg_cinovp"
#define S2MU003_CHGTSD_IRQ_NAME "chg_chgtsd"
#define S2MU003_CHGVINVR_IRQ_NAME "chg_chgvinvr"
#define S2MU003_CHGTR_IRQ_NAME "chg_chgtr"
#define S2MU003_TMROUT_IRQ_NAME "chg_tmrout"
#define S2MU003_RECHG_IRQ_NAME "chg_rechg"
#define S2MU003_CHGTERM_IRQ_NAME "chg_chgterm"
#define S2MU003_BATOVP_IRQ_NAME "chg_batovp"
#define S2MU003_CHGVIN_IRQ_NAME "chg_chgvin"
#define S2MU003_CIN2VAT_IRQ_NAME "chg_cin2vat"
#define S2MU003_CHGSTS_IRQ_NAME "chg_chgsts"
#define S2MU003_OTGILIM_IRQ_NAME "chg_otgilim"
#define S2MU003_BSTINLV_IRQ_NAME "chg_bstinlv"
#define S2MU003_BSTILIM_IRQ_NAME "chg_bstilim"
#define S2MU003_VMIDOVP_IRQ_NAME "chg_vmidovp"
#define S2MU003_LBPROT_IRQ_NAME "led_lbprot"
#define S2MU003_OPEN_CH2_IRQ_NAME "led_open_ch2"
#define S2MU003_OPEN_CH1_IRQ_NAME "led_open_ch1"
#define S2MU003_SHORT_CH2_IRQ_NAME "led_short_ch2"
#define S2MU003_SHORT_CH1_IRQ_NAME "led_short_ch1"
#define S2MU003_WDT_IRQ_NAME "pmic_wdt"
#define S2MU003_TSD_IRQ_NAME "pmic_tsd"
#define S2MU003_CPWRLV_IRQ_NAME "pmic_cpwrlv"
const char *s2mu003_get_irq_name_by_index(int index);
#endif /* LINUX_MFD_S2MU003_IRQ_H */

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/*
* s2mu005-private.h - Voltage regulator driver for the s2mu005
*
* Copyright (C) 2015 Samsung Electrnoics
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __LINUX_MFD_S2MU005_PRIV_H
#define __LINUX_MFD_S2MU005_PRIV_H
#include <linux/i2c.h>
//#include <linux/battery/charger/s2mu005_charger.h>
//#include <linux/battery/fuelgauge/s2mu005_fuelgauge.h>
#define S2MU005_I2C_ADDR (0x7A)
#define S2MU005_REG_INVALID (0xff)
enum s2mu005_reg {
/* Slave addr = 0x7A */
S2MU005_REG_SC_INT,
S2MU005_REG_SC_INT_MASK,
S2MU005_REG_FLED_INT,
S2MU005_REG_FLED_INT_MASK,
S2MU005_REG_MUIC_INT1,
S2MU005_REG_MUIC_INT2,
S2MU005_REG_MUIC_INT1_MASK,
S2MU005_REG_MUIC_INT2_MASK,
S2MU005_REG_SC_STATUS0,
S2MU005_REG_SC_STATUS1,
S2MU005_REG_SC_STATUS2,
S2MU005_REG_SC_STATUS3,
S2MU005_REG_SC_STATUS4,
S2MU005_REG_SC_STATUS5,
S2MU005_REG_SC_CTRL0,
S2MU005_REG_SC_CTRL1,
S2MU005_REG_SC_CTRL2,
S2MU005_REG_SC_CTRL3,
S2MU005_REG_SC_CTRL4,
S2MU005_REG_SC_CTRL5,
S2MU005_REG_SC_CTRL6,
S2MU005_REG_SC_CTRL7,
S2MU005_REG_SC_CTRL8,
S2MU005_REG_SC_CTRL9,
S2MU005_REG_SC_CTRL10,
S2MU005_REG_SC_CTRL11,
S2MU005_REG_SC_CTRL12,
S2MU005_REG_SC_CTRL13,
S2MU005_REG_SC_CTRL14,
S2MU005_REG_SC_CTRL15,
S2MU005_REG_SC_CTRL16,
S2MU005_REG_SC_CTRL17,
S2MU005_REG_SC_CTRL18,
S2MU005_REG_SC_RSVD21,
S2MU005_REG_SC_TEST0,
S2MU005_REG_SC_TEST1,
S2MU005_REG_SC_TEST2,
S2MU005_REG_SC_TEST3,
S2MU005_REG_SC_TEST4,
S2MU005_REG_SC_TEST5,
S2MU005_REG_SC_TEST6,
S2MU005_REG_SC_TEST7,
S2MU005_REG_SC_TEST8,
S2MU005_REG_SC_RSVD2B,
S2MU005_REG_SC_TEST10,
S2MU005_REG_FLED_STATUS,
S2MU005_REG_FLED_CH1_CTRL0,
S2MU005_REG_FLED_CH1_CTRL1,
S2MU005_REG_FLED_CH1_CTRL2,
S2MU005_REG_FLED_CH1_CTRL3,
S2MU005_REG_FLED_CH2_CTRL0,
S2MU005_REG_FLED_CH2_CTRL1,
S2MU005_REG_FLED_CH2_CTRL2,
S2MU005_REG_FLED_CH2_CTRL3,
S2MU005_REG_FLED_CTRL0,
S2MU005_REG_FLED_CTRL1,
S2MU005_REG_FLED_CTRL2,
S2MU005_REG_FLED_CTRL3,
S2MU005_REG_FLED_CTRL4,
S2MU005_REG_FLED_TEST0,
S2MU005_REG_FLED_RSVD,
S2MU005_REG_LED_EN,
S2MU005_REG_LED1_CURRENT,
S2MU005_REG_LED2_CURRENT,
S2MU005_REG_LED3_CURRENT,
S2MU005_REG_LED1_RAMP,
S2MU005_REG_LED1_DUR,
S2MU005_REG_LED2_RAMP,
S2MU005_REG_LED2_DUR,
S2MU005_REG_LED3_RAMP,
S2MU005_REG_LED3_DUR,
S2MU005_REG_LED_TEST0,
S2MU005_REG_LED_CTRL0,
S2MU005_REG_MUIC_ADC,
S2MU005_REG_MUIC_DEVICE_TYPE1,
S2MU005_REG_MUIC_DEVICE_TYPE2,
S2MU005_REG_MUIC_DEVICE_TYPE3,
S2MU005_REG_MUIC_BUTTON1,
S2MU005_REG_MUIC_BUTTON2,
S2MU005_REG_MUIC_RESET,
S2MU005_REG_MUIC_CHG_TYPE,
S2MU005_REG_MUIC_DEVICE_APPLE,
S2MU005_REG_MUIC_BCD_RESCAN,
S2MU005_REG_MUIC_TEST1,
S2MU005_REG_MUIC_TEST2,
S2MU005_REG_MUIC_TEST3,
S2MU005_REG_MUIC_RSVD56,
S2MU005_REG_COMMON_CFG1,
S2MU005_REG_COMMON_CFG2,
S2MU005_REG_MRSTB,
S2MU005_REG_PWRSEL_CTRL0,
S2MU005_REG_RSVD5B,
S2MU005_REG_RSVD5C,
S2MU005_REG_RSVD5D,
S2MU005_REG_SELFDIS_CFG1,
S2MU005_REG_SELFDIS_CFG2,
S2MU005_REG_SELFDIS_CFG3,
S2MU005_REG_RSVD61,
S2MU005_REG_REV_ID = 0x73,
S2MU005_REG_MUIC_CTRL1 = 0xB2,
S2MU005_REG_MUIC_TIMER_SET1,
S2MU005_REG_MUIC_TIMER_SET2,
S2MU005_REG_MUIC_SW_CTRL,
S2MU005_REG_MUIC_TIMER_SET3,
S2MU005_REG_MUIC_CTRL2,
S2MU005_REG_MUIC_CTRL3,
S2MU005_REG_END,
};
enum s2mu005_irq_source {
CHG_INT = 0,
FLED_INT,
MUIC_INT1,
MUIC_INT2,
S2MU005_IRQ_GROUP_NR,
};
#define MUIC_MAX_INT MUIC_INT2
#define S2MU005_NUM_IRQ_MUIC_REGS (MUIC_MAX_INT - MUIC_INT1 + 1)
enum s2mu005_irq {
S2MU005_CHG_IRQ_DET_BAT,
S2MU005_CHG_IRQ_BAT,
S2MU005_CHG_IRQ_IVR,
S2MU005_CHG_IRQ_EVENT,
S2MU005_CHG_IRQ_CHG,
S2MU005_CHG_IRQ_VMID,
S2MU005_CHG_IRQ_WCIN,
S2MU005_CHG_IRQ_VBUS,
S2MU005_FLED_IRQ_LBPROT,
S2MU005_FLED_IRQ_OPEN_CH2,
S2MU005_FLED_IRQ_OPEN_CH1,
S2MU005_FLED_IRQ_SHORT_CH2,
S2MU005_FLED_IRQ_SHORT_CH1,
S2MU005_MUIC_IRQ1_ATTATCH,
S2MU005_MUIC_IRQ1_DETACH,
S2MU005_MUIC_IRQ1_KP,
S2MU005_MUIC_IRQ1_LKP,
S2MU005_MUIC_IRQ1_LKR,
S2MU005_MUIC_IRQ1_RID_CHG,
S2MU005_MUIC_IRQ2_VBUS_ON,
S2MU005_MUIC_IRQ2_RSVD_ATTACH,
S2MU005_MUIC_IRQ2_ADC_CHANGE,
S2MU005_MUIC_IRQ2_STUCK,
S2MU005_MUIC_IRQ2_STUCKRCV,
S2MU005_MUIC_IRQ2_MHDL,
S2MU005_MUIC_IRQ2_AV_CHARGE,
S2MU005_MUIC_IRQ2_VBUS_OFF,
S2MU005_IRQ_NR,
};
struct s2mu005_dev {
struct device *dev;
struct i2c_client *i2c; /* Slave addr = 0x7A */
struct mutex i2c_lock;
int type;
int irq;
int irq_base;
int irq_gpio;
bool wakeup;
struct mutex irqlock;
int irq_masks_cur[S2MU005_IRQ_GROUP_NR];
int irq_masks_cache[S2MU005_IRQ_GROUP_NR];
#ifdef CONFIG_HIBERNATION
/* For hibernation */
u8 reg_pmic_dump[S2MU005_PMIC_REG_END];
u8 reg_muic_dump[S2MU005_MUIC_REG_END];
u8 reg_led_dump[S2MU005_LED_REG_END];
#endif
/* pmic VER/REV register */
u8 pmic_rev; /* pmic Rev */
u8 pmic_ver; /* pmic version */
struct s2mu005_platform_data *pdata;
};
enum s2mu005_types {
TYPE_S2MU005,
};
extern int s2mu005_irq_init(struct s2mu005_dev *s2mu005);
extern void s2mu005_irq_exit(struct s2mu005_dev *s2mu005);
/* s2mu005 shared i2c API function */
extern int s2mu005_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest);
extern int s2mu005_bulk_read(struct i2c_client *i2c, u8 reg, int count,
u8 *buf);
extern int s2mu005_write_reg(struct i2c_client *i2c, u8 reg, u8 value);
extern int s2mu005_bulk_write(struct i2c_client *i2c, u8 reg, int count,
u8 *buf);
extern int s2mu005_write_word(struct i2c_client *i2c, u8 reg, u16 value);
extern int s2mu005_read_word(struct i2c_client *i2c, u8 reg);
extern int s2mu005_update_reg(struct i2c_client *i2c, u8 reg, u8 val, u8 mask);
/* s2mu005 check muic path fucntion */
extern bool is_muic_usb_path_ap_usb(void);
extern bool is_muic_usb_path_cp_usb(void);
/* s2mu005 Debug. ft */
extern void s2mu005_muic_read_register(struct i2c_client *i2c);
/* for charger api */
extern void s2mu005_hv_muic_charger_init(void);
#endif /* __LINUX_MFD_S2MU005_PRIV_H */

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/*
* s2mu005.h - Driver for the s2mu005
*
* Copyright (C) 2015 Samsung Electrnoics
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* This driver is based on max8997.h
*
* s2mu005 has Flash LED, SVC LED, Haptic, MUIC devices.
* The devices share the same I2C bus and included in
* this mfd driver.
*/
#ifndef __S2MU005_H__
#define __S2MU005_H__
#include <linux/platform_device.h>
#include <linux/regmap.h>
#if defined(CONFIG_SEC_CHARGER_S2MU005)
#include <linux/power/sec_charging_common.h>
#else
#include <linux/battery/sec_charging_common.h>
//#include <linux/battery/charger/s2mu005_charger.h>
//#include <linux/battery/fuelgauge/s2mu005_fuelgauge.h>
#endif
#define MFD_DEV_NAME "s2mu005"
#define M2SH(m) ((m) & 0x0F ? ((m) & 0x03 ? ((m) & 0x01 ? 0 : 1) : ((m) & 0x04 ? 2 : 3)) : \
((m) & 0x30 ? ((m) & 0x10 ? 4 : 5) : ((m) & 0x40 ? 6 : 7)))
#ifdef CONFIG_VIBETONZ
struct s2mu005_haptic_platform_data {
u16 max_timeout;
u16 duty;
u16 period;
u16 reg2;
char *regulator_name;
unsigned int pwm_id;
void (*init_hw) (void);
void (*motor_en) (bool);
};
#endif
struct s2mu005_regulator_data {
int id;
struct regulator_init_data *initdata;
struct device_node *reg_node;
};
typedef struct s2mu005_charger_platform_data {
sec_charging_current_t *charging_current_table;
int chg_float_voltage;
char *charger_name;
#if defined(CONFIG_SEC_FUELGAUGE_S2MU005)
char *fuelgauge_name;
#endif
bool chg_eoc_dualpath;
int recharge_vcell;
uint32_t is_1MHz_switching:1;
/* 2nd full check */
sec_battery_full_charged_t full_check_type_2nd;
} s2mu005_charger_platform_data_t;
struct s2mu005_platform_data {
/* IRQ */
int irq_base;
int irq_gpio;
bool wakeup;
#if defined(CONFIG_CHARGER_S2MU005)
s2mu005_charger_platform_data_t *pdata;
sec_charger_platform_data_t *charger_data;
// sec_fuelgauge_platform_data_t *fuelgauge_data;
#endif
int num_regulators;
struct s2mu005_regulator_data *regulators;
#ifdef CONFIG_VIBETONZ
/* haptic motor data */
struct s2mu005_haptic_platform_data *haptic_data;
#endif
struct mfd_cell *sub_devices;
int num_subdevs;
};
struct s2mu005
{
struct regmap *regmap;
};
#endif /* __S2MU005_H__ */

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/* s5m8763.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_S5M8763_H
#define __LINUX_MFD_S5M8763_H
/* S5M8763 registers */
enum s5m8763_reg {
S5M8763_REG_IRQ1,
S5M8763_REG_IRQ2,
S5M8763_REG_IRQ3,
S5M8763_REG_IRQ4,
S5M8763_REG_IRQM1,
S5M8763_REG_IRQM2,
S5M8763_REG_IRQM3,
S5M8763_REG_IRQM4,
S5M8763_REG_STATUS1,
S5M8763_REG_STATUS2,
S5M8763_REG_STATUSM1,
S5M8763_REG_STATUSM2,
S5M8763_REG_CHGR1,
S5M8763_REG_CHGR2,
S5M8763_REG_LDO_ACTIVE_DISCHARGE1,
S5M8763_REG_LDO_ACTIVE_DISCHARGE2,
S5M8763_REG_BUCK_ACTIVE_DISCHARGE3,
S5M8763_REG_ONOFF1,
S5M8763_REG_ONOFF2,
S5M8763_REG_ONOFF3,
S5M8763_REG_ONOFF4,
S5M8763_REG_BUCK1_VOLTAGE1,
S5M8763_REG_BUCK1_VOLTAGE2,
S5M8763_REG_BUCK1_VOLTAGE3,
S5M8763_REG_BUCK1_VOLTAGE4,
S5M8763_REG_BUCK2_VOLTAGE1,
S5M8763_REG_BUCK2_VOLTAGE2,
S5M8763_REG_BUCK3,
S5M8763_REG_BUCK4,
S5M8763_REG_LDO1_LDO2,
S5M8763_REG_LDO3,
S5M8763_REG_LDO4,
S5M8763_REG_LDO5,
S5M8763_REG_LDO6,
S5M8763_REG_LDO7,
S5M8763_REG_LDO7_LDO8,
S5M8763_REG_LDO9_LDO10,
S5M8763_REG_LDO11,
S5M8763_REG_LDO12,
S5M8763_REG_LDO13,
S5M8763_REG_LDO14,
S5M8763_REG_LDO15,
S5M8763_REG_LDO16,
S5M8763_REG_BKCHR,
S5M8763_REG_LBCNFG1,
S5M8763_REG_LBCNFG2,
};
/* S5M8763 regulator ids */
enum s5m8763_regulators {
S5M8763_LDO1,
S5M8763_LDO2,
S5M8763_LDO3,
S5M8763_LDO4,
S5M8763_LDO5,
S5M8763_LDO6,
S5M8763_LDO7,
S5M8763_LDO8,
S5M8763_LDO9,
S5M8763_LDO10,
S5M8763_LDO11,
S5M8763_LDO12,
S5M8763_LDO13,
S5M8763_LDO14,
S5M8763_LDO15,
S5M8763_LDO16,
S5M8763_BUCK1,
S5M8763_BUCK2,
S5M8763_BUCK3,
S5M8763_BUCK4,
S5M8763_AP_EN32KHZ,
S5M8763_CP_EN32KHZ,
S5M8763_ENCHGVI,
S5M8763_ESAFEUSB1,
S5M8763_ESAFEUSB2,
};
#define S5M8763_ENRAMP (1 << 4)
#endif /* __LINUX_MFD_S5M8763_H */

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/* s5m8767.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __LINUX_MFD_S5M8767_H
#define __LINUX_MFD_S5M8767_H
/* S5M8767 registers */
enum s5m8767_reg {
S5M8767_REG_ID,
S5M8767_REG_INT1,
S5M8767_REG_INT2,
S5M8767_REG_INT3,
S5M8767_REG_INT1M,
S5M8767_REG_INT2M,
S5M8767_REG_INT3M,
S5M8767_REG_STATUS1,
S5M8767_REG_STATUS2,
S5M8767_REG_STATUS3,
S5M8767_REG_CTRL1,
S5M8767_REG_CTRL2,
S5M8767_REG_LOWBAT1,
S5M8767_REG_LOWBAT2,
S5M8767_REG_BUCHG,
S5M8767_REG_DVSRAMP,
S5M8767_REG_DVSTIMER2 = 0x10,
S5M8767_REG_DVSTIMER3,
S5M8767_REG_DVSTIMER4,
S5M8767_REG_LDO1,
S5M8767_REG_LDO2,
S5M8767_REG_LDO3,
S5M8767_REG_LDO4,
S5M8767_REG_LDO5,
S5M8767_REG_LDO6,
S5M8767_REG_LDO7,
S5M8767_REG_LDO8,
S5M8767_REG_LDO9,
S5M8767_REG_LDO10,
S5M8767_REG_LDO11,
S5M8767_REG_LDO12,
S5M8767_REG_LDO13,
S5M8767_REG_LDO14 = 0x20,
S5M8767_REG_LDO15,
S5M8767_REG_LDO16,
S5M8767_REG_LDO17,
S5M8767_REG_LDO18,
S5M8767_REG_LDO19,
S5M8767_REG_LDO20,
S5M8767_REG_LDO21,
S5M8767_REG_LDO22,
S5M8767_REG_LDO23,
S5M8767_REG_LDO24,
S5M8767_REG_LDO25,
S5M8767_REG_LDO26,
S5M8767_REG_LDO27,
S5M8767_REG_LDO28,
S5M8767_REG_UVLO = 0x31,
S5M8767_REG_BUCK1CTRL1,
S5M8767_REG_BUCK1CTRL2,
S5M8767_REG_BUCK2CTRL,
S5M8767_REG_BUCK2DVS1,
S5M8767_REG_BUCK2DVS2,
S5M8767_REG_BUCK2DVS3,
S5M8767_REG_BUCK2DVS4,
S5M8767_REG_BUCK2DVS5,
S5M8767_REG_BUCK2DVS6,
S5M8767_REG_BUCK2DVS7,
S5M8767_REG_BUCK2DVS8,
S5M8767_REG_BUCK3CTRL,
S5M8767_REG_BUCK3DVS1,
S5M8767_REG_BUCK3DVS2,
S5M8767_REG_BUCK3DVS3,
S5M8767_REG_BUCK3DVS4,
S5M8767_REG_BUCK3DVS5,
S5M8767_REG_BUCK3DVS6,
S5M8767_REG_BUCK3DVS7,
S5M8767_REG_BUCK3DVS8,
S5M8767_REG_BUCK4CTRL,
S5M8767_REG_BUCK4DVS1,
S5M8767_REG_BUCK4DVS2,
S5M8767_REG_BUCK4DVS3,
S5M8767_REG_BUCK4DVS4,
S5M8767_REG_BUCK4DVS5,
S5M8767_REG_BUCK4DVS6,
S5M8767_REG_BUCK4DVS7,
S5M8767_REG_BUCK4DVS8,
S5M8767_REG_BUCK5CTRL1,
S5M8767_REG_BUCK5CTRL2,
S5M8767_REG_BUCK5CTRL3,
S5M8767_REG_BUCK5CTRL4,
S5M8767_REG_BUCK5CTRL5,
S5M8767_REG_BUCK6CTRL1,
S5M8767_REG_BUCK6CTRL2,
S5M8767_REG_BUCK7CTRL1,
S5M8767_REG_BUCK7CTRL2,
S5M8767_REG_BUCK8CTRL1,
S5M8767_REG_BUCK8CTRL2,
S5M8767_REG_BUCK9CTRL1,
S5M8767_REG_BUCK9CTRL2,
S5M8767_REG_LDO1CTRL,
S5M8767_REG_LDO2_1CTRL,
S5M8767_REG_LDO2_2CTRL,
S5M8767_REG_LDO2_3CTRL,
S5M8767_REG_LDO2_4CTRL,
S5M8767_REG_LDO3CTRL,
S5M8767_REG_LDO4CTRL,
S5M8767_REG_LDO5CTRL,
S5M8767_REG_LDO6CTRL,
S5M8767_REG_LDO7CTRL,
S5M8767_REG_LDO8CTRL,
S5M8767_REG_LDO9CTRL,
S5M8767_REG_LDO10CTRL,
S5M8767_REG_LDO11CTRL,
S5M8767_REG_LDO12CTRL,
S5M8767_REG_LDO13CTRL,
S5M8767_REG_LDO14CTRL,
S5M8767_REG_LDO15CTRL,
S5M8767_REG_LDO16CTRL,
S5M8767_REG_LDO17CTRL,
S5M8767_REG_LDO18CTRL,
S5M8767_REG_LDO19CTRL,
S5M8767_REG_LDO20CTRL,
S5M8767_REG_LDO21CTRL,
S5M8767_REG_LDO22CTRL,
S5M8767_REG_LDO23CTRL,
S5M8767_REG_LDO24CTRL,
S5M8767_REG_LDO25CTRL,
S5M8767_REG_LDO26CTRL,
S5M8767_REG_LDO27CTRL,
S5M8767_REG_LDO28CTRL,
};
/* S5M8767 regulator ids */
enum s5m8767_regulators {
S5M8767_LDO1,
S5M8767_LDO2,
S5M8767_LDO3,
S5M8767_LDO4,
S5M8767_LDO5,
S5M8767_LDO6,
S5M8767_LDO7,
S5M8767_LDO8,
S5M8767_LDO9,
S5M8767_LDO10,
S5M8767_LDO11,
S5M8767_LDO12,
S5M8767_LDO13,
S5M8767_LDO14,
S5M8767_LDO15,
S5M8767_LDO16,
S5M8767_LDO17,
S5M8767_LDO18,
S5M8767_LDO19,
S5M8767_LDO20,
S5M8767_LDO21,
S5M8767_LDO22,
S5M8767_LDO23,
S5M8767_LDO24,
S5M8767_LDO25,
S5M8767_LDO26,
S5M8767_LDO27,
S5M8767_LDO28,
S5M8767_BUCK1,
S5M8767_BUCK2,
S5M8767_BUCK3,
S5M8767_BUCK4,
S5M8767_BUCK5,
S5M8767_BUCK6,
S5M8767_BUCK7,
S5M8767_BUCK8,
S5M8767_BUCK9,
S5M8767_AP_EN32KHZ,
S5M8767_CP_EN32KHZ,
S5M8767_REG_MAX,
};
#define S5M8767_ENCTRL_SHIFT 6
#endif /* __LINUX_MFD_S5M8767_H */