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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
commit f6dfaef42e
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218
include/linux/mfd/wm831x/auxadc.h Normal file
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/*
* include/linux/mfd/wm831x/auxadc.h -- Auxiliary ADC interface for WM831x
*
* Copyright 2009 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __MFD_WM831X_AUXADC_H__
#define __MFD_WM831X_AUXADC_H__
struct wm831x;
/*
* R16429 (0x402D) - AuxADC Data
*/
#define WM831X_AUX_DATA_SRC_MASK 0xF000 /* AUX_DATA_SRC - [15:12] */
#define WM831X_AUX_DATA_SRC_SHIFT 12 /* AUX_DATA_SRC - [15:12] */
#define WM831X_AUX_DATA_SRC_WIDTH 4 /* AUX_DATA_SRC - [15:12] */
#define WM831X_AUX_DATA_MASK 0x0FFF /* AUX_DATA - [11:0] */
#define WM831X_AUX_DATA_SHIFT 0 /* AUX_DATA - [11:0] */
#define WM831X_AUX_DATA_WIDTH 12 /* AUX_DATA - [11:0] */
/*
* R16430 (0x402E) - AuxADC Control
*/
#define WM831X_AUX_ENA 0x8000 /* AUX_ENA */
#define WM831X_AUX_ENA_MASK 0x8000 /* AUX_ENA */
#define WM831X_AUX_ENA_SHIFT 15 /* AUX_ENA */
#define WM831X_AUX_ENA_WIDTH 1 /* AUX_ENA */
#define WM831X_AUX_CVT_ENA 0x4000 /* AUX_CVT_ENA */
#define WM831X_AUX_CVT_ENA_MASK 0x4000 /* AUX_CVT_ENA */
#define WM831X_AUX_CVT_ENA_SHIFT 14 /* AUX_CVT_ENA */
#define WM831X_AUX_CVT_ENA_WIDTH 1 /* AUX_CVT_ENA */
#define WM831X_AUX_SLPENA 0x1000 /* AUX_SLPENA */
#define WM831X_AUX_SLPENA_MASK 0x1000 /* AUX_SLPENA */
#define WM831X_AUX_SLPENA_SHIFT 12 /* AUX_SLPENA */
#define WM831X_AUX_SLPENA_WIDTH 1 /* AUX_SLPENA */
#define WM831X_AUX_FRC_ENA 0x0800 /* AUX_FRC_ENA */
#define WM831X_AUX_FRC_ENA_MASK 0x0800 /* AUX_FRC_ENA */
#define WM831X_AUX_FRC_ENA_SHIFT 11 /* AUX_FRC_ENA */
#define WM831X_AUX_FRC_ENA_WIDTH 1 /* AUX_FRC_ENA */
#define WM831X_AUX_RATE_MASK 0x003F /* AUX_RATE - [5:0] */
#define WM831X_AUX_RATE_SHIFT 0 /* AUX_RATE - [5:0] */
#define WM831X_AUX_RATE_WIDTH 6 /* AUX_RATE - [5:0] */
/*
* R16431 (0x402F) - AuxADC Source
*/
#define WM831X_AUX_CAL_SEL 0x8000 /* AUX_CAL_SEL */
#define WM831X_AUX_CAL_SEL_MASK 0x8000 /* AUX_CAL_SEL */
#define WM831X_AUX_CAL_SEL_SHIFT 15 /* AUX_CAL_SEL */
#define WM831X_AUX_CAL_SEL_WIDTH 1 /* AUX_CAL_SEL */
#define WM831X_AUX_BKUP_BATT_SEL 0x0400 /* AUX_BKUP_BATT_SEL */
#define WM831X_AUX_BKUP_BATT_SEL_MASK 0x0400 /* AUX_BKUP_BATT_SEL */
#define WM831X_AUX_BKUP_BATT_SEL_SHIFT 10 /* AUX_BKUP_BATT_SEL */
#define WM831X_AUX_BKUP_BATT_SEL_WIDTH 1 /* AUX_BKUP_BATT_SEL */
#define WM831X_AUX_WALL_SEL 0x0200 /* AUX_WALL_SEL */
#define WM831X_AUX_WALL_SEL_MASK 0x0200 /* AUX_WALL_SEL */
#define WM831X_AUX_WALL_SEL_SHIFT 9 /* AUX_WALL_SEL */
#define WM831X_AUX_WALL_SEL_WIDTH 1 /* AUX_WALL_SEL */
#define WM831X_AUX_BATT_SEL 0x0100 /* AUX_BATT_SEL */
#define WM831X_AUX_BATT_SEL_MASK 0x0100 /* AUX_BATT_SEL */
#define WM831X_AUX_BATT_SEL_SHIFT 8 /* AUX_BATT_SEL */
#define WM831X_AUX_BATT_SEL_WIDTH 1 /* AUX_BATT_SEL */
#define WM831X_AUX_USB_SEL 0x0080 /* AUX_USB_SEL */
#define WM831X_AUX_USB_SEL_MASK 0x0080 /* AUX_USB_SEL */
#define WM831X_AUX_USB_SEL_SHIFT 7 /* AUX_USB_SEL */
#define WM831X_AUX_USB_SEL_WIDTH 1 /* AUX_USB_SEL */
#define WM831X_AUX_SYSVDD_SEL 0x0040 /* AUX_SYSVDD_SEL */
#define WM831X_AUX_SYSVDD_SEL_MASK 0x0040 /* AUX_SYSVDD_SEL */
#define WM831X_AUX_SYSVDD_SEL_SHIFT 6 /* AUX_SYSVDD_SEL */
#define WM831X_AUX_SYSVDD_SEL_WIDTH 1 /* AUX_SYSVDD_SEL */
#define WM831X_AUX_BATT_TEMP_SEL 0x0020 /* AUX_BATT_TEMP_SEL */
#define WM831X_AUX_BATT_TEMP_SEL_MASK 0x0020 /* AUX_BATT_TEMP_SEL */
#define WM831X_AUX_BATT_TEMP_SEL_SHIFT 5 /* AUX_BATT_TEMP_SEL */
#define WM831X_AUX_BATT_TEMP_SEL_WIDTH 1 /* AUX_BATT_TEMP_SEL */
#define WM831X_AUX_CHIP_TEMP_SEL 0x0010 /* AUX_CHIP_TEMP_SEL */
#define WM831X_AUX_CHIP_TEMP_SEL_MASK 0x0010 /* AUX_CHIP_TEMP_SEL */
#define WM831X_AUX_CHIP_TEMP_SEL_SHIFT 4 /* AUX_CHIP_TEMP_SEL */
#define WM831X_AUX_CHIP_TEMP_SEL_WIDTH 1 /* AUX_CHIP_TEMP_SEL */
#define WM831X_AUX_AUX4_SEL 0x0008 /* AUX_AUX4_SEL */
#define WM831X_AUX_AUX4_SEL_MASK 0x0008 /* AUX_AUX4_SEL */
#define WM831X_AUX_AUX4_SEL_SHIFT 3 /* AUX_AUX4_SEL */
#define WM831X_AUX_AUX4_SEL_WIDTH 1 /* AUX_AUX4_SEL */
#define WM831X_AUX_AUX3_SEL 0x0004 /* AUX_AUX3_SEL */
#define WM831X_AUX_AUX3_SEL_MASK 0x0004 /* AUX_AUX3_SEL */
#define WM831X_AUX_AUX3_SEL_SHIFT 2 /* AUX_AUX3_SEL */
#define WM831X_AUX_AUX3_SEL_WIDTH 1 /* AUX_AUX3_SEL */
#define WM831X_AUX_AUX2_SEL 0x0002 /* AUX_AUX2_SEL */
#define WM831X_AUX_AUX2_SEL_MASK 0x0002 /* AUX_AUX2_SEL */
#define WM831X_AUX_AUX2_SEL_SHIFT 1 /* AUX_AUX2_SEL */
#define WM831X_AUX_AUX2_SEL_WIDTH 1 /* AUX_AUX2_SEL */
#define WM831X_AUX_AUX1_SEL 0x0001 /* AUX_AUX1_SEL */
#define WM831X_AUX_AUX1_SEL_MASK 0x0001 /* AUX_AUX1_SEL */
#define WM831X_AUX_AUX1_SEL_SHIFT 0 /* AUX_AUX1_SEL */
#define WM831X_AUX_AUX1_SEL_WIDTH 1 /* AUX_AUX1_SEL */
/*
* R16432 (0x4030) - Comparator Control
*/
#define WM831X_DCOMP4_STS 0x0800 /* DCOMP4_STS */
#define WM831X_DCOMP4_STS_MASK 0x0800 /* DCOMP4_STS */
#define WM831X_DCOMP4_STS_SHIFT 11 /* DCOMP4_STS */
#define WM831X_DCOMP4_STS_WIDTH 1 /* DCOMP4_STS */
#define WM831X_DCOMP3_STS 0x0400 /* DCOMP3_STS */
#define WM831X_DCOMP3_STS_MASK 0x0400 /* DCOMP3_STS */
#define WM831X_DCOMP3_STS_SHIFT 10 /* DCOMP3_STS */
#define WM831X_DCOMP3_STS_WIDTH 1 /* DCOMP3_STS */
#define WM831X_DCOMP2_STS 0x0200 /* DCOMP2_STS */
#define WM831X_DCOMP2_STS_MASK 0x0200 /* DCOMP2_STS */
#define WM831X_DCOMP2_STS_SHIFT 9 /* DCOMP2_STS */
#define WM831X_DCOMP2_STS_WIDTH 1 /* DCOMP2_STS */
#define WM831X_DCOMP1_STS 0x0100 /* DCOMP1_STS */
#define WM831X_DCOMP1_STS_MASK 0x0100 /* DCOMP1_STS */
#define WM831X_DCOMP1_STS_SHIFT 8 /* DCOMP1_STS */
#define WM831X_DCOMP1_STS_WIDTH 1 /* DCOMP1_STS */
#define WM831X_DCMP4_ENA 0x0008 /* DCMP4_ENA */
#define WM831X_DCMP4_ENA_MASK 0x0008 /* DCMP4_ENA */
#define WM831X_DCMP4_ENA_SHIFT 3 /* DCMP4_ENA */
#define WM831X_DCMP4_ENA_WIDTH 1 /* DCMP4_ENA */
#define WM831X_DCMP3_ENA 0x0004 /* DCMP3_ENA */
#define WM831X_DCMP3_ENA_MASK 0x0004 /* DCMP3_ENA */
#define WM831X_DCMP3_ENA_SHIFT 2 /* DCMP3_ENA */
#define WM831X_DCMP3_ENA_WIDTH 1 /* DCMP3_ENA */
#define WM831X_DCMP2_ENA 0x0002 /* DCMP2_ENA */
#define WM831X_DCMP2_ENA_MASK 0x0002 /* DCMP2_ENA */
#define WM831X_DCMP2_ENA_SHIFT 1 /* DCMP2_ENA */
#define WM831X_DCMP2_ENA_WIDTH 1 /* DCMP2_ENA */
#define WM831X_DCMP1_ENA 0x0001 /* DCMP1_ENA */
#define WM831X_DCMP1_ENA_MASK 0x0001 /* DCMP1_ENA */
#define WM831X_DCMP1_ENA_SHIFT 0 /* DCMP1_ENA */
#define WM831X_DCMP1_ENA_WIDTH 1 /* DCMP1_ENA */
/*
* R16433 (0x4031) - Comparator 1
*/
#define WM831X_DCMP1_SRC_MASK 0xE000 /* DCMP1_SRC - [15:13] */
#define WM831X_DCMP1_SRC_SHIFT 13 /* DCMP1_SRC - [15:13] */
#define WM831X_DCMP1_SRC_WIDTH 3 /* DCMP1_SRC - [15:13] */
#define WM831X_DCMP1_GT 0x1000 /* DCMP1_GT */
#define WM831X_DCMP1_GT_MASK 0x1000 /* DCMP1_GT */
#define WM831X_DCMP1_GT_SHIFT 12 /* DCMP1_GT */
#define WM831X_DCMP1_GT_WIDTH 1 /* DCMP1_GT */
#define WM831X_DCMP1_THR_MASK 0x0FFF /* DCMP1_THR - [11:0] */
#define WM831X_DCMP1_THR_SHIFT 0 /* DCMP1_THR - [11:0] */
#define WM831X_DCMP1_THR_WIDTH 12 /* DCMP1_THR - [11:0] */
/*
* R16434 (0x4032) - Comparator 2
*/
#define WM831X_DCMP2_SRC_MASK 0xE000 /* DCMP2_SRC - [15:13] */
#define WM831X_DCMP2_SRC_SHIFT 13 /* DCMP2_SRC - [15:13] */
#define WM831X_DCMP2_SRC_WIDTH 3 /* DCMP2_SRC - [15:13] */
#define WM831X_DCMP2_GT 0x1000 /* DCMP2_GT */
#define WM831X_DCMP2_GT_MASK 0x1000 /* DCMP2_GT */
#define WM831X_DCMP2_GT_SHIFT 12 /* DCMP2_GT */
#define WM831X_DCMP2_GT_WIDTH 1 /* DCMP2_GT */
#define WM831X_DCMP2_THR_MASK 0x0FFF /* DCMP2_THR - [11:0] */
#define WM831X_DCMP2_THR_SHIFT 0 /* DCMP2_THR - [11:0] */
#define WM831X_DCMP2_THR_WIDTH 12 /* DCMP2_THR - [11:0] */
/*
* R16435 (0x4033) - Comparator 3
*/
#define WM831X_DCMP3_SRC_MASK 0xE000 /* DCMP3_SRC - [15:13] */
#define WM831X_DCMP3_SRC_SHIFT 13 /* DCMP3_SRC - [15:13] */
#define WM831X_DCMP3_SRC_WIDTH 3 /* DCMP3_SRC - [15:13] */
#define WM831X_DCMP3_GT 0x1000 /* DCMP3_GT */
#define WM831X_DCMP3_GT_MASK 0x1000 /* DCMP3_GT */
#define WM831X_DCMP3_GT_SHIFT 12 /* DCMP3_GT */
#define WM831X_DCMP3_GT_WIDTH 1 /* DCMP3_GT */
#define WM831X_DCMP3_THR_MASK 0x0FFF /* DCMP3_THR - [11:0] */
#define WM831X_DCMP3_THR_SHIFT 0 /* DCMP3_THR - [11:0] */
#define WM831X_DCMP3_THR_WIDTH 12 /* DCMP3_THR - [11:0] */
/*
* R16436 (0x4034) - Comparator 4
*/
#define WM831X_DCMP4_SRC_MASK 0xE000 /* DCMP4_SRC - [15:13] */
#define WM831X_DCMP4_SRC_SHIFT 13 /* DCMP4_SRC - [15:13] */
#define WM831X_DCMP4_SRC_WIDTH 3 /* DCMP4_SRC - [15:13] */
#define WM831X_DCMP4_GT 0x1000 /* DCMP4_GT */
#define WM831X_DCMP4_GT_MASK 0x1000 /* DCMP4_GT */
#define WM831X_DCMP4_GT_SHIFT 12 /* DCMP4_GT */
#define WM831X_DCMP4_GT_WIDTH 1 /* DCMP4_GT */
#define WM831X_DCMP4_THR_MASK 0x0FFF /* DCMP4_THR - [11:0] */
#define WM831X_DCMP4_THR_SHIFT 0 /* DCMP4_THR - [11:0] */
#define WM831X_DCMP4_THR_WIDTH 12 /* DCMP4_THR - [11:0] */
#define WM831X_AUX_CAL_FACTOR 0xfff
#define WM831X_AUX_CAL_NOMINAL 0x222
enum wm831x_auxadc {
WM831X_AUX_CAL = 15,
WM831X_AUX_BKUP_BATT = 10,
WM831X_AUX_WALL = 9,
WM831X_AUX_BATT = 8,
WM831X_AUX_USB = 7,
WM831X_AUX_SYSVDD = 6,
WM831X_AUX_BATT_TEMP = 5,
WM831X_AUX_CHIP_TEMP = 4,
WM831X_AUX_AUX4 = 3,
WM831X_AUX_AUX3 = 2,
WM831X_AUX_AUX2 = 1,
WM831X_AUX_AUX1 = 0,
};
int wm831x_auxadc_read(struct wm831x *wm831x, enum wm831x_auxadc input);
int wm831x_auxadc_read_uv(struct wm831x *wm831x, enum wm831x_auxadc input);
#endif

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include/linux/mfd/wm831x/core.h Normal file
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/*
* include/linux/mfd/wm831x/core.h -- Core interface for WM831x
*
* Copyright 2009 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __MFD_WM831X_CORE_H__
#define __MFD_WM831X_CORE_H__
#include <linux/completion.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/list.h>
#include <linux/regmap.h>
#include <linux/mfd/wm831x/auxadc.h>
/*
* Register values.
*/
#define WM831X_RESET_ID 0x00
#define WM831X_REVISION 0x01
#define WM831X_PARENT_ID 0x4000
#define WM831X_SYSVDD_CONTROL 0x4001
#define WM831X_THERMAL_MONITORING 0x4002
#define WM831X_POWER_STATE 0x4003
#define WM831X_WATCHDOG 0x4004
#define WM831X_ON_PIN_CONTROL 0x4005
#define WM831X_RESET_CONTROL 0x4006
#define WM831X_CONTROL_INTERFACE 0x4007
#define WM831X_SECURITY_KEY 0x4008
#define WM831X_SOFTWARE_SCRATCH 0x4009
#define WM831X_OTP_CONTROL 0x400A
#define WM831X_GPIO_LEVEL 0x400C
#define WM831X_SYSTEM_STATUS 0x400D
#define WM831X_ON_SOURCE 0x400E
#define WM831X_OFF_SOURCE 0x400F
#define WM831X_SYSTEM_INTERRUPTS 0x4010
#define WM831X_INTERRUPT_STATUS_1 0x4011
#define WM831X_INTERRUPT_STATUS_2 0x4012
#define WM831X_INTERRUPT_STATUS_3 0x4013
#define WM831X_INTERRUPT_STATUS_4 0x4014
#define WM831X_INTERRUPT_STATUS_5 0x4015
#define WM831X_IRQ_CONFIG 0x4017
#define WM831X_SYSTEM_INTERRUPTS_MASK 0x4018
#define WM831X_INTERRUPT_STATUS_1_MASK 0x4019
#define WM831X_INTERRUPT_STATUS_2_MASK 0x401A
#define WM831X_INTERRUPT_STATUS_3_MASK 0x401B
#define WM831X_INTERRUPT_STATUS_4_MASK 0x401C
#define WM831X_INTERRUPT_STATUS_5_MASK 0x401D
#define WM831X_RTC_WRITE_COUNTER 0x4020
#define WM831X_RTC_TIME_1 0x4021
#define WM831X_RTC_TIME_2 0x4022
#define WM831X_RTC_ALARM_1 0x4023
#define WM831X_RTC_ALARM_2 0x4024
#define WM831X_RTC_CONTROL 0x4025
#define WM831X_RTC_TRIM 0x4026
#define WM831X_TOUCH_CONTROL_1 0x4028
#define WM831X_TOUCH_CONTROL_2 0x4029
#define WM831X_TOUCH_DATA_X 0x402A
#define WM831X_TOUCH_DATA_Y 0x402B
#define WM831X_TOUCH_DATA_Z 0x402C
#define WM831X_AUXADC_DATA 0x402D
#define WM831X_AUXADC_CONTROL 0x402E
#define WM831X_AUXADC_SOURCE 0x402F
#define WM831X_COMPARATOR_CONTROL 0x4030
#define WM831X_COMPARATOR_1 0x4031
#define WM831X_COMPARATOR_2 0x4032
#define WM831X_COMPARATOR_3 0x4033
#define WM831X_COMPARATOR_4 0x4034
#define WM831X_GPIO1_CONTROL 0x4038
#define WM831X_GPIO2_CONTROL 0x4039
#define WM831X_GPIO3_CONTROL 0x403A
#define WM831X_GPIO4_CONTROL 0x403B
#define WM831X_GPIO5_CONTROL 0x403C
#define WM831X_GPIO6_CONTROL 0x403D
#define WM831X_GPIO7_CONTROL 0x403E
#define WM831X_GPIO8_CONTROL 0x403F
#define WM831X_GPIO9_CONTROL 0x4040
#define WM831X_GPIO10_CONTROL 0x4041
#define WM831X_GPIO11_CONTROL 0x4042
#define WM831X_GPIO12_CONTROL 0x4043
#define WM831X_GPIO13_CONTROL 0x4044
#define WM831X_GPIO14_CONTROL 0x4045
#define WM831X_GPIO15_CONTROL 0x4046
#define WM831X_GPIO16_CONTROL 0x4047
#define WM831X_CHARGER_CONTROL_1 0x4048
#define WM831X_CHARGER_CONTROL_2 0x4049
#define WM831X_CHARGER_STATUS 0x404A
#define WM831X_BACKUP_CHARGER_CONTROL 0x404B
#define WM831X_STATUS_LED_1 0x404C
#define WM831X_STATUS_LED_2 0x404D
#define WM831X_CURRENT_SINK_1 0x404E
#define WM831X_CURRENT_SINK_2 0x404F
#define WM831X_DCDC_ENABLE 0x4050
#define WM831X_LDO_ENABLE 0x4051
#define WM831X_DCDC_STATUS 0x4052
#define WM831X_LDO_STATUS 0x4053
#define WM831X_DCDC_UV_STATUS 0x4054
#define WM831X_LDO_UV_STATUS 0x4055
#define WM831X_DC1_CONTROL_1 0x4056
#define WM831X_DC1_CONTROL_2 0x4057
#define WM831X_DC1_ON_CONFIG 0x4058
#define WM831X_DC1_SLEEP_CONTROL 0x4059
#define WM831X_DC1_DVS_CONTROL 0x405A
#define WM831X_DC2_CONTROL_1 0x405B
#define WM831X_DC2_CONTROL_2 0x405C
#define WM831X_DC2_ON_CONFIG 0x405D
#define WM831X_DC2_SLEEP_CONTROL 0x405E
#define WM831X_DC2_DVS_CONTROL 0x405F
#define WM831X_DC3_CONTROL_1 0x4060
#define WM831X_DC3_CONTROL_2 0x4061
#define WM831X_DC3_ON_CONFIG 0x4062
#define WM831X_DC3_SLEEP_CONTROL 0x4063
#define WM831X_DC4_CONTROL 0x4064
#define WM831X_DC4_SLEEP_CONTROL 0x4065
#define WM832X_DC4_SLEEP_CONTROL 0x4067
#define WM831X_EPE1_CONTROL 0x4066
#define WM831X_EPE2_CONTROL 0x4067
#define WM831X_LDO1_CONTROL 0x4068
#define WM831X_LDO1_ON_CONTROL 0x4069
#define WM831X_LDO1_SLEEP_CONTROL 0x406A
#define WM831X_LDO2_CONTROL 0x406B
#define WM831X_LDO2_ON_CONTROL 0x406C
#define WM831X_LDO2_SLEEP_CONTROL 0x406D
#define WM831X_LDO3_CONTROL 0x406E
#define WM831X_LDO3_ON_CONTROL 0x406F
#define WM831X_LDO3_SLEEP_CONTROL 0x4070
#define WM831X_LDO4_CONTROL 0x4071
#define WM831X_LDO4_ON_CONTROL 0x4072
#define WM831X_LDO4_SLEEP_CONTROL 0x4073
#define WM831X_LDO5_CONTROL 0x4074
#define WM831X_LDO5_ON_CONTROL 0x4075
#define WM831X_LDO5_SLEEP_CONTROL 0x4076
#define WM831X_LDO6_CONTROL 0x4077
#define WM831X_LDO6_ON_CONTROL 0x4078
#define WM831X_LDO6_SLEEP_CONTROL 0x4079
#define WM831X_LDO7_CONTROL 0x407A
#define WM831X_LDO7_ON_CONTROL 0x407B
#define WM831X_LDO7_SLEEP_CONTROL 0x407C
#define WM831X_LDO8_CONTROL 0x407D
#define WM831X_LDO8_ON_CONTROL 0x407E
#define WM831X_LDO8_SLEEP_CONTROL 0x407F
#define WM831X_LDO9_CONTROL 0x4080
#define WM831X_LDO9_ON_CONTROL 0x4081
#define WM831X_LDO9_SLEEP_CONTROL 0x4082
#define WM831X_LDO10_CONTROL 0x4083
#define WM831X_LDO10_ON_CONTROL 0x4084
#define WM831X_LDO10_SLEEP_CONTROL 0x4085
#define WM831X_LDO11_ON_CONTROL 0x4087
#define WM831X_LDO11_SLEEP_CONTROL 0x4088
#define WM831X_POWER_GOOD_SOURCE_1 0x408E
#define WM831X_POWER_GOOD_SOURCE_2 0x408F
#define WM831X_CLOCK_CONTROL_1 0x4090
#define WM831X_CLOCK_CONTROL_2 0x4091
#define WM831X_FLL_CONTROL_1 0x4092
#define WM831X_FLL_CONTROL_2 0x4093
#define WM831X_FLL_CONTROL_3 0x4094
#define WM831X_FLL_CONTROL_4 0x4095
#define WM831X_FLL_CONTROL_5 0x4096
#define WM831X_UNIQUE_ID_1 0x7800
#define WM831X_UNIQUE_ID_2 0x7801
#define WM831X_UNIQUE_ID_3 0x7802
#define WM831X_UNIQUE_ID_4 0x7803
#define WM831X_UNIQUE_ID_5 0x7804
#define WM831X_UNIQUE_ID_6 0x7805
#define WM831X_UNIQUE_ID_7 0x7806
#define WM831X_UNIQUE_ID_8 0x7807
#define WM831X_FACTORY_OTP_ID 0x7808
#define WM831X_FACTORY_OTP_1 0x7809
#define WM831X_FACTORY_OTP_2 0x780A
#define WM831X_FACTORY_OTP_3 0x780B
#define WM831X_FACTORY_OTP_4 0x780C
#define WM831X_FACTORY_OTP_5 0x780D
#define WM831X_CUSTOMER_OTP_ID 0x7810
#define WM831X_DC1_OTP_CONTROL 0x7811
#define WM831X_DC2_OTP_CONTROL 0x7812
#define WM831X_DC3_OTP_CONTROL 0x7813
#define WM831X_LDO1_2_OTP_CONTROL 0x7814
#define WM831X_LDO3_4_OTP_CONTROL 0x7815
#define WM831X_LDO5_6_OTP_CONTROL 0x7816
#define WM831X_LDO7_8_OTP_CONTROL 0x7817
#define WM831X_LDO9_10_OTP_CONTROL 0x7818
#define WM831X_LDO11_EPE_CONTROL 0x7819
#define WM831X_GPIO1_OTP_CONTROL 0x781A
#define WM831X_GPIO2_OTP_CONTROL 0x781B
#define WM831X_GPIO3_OTP_CONTROL 0x781C
#define WM831X_GPIO4_OTP_CONTROL 0x781D
#define WM831X_GPIO5_OTP_CONTROL 0x781E
#define WM831X_GPIO6_OTP_CONTROL 0x781F
#define WM831X_DBE_CHECK_DATA 0x7827
/*
* R0 (0x00) - Reset ID
*/
#define WM831X_CHIP_ID_MASK 0xFFFF /* CHIP_ID - [15:0] */
#define WM831X_CHIP_ID_SHIFT 0 /* CHIP_ID - [15:0] */
#define WM831X_CHIP_ID_WIDTH 16 /* CHIP_ID - [15:0] */
/*
* R1 (0x01) - Revision
*/
#define WM831X_PARENT_REV_MASK 0xFF00 /* PARENT_REV - [15:8] */
#define WM831X_PARENT_REV_SHIFT 8 /* PARENT_REV - [15:8] */
#define WM831X_PARENT_REV_WIDTH 8 /* PARENT_REV - [15:8] */
#define WM831X_CHILD_REV_MASK 0x00FF /* CHILD_REV - [7:0] */
#define WM831X_CHILD_REV_SHIFT 0 /* CHILD_REV - [7:0] */
#define WM831X_CHILD_REV_WIDTH 8 /* CHILD_REV - [7:0] */
/*
* R16384 (0x4000) - Parent ID
*/
#define WM831X_PARENT_ID_MASK 0xFFFF /* PARENT_ID - [15:0] */
#define WM831X_PARENT_ID_SHIFT 0 /* PARENT_ID - [15:0] */
#define WM831X_PARENT_ID_WIDTH 16 /* PARENT_ID - [15:0] */
/*
* R16389 (0x4005) - ON Pin Control
*/
#define WM831X_ON_PIN_SECACT_MASK 0x0300 /* ON_PIN_SECACT - [9:8] */
#define WM831X_ON_PIN_SECACT_SHIFT 8 /* ON_PIN_SECACT - [9:8] */
#define WM831X_ON_PIN_SECACT_WIDTH 2 /* ON_PIN_SECACT - [9:8] */
#define WM831X_ON_PIN_PRIMACT_MASK 0x0030 /* ON_PIN_PRIMACT - [5:4] */
#define WM831X_ON_PIN_PRIMACT_SHIFT 4 /* ON_PIN_PRIMACT - [5:4] */
#define WM831X_ON_PIN_PRIMACT_WIDTH 2 /* ON_PIN_PRIMACT - [5:4] */
#define WM831X_ON_PIN_STS 0x0008 /* ON_PIN_STS */
#define WM831X_ON_PIN_STS_MASK 0x0008 /* ON_PIN_STS */
#define WM831X_ON_PIN_STS_SHIFT 3 /* ON_PIN_STS */
#define WM831X_ON_PIN_STS_WIDTH 1 /* ON_PIN_STS */
#define WM831X_ON_PIN_TO_MASK 0x0003 /* ON_PIN_TO - [1:0] */
#define WM831X_ON_PIN_TO_SHIFT 0 /* ON_PIN_TO - [1:0] */
#define WM831X_ON_PIN_TO_WIDTH 2 /* ON_PIN_TO - [1:0] */
/*
* R16528 (0x4090) - Clock Control 1
*/
#define WM831X_CLKOUT_ENA 0x8000 /* CLKOUT_ENA */
#define WM831X_CLKOUT_ENA_MASK 0x8000 /* CLKOUT_ENA */
#define WM831X_CLKOUT_ENA_SHIFT 15 /* CLKOUT_ENA */
#define WM831X_CLKOUT_ENA_WIDTH 1 /* CLKOUT_ENA */
#define WM831X_CLKOUT_OD 0x2000 /* CLKOUT_OD */
#define WM831X_CLKOUT_OD_MASK 0x2000 /* CLKOUT_OD */
#define WM831X_CLKOUT_OD_SHIFT 13 /* CLKOUT_OD */
#define WM831X_CLKOUT_OD_WIDTH 1 /* CLKOUT_OD */
#define WM831X_CLKOUT_SLOT_MASK 0x0700 /* CLKOUT_SLOT - [10:8] */
#define WM831X_CLKOUT_SLOT_SHIFT 8 /* CLKOUT_SLOT - [10:8] */
#define WM831X_CLKOUT_SLOT_WIDTH 3 /* CLKOUT_SLOT - [10:8] */
#define WM831X_CLKOUT_SLPSLOT_MASK 0x0070 /* CLKOUT_SLPSLOT - [6:4] */
#define WM831X_CLKOUT_SLPSLOT_SHIFT 4 /* CLKOUT_SLPSLOT - [6:4] */
#define WM831X_CLKOUT_SLPSLOT_WIDTH 3 /* CLKOUT_SLPSLOT - [6:4] */
#define WM831X_CLKOUT_SRC 0x0001 /* CLKOUT_SRC */
#define WM831X_CLKOUT_SRC_MASK 0x0001 /* CLKOUT_SRC */
#define WM831X_CLKOUT_SRC_SHIFT 0 /* CLKOUT_SRC */
#define WM831X_CLKOUT_SRC_WIDTH 1 /* CLKOUT_SRC */
/*
* R16529 (0x4091) - Clock Control 2
*/
#define WM831X_XTAL_INH 0x8000 /* XTAL_INH */
#define WM831X_XTAL_INH_MASK 0x8000 /* XTAL_INH */
#define WM831X_XTAL_INH_SHIFT 15 /* XTAL_INH */
#define WM831X_XTAL_INH_WIDTH 1 /* XTAL_INH */
#define WM831X_XTAL_ENA 0x2000 /* XTAL_ENA */
#define WM831X_XTAL_ENA_MASK 0x2000 /* XTAL_ENA */
#define WM831X_XTAL_ENA_SHIFT 13 /* XTAL_ENA */
#define WM831X_XTAL_ENA_WIDTH 1 /* XTAL_ENA */
#define WM831X_XTAL_BKUPENA 0x1000 /* XTAL_BKUPENA */
#define WM831X_XTAL_BKUPENA_MASK 0x1000 /* XTAL_BKUPENA */
#define WM831X_XTAL_BKUPENA_SHIFT 12 /* XTAL_BKUPENA */
#define WM831X_XTAL_BKUPENA_WIDTH 1 /* XTAL_BKUPENA */
#define WM831X_FLL_AUTO 0x0080 /* FLL_AUTO */
#define WM831X_FLL_AUTO_MASK 0x0080 /* FLL_AUTO */
#define WM831X_FLL_AUTO_SHIFT 7 /* FLL_AUTO */
#define WM831X_FLL_AUTO_WIDTH 1 /* FLL_AUTO */
#define WM831X_FLL_AUTO_FREQ_MASK 0x0007 /* FLL_AUTO_FREQ - [2:0] */
#define WM831X_FLL_AUTO_FREQ_SHIFT 0 /* FLL_AUTO_FREQ - [2:0] */
#define WM831X_FLL_AUTO_FREQ_WIDTH 3 /* FLL_AUTO_FREQ - [2:0] */
/*
* R16530 (0x4092) - FLL Control 1
*/
#define WM831X_FLL_FRAC 0x0004 /* FLL_FRAC */
#define WM831X_FLL_FRAC_MASK 0x0004 /* FLL_FRAC */
#define WM831X_FLL_FRAC_SHIFT 2 /* FLL_FRAC */
#define WM831X_FLL_FRAC_WIDTH 1 /* FLL_FRAC */
#define WM831X_FLL_OSC_ENA 0x0002 /* FLL_OSC_ENA */
#define WM831X_FLL_OSC_ENA_MASK 0x0002 /* FLL_OSC_ENA */
#define WM831X_FLL_OSC_ENA_SHIFT 1 /* FLL_OSC_ENA */
#define WM831X_FLL_OSC_ENA_WIDTH 1 /* FLL_OSC_ENA */
#define WM831X_FLL_ENA 0x0001 /* FLL_ENA */
#define WM831X_FLL_ENA_MASK 0x0001 /* FLL_ENA */
#define WM831X_FLL_ENA_SHIFT 0 /* FLL_ENA */
#define WM831X_FLL_ENA_WIDTH 1 /* FLL_ENA */
/*
* R16531 (0x4093) - FLL Control 2
*/
#define WM831X_FLL_OUTDIV_MASK 0x3F00 /* FLL_OUTDIV - [13:8] */
#define WM831X_FLL_OUTDIV_SHIFT 8 /* FLL_OUTDIV - [13:8] */
#define WM831X_FLL_OUTDIV_WIDTH 6 /* FLL_OUTDIV - [13:8] */
#define WM831X_FLL_CTRL_RATE_MASK 0x0070 /* FLL_CTRL_RATE - [6:4] */
#define WM831X_FLL_CTRL_RATE_SHIFT 4 /* FLL_CTRL_RATE - [6:4] */
#define WM831X_FLL_CTRL_RATE_WIDTH 3 /* FLL_CTRL_RATE - [6:4] */
#define WM831X_FLL_FRATIO_MASK 0x0007 /* FLL_FRATIO - [2:0] */
#define WM831X_FLL_FRATIO_SHIFT 0 /* FLL_FRATIO - [2:0] */
#define WM831X_FLL_FRATIO_WIDTH 3 /* FLL_FRATIO - [2:0] */
/*
* R16532 (0x4094) - FLL Control 3
*/
#define WM831X_FLL_K_MASK 0xFFFF /* FLL_K - [15:0] */
#define WM831X_FLL_K_SHIFT 0 /* FLL_K - [15:0] */
#define WM831X_FLL_K_WIDTH 16 /* FLL_K - [15:0] */
/*
* R16533 (0x4095) - FLL Control 4
*/
#define WM831X_FLL_N_MASK 0x7FE0 /* FLL_N - [14:5] */
#define WM831X_FLL_N_SHIFT 5 /* FLL_N - [14:5] */
#define WM831X_FLL_N_WIDTH 10 /* FLL_N - [14:5] */
#define WM831X_FLL_GAIN_MASK 0x000F /* FLL_GAIN - [3:0] */
#define WM831X_FLL_GAIN_SHIFT 0 /* FLL_GAIN - [3:0] */
#define WM831X_FLL_GAIN_WIDTH 4 /* FLL_GAIN - [3:0] */
/*
* R16534 (0x4096) - FLL Control 5
*/
#define WM831X_FLL_CLK_REF_DIV_MASK 0x0018 /* FLL_CLK_REF_DIV - [4:3] */
#define WM831X_FLL_CLK_REF_DIV_SHIFT 3 /* FLL_CLK_REF_DIV - [4:3] */
#define WM831X_FLL_CLK_REF_DIV_WIDTH 2 /* FLL_CLK_REF_DIV - [4:3] */
#define WM831X_FLL_CLK_SRC_MASK 0x0003 /* FLL_CLK_SRC - [1:0] */
#define WM831X_FLL_CLK_SRC_SHIFT 0 /* FLL_CLK_SRC - [1:0] */
#define WM831X_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [1:0] */
struct regulator_dev;
struct irq_domain;
#define WM831X_NUM_IRQ_REGS 5
#define WM831X_NUM_GPIO_REGS 16
enum wm831x_parent {
WM8310 = 0x8310,
WM8311 = 0x8311,
WM8312 = 0x8312,
WM8320 = 0x8320,
WM8321 = 0x8321,
WM8325 = 0x8325,
WM8326 = 0x8326,
};
struct wm831x;
typedef int (*wm831x_auxadc_read_fn)(struct wm831x *wm831x,
enum wm831x_auxadc input);
struct wm831x {
struct mutex io_lock;
struct device *dev;
struct regmap *regmap;
int irq; /* Our chip IRQ */
struct mutex irq_lock;
struct irq_domain *irq_domain;
int irq_masks_cur[WM831X_NUM_IRQ_REGS]; /* Currently active value */
int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */
bool soft_shutdown;
/* Chip revision based flags */
unsigned has_gpio_ena:1; /* Has GPIO enable bit */
unsigned has_cs_sts:1; /* Has current sink status bit */
unsigned charger_irq_wake:1; /* Are charger IRQs a wake source? */
int num_gpio;
/* Used by the interrupt controller code to post writes */
int gpio_update[WM831X_NUM_GPIO_REGS];
bool gpio_level_high[WM831X_NUM_GPIO_REGS];
bool gpio_level_low[WM831X_NUM_GPIO_REGS];
struct mutex auxadc_lock;
struct list_head auxadc_pending;
u16 auxadc_active;
wm831x_auxadc_read_fn auxadc_read;
/* The WM831x has a security key blocking access to certain
* registers. The mutex is taken by the accessors for locking
* and unlocking the security key, locked is used to fail
* writes if the lock is held.
*/
struct mutex key_lock;
unsigned int locked:1;
};
/* Device I/O API */
int wm831x_reg_read(struct wm831x *wm831x, unsigned short reg);
int wm831x_reg_write(struct wm831x *wm831x, unsigned short reg,
unsigned short val);
void wm831x_reg_lock(struct wm831x *wm831x);
int wm831x_reg_unlock(struct wm831x *wm831x);
int wm831x_set_bits(struct wm831x *wm831x, unsigned short reg,
unsigned short mask, unsigned short val);
int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg,
int count, u16 *buf);
int wm831x_device_init(struct wm831x *wm831x, unsigned long id, int irq);
void wm831x_device_exit(struct wm831x *wm831x);
int wm831x_device_suspend(struct wm831x *wm831x);
void wm831x_device_shutdown(struct wm831x *wm831x);
int wm831x_irq_init(struct wm831x *wm831x, int irq);
void wm831x_irq_exit(struct wm831x *wm831x);
void wm831x_auxadc_init(struct wm831x *wm831x);
static inline int wm831x_irq(struct wm831x *wm831x, int irq)
{
return irq_create_mapping(wm831x->irq_domain, irq);
}
extern struct regmap_config wm831x_regmap_config;
#endif

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/*
* include/linux/mfd/wm831x/gpio.h -- GPIO for WM831x
*
* Copyright 2009 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __MFD_WM831X_GPIO_H__
#define __MFD_WM831X_GPIO_H__
/*
* R16440-16455 (0x4038-0x4047) - GPIOx Control
*/
#define WM831X_GPN_DIR 0x8000 /* GPN_DIR */
#define WM831X_GPN_DIR_MASK 0x8000 /* GPN_DIR */
#define WM831X_GPN_DIR_SHIFT 15 /* GPN_DIR */
#define WM831X_GPN_DIR_WIDTH 1 /* GPN_DIR */
#define WM831X_GPN_PULL_MASK 0x6000 /* GPN_PULL - [14:13] */
#define WM831X_GPN_PULL_SHIFT 13 /* GPN_PULL - [14:13] */
#define WM831X_GPN_PULL_WIDTH 2 /* GPN_PULL - [14:13] */
#define WM831X_GPN_INT_MODE 0x1000 /* GPN_INT_MODE */
#define WM831X_GPN_INT_MODE_MASK 0x1000 /* GPN_INT_MODE */
#define WM831X_GPN_INT_MODE_SHIFT 12 /* GPN_INT_MODE */
#define WM831X_GPN_INT_MODE_WIDTH 1 /* GPN_INT_MODE */
#define WM831X_GPN_PWR_DOM 0x0800 /* GPN_PWR_DOM */
#define WM831X_GPN_PWR_DOM_MASK 0x0800 /* GPN_PWR_DOM */
#define WM831X_GPN_PWR_DOM_SHIFT 11 /* GPN_PWR_DOM */
#define WM831X_GPN_PWR_DOM_WIDTH 1 /* GPN_PWR_DOM */
#define WM831X_GPN_POL 0x0400 /* GPN_POL */
#define WM831X_GPN_POL_MASK 0x0400 /* GPN_POL */
#define WM831X_GPN_POL_SHIFT 10 /* GPN_POL */
#define WM831X_GPN_POL_WIDTH 1 /* GPN_POL */
#define WM831X_GPN_OD 0x0200 /* GPN_OD */
#define WM831X_GPN_OD_MASK 0x0200 /* GPN_OD */
#define WM831X_GPN_OD_SHIFT 9 /* GPN_OD */
#define WM831X_GPN_OD_WIDTH 1 /* GPN_OD */
#define WM831X_GPN_ENA 0x0080 /* GPN_ENA */
#define WM831X_GPN_ENA_MASK 0x0080 /* GPN_ENA */
#define WM831X_GPN_ENA_SHIFT 7 /* GPN_ENA */
#define WM831X_GPN_ENA_WIDTH 1 /* GPN_ENA */
#define WM831X_GPN_TRI 0x0080 /* GPN_TRI */
#define WM831X_GPN_TRI_MASK 0x0080 /* GPN_TRI */
#define WM831X_GPN_TRI_SHIFT 7 /* GPN_TRI */
#define WM831X_GPN_TRI_WIDTH 1 /* GPN_TRI */
#define WM831X_GPN_FN_MASK 0x000F /* GPN_FN - [3:0] */
#define WM831X_GPN_FN_SHIFT 0 /* GPN_FN - [3:0] */
#define WM831X_GPN_FN_WIDTH 4 /* GPN_FN - [3:0] */
#define WM831X_GPIO_PULL_NONE (0 << WM831X_GPN_PULL_SHIFT)
#define WM831X_GPIO_PULL_DOWN (1 << WM831X_GPN_PULL_SHIFT)
#define WM831X_GPIO_PULL_UP (2 << WM831X_GPN_PULL_SHIFT)
#endif

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/*
* include/linux/mfd/wm831x/irq.h -- Interrupt controller for WM831x
*
* Copyright 2009 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __MFD_WM831X_IRQ_H__
#define __MFD_WM831X_IRQ_H__
/* Interrupt number assignments within Linux */
#define WM831X_IRQ_TEMP_THW 0
#define WM831X_IRQ_GPIO_1 1
#define WM831X_IRQ_GPIO_2 2
#define WM831X_IRQ_GPIO_3 3
#define WM831X_IRQ_GPIO_4 4
#define WM831X_IRQ_GPIO_5 5
#define WM831X_IRQ_GPIO_6 6
#define WM831X_IRQ_GPIO_7 7
#define WM831X_IRQ_GPIO_8 8
#define WM831X_IRQ_GPIO_9 9
#define WM831X_IRQ_GPIO_10 10
#define WM831X_IRQ_GPIO_11 11
#define WM831X_IRQ_GPIO_12 12
#define WM831X_IRQ_GPIO_13 13
#define WM831X_IRQ_GPIO_14 14
#define WM831X_IRQ_GPIO_15 15
#define WM831X_IRQ_GPIO_16 16
#define WM831X_IRQ_ON 17
#define WM831X_IRQ_PPM_SYSLO 18
#define WM831X_IRQ_PPM_PWR_SRC 19
#define WM831X_IRQ_PPM_USB_CURR 20
#define WM831X_IRQ_WDOG_TO 21
#define WM831X_IRQ_RTC_PER 22
#define WM831X_IRQ_RTC_ALM 23
#define WM831X_IRQ_CHG_BATT_HOT 24
#define WM831X_IRQ_CHG_BATT_COLD 25
#define WM831X_IRQ_CHG_BATT_FAIL 26
#define WM831X_IRQ_CHG_OV 27
#define WM831X_IRQ_CHG_END 29
#define WM831X_IRQ_CHG_TO 30
#define WM831X_IRQ_CHG_MODE 31
#define WM831X_IRQ_CHG_START 32
#define WM831X_IRQ_TCHDATA 33
#define WM831X_IRQ_TCHPD 34
#define WM831X_IRQ_AUXADC_DATA 35
#define WM831X_IRQ_AUXADC_DCOMP1 36
#define WM831X_IRQ_AUXADC_DCOMP2 37
#define WM831X_IRQ_AUXADC_DCOMP3 38
#define WM831X_IRQ_AUXADC_DCOMP4 39
#define WM831X_IRQ_CS1 40
#define WM831X_IRQ_CS2 41
#define WM831X_IRQ_HC_DC1 42
#define WM831X_IRQ_HC_DC2 43
#define WM831X_IRQ_UV_LDO1 44
#define WM831X_IRQ_UV_LDO2 45
#define WM831X_IRQ_UV_LDO3 46
#define WM831X_IRQ_UV_LDO4 47
#define WM831X_IRQ_UV_LDO5 48
#define WM831X_IRQ_UV_LDO6 49
#define WM831X_IRQ_UV_LDO7 50
#define WM831X_IRQ_UV_LDO8 51
#define WM831X_IRQ_UV_LDO9 52
#define WM831X_IRQ_UV_LDO10 53
#define WM831X_IRQ_UV_DC1 54
#define WM831X_IRQ_UV_DC2 55
#define WM831X_IRQ_UV_DC3 56
#define WM831X_IRQ_UV_DC4 57
#define WM831X_NUM_IRQS 58
/*
* R16400 (0x4010) - System Interrupts
*/
#define WM831X_PS_INT 0x8000 /* PS_INT */
#define WM831X_PS_INT_MASK 0x8000 /* PS_INT */
#define WM831X_PS_INT_SHIFT 15 /* PS_INT */
#define WM831X_PS_INT_WIDTH 1 /* PS_INT */
#define WM831X_TEMP_INT 0x4000 /* TEMP_INT */
#define WM831X_TEMP_INT_MASK 0x4000 /* TEMP_INT */
#define WM831X_TEMP_INT_SHIFT 14 /* TEMP_INT */
#define WM831X_TEMP_INT_WIDTH 1 /* TEMP_INT */
#define WM831X_GP_INT 0x2000 /* GP_INT */
#define WM831X_GP_INT_MASK 0x2000 /* GP_INT */
#define WM831X_GP_INT_SHIFT 13 /* GP_INT */
#define WM831X_GP_INT_WIDTH 1 /* GP_INT */
#define WM831X_ON_PIN_INT 0x1000 /* ON_PIN_INT */
#define WM831X_ON_PIN_INT_MASK 0x1000 /* ON_PIN_INT */
#define WM831X_ON_PIN_INT_SHIFT 12 /* ON_PIN_INT */
#define WM831X_ON_PIN_INT_WIDTH 1 /* ON_PIN_INT */
#define WM831X_WDOG_INT 0x0800 /* WDOG_INT */
#define WM831X_WDOG_INT_MASK 0x0800 /* WDOG_INT */
#define WM831X_WDOG_INT_SHIFT 11 /* WDOG_INT */
#define WM831X_WDOG_INT_WIDTH 1 /* WDOG_INT */
#define WM831X_TCHDATA_INT 0x0400 /* TCHDATA_INT */
#define WM831X_TCHDATA_INT_MASK 0x0400 /* TCHDATA_INT */
#define WM831X_TCHDATA_INT_SHIFT 10 /* TCHDATA_INT */
#define WM831X_TCHDATA_INT_WIDTH 1 /* TCHDATA_INT */
#define WM831X_TCHPD_INT 0x0200 /* TCHPD_INT */
#define WM831X_TCHPD_INT_MASK 0x0200 /* TCHPD_INT */
#define WM831X_TCHPD_INT_SHIFT 9 /* TCHPD_INT */
#define WM831X_TCHPD_INT_WIDTH 1 /* TCHPD_INT */
#define WM831X_AUXADC_INT 0x0100 /* AUXADC_INT */
#define WM831X_AUXADC_INT_MASK 0x0100 /* AUXADC_INT */
#define WM831X_AUXADC_INT_SHIFT 8 /* AUXADC_INT */
#define WM831X_AUXADC_INT_WIDTH 1 /* AUXADC_INT */
#define WM831X_PPM_INT 0x0080 /* PPM_INT */
#define WM831X_PPM_INT_MASK 0x0080 /* PPM_INT */
#define WM831X_PPM_INT_SHIFT 7 /* PPM_INT */
#define WM831X_PPM_INT_WIDTH 1 /* PPM_INT */
#define WM831X_CS_INT 0x0040 /* CS_INT */
#define WM831X_CS_INT_MASK 0x0040 /* CS_INT */
#define WM831X_CS_INT_SHIFT 6 /* CS_INT */
#define WM831X_CS_INT_WIDTH 1 /* CS_INT */
#define WM831X_RTC_INT 0x0020 /* RTC_INT */
#define WM831X_RTC_INT_MASK 0x0020 /* RTC_INT */
#define WM831X_RTC_INT_SHIFT 5 /* RTC_INT */
#define WM831X_RTC_INT_WIDTH 1 /* RTC_INT */
#define WM831X_OTP_INT 0x0010 /* OTP_INT */
#define WM831X_OTP_INT_MASK 0x0010 /* OTP_INT */
#define WM831X_OTP_INT_SHIFT 4 /* OTP_INT */
#define WM831X_OTP_INT_WIDTH 1 /* OTP_INT */
#define WM831X_CHILD_INT 0x0008 /* CHILD_INT */
#define WM831X_CHILD_INT_MASK 0x0008 /* CHILD_INT */
#define WM831X_CHILD_INT_SHIFT 3 /* CHILD_INT */
#define WM831X_CHILD_INT_WIDTH 1 /* CHILD_INT */
#define WM831X_CHG_INT 0x0004 /* CHG_INT */
#define WM831X_CHG_INT_MASK 0x0004 /* CHG_INT */
#define WM831X_CHG_INT_SHIFT 2 /* CHG_INT */
#define WM831X_CHG_INT_WIDTH 1 /* CHG_INT */
#define WM831X_HC_INT 0x0002 /* HC_INT */
#define WM831X_HC_INT_MASK 0x0002 /* HC_INT */
#define WM831X_HC_INT_SHIFT 1 /* HC_INT */
#define WM831X_HC_INT_WIDTH 1 /* HC_INT */
#define WM831X_UV_INT 0x0001 /* UV_INT */
#define WM831X_UV_INT_MASK 0x0001 /* UV_INT */
#define WM831X_UV_INT_SHIFT 0 /* UV_INT */
#define WM831X_UV_INT_WIDTH 1 /* UV_INT */
/*
* R16401 (0x4011) - Interrupt Status 1
*/
#define WM831X_PPM_SYSLO_EINT 0x8000 /* PPM_SYSLO_EINT */
#define WM831X_PPM_SYSLO_EINT_MASK 0x8000 /* PPM_SYSLO_EINT */
#define WM831X_PPM_SYSLO_EINT_SHIFT 15 /* PPM_SYSLO_EINT */
#define WM831X_PPM_SYSLO_EINT_WIDTH 1 /* PPM_SYSLO_EINT */
#define WM831X_PPM_PWR_SRC_EINT 0x4000 /* PPM_PWR_SRC_EINT */
#define WM831X_PPM_PWR_SRC_EINT_MASK 0x4000 /* PPM_PWR_SRC_EINT */
#define WM831X_PPM_PWR_SRC_EINT_SHIFT 14 /* PPM_PWR_SRC_EINT */
#define WM831X_PPM_PWR_SRC_EINT_WIDTH 1 /* PPM_PWR_SRC_EINT */
#define WM831X_PPM_USB_CURR_EINT 0x2000 /* PPM_USB_CURR_EINT */
#define WM831X_PPM_USB_CURR_EINT_MASK 0x2000 /* PPM_USB_CURR_EINT */
#define WM831X_PPM_USB_CURR_EINT_SHIFT 13 /* PPM_USB_CURR_EINT */
#define WM831X_PPM_USB_CURR_EINT_WIDTH 1 /* PPM_USB_CURR_EINT */
#define WM831X_ON_PIN_EINT 0x1000 /* ON_PIN_EINT */
#define WM831X_ON_PIN_EINT_MASK 0x1000 /* ON_PIN_EINT */
#define WM831X_ON_PIN_EINT_SHIFT 12 /* ON_PIN_EINT */
#define WM831X_ON_PIN_EINT_WIDTH 1 /* ON_PIN_EINT */
#define WM831X_WDOG_TO_EINT 0x0800 /* WDOG_TO_EINT */
#define WM831X_WDOG_TO_EINT_MASK 0x0800 /* WDOG_TO_EINT */
#define WM831X_WDOG_TO_EINT_SHIFT 11 /* WDOG_TO_EINT */
#define WM831X_WDOG_TO_EINT_WIDTH 1 /* WDOG_TO_EINT */
#define WM831X_TCHDATA_EINT 0x0400 /* TCHDATA_EINT */
#define WM831X_TCHDATA_EINT_MASK 0x0400 /* TCHDATA_EINT */
#define WM831X_TCHDATA_EINT_SHIFT 10 /* TCHDATA_EINT */
#define WM831X_TCHDATA_EINT_WIDTH 1 /* TCHDATA_EINT */
#define WM831X_TCHPD_EINT 0x0200 /* TCHPD_EINT */
#define WM831X_TCHPD_EINT_MASK 0x0200 /* TCHPD_EINT */
#define WM831X_TCHPD_EINT_SHIFT 9 /* TCHPD_EINT */
#define WM831X_TCHPD_EINT_WIDTH 1 /* TCHPD_EINT */
#define WM831X_AUXADC_DATA_EINT 0x0100 /* AUXADC_DATA_EINT */
#define WM831X_AUXADC_DATA_EINT_MASK 0x0100 /* AUXADC_DATA_EINT */
#define WM831X_AUXADC_DATA_EINT_SHIFT 8 /* AUXADC_DATA_EINT */
#define WM831X_AUXADC_DATA_EINT_WIDTH 1 /* AUXADC_DATA_EINT */
#define WM831X_AUXADC_DCOMP4_EINT 0x0080 /* AUXADC_DCOMP4_EINT */
#define WM831X_AUXADC_DCOMP4_EINT_MASK 0x0080 /* AUXADC_DCOMP4_EINT */
#define WM831X_AUXADC_DCOMP4_EINT_SHIFT 7 /* AUXADC_DCOMP4_EINT */
#define WM831X_AUXADC_DCOMP4_EINT_WIDTH 1 /* AUXADC_DCOMP4_EINT */
#define WM831X_AUXADC_DCOMP3_EINT 0x0040 /* AUXADC_DCOMP3_EINT */
#define WM831X_AUXADC_DCOMP3_EINT_MASK 0x0040 /* AUXADC_DCOMP3_EINT */
#define WM831X_AUXADC_DCOMP3_EINT_SHIFT 6 /* AUXADC_DCOMP3_EINT */
#define WM831X_AUXADC_DCOMP3_EINT_WIDTH 1 /* AUXADC_DCOMP3_EINT */
#define WM831X_AUXADC_DCOMP2_EINT 0x0020 /* AUXADC_DCOMP2_EINT */
#define WM831X_AUXADC_DCOMP2_EINT_MASK 0x0020 /* AUXADC_DCOMP2_EINT */
#define WM831X_AUXADC_DCOMP2_EINT_SHIFT 5 /* AUXADC_DCOMP2_EINT */
#define WM831X_AUXADC_DCOMP2_EINT_WIDTH 1 /* AUXADC_DCOMP2_EINT */
#define WM831X_AUXADC_DCOMP1_EINT 0x0010 /* AUXADC_DCOMP1_EINT */
#define WM831X_AUXADC_DCOMP1_EINT_MASK 0x0010 /* AUXADC_DCOMP1_EINT */
#define WM831X_AUXADC_DCOMP1_EINT_SHIFT 4 /* AUXADC_DCOMP1_EINT */
#define WM831X_AUXADC_DCOMP1_EINT_WIDTH 1 /* AUXADC_DCOMP1_EINT */
#define WM831X_RTC_PER_EINT 0x0008 /* RTC_PER_EINT */
#define WM831X_RTC_PER_EINT_MASK 0x0008 /* RTC_PER_EINT */
#define WM831X_RTC_PER_EINT_SHIFT 3 /* RTC_PER_EINT */
#define WM831X_RTC_PER_EINT_WIDTH 1 /* RTC_PER_EINT */
#define WM831X_RTC_ALM_EINT 0x0004 /* RTC_ALM_EINT */
#define WM831X_RTC_ALM_EINT_MASK 0x0004 /* RTC_ALM_EINT */
#define WM831X_RTC_ALM_EINT_SHIFT 2 /* RTC_ALM_EINT */
#define WM831X_RTC_ALM_EINT_WIDTH 1 /* RTC_ALM_EINT */
#define WM831X_TEMP_THW_EINT 0x0002 /* TEMP_THW_EINT */
#define WM831X_TEMP_THW_EINT_MASK 0x0002 /* TEMP_THW_EINT */
#define WM831X_TEMP_THW_EINT_SHIFT 1 /* TEMP_THW_EINT */
#define WM831X_TEMP_THW_EINT_WIDTH 1 /* TEMP_THW_EINT */
/*
* R16402 (0x4012) - Interrupt Status 2
*/
#define WM831X_CHG_BATT_HOT_EINT 0x8000 /* CHG_BATT_HOT_EINT */
#define WM831X_CHG_BATT_HOT_EINT_MASK 0x8000 /* CHG_BATT_HOT_EINT */
#define WM831X_CHG_BATT_HOT_EINT_SHIFT 15 /* CHG_BATT_HOT_EINT */
#define WM831X_CHG_BATT_HOT_EINT_WIDTH 1 /* CHG_BATT_HOT_EINT */
#define WM831X_CHG_BATT_COLD_EINT 0x4000 /* CHG_BATT_COLD_EINT */
#define WM831X_CHG_BATT_COLD_EINT_MASK 0x4000 /* CHG_BATT_COLD_EINT */
#define WM831X_CHG_BATT_COLD_EINT_SHIFT 14 /* CHG_BATT_COLD_EINT */
#define WM831X_CHG_BATT_COLD_EINT_WIDTH 1 /* CHG_BATT_COLD_EINT */
#define WM831X_CHG_BATT_FAIL_EINT 0x2000 /* CHG_BATT_FAIL_EINT */
#define WM831X_CHG_BATT_FAIL_EINT_MASK 0x2000 /* CHG_BATT_FAIL_EINT */
#define WM831X_CHG_BATT_FAIL_EINT_SHIFT 13 /* CHG_BATT_FAIL_EINT */
#define WM831X_CHG_BATT_FAIL_EINT_WIDTH 1 /* CHG_BATT_FAIL_EINT */
#define WM831X_CHG_OV_EINT 0x1000 /* CHG_OV_EINT */
#define WM831X_CHG_OV_EINT_MASK 0x1000 /* CHG_OV_EINT */
#define WM831X_CHG_OV_EINT_SHIFT 12 /* CHG_OV_EINT */
#define WM831X_CHG_OV_EINT_WIDTH 1 /* CHG_OV_EINT */
#define WM831X_CHG_END_EINT 0x0800 /* CHG_END_EINT */
#define WM831X_CHG_END_EINT_MASK 0x0800 /* CHG_END_EINT */
#define WM831X_CHG_END_EINT_SHIFT 11 /* CHG_END_EINT */
#define WM831X_CHG_END_EINT_WIDTH 1 /* CHG_END_EINT */
#define WM831X_CHG_TO_EINT 0x0400 /* CHG_TO_EINT */
#define WM831X_CHG_TO_EINT_MASK 0x0400 /* CHG_TO_EINT */
#define WM831X_CHG_TO_EINT_SHIFT 10 /* CHG_TO_EINT */
#define WM831X_CHG_TO_EINT_WIDTH 1 /* CHG_TO_EINT */
#define WM831X_CHG_MODE_EINT 0x0200 /* CHG_MODE_EINT */
#define WM831X_CHG_MODE_EINT_MASK 0x0200 /* CHG_MODE_EINT */
#define WM831X_CHG_MODE_EINT_SHIFT 9 /* CHG_MODE_EINT */
#define WM831X_CHG_MODE_EINT_WIDTH 1 /* CHG_MODE_EINT */
#define WM831X_CHG_START_EINT 0x0100 /* CHG_START_EINT */
#define WM831X_CHG_START_EINT_MASK 0x0100 /* CHG_START_EINT */
#define WM831X_CHG_START_EINT_SHIFT 8 /* CHG_START_EINT */
#define WM831X_CHG_START_EINT_WIDTH 1 /* CHG_START_EINT */
#define WM831X_CS2_EINT 0x0080 /* CS2_EINT */
#define WM831X_CS2_EINT_MASK 0x0080 /* CS2_EINT */
#define WM831X_CS2_EINT_SHIFT 7 /* CS2_EINT */
#define WM831X_CS2_EINT_WIDTH 1 /* CS2_EINT */
#define WM831X_CS1_EINT 0x0040 /* CS1_EINT */
#define WM831X_CS1_EINT_MASK 0x0040 /* CS1_EINT */
#define WM831X_CS1_EINT_SHIFT 6 /* CS1_EINT */
#define WM831X_CS1_EINT_WIDTH 1 /* CS1_EINT */
#define WM831X_OTP_CMD_END_EINT 0x0020 /* OTP_CMD_END_EINT */
#define WM831X_OTP_CMD_END_EINT_MASK 0x0020 /* OTP_CMD_END_EINT */
#define WM831X_OTP_CMD_END_EINT_SHIFT 5 /* OTP_CMD_END_EINT */
#define WM831X_OTP_CMD_END_EINT_WIDTH 1 /* OTP_CMD_END_EINT */
#define WM831X_OTP_ERR_EINT 0x0010 /* OTP_ERR_EINT */
#define WM831X_OTP_ERR_EINT_MASK 0x0010 /* OTP_ERR_EINT */
#define WM831X_OTP_ERR_EINT_SHIFT 4 /* OTP_ERR_EINT */
#define WM831X_OTP_ERR_EINT_WIDTH 1 /* OTP_ERR_EINT */
#define WM831X_PS_POR_EINT 0x0004 /* PS_POR_EINT */
#define WM831X_PS_POR_EINT_MASK 0x0004 /* PS_POR_EINT */
#define WM831X_PS_POR_EINT_SHIFT 2 /* PS_POR_EINT */
#define WM831X_PS_POR_EINT_WIDTH 1 /* PS_POR_EINT */
#define WM831X_PS_SLEEP_OFF_EINT 0x0002 /* PS_SLEEP_OFF_EINT */
#define WM831X_PS_SLEEP_OFF_EINT_MASK 0x0002 /* PS_SLEEP_OFF_EINT */
#define WM831X_PS_SLEEP_OFF_EINT_SHIFT 1 /* PS_SLEEP_OFF_EINT */
#define WM831X_PS_SLEEP_OFF_EINT_WIDTH 1 /* PS_SLEEP_OFF_EINT */
#define WM831X_PS_ON_WAKE_EINT 0x0001 /* PS_ON_WAKE_EINT */
#define WM831X_PS_ON_WAKE_EINT_MASK 0x0001 /* PS_ON_WAKE_EINT */
#define WM831X_PS_ON_WAKE_EINT_SHIFT 0 /* PS_ON_WAKE_EINT */
#define WM831X_PS_ON_WAKE_EINT_WIDTH 1 /* PS_ON_WAKE_EINT */
/*
* R16403 (0x4013) - Interrupt Status 3
*/
#define WM831X_UV_LDO10_EINT 0x0200 /* UV_LDO10_EINT */
#define WM831X_UV_LDO10_EINT_MASK 0x0200 /* UV_LDO10_EINT */
#define WM831X_UV_LDO10_EINT_SHIFT 9 /* UV_LDO10_EINT */
#define WM831X_UV_LDO10_EINT_WIDTH 1 /* UV_LDO10_EINT */
#define WM831X_UV_LDO9_EINT 0x0100 /* UV_LDO9_EINT */
#define WM831X_UV_LDO9_EINT_MASK 0x0100 /* UV_LDO9_EINT */
#define WM831X_UV_LDO9_EINT_SHIFT 8 /* UV_LDO9_EINT */
#define WM831X_UV_LDO9_EINT_WIDTH 1 /* UV_LDO9_EINT */
#define WM831X_UV_LDO8_EINT 0x0080 /* UV_LDO8_EINT */
#define WM831X_UV_LDO8_EINT_MASK 0x0080 /* UV_LDO8_EINT */
#define WM831X_UV_LDO8_EINT_SHIFT 7 /* UV_LDO8_EINT */
#define WM831X_UV_LDO8_EINT_WIDTH 1 /* UV_LDO8_EINT */
#define WM831X_UV_LDO7_EINT 0x0040 /* UV_LDO7_EINT */
#define WM831X_UV_LDO7_EINT_MASK 0x0040 /* UV_LDO7_EINT */
#define WM831X_UV_LDO7_EINT_SHIFT 6 /* UV_LDO7_EINT */
#define WM831X_UV_LDO7_EINT_WIDTH 1 /* UV_LDO7_EINT */
#define WM831X_UV_LDO6_EINT 0x0020 /* UV_LDO6_EINT */
#define WM831X_UV_LDO6_EINT_MASK 0x0020 /* UV_LDO6_EINT */
#define WM831X_UV_LDO6_EINT_SHIFT 5 /* UV_LDO6_EINT */
#define WM831X_UV_LDO6_EINT_WIDTH 1 /* UV_LDO6_EINT */
#define WM831X_UV_LDO5_EINT 0x0010 /* UV_LDO5_EINT */
#define WM831X_UV_LDO5_EINT_MASK 0x0010 /* UV_LDO5_EINT */
#define WM831X_UV_LDO5_EINT_SHIFT 4 /* UV_LDO5_EINT */
#define WM831X_UV_LDO5_EINT_WIDTH 1 /* UV_LDO5_EINT */
#define WM831X_UV_LDO4_EINT 0x0008 /* UV_LDO4_EINT */
#define WM831X_UV_LDO4_EINT_MASK 0x0008 /* UV_LDO4_EINT */
#define WM831X_UV_LDO4_EINT_SHIFT 3 /* UV_LDO4_EINT */
#define WM831X_UV_LDO4_EINT_WIDTH 1 /* UV_LDO4_EINT */
#define WM831X_UV_LDO3_EINT 0x0004 /* UV_LDO3_EINT */
#define WM831X_UV_LDO3_EINT_MASK 0x0004 /* UV_LDO3_EINT */
#define WM831X_UV_LDO3_EINT_SHIFT 2 /* UV_LDO3_EINT */
#define WM831X_UV_LDO3_EINT_WIDTH 1 /* UV_LDO3_EINT */
#define WM831X_UV_LDO2_EINT 0x0002 /* UV_LDO2_EINT */
#define WM831X_UV_LDO2_EINT_MASK 0x0002 /* UV_LDO2_EINT */
#define WM831X_UV_LDO2_EINT_SHIFT 1 /* UV_LDO2_EINT */
#define WM831X_UV_LDO2_EINT_WIDTH 1 /* UV_LDO2_EINT */
#define WM831X_UV_LDO1_EINT 0x0001 /* UV_LDO1_EINT */
#define WM831X_UV_LDO1_EINT_MASK 0x0001 /* UV_LDO1_EINT */
#define WM831X_UV_LDO1_EINT_SHIFT 0 /* UV_LDO1_EINT */
#define WM831X_UV_LDO1_EINT_WIDTH 1 /* UV_LDO1_EINT */
/*
* R16404 (0x4014) - Interrupt Status 4
*/
#define WM831X_HC_DC2_EINT 0x0200 /* HC_DC2_EINT */
#define WM831X_HC_DC2_EINT_MASK 0x0200 /* HC_DC2_EINT */
#define WM831X_HC_DC2_EINT_SHIFT 9 /* HC_DC2_EINT */
#define WM831X_HC_DC2_EINT_WIDTH 1 /* HC_DC2_EINT */
#define WM831X_HC_DC1_EINT 0x0100 /* HC_DC1_EINT */
#define WM831X_HC_DC1_EINT_MASK 0x0100 /* HC_DC1_EINT */
#define WM831X_HC_DC1_EINT_SHIFT 8 /* HC_DC1_EINT */
#define WM831X_HC_DC1_EINT_WIDTH 1 /* HC_DC1_EINT */
#define WM831X_UV_DC4_EINT 0x0008 /* UV_DC4_EINT */
#define WM831X_UV_DC4_EINT_MASK 0x0008 /* UV_DC4_EINT */
#define WM831X_UV_DC4_EINT_SHIFT 3 /* UV_DC4_EINT */
#define WM831X_UV_DC4_EINT_WIDTH 1 /* UV_DC4_EINT */
#define WM831X_UV_DC3_EINT 0x0004 /* UV_DC3_EINT */
#define WM831X_UV_DC3_EINT_MASK 0x0004 /* UV_DC3_EINT */
#define WM831X_UV_DC3_EINT_SHIFT 2 /* UV_DC3_EINT */
#define WM831X_UV_DC3_EINT_WIDTH 1 /* UV_DC3_EINT */
#define WM831X_UV_DC2_EINT 0x0002 /* UV_DC2_EINT */
#define WM831X_UV_DC2_EINT_MASK 0x0002 /* UV_DC2_EINT */
#define WM831X_UV_DC2_EINT_SHIFT 1 /* UV_DC2_EINT */
#define WM831X_UV_DC2_EINT_WIDTH 1 /* UV_DC2_EINT */
#define WM831X_UV_DC1_EINT 0x0001 /* UV_DC1_EINT */
#define WM831X_UV_DC1_EINT_MASK 0x0001 /* UV_DC1_EINT */
#define WM831X_UV_DC1_EINT_SHIFT 0 /* UV_DC1_EINT */
#define WM831X_UV_DC1_EINT_WIDTH 1 /* UV_DC1_EINT */
/*
* R16405 (0x4015) - Interrupt Status 5
*/
#define WM831X_GP16_EINT 0x8000 /* GP16_EINT */
#define WM831X_GP16_EINT_MASK 0x8000 /* GP16_EINT */
#define WM831X_GP16_EINT_SHIFT 15 /* GP16_EINT */
#define WM831X_GP16_EINT_WIDTH 1 /* GP16_EINT */
#define WM831X_GP15_EINT 0x4000 /* GP15_EINT */
#define WM831X_GP15_EINT_MASK 0x4000 /* GP15_EINT */
#define WM831X_GP15_EINT_SHIFT 14 /* GP15_EINT */
#define WM831X_GP15_EINT_WIDTH 1 /* GP15_EINT */
#define WM831X_GP14_EINT 0x2000 /* GP14_EINT */
#define WM831X_GP14_EINT_MASK 0x2000 /* GP14_EINT */
#define WM831X_GP14_EINT_SHIFT 13 /* GP14_EINT */
#define WM831X_GP14_EINT_WIDTH 1 /* GP14_EINT */
#define WM831X_GP13_EINT 0x1000 /* GP13_EINT */
#define WM831X_GP13_EINT_MASK 0x1000 /* GP13_EINT */
#define WM831X_GP13_EINT_SHIFT 12 /* GP13_EINT */
#define WM831X_GP13_EINT_WIDTH 1 /* GP13_EINT */
#define WM831X_GP12_EINT 0x0800 /* GP12_EINT */
#define WM831X_GP12_EINT_MASK 0x0800 /* GP12_EINT */
#define WM831X_GP12_EINT_SHIFT 11 /* GP12_EINT */
#define WM831X_GP12_EINT_WIDTH 1 /* GP12_EINT */
#define WM831X_GP11_EINT 0x0400 /* GP11_EINT */
#define WM831X_GP11_EINT_MASK 0x0400 /* GP11_EINT */
#define WM831X_GP11_EINT_SHIFT 10 /* GP11_EINT */
#define WM831X_GP11_EINT_WIDTH 1 /* GP11_EINT */
#define WM831X_GP10_EINT 0x0200 /* GP10_EINT */
#define WM831X_GP10_EINT_MASK 0x0200 /* GP10_EINT */
#define WM831X_GP10_EINT_SHIFT 9 /* GP10_EINT */
#define WM831X_GP10_EINT_WIDTH 1 /* GP10_EINT */
#define WM831X_GP9_EINT 0x0100 /* GP9_EINT */
#define WM831X_GP9_EINT_MASK 0x0100 /* GP9_EINT */
#define WM831X_GP9_EINT_SHIFT 8 /* GP9_EINT */
#define WM831X_GP9_EINT_WIDTH 1 /* GP9_EINT */
#define WM831X_GP8_EINT 0x0080 /* GP8_EINT */
#define WM831X_GP8_EINT_MASK 0x0080 /* GP8_EINT */
#define WM831X_GP8_EINT_SHIFT 7 /* GP8_EINT */
#define WM831X_GP8_EINT_WIDTH 1 /* GP8_EINT */
#define WM831X_GP7_EINT 0x0040 /* GP7_EINT */
#define WM831X_GP7_EINT_MASK 0x0040 /* GP7_EINT */
#define WM831X_GP7_EINT_SHIFT 6 /* GP7_EINT */
#define WM831X_GP7_EINT_WIDTH 1 /* GP7_EINT */
#define WM831X_GP6_EINT 0x0020 /* GP6_EINT */
#define WM831X_GP6_EINT_MASK 0x0020 /* GP6_EINT */
#define WM831X_GP6_EINT_SHIFT 5 /* GP6_EINT */
#define WM831X_GP6_EINT_WIDTH 1 /* GP6_EINT */
#define WM831X_GP5_EINT 0x0010 /* GP5_EINT */
#define WM831X_GP5_EINT_MASK 0x0010 /* GP5_EINT */
#define WM831X_GP5_EINT_SHIFT 4 /* GP5_EINT */
#define WM831X_GP5_EINT_WIDTH 1 /* GP5_EINT */
#define WM831X_GP4_EINT 0x0008 /* GP4_EINT */
#define WM831X_GP4_EINT_MASK 0x0008 /* GP4_EINT */
#define WM831X_GP4_EINT_SHIFT 3 /* GP4_EINT */
#define WM831X_GP4_EINT_WIDTH 1 /* GP4_EINT */
#define WM831X_GP3_EINT 0x0004 /* GP3_EINT */
#define WM831X_GP3_EINT_MASK 0x0004 /* GP3_EINT */
#define WM831X_GP3_EINT_SHIFT 2 /* GP3_EINT */
#define WM831X_GP3_EINT_WIDTH 1 /* GP3_EINT */
#define WM831X_GP2_EINT 0x0002 /* GP2_EINT */
#define WM831X_GP2_EINT_MASK 0x0002 /* GP2_EINT */
#define WM831X_GP2_EINT_SHIFT 1 /* GP2_EINT */
#define WM831X_GP2_EINT_WIDTH 1 /* GP2_EINT */
#define WM831X_GP1_EINT 0x0001 /* GP1_EINT */
#define WM831X_GP1_EINT_MASK 0x0001 /* GP1_EINT */
#define WM831X_GP1_EINT_SHIFT 0 /* GP1_EINT */
#define WM831X_GP1_EINT_WIDTH 1 /* GP1_EINT */
/*
* R16407 (0x4017) - IRQ Config
*/
#define WM831X_IRQ_OD 0x0002 /* IRQ_OD */
#define WM831X_IRQ_OD_MASK 0x0002 /* IRQ_OD */
#define WM831X_IRQ_OD_SHIFT 1 /* IRQ_OD */
#define WM831X_IRQ_OD_WIDTH 1 /* IRQ_OD */
#define WM831X_IM_IRQ 0x0001 /* IM_IRQ */
#define WM831X_IM_IRQ_MASK 0x0001 /* IM_IRQ */
#define WM831X_IM_IRQ_SHIFT 0 /* IM_IRQ */
#define WM831X_IM_IRQ_WIDTH 1 /* IM_IRQ */
/*
* R16408 (0x4018) - System Interrupts Mask
*/
#define WM831X_IM_PS_INT 0x8000 /* IM_PS_INT */
#define WM831X_IM_PS_INT_MASK 0x8000 /* IM_PS_INT */
#define WM831X_IM_PS_INT_SHIFT 15 /* IM_PS_INT */
#define WM831X_IM_PS_INT_WIDTH 1 /* IM_PS_INT */
#define WM831X_IM_TEMP_INT 0x4000 /* IM_TEMP_INT */
#define WM831X_IM_TEMP_INT_MASK 0x4000 /* IM_TEMP_INT */
#define WM831X_IM_TEMP_INT_SHIFT 14 /* IM_TEMP_INT */
#define WM831X_IM_TEMP_INT_WIDTH 1 /* IM_TEMP_INT */
#define WM831X_IM_GP_INT 0x2000 /* IM_GP_INT */
#define WM831X_IM_GP_INT_MASK 0x2000 /* IM_GP_INT */
#define WM831X_IM_GP_INT_SHIFT 13 /* IM_GP_INT */
#define WM831X_IM_GP_INT_WIDTH 1 /* IM_GP_INT */
#define WM831X_IM_ON_PIN_INT 0x1000 /* IM_ON_PIN_INT */
#define WM831X_IM_ON_PIN_INT_MASK 0x1000 /* IM_ON_PIN_INT */
#define WM831X_IM_ON_PIN_INT_SHIFT 12 /* IM_ON_PIN_INT */
#define WM831X_IM_ON_PIN_INT_WIDTH 1 /* IM_ON_PIN_INT */
#define WM831X_IM_WDOG_INT 0x0800 /* IM_WDOG_INT */
#define WM831X_IM_WDOG_INT_MASK 0x0800 /* IM_WDOG_INT */
#define WM831X_IM_WDOG_INT_SHIFT 11 /* IM_WDOG_INT */
#define WM831X_IM_WDOG_INT_WIDTH 1 /* IM_WDOG_INT */
#define WM831X_IM_TCHDATA_INT 0x0400 /* IM_TCHDATA_INT */
#define WM831X_IM_TCHDATA_INT_MASK 0x0400 /* IM_TCHDATA_INT */
#define WM831X_IM_TCHDATA_INT_SHIFT 10 /* IM_TCHDATA_INT */
#define WM831X_IM_TCHDATA_INT_WIDTH 1 /* IM_TCHDATA_INT */
#define WM831X_IM_TCHPD_INT 0x0200 /* IM_TCHPD_INT */
#define WM831X_IM_TCHPD_INT_MASK 0x0200 /* IM_TCHPD_INT */
#define WM831X_IM_TCHPD_INT_SHIFT 9 /* IM_TCHPD_INT */
#define WM831X_IM_TCHPD_INT_WIDTH 1 /* IM_TCHPD_INT */
#define WM831X_IM_AUXADC_INT 0x0100 /* IM_AUXADC_INT */
#define WM831X_IM_AUXADC_INT_MASK 0x0100 /* IM_AUXADC_INT */
#define WM831X_IM_AUXADC_INT_SHIFT 8 /* IM_AUXADC_INT */
#define WM831X_IM_AUXADC_INT_WIDTH 1 /* IM_AUXADC_INT */
#define WM831X_IM_PPM_INT 0x0080 /* IM_PPM_INT */
#define WM831X_IM_PPM_INT_MASK 0x0080 /* IM_PPM_INT */
#define WM831X_IM_PPM_INT_SHIFT 7 /* IM_PPM_INT */
#define WM831X_IM_PPM_INT_WIDTH 1 /* IM_PPM_INT */
#define WM831X_IM_CS_INT 0x0040 /* IM_CS_INT */
#define WM831X_IM_CS_INT_MASK 0x0040 /* IM_CS_INT */
#define WM831X_IM_CS_INT_SHIFT 6 /* IM_CS_INT */
#define WM831X_IM_CS_INT_WIDTH 1 /* IM_CS_INT */
#define WM831X_IM_RTC_INT 0x0020 /* IM_RTC_INT */
#define WM831X_IM_RTC_INT_MASK 0x0020 /* IM_RTC_INT */
#define WM831X_IM_RTC_INT_SHIFT 5 /* IM_RTC_INT */
#define WM831X_IM_RTC_INT_WIDTH 1 /* IM_RTC_INT */
#define WM831X_IM_OTP_INT 0x0010 /* IM_OTP_INT */
#define WM831X_IM_OTP_INT_MASK 0x0010 /* IM_OTP_INT */
#define WM831X_IM_OTP_INT_SHIFT 4 /* IM_OTP_INT */
#define WM831X_IM_OTP_INT_WIDTH 1 /* IM_OTP_INT */
#define WM831X_IM_CHILD_INT 0x0008 /* IM_CHILD_INT */
#define WM831X_IM_CHILD_INT_MASK 0x0008 /* IM_CHILD_INT */
#define WM831X_IM_CHILD_INT_SHIFT 3 /* IM_CHILD_INT */
#define WM831X_IM_CHILD_INT_WIDTH 1 /* IM_CHILD_INT */
#define WM831X_IM_CHG_INT 0x0004 /* IM_CHG_INT */
#define WM831X_IM_CHG_INT_MASK 0x0004 /* IM_CHG_INT */
#define WM831X_IM_CHG_INT_SHIFT 2 /* IM_CHG_INT */
#define WM831X_IM_CHG_INT_WIDTH 1 /* IM_CHG_INT */
#define WM831X_IM_HC_INT 0x0002 /* IM_HC_INT */
#define WM831X_IM_HC_INT_MASK 0x0002 /* IM_HC_INT */
#define WM831X_IM_HC_INT_SHIFT 1 /* IM_HC_INT */
#define WM831X_IM_HC_INT_WIDTH 1 /* IM_HC_INT */
#define WM831X_IM_UV_INT 0x0001 /* IM_UV_INT */
#define WM831X_IM_UV_INT_MASK 0x0001 /* IM_UV_INT */
#define WM831X_IM_UV_INT_SHIFT 0 /* IM_UV_INT */
#define WM831X_IM_UV_INT_WIDTH 1 /* IM_UV_INT */
/*
* R16409 (0x4019) - Interrupt Status 1 Mask
*/
#define WM831X_IM_PPM_SYSLO_EINT 0x8000 /* IM_PPM_SYSLO_EINT */
#define WM831X_IM_PPM_SYSLO_EINT_MASK 0x8000 /* IM_PPM_SYSLO_EINT */
#define WM831X_IM_PPM_SYSLO_EINT_SHIFT 15 /* IM_PPM_SYSLO_EINT */
#define WM831X_IM_PPM_SYSLO_EINT_WIDTH 1 /* IM_PPM_SYSLO_EINT */
#define WM831X_IM_PPM_PWR_SRC_EINT 0x4000 /* IM_PPM_PWR_SRC_EINT */
#define WM831X_IM_PPM_PWR_SRC_EINT_MASK 0x4000 /* IM_PPM_PWR_SRC_EINT */
#define WM831X_IM_PPM_PWR_SRC_EINT_SHIFT 14 /* IM_PPM_PWR_SRC_EINT */
#define WM831X_IM_PPM_PWR_SRC_EINT_WIDTH 1 /* IM_PPM_PWR_SRC_EINT */
#define WM831X_IM_PPM_USB_CURR_EINT 0x2000 /* IM_PPM_USB_CURR_EINT */
#define WM831X_IM_PPM_USB_CURR_EINT_MASK 0x2000 /* IM_PPM_USB_CURR_EINT */
#define WM831X_IM_PPM_USB_CURR_EINT_SHIFT 13 /* IM_PPM_USB_CURR_EINT */
#define WM831X_IM_PPM_USB_CURR_EINT_WIDTH 1 /* IM_PPM_USB_CURR_EINT */
#define WM831X_IM_ON_PIN_EINT 0x1000 /* IM_ON_PIN_EINT */
#define WM831X_IM_ON_PIN_EINT_MASK 0x1000 /* IM_ON_PIN_EINT */
#define WM831X_IM_ON_PIN_EINT_SHIFT 12 /* IM_ON_PIN_EINT */
#define WM831X_IM_ON_PIN_EINT_WIDTH 1 /* IM_ON_PIN_EINT */
#define WM831X_IM_WDOG_TO_EINT 0x0800 /* IM_WDOG_TO_EINT */
#define WM831X_IM_WDOG_TO_EINT_MASK 0x0800 /* IM_WDOG_TO_EINT */
#define WM831X_IM_WDOG_TO_EINT_SHIFT 11 /* IM_WDOG_TO_EINT */
#define WM831X_IM_WDOG_TO_EINT_WIDTH 1 /* IM_WDOG_TO_EINT */
#define WM831X_IM_TCHDATA_EINT 0x0400 /* IM_TCHDATA_EINT */
#define WM831X_IM_TCHDATA_EINT_MASK 0x0400 /* IM_TCHDATA_EINT */
#define WM831X_IM_TCHDATA_EINT_SHIFT 10 /* IM_TCHDATA_EINT */
#define WM831X_IM_TCHDATA_EINT_WIDTH 1 /* IM_TCHDATA_EINT */
#define WM831X_IM_TCHPD_EINT 0x0200 /* IM_TCHPD_EINT */
#define WM831X_IM_TCHPD_EINT_MASK 0x0200 /* IM_TCHPD_EINT */
#define WM831X_IM_TCHPD_EINT_SHIFT 9 /* IM_TCHPD_EINT */
#define WM831X_IM_TCHPD_EINT_WIDTH 1 /* IM_TCHPD_EINT */
#define WM831X_IM_AUXADC_DATA_EINT 0x0100 /* IM_AUXADC_DATA_EINT */
#define WM831X_IM_AUXADC_DATA_EINT_MASK 0x0100 /* IM_AUXADC_DATA_EINT */
#define WM831X_IM_AUXADC_DATA_EINT_SHIFT 8 /* IM_AUXADC_DATA_EINT */
#define WM831X_IM_AUXADC_DATA_EINT_WIDTH 1 /* IM_AUXADC_DATA_EINT */
#define WM831X_IM_AUXADC_DCOMP4_EINT 0x0080 /* IM_AUXADC_DCOMP4_EINT */
#define WM831X_IM_AUXADC_DCOMP4_EINT_MASK 0x0080 /* IM_AUXADC_DCOMP4_EINT */
#define WM831X_IM_AUXADC_DCOMP4_EINT_SHIFT 7 /* IM_AUXADC_DCOMP4_EINT */
#define WM831X_IM_AUXADC_DCOMP4_EINT_WIDTH 1 /* IM_AUXADC_DCOMP4_EINT */
#define WM831X_IM_AUXADC_DCOMP3_EINT 0x0040 /* IM_AUXADC_DCOMP3_EINT */
#define WM831X_IM_AUXADC_DCOMP3_EINT_MASK 0x0040 /* IM_AUXADC_DCOMP3_EINT */
#define WM831X_IM_AUXADC_DCOMP3_EINT_SHIFT 6 /* IM_AUXADC_DCOMP3_EINT */
#define WM831X_IM_AUXADC_DCOMP3_EINT_WIDTH 1 /* IM_AUXADC_DCOMP3_EINT */
#define WM831X_IM_AUXADC_DCOMP2_EINT 0x0020 /* IM_AUXADC_DCOMP2_EINT */
#define WM831X_IM_AUXADC_DCOMP2_EINT_MASK 0x0020 /* IM_AUXADC_DCOMP2_EINT */
#define WM831X_IM_AUXADC_DCOMP2_EINT_SHIFT 5 /* IM_AUXADC_DCOMP2_EINT */
#define WM831X_IM_AUXADC_DCOMP2_EINT_WIDTH 1 /* IM_AUXADC_DCOMP2_EINT */
#define WM831X_IM_AUXADC_DCOMP1_EINT 0x0010 /* IM_AUXADC_DCOMP1_EINT */
#define WM831X_IM_AUXADC_DCOMP1_EINT_MASK 0x0010 /* IM_AUXADC_DCOMP1_EINT */
#define WM831X_IM_AUXADC_DCOMP1_EINT_SHIFT 4 /* IM_AUXADC_DCOMP1_EINT */
#define WM831X_IM_AUXADC_DCOMP1_EINT_WIDTH 1 /* IM_AUXADC_DCOMP1_EINT */
#define WM831X_IM_RTC_PER_EINT 0x0008 /* IM_RTC_PER_EINT */
#define WM831X_IM_RTC_PER_EINT_MASK 0x0008 /* IM_RTC_PER_EINT */
#define WM831X_IM_RTC_PER_EINT_SHIFT 3 /* IM_RTC_PER_EINT */
#define WM831X_IM_RTC_PER_EINT_WIDTH 1 /* IM_RTC_PER_EINT */
#define WM831X_IM_RTC_ALM_EINT 0x0004 /* IM_RTC_ALM_EINT */
#define WM831X_IM_RTC_ALM_EINT_MASK 0x0004 /* IM_RTC_ALM_EINT */
#define WM831X_IM_RTC_ALM_EINT_SHIFT 2 /* IM_RTC_ALM_EINT */
#define WM831X_IM_RTC_ALM_EINT_WIDTH 1 /* IM_RTC_ALM_EINT */
#define WM831X_IM_TEMP_THW_EINT 0x0002 /* IM_TEMP_THW_EINT */
#define WM831X_IM_TEMP_THW_EINT_MASK 0x0002 /* IM_TEMP_THW_EINT */
#define WM831X_IM_TEMP_THW_EINT_SHIFT 1 /* IM_TEMP_THW_EINT */
#define WM831X_IM_TEMP_THW_EINT_WIDTH 1 /* IM_TEMP_THW_EINT */
/*
* R16410 (0x401A) - Interrupt Status 2 Mask
*/
#define WM831X_IM_CHG_BATT_HOT_EINT 0x8000 /* IM_CHG_BATT_HOT_EINT */
#define WM831X_IM_CHG_BATT_HOT_EINT_MASK 0x8000 /* IM_CHG_BATT_HOT_EINT */
#define WM831X_IM_CHG_BATT_HOT_EINT_SHIFT 15 /* IM_CHG_BATT_HOT_EINT */
#define WM831X_IM_CHG_BATT_HOT_EINT_WIDTH 1 /* IM_CHG_BATT_HOT_EINT */
#define WM831X_IM_CHG_BATT_COLD_EINT 0x4000 /* IM_CHG_BATT_COLD_EINT */
#define WM831X_IM_CHG_BATT_COLD_EINT_MASK 0x4000 /* IM_CHG_BATT_COLD_EINT */
#define WM831X_IM_CHG_BATT_COLD_EINT_SHIFT 14 /* IM_CHG_BATT_COLD_EINT */
#define WM831X_IM_CHG_BATT_COLD_EINT_WIDTH 1 /* IM_CHG_BATT_COLD_EINT */
#define WM831X_IM_CHG_BATT_FAIL_EINT 0x2000 /* IM_CHG_BATT_FAIL_EINT */
#define WM831X_IM_CHG_BATT_FAIL_EINT_MASK 0x2000 /* IM_CHG_BATT_FAIL_EINT */
#define WM831X_IM_CHG_BATT_FAIL_EINT_SHIFT 13 /* IM_CHG_BATT_FAIL_EINT */
#define WM831X_IM_CHG_BATT_FAIL_EINT_WIDTH 1 /* IM_CHG_BATT_FAIL_EINT */
#define WM831X_IM_CHG_OV_EINT 0x1000 /* IM_CHG_OV_EINT */
#define WM831X_IM_CHG_OV_EINT_MASK 0x1000 /* IM_CHG_OV_EINT */
#define WM831X_IM_CHG_OV_EINT_SHIFT 12 /* IM_CHG_OV_EINT */
#define WM831X_IM_CHG_OV_EINT_WIDTH 1 /* IM_CHG_OV_EINT */
#define WM831X_IM_CHG_END_EINT 0x0800 /* IM_CHG_END_EINT */
#define WM831X_IM_CHG_END_EINT_MASK 0x0800 /* IM_CHG_END_EINT */
#define WM831X_IM_CHG_END_EINT_SHIFT 11 /* IM_CHG_END_EINT */
#define WM831X_IM_CHG_END_EINT_WIDTH 1 /* IM_CHG_END_EINT */
#define WM831X_IM_CHG_TO_EINT 0x0400 /* IM_CHG_TO_EINT */
#define WM831X_IM_CHG_TO_EINT_MASK 0x0400 /* IM_CHG_TO_EINT */
#define WM831X_IM_CHG_TO_EINT_SHIFT 10 /* IM_CHG_TO_EINT */
#define WM831X_IM_CHG_TO_EINT_WIDTH 1 /* IM_CHG_TO_EINT */
#define WM831X_IM_CHG_MODE_EINT 0x0200 /* IM_CHG_MODE_EINT */
#define WM831X_IM_CHG_MODE_EINT_MASK 0x0200 /* IM_CHG_MODE_EINT */
#define WM831X_IM_CHG_MODE_EINT_SHIFT 9 /* IM_CHG_MODE_EINT */
#define WM831X_IM_CHG_MODE_EINT_WIDTH 1 /* IM_CHG_MODE_EINT */
#define WM831X_IM_CHG_START_EINT 0x0100 /* IM_CHG_START_EINT */
#define WM831X_IM_CHG_START_EINT_MASK 0x0100 /* IM_CHG_START_EINT */
#define WM831X_IM_CHG_START_EINT_SHIFT 8 /* IM_CHG_START_EINT */
#define WM831X_IM_CHG_START_EINT_WIDTH 1 /* IM_CHG_START_EINT */
#define WM831X_IM_CS2_EINT 0x0080 /* IM_CS2_EINT */
#define WM831X_IM_CS2_EINT_MASK 0x0080 /* IM_CS2_EINT */
#define WM831X_IM_CS2_EINT_SHIFT 7 /* IM_CS2_EINT */
#define WM831X_IM_CS2_EINT_WIDTH 1 /* IM_CS2_EINT */
#define WM831X_IM_CS1_EINT 0x0040 /* IM_CS1_EINT */
#define WM831X_IM_CS1_EINT_MASK 0x0040 /* IM_CS1_EINT */
#define WM831X_IM_CS1_EINT_SHIFT 6 /* IM_CS1_EINT */
#define WM831X_IM_CS1_EINT_WIDTH 1 /* IM_CS1_EINT */
#define WM831X_IM_OTP_CMD_END_EINT 0x0020 /* IM_OTP_CMD_END_EINT */
#define WM831X_IM_OTP_CMD_END_EINT_MASK 0x0020 /* IM_OTP_CMD_END_EINT */
#define WM831X_IM_OTP_CMD_END_EINT_SHIFT 5 /* IM_OTP_CMD_END_EINT */
#define WM831X_IM_OTP_CMD_END_EINT_WIDTH 1 /* IM_OTP_CMD_END_EINT */
#define WM831X_IM_OTP_ERR_EINT 0x0010 /* IM_OTP_ERR_EINT */
#define WM831X_IM_OTP_ERR_EINT_MASK 0x0010 /* IM_OTP_ERR_EINT */
#define WM831X_IM_OTP_ERR_EINT_SHIFT 4 /* IM_OTP_ERR_EINT */
#define WM831X_IM_OTP_ERR_EINT_WIDTH 1 /* IM_OTP_ERR_EINT */
#define WM831X_IM_PS_POR_EINT 0x0004 /* IM_PS_POR_EINT */
#define WM831X_IM_PS_POR_EINT_MASK 0x0004 /* IM_PS_POR_EINT */
#define WM831X_IM_PS_POR_EINT_SHIFT 2 /* IM_PS_POR_EINT */
#define WM831X_IM_PS_POR_EINT_WIDTH 1 /* IM_PS_POR_EINT */
#define WM831X_IM_PS_SLEEP_OFF_EINT 0x0002 /* IM_PS_SLEEP_OFF_EINT */
#define WM831X_IM_PS_SLEEP_OFF_EINT_MASK 0x0002 /* IM_PS_SLEEP_OFF_EINT */
#define WM831X_IM_PS_SLEEP_OFF_EINT_SHIFT 1 /* IM_PS_SLEEP_OFF_EINT */
#define WM831X_IM_PS_SLEEP_OFF_EINT_WIDTH 1 /* IM_PS_SLEEP_OFF_EINT */
#define WM831X_IM_PS_ON_WAKE_EINT 0x0001 /* IM_PS_ON_WAKE_EINT */
#define WM831X_IM_PS_ON_WAKE_EINT_MASK 0x0001 /* IM_PS_ON_WAKE_EINT */
#define WM831X_IM_PS_ON_WAKE_EINT_SHIFT 0 /* IM_PS_ON_WAKE_EINT */
#define WM831X_IM_PS_ON_WAKE_EINT_WIDTH 1 /* IM_PS_ON_WAKE_EINT */
/*
* R16411 (0x401B) - Interrupt Status 3 Mask
*/
#define WM831X_IM_UV_LDO10_EINT 0x0200 /* IM_UV_LDO10_EINT */
#define WM831X_IM_UV_LDO10_EINT_MASK 0x0200 /* IM_UV_LDO10_EINT */
#define WM831X_IM_UV_LDO10_EINT_SHIFT 9 /* IM_UV_LDO10_EINT */
#define WM831X_IM_UV_LDO10_EINT_WIDTH 1 /* IM_UV_LDO10_EINT */
#define WM831X_IM_UV_LDO9_EINT 0x0100 /* IM_UV_LDO9_EINT */
#define WM831X_IM_UV_LDO9_EINT_MASK 0x0100 /* IM_UV_LDO9_EINT */
#define WM831X_IM_UV_LDO9_EINT_SHIFT 8 /* IM_UV_LDO9_EINT */
#define WM831X_IM_UV_LDO9_EINT_WIDTH 1 /* IM_UV_LDO9_EINT */
#define WM831X_IM_UV_LDO8_EINT 0x0080 /* IM_UV_LDO8_EINT */
#define WM831X_IM_UV_LDO8_EINT_MASK 0x0080 /* IM_UV_LDO8_EINT */
#define WM831X_IM_UV_LDO8_EINT_SHIFT 7 /* IM_UV_LDO8_EINT */
#define WM831X_IM_UV_LDO8_EINT_WIDTH 1 /* IM_UV_LDO8_EINT */
#define WM831X_IM_UV_LDO7_EINT 0x0040 /* IM_UV_LDO7_EINT */
#define WM831X_IM_UV_LDO7_EINT_MASK 0x0040 /* IM_UV_LDO7_EINT */
#define WM831X_IM_UV_LDO7_EINT_SHIFT 6 /* IM_UV_LDO7_EINT */
#define WM831X_IM_UV_LDO7_EINT_WIDTH 1 /* IM_UV_LDO7_EINT */
#define WM831X_IM_UV_LDO6_EINT 0x0020 /* IM_UV_LDO6_EINT */
#define WM831X_IM_UV_LDO6_EINT_MASK 0x0020 /* IM_UV_LDO6_EINT */
#define WM831X_IM_UV_LDO6_EINT_SHIFT 5 /* IM_UV_LDO6_EINT */
#define WM831X_IM_UV_LDO6_EINT_WIDTH 1 /* IM_UV_LDO6_EINT */
#define WM831X_IM_UV_LDO5_EINT 0x0010 /* IM_UV_LDO5_EINT */
#define WM831X_IM_UV_LDO5_EINT_MASK 0x0010 /* IM_UV_LDO5_EINT */
#define WM831X_IM_UV_LDO5_EINT_SHIFT 4 /* IM_UV_LDO5_EINT */
#define WM831X_IM_UV_LDO5_EINT_WIDTH 1 /* IM_UV_LDO5_EINT */
#define WM831X_IM_UV_LDO4_EINT 0x0008 /* IM_UV_LDO4_EINT */
#define WM831X_IM_UV_LDO4_EINT_MASK 0x0008 /* IM_UV_LDO4_EINT */
#define WM831X_IM_UV_LDO4_EINT_SHIFT 3 /* IM_UV_LDO4_EINT */
#define WM831X_IM_UV_LDO4_EINT_WIDTH 1 /* IM_UV_LDO4_EINT */
#define WM831X_IM_UV_LDO3_EINT 0x0004 /* IM_UV_LDO3_EINT */
#define WM831X_IM_UV_LDO3_EINT_MASK 0x0004 /* IM_UV_LDO3_EINT */
#define WM831X_IM_UV_LDO3_EINT_SHIFT 2 /* IM_UV_LDO3_EINT */
#define WM831X_IM_UV_LDO3_EINT_WIDTH 1 /* IM_UV_LDO3_EINT */
#define WM831X_IM_UV_LDO2_EINT 0x0002 /* IM_UV_LDO2_EINT */
#define WM831X_IM_UV_LDO2_EINT_MASK 0x0002 /* IM_UV_LDO2_EINT */
#define WM831X_IM_UV_LDO2_EINT_SHIFT 1 /* IM_UV_LDO2_EINT */
#define WM831X_IM_UV_LDO2_EINT_WIDTH 1 /* IM_UV_LDO2_EINT */
#define WM831X_IM_UV_LDO1_EINT 0x0001 /* IM_UV_LDO1_EINT */
#define WM831X_IM_UV_LDO1_EINT_MASK 0x0001 /* IM_UV_LDO1_EINT */
#define WM831X_IM_UV_LDO1_EINT_SHIFT 0 /* IM_UV_LDO1_EINT */
#define WM831X_IM_UV_LDO1_EINT_WIDTH 1 /* IM_UV_LDO1_EINT */
/*
* R16412 (0x401C) - Interrupt Status 4 Mask
*/
#define WM831X_IM_HC_DC2_EINT 0x0200 /* IM_HC_DC2_EINT */
#define WM831X_IM_HC_DC2_EINT_MASK 0x0200 /* IM_HC_DC2_EINT */
#define WM831X_IM_HC_DC2_EINT_SHIFT 9 /* IM_HC_DC2_EINT */
#define WM831X_IM_HC_DC2_EINT_WIDTH 1 /* IM_HC_DC2_EINT */
#define WM831X_IM_HC_DC1_EINT 0x0100 /* IM_HC_DC1_EINT */
#define WM831X_IM_HC_DC1_EINT_MASK 0x0100 /* IM_HC_DC1_EINT */
#define WM831X_IM_HC_DC1_EINT_SHIFT 8 /* IM_HC_DC1_EINT */
#define WM831X_IM_HC_DC1_EINT_WIDTH 1 /* IM_HC_DC1_EINT */
#define WM831X_IM_UV_DC4_EINT 0x0008 /* IM_UV_DC4_EINT */
#define WM831X_IM_UV_DC4_EINT_MASK 0x0008 /* IM_UV_DC4_EINT */
#define WM831X_IM_UV_DC4_EINT_SHIFT 3 /* IM_UV_DC4_EINT */
#define WM831X_IM_UV_DC4_EINT_WIDTH 1 /* IM_UV_DC4_EINT */
#define WM831X_IM_UV_DC3_EINT 0x0004 /* IM_UV_DC3_EINT */
#define WM831X_IM_UV_DC3_EINT_MASK 0x0004 /* IM_UV_DC3_EINT */
#define WM831X_IM_UV_DC3_EINT_SHIFT 2 /* IM_UV_DC3_EINT */
#define WM831X_IM_UV_DC3_EINT_WIDTH 1 /* IM_UV_DC3_EINT */
#define WM831X_IM_UV_DC2_EINT 0x0002 /* IM_UV_DC2_EINT */
#define WM831X_IM_UV_DC2_EINT_MASK 0x0002 /* IM_UV_DC2_EINT */
#define WM831X_IM_UV_DC2_EINT_SHIFT 1 /* IM_UV_DC2_EINT */
#define WM831X_IM_UV_DC2_EINT_WIDTH 1 /* IM_UV_DC2_EINT */
#define WM831X_IM_UV_DC1_EINT 0x0001 /* IM_UV_DC1_EINT */
#define WM831X_IM_UV_DC1_EINT_MASK 0x0001 /* IM_UV_DC1_EINT */
#define WM831X_IM_UV_DC1_EINT_SHIFT 0 /* IM_UV_DC1_EINT */
#define WM831X_IM_UV_DC1_EINT_WIDTH 1 /* IM_UV_DC1_EINT */
/*
* R16413 (0x401D) - Interrupt Status 5 Mask
*/
#define WM831X_IM_GP16_EINT 0x8000 /* IM_GP16_EINT */
#define WM831X_IM_GP16_EINT_MASK 0x8000 /* IM_GP16_EINT */
#define WM831X_IM_GP16_EINT_SHIFT 15 /* IM_GP16_EINT */
#define WM831X_IM_GP16_EINT_WIDTH 1 /* IM_GP16_EINT */
#define WM831X_IM_GP15_EINT 0x4000 /* IM_GP15_EINT */
#define WM831X_IM_GP15_EINT_MASK 0x4000 /* IM_GP15_EINT */
#define WM831X_IM_GP15_EINT_SHIFT 14 /* IM_GP15_EINT */
#define WM831X_IM_GP15_EINT_WIDTH 1 /* IM_GP15_EINT */
#define WM831X_IM_GP14_EINT 0x2000 /* IM_GP14_EINT */
#define WM831X_IM_GP14_EINT_MASK 0x2000 /* IM_GP14_EINT */
#define WM831X_IM_GP14_EINT_SHIFT 13 /* IM_GP14_EINT */
#define WM831X_IM_GP14_EINT_WIDTH 1 /* IM_GP14_EINT */
#define WM831X_IM_GP13_EINT 0x1000 /* IM_GP13_EINT */
#define WM831X_IM_GP13_EINT_MASK 0x1000 /* IM_GP13_EINT */
#define WM831X_IM_GP13_EINT_SHIFT 12 /* IM_GP13_EINT */
#define WM831X_IM_GP13_EINT_WIDTH 1 /* IM_GP13_EINT */
#define WM831X_IM_GP12_EINT 0x0800 /* IM_GP12_EINT */
#define WM831X_IM_GP12_EINT_MASK 0x0800 /* IM_GP12_EINT */
#define WM831X_IM_GP12_EINT_SHIFT 11 /* IM_GP12_EINT */
#define WM831X_IM_GP12_EINT_WIDTH 1 /* IM_GP12_EINT */
#define WM831X_IM_GP11_EINT 0x0400 /* IM_GP11_EINT */
#define WM831X_IM_GP11_EINT_MASK 0x0400 /* IM_GP11_EINT */
#define WM831X_IM_GP11_EINT_SHIFT 10 /* IM_GP11_EINT */
#define WM831X_IM_GP11_EINT_WIDTH 1 /* IM_GP11_EINT */
#define WM831X_IM_GP10_EINT 0x0200 /* IM_GP10_EINT */
#define WM831X_IM_GP10_EINT_MASK 0x0200 /* IM_GP10_EINT */
#define WM831X_IM_GP10_EINT_SHIFT 9 /* IM_GP10_EINT */
#define WM831X_IM_GP10_EINT_WIDTH 1 /* IM_GP10_EINT */
#define WM831X_IM_GP9_EINT 0x0100 /* IM_GP9_EINT */
#define WM831X_IM_GP9_EINT_MASK 0x0100 /* IM_GP9_EINT */
#define WM831X_IM_GP9_EINT_SHIFT 8 /* IM_GP9_EINT */
#define WM831X_IM_GP9_EINT_WIDTH 1 /* IM_GP9_EINT */
#define WM831X_IM_GP8_EINT 0x0080 /* IM_GP8_EINT */
#define WM831X_IM_GP8_EINT_MASK 0x0080 /* IM_GP8_EINT */
#define WM831X_IM_GP8_EINT_SHIFT 7 /* IM_GP8_EINT */
#define WM831X_IM_GP8_EINT_WIDTH 1 /* IM_GP8_EINT */
#define WM831X_IM_GP7_EINT 0x0040 /* IM_GP7_EINT */
#define WM831X_IM_GP7_EINT_MASK 0x0040 /* IM_GP7_EINT */
#define WM831X_IM_GP7_EINT_SHIFT 6 /* IM_GP7_EINT */
#define WM831X_IM_GP7_EINT_WIDTH 1 /* IM_GP7_EINT */
#define WM831X_IM_GP6_EINT 0x0020 /* IM_GP6_EINT */
#define WM831X_IM_GP6_EINT_MASK 0x0020 /* IM_GP6_EINT */
#define WM831X_IM_GP6_EINT_SHIFT 5 /* IM_GP6_EINT */
#define WM831X_IM_GP6_EINT_WIDTH 1 /* IM_GP6_EINT */
#define WM831X_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */
#define WM831X_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */
#define WM831X_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */
#define WM831X_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */
#define WM831X_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */
#define WM831X_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */
#define WM831X_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */
#define WM831X_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */
#define WM831X_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */
#define WM831X_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */
#define WM831X_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */
#define WM831X_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */
#define WM831X_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */
#define WM831X_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */
#define WM831X_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */
#define WM831X_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */
#define WM831X_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */
#define WM831X_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */
#define WM831X_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */
#define WM831X_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */
#endif

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/*
* include/linux/mfd/wm831x/otp.h -- OTP interface for WM831x
*
* Copyright 2009 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __MFD_WM831X_OTP_H__
#define __MFD_WM831X_OTP_H__
int wm831x_otp_init(struct wm831x *wm831x);
void wm831x_otp_exit(struct wm831x *wm831x);
/*
* R30720 (0x7800) - Unique ID 1
*/
#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
/*
* R30721 (0x7801) - Unique ID 2
*/
#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
/*
* R30722 (0x7802) - Unique ID 3
*/
#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
/*
* R30723 (0x7803) - Unique ID 4
*/
#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
/*
* R30724 (0x7804) - Unique ID 5
*/
#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
/*
* R30725 (0x7805) - Unique ID 6
*/
#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
/*
* R30726 (0x7806) - Unique ID 7
*/
#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
/*
* R30727 (0x7807) - Unique ID 8
*/
#define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
#define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
/*
* R30728 (0x7808) - Factory OTP ID
*/
#define WM831X_OTP_FACT_ID_MASK 0xFFFE /* OTP_FACT_ID - [15:1] */
#define WM831X_OTP_FACT_ID_SHIFT 1 /* OTP_FACT_ID - [15:1] */
#define WM831X_OTP_FACT_ID_WIDTH 15 /* OTP_FACT_ID - [15:1] */
#define WM831X_OTP_FACT_FINAL 0x0001 /* OTP_FACT_FINAL */
#define WM831X_OTP_FACT_FINAL_MASK 0x0001 /* OTP_FACT_FINAL */
#define WM831X_OTP_FACT_FINAL_SHIFT 0 /* OTP_FACT_FINAL */
#define WM831X_OTP_FACT_FINAL_WIDTH 1 /* OTP_FACT_FINAL */
/*
* R30729 (0x7809) - Factory OTP 1
*/
#define WM831X_DC3_TRIM_MASK 0xF000 /* DC3_TRIM - [15:12] */
#define WM831X_DC3_TRIM_SHIFT 12 /* DC3_TRIM - [15:12] */
#define WM831X_DC3_TRIM_WIDTH 4 /* DC3_TRIM - [15:12] */
#define WM831X_DC2_TRIM_MASK 0x0FC0 /* DC2_TRIM - [11:6] */
#define WM831X_DC2_TRIM_SHIFT 6 /* DC2_TRIM - [11:6] */
#define WM831X_DC2_TRIM_WIDTH 6 /* DC2_TRIM - [11:6] */
#define WM831X_DC1_TRIM_MASK 0x003F /* DC1_TRIM - [5:0] */
#define WM831X_DC1_TRIM_SHIFT 0 /* DC1_TRIM - [5:0] */
#define WM831X_DC1_TRIM_WIDTH 6 /* DC1_TRIM - [5:0] */
/*
* R30730 (0x780A) - Factory OTP 2
*/
#define WM831X_CHIP_ID_MASK 0xFFFF /* CHIP_ID - [15:0] */
#define WM831X_CHIP_ID_SHIFT 0 /* CHIP_ID - [15:0] */
#define WM831X_CHIP_ID_WIDTH 16 /* CHIP_ID - [15:0] */
/*
* R30731 (0x780B) - Factory OTP 3
*/
#define WM831X_OSC_TRIM_MASK 0x0780 /* OSC_TRIM - [10:7] */
#define WM831X_OSC_TRIM_SHIFT 7 /* OSC_TRIM - [10:7] */
#define WM831X_OSC_TRIM_WIDTH 4 /* OSC_TRIM - [10:7] */
#define WM831X_BG_TRIM_MASK 0x0078 /* BG_TRIM - [6:3] */
#define WM831X_BG_TRIM_SHIFT 3 /* BG_TRIM - [6:3] */
#define WM831X_BG_TRIM_WIDTH 4 /* BG_TRIM - [6:3] */
#define WM831X_LPBG_TRIM_MASK 0x0007 /* LPBG_TRIM - [2:0] */
#define WM831X_LPBG_TRIM_SHIFT 0 /* LPBG_TRIM - [2:0] */
#define WM831X_LPBG_TRIM_WIDTH 3 /* LPBG_TRIM - [2:0] */
/*
* R30732 (0x780C) - Factory OTP 4
*/
#define WM831X_CHILD_I2C_ADDR_MASK 0x00FE /* CHILD_I2C_ADDR - [7:1] */
#define WM831X_CHILD_I2C_ADDR_SHIFT 1 /* CHILD_I2C_ADDR - [7:1] */
#define WM831X_CHILD_I2C_ADDR_WIDTH 7 /* CHILD_I2C_ADDR - [7:1] */
#define WM831X_CH_AW 0x0001 /* CH_AW */
#define WM831X_CH_AW_MASK 0x0001 /* CH_AW */
#define WM831X_CH_AW_SHIFT 0 /* CH_AW */
#define WM831X_CH_AW_WIDTH 1 /* CH_AW */
/*
* R30733 (0x780D) - Factory OTP 5
*/
#define WM831X_CHARGE_TRIM_MASK 0x003F /* CHARGE_TRIM - [5:0] */
#define WM831X_CHARGE_TRIM_SHIFT 0 /* CHARGE_TRIM - [5:0] */
#define WM831X_CHARGE_TRIM_WIDTH 6 /* CHARGE_TRIM - [5:0] */
/*
* R30736 (0x7810) - Customer OTP ID
*/
#define WM831X_OTP_AUTO_PROG 0x8000 /* OTP_AUTO_PROG */
#define WM831X_OTP_AUTO_PROG_MASK 0x8000 /* OTP_AUTO_PROG */
#define WM831X_OTP_AUTO_PROG_SHIFT 15 /* OTP_AUTO_PROG */
#define WM831X_OTP_AUTO_PROG_WIDTH 1 /* OTP_AUTO_PROG */
#define WM831X_OTP_CUST_ID_MASK 0x7FFE /* OTP_CUST_ID - [14:1] */
#define WM831X_OTP_CUST_ID_SHIFT 1 /* OTP_CUST_ID - [14:1] */
#define WM831X_OTP_CUST_ID_WIDTH 14 /* OTP_CUST_ID - [14:1] */
#define WM831X_OTP_CUST_FINAL 0x0001 /* OTP_CUST_FINAL */
#define WM831X_OTP_CUST_FINAL_MASK 0x0001 /* OTP_CUST_FINAL */
#define WM831X_OTP_CUST_FINAL_SHIFT 0 /* OTP_CUST_FINAL */
#define WM831X_OTP_CUST_FINAL_WIDTH 1 /* OTP_CUST_FINAL */
/*
* R30759 (0x7827) - DBE CHECK DATA
*/
#define WM831X_DBE_VALID_DATA_MASK 0xFFFF /* DBE_VALID_DATA - [15:0] */
#define WM831X_DBE_VALID_DATA_SHIFT 0 /* DBE_VALID_DATA - [15:0] */
#define WM831X_DBE_VALID_DATA_WIDTH 16 /* DBE_VALID_DATA - [15:0] */
#endif

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/*
* include/linux/mfd/wm831x/pdata.h -- Platform data for WM831x
*
* Copyright 2009 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __MFD_WM831X_PDATA_H__
#define __MFD_WM831X_PDATA_H__
struct wm831x;
struct regulator_init_data;
struct wm831x_backlight_pdata {
int isink; /** ISINK to use, 1 or 2 */
int max_uA; /** Maximum current to allow */
};
struct wm831x_backup_pdata {
int charger_enable;
int no_constant_voltage; /** Disable constant voltage charging */
int vlim; /** Voltage limit in millivolts */
int ilim; /** Current limit in microamps */
};
struct wm831x_battery_pdata {
int enable; /** Enable charging */
int fast_enable; /** Enable fast charging */
int off_mask; /** Mask OFF while charging */
int trickle_ilim; /** Trickle charge current limit, in mA */
int vsel; /** Target voltage, in mV */
int eoc_iterm; /** End of trickle charge current, in mA */
int fast_ilim; /** Fast charge current limit, in mA */
int timeout; /** Charge cycle timeout, in minutes */
};
/**
* Configuration for the WM831x DC-DC BuckWise convertors. This
* should be passed as driver_data in the regulator_init_data.
*
* Currently all the configuration is for the fast DVS switching
* support of the devices. This allows MFPs on the device to be
* configured as an input to switch between two output voltages,
* allowing voltage transitions without the expense of an access over
* I2C or SPI buses.
*/
struct wm831x_buckv_pdata {
int dvs_gpio; /** CPU GPIO to use for DVS switching */
int dvs_control_src; /** Hardware DVS source to use (1 or 2) */
int dvs_init_state; /** DVS state to expect on startup */
int dvs_state_gpio; /** CPU GPIO to use for monitoring status */
};
/* Sources for status LED configuration. Values are register values
* plus 1 to allow for a zero default for preserve.
*/
enum wm831x_status_src {
WM831X_STATUS_PRESERVE = 0, /* Keep the current hardware setting */
WM831X_STATUS_OTP = 1,
WM831X_STATUS_POWER = 2,
WM831X_STATUS_CHARGER = 3,
WM831X_STATUS_MANUAL = 4,
};
struct wm831x_status_pdata {
enum wm831x_status_src default_src;
const char *name;
const char *default_trigger;
};
struct wm831x_touch_pdata {
int fivewire; /** 1 for five wire mode, 0 for 4 wire */
int isel; /** Current for pen down (uA) */
int rpu; /** Pen down sensitivity resistor divider */
int pressure; /** Report pressure (boolean) */
unsigned int data_irq; /** Touch data ready IRQ */
int data_irqf; /** IRQ flags for data ready IRQ */
unsigned int pd_irq; /** Touch pendown detect IRQ */
int pd_irqf; /** IRQ flags for pen down IRQ */
};
enum wm831x_watchdog_action {
WM831X_WDOG_NONE = 0,
WM831X_WDOG_INTERRUPT = 1,
WM831X_WDOG_RESET = 2,
WM831X_WDOG_WAKE = 3,
};
struct wm831x_watchdog_pdata {
enum wm831x_watchdog_action primary, secondary;
int update_gpio;
unsigned int software:1;
};
#define WM831X_MAX_STATUS 2
#define WM831X_MAX_DCDC 4
#define WM831X_MAX_EPE 2
#define WM831X_MAX_LDO 11
#define WM831X_MAX_ISINK 2
#define WM831X_GPIO_CONFIGURE 0x10000
#define WM831X_GPIO_NUM 16
struct wm831x_pdata {
/** Used to distinguish multiple WM831x chips */
int wm831x_num;
/** Called before subdevices are set up */
int (*pre_init)(struct wm831x *wm831x);
/** Called after subdevices are set up */
int (*post_init)(struct wm831x *wm831x);
/** Put the /IRQ line into CMOS mode */
bool irq_cmos;
/** Disable the touchscreen */
bool disable_touch;
/** The driver should initiate a power off sequence during shutdown */
bool soft_shutdown;
int irq_base;
int gpio_base;
int gpio_defaults[WM831X_GPIO_NUM];
struct wm831x_backlight_pdata *backlight;
struct wm831x_backup_pdata *backup;
struct wm831x_battery_pdata *battery;
struct wm831x_touch_pdata *touch;
struct wm831x_watchdog_pdata *watchdog;
/** LED1 = 0 and so on */
struct wm831x_status_pdata *status[WM831X_MAX_STATUS];
/** DCDC1 = 0 and so on */
struct regulator_init_data *dcdc[WM831X_MAX_DCDC];
/** EPE1 = 0 and so on */
struct regulator_init_data *epe[WM831X_MAX_EPE];
/** LDO1 = 0 and so on */
struct regulator_init_data *ldo[WM831X_MAX_LDO];
/** ISINK1 = 0 and so on*/
struct regulator_init_data *isink[WM831X_MAX_ISINK];
};
#endif

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/*
* include/linux/mfd/wm831x/pmu.h -- PMU for WM831x
*
* Copyright 2009 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __MFD_WM831X_PMU_H__
#define __MFD_WM831X_PMU_H__
/*
* R16387 (0x4003) - Power State
*/
#define WM831X_CHIP_ON 0x8000 /* CHIP_ON */
#define WM831X_CHIP_ON_MASK 0x8000 /* CHIP_ON */
#define WM831X_CHIP_ON_SHIFT 15 /* CHIP_ON */
#define WM831X_CHIP_ON_WIDTH 1 /* CHIP_ON */
#define WM831X_CHIP_SLP 0x4000 /* CHIP_SLP */
#define WM831X_CHIP_SLP_MASK 0x4000 /* CHIP_SLP */
#define WM831X_CHIP_SLP_SHIFT 14 /* CHIP_SLP */
#define WM831X_CHIP_SLP_WIDTH 1 /* CHIP_SLP */
#define WM831X_REF_LP 0x1000 /* REF_LP */
#define WM831X_REF_LP_MASK 0x1000 /* REF_LP */
#define WM831X_REF_LP_SHIFT 12 /* REF_LP */
#define WM831X_REF_LP_WIDTH 1 /* REF_LP */
#define WM831X_PWRSTATE_DLY_MASK 0x0C00 /* PWRSTATE_DLY - [11:10] */
#define WM831X_PWRSTATE_DLY_SHIFT 10 /* PWRSTATE_DLY - [11:10] */
#define WM831X_PWRSTATE_DLY_WIDTH 2 /* PWRSTATE_DLY - [11:10] */
#define WM831X_SWRST_DLY 0x0200 /* SWRST_DLY */
#define WM831X_SWRST_DLY_MASK 0x0200 /* SWRST_DLY */
#define WM831X_SWRST_DLY_SHIFT 9 /* SWRST_DLY */
#define WM831X_SWRST_DLY_WIDTH 1 /* SWRST_DLY */
#define WM831X_USB100MA_STARTUP_MASK 0x0030 /* USB100MA_STARTUP - [5:4] */
#define WM831X_USB100MA_STARTUP_SHIFT 4 /* USB100MA_STARTUP - [5:4] */
#define WM831X_USB100MA_STARTUP_WIDTH 2 /* USB100MA_STARTUP - [5:4] */
#define WM831X_USB_CURR_STS 0x0008 /* USB_CURR_STS */
#define WM831X_USB_CURR_STS_MASK 0x0008 /* USB_CURR_STS */
#define WM831X_USB_CURR_STS_SHIFT 3 /* USB_CURR_STS */
#define WM831X_USB_CURR_STS_WIDTH 1 /* USB_CURR_STS */
#define WM831X_USB_ILIM_MASK 0x0007 /* USB_ILIM - [2:0] */
#define WM831X_USB_ILIM_SHIFT 0 /* USB_ILIM - [2:0] */
#define WM831X_USB_ILIM_WIDTH 3 /* USB_ILIM - [2:0] */
/*
* R16397 (0x400D) - System Status
*/
#define WM831X_THW_STS 0x8000 /* THW_STS */
#define WM831X_THW_STS_MASK 0x8000 /* THW_STS */
#define WM831X_THW_STS_SHIFT 15 /* THW_STS */
#define WM831X_THW_STS_WIDTH 1 /* THW_STS */
#define WM831X_PWR_SRC_BATT 0x0400 /* PWR_SRC_BATT */
#define WM831X_PWR_SRC_BATT_MASK 0x0400 /* PWR_SRC_BATT */
#define WM831X_PWR_SRC_BATT_SHIFT 10 /* PWR_SRC_BATT */
#define WM831X_PWR_SRC_BATT_WIDTH 1 /* PWR_SRC_BATT */
#define WM831X_PWR_WALL 0x0200 /* PWR_WALL */
#define WM831X_PWR_WALL_MASK 0x0200 /* PWR_WALL */
#define WM831X_PWR_WALL_SHIFT 9 /* PWR_WALL */
#define WM831X_PWR_WALL_WIDTH 1 /* PWR_WALL */
#define WM831X_PWR_USB 0x0100 /* PWR_USB */
#define WM831X_PWR_USB_MASK 0x0100 /* PWR_USB */
#define WM831X_PWR_USB_SHIFT 8 /* PWR_USB */
#define WM831X_PWR_USB_WIDTH 1 /* PWR_USB */
#define WM831X_MAIN_STATE_MASK 0x001F /* MAIN_STATE - [4:0] */
#define WM831X_MAIN_STATE_SHIFT 0 /* MAIN_STATE - [4:0] */
#define WM831X_MAIN_STATE_WIDTH 5 /* MAIN_STATE - [4:0] */
/*
* R16456 (0x4048) - Charger Control 1
*/
#define WM831X_CHG_ENA 0x8000 /* CHG_ENA */
#define WM831X_CHG_ENA_MASK 0x8000 /* CHG_ENA */
#define WM831X_CHG_ENA_SHIFT 15 /* CHG_ENA */
#define WM831X_CHG_ENA_WIDTH 1 /* CHG_ENA */
#define WM831X_CHG_FRC 0x4000 /* CHG_FRC */
#define WM831X_CHG_FRC_MASK 0x4000 /* CHG_FRC */
#define WM831X_CHG_FRC_SHIFT 14 /* CHG_FRC */
#define WM831X_CHG_FRC_WIDTH 1 /* CHG_FRC */
#define WM831X_CHG_ITERM_MASK 0x1C00 /* CHG_ITERM - [12:10] */
#define WM831X_CHG_ITERM_SHIFT 10 /* CHG_ITERM - [12:10] */
#define WM831X_CHG_ITERM_WIDTH 3 /* CHG_ITERM - [12:10] */
#define WM831X_CHG_FAST 0x0020 /* CHG_FAST */
#define WM831X_CHG_FAST_MASK 0x0020 /* CHG_FAST */
#define WM831X_CHG_FAST_SHIFT 5 /* CHG_FAST */
#define WM831X_CHG_FAST_WIDTH 1 /* CHG_FAST */
#define WM831X_CHG_IMON_ENA 0x0002 /* CHG_IMON_ENA */
#define WM831X_CHG_IMON_ENA_MASK 0x0002 /* CHG_IMON_ENA */
#define WM831X_CHG_IMON_ENA_SHIFT 1 /* CHG_IMON_ENA */
#define WM831X_CHG_IMON_ENA_WIDTH 1 /* CHG_IMON_ENA */
#define WM831X_CHG_CHIP_TEMP_MON 0x0001 /* CHG_CHIP_TEMP_MON */
#define WM831X_CHG_CHIP_TEMP_MON_MASK 0x0001 /* CHG_CHIP_TEMP_MON */
#define WM831X_CHG_CHIP_TEMP_MON_SHIFT 0 /* CHG_CHIP_TEMP_MON */
#define WM831X_CHG_CHIP_TEMP_MON_WIDTH 1 /* CHG_CHIP_TEMP_MON */
/*
* R16457 (0x4049) - Charger Control 2
*/
#define WM831X_CHG_OFF_MSK 0x4000 /* CHG_OFF_MSK */
#define WM831X_CHG_OFF_MSK_MASK 0x4000 /* CHG_OFF_MSK */
#define WM831X_CHG_OFF_MSK_SHIFT 14 /* CHG_OFF_MSK */
#define WM831X_CHG_OFF_MSK_WIDTH 1 /* CHG_OFF_MSK */
#define WM831X_CHG_TIME_MASK 0x0F00 /* CHG_TIME - [11:8] */
#define WM831X_CHG_TIME_SHIFT 8 /* CHG_TIME - [11:8] */
#define WM831X_CHG_TIME_WIDTH 4 /* CHG_TIME - [11:8] */
#define WM831X_CHG_TRKL_ILIM_MASK 0x00C0 /* CHG_TRKL_ILIM - [7:6] */
#define WM831X_CHG_TRKL_ILIM_SHIFT 6 /* CHG_TRKL_ILIM - [7:6] */
#define WM831X_CHG_TRKL_ILIM_WIDTH 2 /* CHG_TRKL_ILIM - [7:6] */
#define WM831X_CHG_VSEL_MASK 0x0030 /* CHG_VSEL - [5:4] */
#define WM831X_CHG_VSEL_SHIFT 4 /* CHG_VSEL - [5:4] */
#define WM831X_CHG_VSEL_WIDTH 2 /* CHG_VSEL - [5:4] */
#define WM831X_CHG_FAST_ILIM_MASK 0x000F /* CHG_FAST_ILIM - [3:0] */
#define WM831X_CHG_FAST_ILIM_SHIFT 0 /* CHG_FAST_ILIM - [3:0] */
#define WM831X_CHG_FAST_ILIM_WIDTH 4 /* CHG_FAST_ILIM - [3:0] */
/*
* R16458 (0x404A) - Charger Status
*/
#define WM831X_BATT_OV_STS 0x8000 /* BATT_OV_STS */
#define WM831X_BATT_OV_STS_MASK 0x8000 /* BATT_OV_STS */
#define WM831X_BATT_OV_STS_SHIFT 15 /* BATT_OV_STS */
#define WM831X_BATT_OV_STS_WIDTH 1 /* BATT_OV_STS */
#define WM831X_CHG_STATE_MASK 0x7000 /* CHG_STATE - [14:12] */
#define WM831X_CHG_STATE_SHIFT 12 /* CHG_STATE - [14:12] */
#define WM831X_CHG_STATE_WIDTH 3 /* CHG_STATE - [14:12] */
#define WM831X_BATT_HOT_STS 0x0800 /* BATT_HOT_STS */
#define WM831X_BATT_HOT_STS_MASK 0x0800 /* BATT_HOT_STS */
#define WM831X_BATT_HOT_STS_SHIFT 11 /* BATT_HOT_STS */
#define WM831X_BATT_HOT_STS_WIDTH 1 /* BATT_HOT_STS */
#define WM831X_BATT_COLD_STS 0x0400 /* BATT_COLD_STS */
#define WM831X_BATT_COLD_STS_MASK 0x0400 /* BATT_COLD_STS */
#define WM831X_BATT_COLD_STS_SHIFT 10 /* BATT_COLD_STS */
#define WM831X_BATT_COLD_STS_WIDTH 1 /* BATT_COLD_STS */
#define WM831X_CHG_TOPOFF 0x0200 /* CHG_TOPOFF */
#define WM831X_CHG_TOPOFF_MASK 0x0200 /* CHG_TOPOFF */
#define WM831X_CHG_TOPOFF_SHIFT 9 /* CHG_TOPOFF */
#define WM831X_CHG_TOPOFF_WIDTH 1 /* CHG_TOPOFF */
#define WM831X_CHG_ACTIVE 0x0100 /* CHG_ACTIVE */
#define WM831X_CHG_ACTIVE_MASK 0x0100 /* CHG_ACTIVE */
#define WM831X_CHG_ACTIVE_SHIFT 8 /* CHG_ACTIVE */
#define WM831X_CHG_ACTIVE_WIDTH 1 /* CHG_ACTIVE */
#define WM831X_CHG_TIME_ELAPSED_MASK 0x00FF /* CHG_TIME_ELAPSED - [7:0] */
#define WM831X_CHG_TIME_ELAPSED_SHIFT 0 /* CHG_TIME_ELAPSED - [7:0] */
#define WM831X_CHG_TIME_ELAPSED_WIDTH 8 /* CHG_TIME_ELAPSED - [7:0] */
#define WM831X_CHG_STATE_OFF (0 << WM831X_CHG_STATE_SHIFT)
#define WM831X_CHG_STATE_TRICKLE (1 << WM831X_CHG_STATE_SHIFT)
#define WM831X_CHG_STATE_FAST (2 << WM831X_CHG_STATE_SHIFT)
#define WM831X_CHG_STATE_TRICKLE_OT (3 << WM831X_CHG_STATE_SHIFT)
#define WM831X_CHG_STATE_FAST_OT (4 << WM831X_CHG_STATE_SHIFT)
#define WM831X_CHG_STATE_DEFECTIVE (5 << WM831X_CHG_STATE_SHIFT)
/*
* R16459 (0x404B) - Backup Charger Control
*/
#define WM831X_BKUP_CHG_ENA 0x8000 /* BKUP_CHG_ENA */
#define WM831X_BKUP_CHG_ENA_MASK 0x8000 /* BKUP_CHG_ENA */
#define WM831X_BKUP_CHG_ENA_SHIFT 15 /* BKUP_CHG_ENA */
#define WM831X_BKUP_CHG_ENA_WIDTH 1 /* BKUP_CHG_ENA */
#define WM831X_BKUP_CHG_STS 0x4000 /* BKUP_CHG_STS */
#define WM831X_BKUP_CHG_STS_MASK 0x4000 /* BKUP_CHG_STS */
#define WM831X_BKUP_CHG_STS_SHIFT 14 /* BKUP_CHG_STS */
#define WM831X_BKUP_CHG_STS_WIDTH 1 /* BKUP_CHG_STS */
#define WM831X_BKUP_CHG_MODE 0x1000 /* BKUP_CHG_MODE */
#define WM831X_BKUP_CHG_MODE_MASK 0x1000 /* BKUP_CHG_MODE */
#define WM831X_BKUP_CHG_MODE_SHIFT 12 /* BKUP_CHG_MODE */
#define WM831X_BKUP_CHG_MODE_WIDTH 1 /* BKUP_CHG_MODE */
#define WM831X_BKUP_BATT_DET_ENA 0x0800 /* BKUP_BATT_DET_ENA */
#define WM831X_BKUP_BATT_DET_ENA_MASK 0x0800 /* BKUP_BATT_DET_ENA */
#define WM831X_BKUP_BATT_DET_ENA_SHIFT 11 /* BKUP_BATT_DET_ENA */
#define WM831X_BKUP_BATT_DET_ENA_WIDTH 1 /* BKUP_BATT_DET_ENA */
#define WM831X_BKUP_BATT_STS 0x0400 /* BKUP_BATT_STS */
#define WM831X_BKUP_BATT_STS_MASK 0x0400 /* BKUP_BATT_STS */
#define WM831X_BKUP_BATT_STS_SHIFT 10 /* BKUP_BATT_STS */
#define WM831X_BKUP_BATT_STS_WIDTH 1 /* BKUP_BATT_STS */
#define WM831X_BKUP_CHG_VLIM 0x0010 /* BKUP_CHG_VLIM */
#define WM831X_BKUP_CHG_VLIM_MASK 0x0010 /* BKUP_CHG_VLIM */
#define WM831X_BKUP_CHG_VLIM_SHIFT 4 /* BKUP_CHG_VLIM */
#define WM831X_BKUP_CHG_VLIM_WIDTH 1 /* BKUP_CHG_VLIM */
#define WM831X_BKUP_CHG_ILIM_MASK 0x0003 /* BKUP_CHG_ILIM - [1:0] */
#define WM831X_BKUP_CHG_ILIM_SHIFT 0 /* BKUP_CHG_ILIM - [1:0] */
#define WM831X_BKUP_CHG_ILIM_WIDTH 2 /* BKUP_CHG_ILIM - [1:0] */
#endif

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include/linux/mfd/wm831x/regulator.h Normal file
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include/linux/mfd/wm831x/status.h Normal file
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/*
* include/linux/mfd/wm831x/status.h -- Status LEDs for WM831x
*
* Copyright 2009 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __MFD_WM831X_STATUS_H__
#define __MFD_WM831X_STATUS_H__
#define WM831X_LED_SRC_MASK 0xC000 /* LED_SRC - [15:14] */
#define WM831X_LED_SRC_SHIFT 14 /* LED_SRC - [15:14] */
#define WM831X_LED_SRC_WIDTH 2 /* LED_SRC - [15:14] */
#define WM831X_LED_MODE_MASK 0x0300 /* LED_MODE - [9:8] */
#define WM831X_LED_MODE_SHIFT 8 /* LED_MODE - [9:8] */
#define WM831X_LED_MODE_WIDTH 2 /* LED_MODE - [9:8] */
#define WM831X_LED_SEQ_LEN_MASK 0x0030 /* LED_SEQ_LEN - [5:4] */
#define WM831X_LED_SEQ_LEN_SHIFT 4 /* LED_SEQ_LEN - [5:4] */
#define WM831X_LED_SEQ_LEN_WIDTH 2 /* LED_SEQ_LEN - [5:4] */
#define WM831X_LED_DUR_MASK 0x000C /* LED_DUR - [3:2] */
#define WM831X_LED_DUR_SHIFT 2 /* LED_DUR - [3:2] */
#define WM831X_LED_DUR_WIDTH 2 /* LED_DUR - [3:2] */
#define WM831X_LED_DUTY_CYC_MASK 0x0003 /* LED_DUTY_CYC - [1:0] */
#define WM831X_LED_DUTY_CYC_SHIFT 0 /* LED_DUTY_CYC - [1:0] */
#define WM831X_LED_DUTY_CYC_WIDTH 2 /* LED_DUTY_CYC - [1:0] */
#endif

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/*
* include/linux/mfd/wm831x/watchdog.h -- Watchdog for WM831x
*
* Copyright 2009 Wolfson Microelectronics PLC.
*
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __MFD_WM831X_WATCHDOG_H__
#define __MFD_WM831X_WATCHDOG_H__
/*
* R16388 (0x4004) - Watchdog
*/
#define WM831X_WDOG_ENA 0x8000 /* WDOG_ENA */
#define WM831X_WDOG_ENA_MASK 0x8000 /* WDOG_ENA */
#define WM831X_WDOG_ENA_SHIFT 15 /* WDOG_ENA */
#define WM831X_WDOG_ENA_WIDTH 1 /* WDOG_ENA */
#define WM831X_WDOG_DEBUG 0x4000 /* WDOG_DEBUG */
#define WM831X_WDOG_DEBUG_MASK 0x4000 /* WDOG_DEBUG */
#define WM831X_WDOG_DEBUG_SHIFT 14 /* WDOG_DEBUG */
#define WM831X_WDOG_DEBUG_WIDTH 1 /* WDOG_DEBUG */
#define WM831X_WDOG_RST_SRC 0x2000 /* WDOG_RST_SRC */
#define WM831X_WDOG_RST_SRC_MASK 0x2000 /* WDOG_RST_SRC */
#define WM831X_WDOG_RST_SRC_SHIFT 13 /* WDOG_RST_SRC */
#define WM831X_WDOG_RST_SRC_WIDTH 1 /* WDOG_RST_SRC */
#define WM831X_WDOG_SLPENA 0x1000 /* WDOG_SLPENA */
#define WM831X_WDOG_SLPENA_MASK 0x1000 /* WDOG_SLPENA */
#define WM831X_WDOG_SLPENA_SHIFT 12 /* WDOG_SLPENA */
#define WM831X_WDOG_SLPENA_WIDTH 1 /* WDOG_SLPENA */
#define WM831X_WDOG_RESET 0x0800 /* WDOG_RESET */
#define WM831X_WDOG_RESET_MASK 0x0800 /* WDOG_RESET */
#define WM831X_WDOG_RESET_SHIFT 11 /* WDOG_RESET */
#define WM831X_WDOG_RESET_WIDTH 1 /* WDOG_RESET */
#define WM831X_WDOG_SECACT_MASK 0x0300 /* WDOG_SECACT - [9:8] */
#define WM831X_WDOG_SECACT_SHIFT 8 /* WDOG_SECACT - [9:8] */
#define WM831X_WDOG_SECACT_WIDTH 2 /* WDOG_SECACT - [9:8] */
#define WM831X_WDOG_PRIMACT_MASK 0x0030 /* WDOG_PRIMACT - [5:4] */
#define WM831X_WDOG_PRIMACT_SHIFT 4 /* WDOG_PRIMACT - [5:4] */
#define WM831X_WDOG_PRIMACT_WIDTH 2 /* WDOG_PRIMACT - [5:4] */
#define WM831X_WDOG_TO_MASK 0x0007 /* WDOG_TO - [2:0] */
#define WM831X_WDOG_TO_SHIFT 0 /* WDOG_TO - [2:0] */
#define WM831X_WDOG_TO_WIDTH 3 /* WDOG_TO - [2:0] */
#endif