mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
7
include/linux/mmc/boot.h
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7
include/linux/mmc/boot.h
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@ -0,0 +1,7 @@
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#ifndef LINUX_MMC_BOOT_H
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#define LINUX_MMC_BOOT_H
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enum { MMC_PROGRESS_ENTER, MMC_PROGRESS_INIT,
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MMC_PROGRESS_LOAD, MMC_PROGRESS_DONE };
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#endif /* LINUX_MMC_BOOT_H */
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553
include/linux/mmc/card.h
Normal file
553
include/linux/mmc/card.h
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@ -0,0 +1,553 @@
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/*
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* linux/include/linux/mmc/card.h
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Card driver specific definitions.
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*/
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#ifndef LINUX_MMC_CARD_H
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#define LINUX_MMC_CARD_H
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#include <linux/device.h>
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#include <linux/mmc/core.h>
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#include <linux/mod_devicetable.h>
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struct mmc_cid {
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unsigned int manfid;
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char prod_name[8];
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unsigned char prv;
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unsigned int serial;
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unsigned short oemid;
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unsigned short year;
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unsigned char hwrev;
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unsigned char fwrev;
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unsigned char month;
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};
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struct mmc_csd {
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unsigned char structure;
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unsigned char mmca_vsn;
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unsigned short cmdclass;
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unsigned short tacc_clks;
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unsigned int tacc_ns;
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unsigned int c_size;
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unsigned int r2w_factor;
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unsigned int max_dtr;
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unsigned int erase_size; /* In sectors */
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unsigned int read_blkbits;
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unsigned int write_blkbits;
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unsigned int capacity;
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unsigned int read_partial:1,
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read_misalign:1,
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write_partial:1,
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write_misalign:1,
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dsr_imp:1;
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};
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struct mmc_ext_csd {
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u8 rev;
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u8 erase_group_def;
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u8 sec_feature_support;
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u8 rel_sectors;
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u8 rel_param;
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u8 part_config;
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u8 cache_ctrl;
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u8 rst_n_function;
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u8 max_packed_writes;
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u8 max_packed_reads;
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u8 packed_event_en;
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unsigned int part_time; /* Units: ms */
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unsigned int sa_timeout; /* Units: 100ns */
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unsigned int generic_cmd6_time; /* Units: 10ms */
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unsigned int power_off_longtime; /* Units: ms */
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u8 power_off_notification; /* state */
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unsigned int hs_max_dtr;
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unsigned int hs200_max_dtr;
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#define MMC_HIGH_26_MAX_DTR 26000000
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#define MMC_HIGH_52_MAX_DTR 52000000
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#define MMC_HIGH_DDR_MAX_DTR 52000000
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#define MMC_HS200_MAX_DTR 200000000
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unsigned int sectors;
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unsigned int hc_erase_size; /* In sectors */
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unsigned int hc_erase_timeout; /* In milliseconds */
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unsigned int sec_trim_mult; /* Secure trim multiplier */
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unsigned int sec_erase_mult; /* Secure erase multiplier */
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unsigned int trim_timeout; /* In milliseconds */
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bool partition_setting_completed; /* enable bit */
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unsigned long long enhanced_area_offset; /* Units: Byte */
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unsigned int enhanced_area_size; /* Units: KB */
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unsigned int cache_size; /* Units: KB */
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bool hpi_en; /* HPI enablebit */
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bool hpi; /* HPI support bit */
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unsigned int hpi_cmd; /* cmd used as HPI */
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bool bkops; /* background support bit */
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bool bkops_en; /* background enable bit */
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unsigned int data_sector_size; /* 512 bytes or 4KB */
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unsigned int data_tag_unit_size; /* DATA TAG UNIT size */
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unsigned int boot_ro_lock; /* ro lock support */
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bool boot_ro_lockable;
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u8 raw_exception_status; /* 54 */
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u8 raw_partition_support; /* 160 */
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u8 raw_rpmb_size_mult; /* 168 */
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u8 raw_erased_mem_count; /* 181 */
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u8 enhanced_strobe_support; /* 184 */
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#define MMC_STROBE_ENHANCED_SUPPORT BIT(0)
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u8 raw_ext_csd_structure; /* 194 */
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u8 raw_card_type; /* 196 */
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u8 out_of_int_time; /* 198 */
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u8 raw_pwr_cl_52_195; /* 200 */
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u8 raw_pwr_cl_26_195; /* 201 */
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u8 raw_pwr_cl_52_360; /* 202 */
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u8 raw_pwr_cl_26_360; /* 203 */
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u8 raw_s_a_timeout; /* 217 */
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u8 raw_hc_erase_gap_size; /* 221 */
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u8 raw_erase_timeout_mult; /* 223 */
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u8 raw_hc_erase_grp_size; /* 224 */
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u8 raw_sec_trim_mult; /* 229 */
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u8 raw_sec_erase_mult; /* 230 */
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u8 raw_sec_feature_support;/* 231 */
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u8 raw_trim_mult; /* 232 */
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u8 raw_pwr_cl_200_195; /* 236 */
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u8 raw_pwr_cl_200_360; /* 237 */
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u8 raw_pwr_cl_ddr_52_195; /* 238 */
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u8 raw_pwr_cl_ddr_52_360; /* 239 */
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u8 raw_pwr_cl_ddr_200_360; /* 253 */
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u8 raw_bkops_status; /* 246 */
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u8 raw_sectors[4]; /* 212 - 4 bytes */
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unsigned int feature_support;
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#define MMC_DISCARD_FEATURE BIT(0) /* CMD38 feature */
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/*
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* smart_info : It's for eMMC 5.0 or later device
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* [63:56] : DEVICE_LIFE_TIME_EST_TYPE_B [269]
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* [55:48] : DEVICE_LIFE_TIME_EST_TYPE_A [268]
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* [47:40] : PRE_EOL_INFO [267]
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* [39:32] : OPTIMAL_TRIM_UNIT_SIZE [264]
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* [31:16] : DEVICE_VERSION [263-262]
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* [15:08] : HC_ERASE_GRP_SIZE [224]
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* [07:00] : HC_WP_GRP_SIZE [221]
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*/
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unsigned long long smart_info;
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/*
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* fwdate : It's for eMMC 5.0 or later device
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* [63:00] : FIRMWARE_VERSION [261-254]
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*/
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unsigned long long fwdate;
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};
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struct sd_scr {
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unsigned char sda_vsn;
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unsigned char sda_spec3;
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unsigned char bus_widths;
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#define SD_SCR_BUS_WIDTH_1 (1<<0)
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#define SD_SCR_BUS_WIDTH_4 (1<<2)
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unsigned char cmds;
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#define SD_SCR_CMD20_SUPPORT (1<<0)
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#define SD_SCR_CMD23_SUPPORT (1<<1)
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};
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struct sd_ssr {
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unsigned int au; /* In sectors */
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unsigned int erase_timeout; /* In milliseconds */
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unsigned int erase_offset; /* In milliseconds */
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};
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struct sd_switch_caps {
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unsigned int hs_max_dtr;
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unsigned int uhs_max_dtr;
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#define HIGH_SPEED_MAX_DTR 50000000
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#define UHS_SDR104_MAX_DTR 208000000
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#define UHS_SDR50_MAX_DTR 100000000
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#define UHS_DDR50_MAX_DTR 50000000
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#define UHS_SDR25_MAX_DTR UHS_DDR50_MAX_DTR
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#define UHS_SDR12_MAX_DTR 25000000
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unsigned int sd3_bus_mode;
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#define UHS_SDR12_BUS_SPEED 0
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#define HIGH_SPEED_BUS_SPEED 1
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#define UHS_SDR25_BUS_SPEED 1
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#define UHS_SDR50_BUS_SPEED 2
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#define UHS_SDR104_BUS_SPEED 3
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#define UHS_DDR50_BUS_SPEED 4
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#define SD_MODE_HIGH_SPEED (1 << HIGH_SPEED_BUS_SPEED)
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#define SD_MODE_UHS_SDR12 (1 << UHS_SDR12_BUS_SPEED)
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#define SD_MODE_UHS_SDR25 (1 << UHS_SDR25_BUS_SPEED)
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#define SD_MODE_UHS_SDR50 (1 << UHS_SDR50_BUS_SPEED)
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#define SD_MODE_UHS_SDR104 (1 << UHS_SDR104_BUS_SPEED)
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#define SD_MODE_UHS_DDR50 (1 << UHS_DDR50_BUS_SPEED)
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unsigned int sd3_drv_type;
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#define SD_DRIVER_TYPE_B 0x01
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#define SD_DRIVER_TYPE_A 0x02
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#define SD_DRIVER_TYPE_C 0x04
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#define SD_DRIVER_TYPE_D 0x08
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unsigned int sd3_curr_limit;
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#define SD_SET_CURRENT_LIMIT_200 0
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#define SD_SET_CURRENT_LIMIT_400 1
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#define SD_SET_CURRENT_LIMIT_600 2
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#define SD_SET_CURRENT_LIMIT_800 3
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#define SD_SET_CURRENT_NO_CHANGE (-1)
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#define SD_MAX_CURRENT_200 (1 << SD_SET_CURRENT_LIMIT_200)
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#define SD_MAX_CURRENT_400 (1 << SD_SET_CURRENT_LIMIT_400)
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#define SD_MAX_CURRENT_600 (1 << SD_SET_CURRENT_LIMIT_600)
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#define SD_MAX_CURRENT_800 (1 << SD_SET_CURRENT_LIMIT_800)
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};
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struct sdio_cccr {
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unsigned int sdio_vsn;
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unsigned int sd_vsn;
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unsigned int multi_block:1,
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low_speed:1,
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wide_bus:1,
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high_power:1,
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high_speed:1,
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disable_cd:1;
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};
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struct sdio_cis {
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unsigned short vendor;
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unsigned short device;
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unsigned short blksize;
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unsigned int max_dtr;
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};
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struct mmc_host;
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struct mmc_ios;
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struct sdio_func;
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struct sdio_func_tuple;
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#define SDIO_MAX_FUNCS 7
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enum mmc_blk_status {
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MMC_BLK_SUCCESS = 0,
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MMC_BLK_PARTIAL,
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MMC_BLK_CMD_ERR,
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MMC_BLK_RETRY,
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MMC_BLK_ABORT,
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MMC_BLK_DATA_ERR,
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MMC_BLK_ECC_ERR,
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MMC_BLK_NOMEDIUM,
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MMC_BLK_NEW_REQUEST,
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};
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/* The number of MMC physical partitions. These consist of:
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* boot partitions (2), general purpose partitions (4) and
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* RPMB partition (1) in MMC v4.4.
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*/
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#define MMC_NUM_BOOT_PARTITION 2
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#define MMC_NUM_GP_PARTITION 4
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#define MMC_NUM_PHY_PARTITION 7
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#define MAX_MMC_PART_NAME_LEN 20
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/*
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* MMC Physical partitions
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*/
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struct mmc_part {
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unsigned int size; /* partition size (in bytes) */
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unsigned int part_cfg; /* partition type */
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char name[MAX_MMC_PART_NAME_LEN];
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bool force_ro; /* to make boot parts RO by default */
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unsigned int area_type;
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#define MMC_BLK_DATA_AREA_MAIN (1<<0)
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#define MMC_BLK_DATA_AREA_BOOT (1<<1)
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#define MMC_BLK_DATA_AREA_GP (1<<2)
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#define MMC_BLK_DATA_AREA_RPMB (1<<3)
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};
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|
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/*
|
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* MMC device
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*/
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struct mmc_card {
|
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struct mmc_host *host; /* the host this device belongs to */
|
||||
struct device dev; /* the device */
|
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u32 ocr; /* the current OCR setting */
|
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unsigned int rca; /* relative card address of device */
|
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unsigned int type; /* card type */
|
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#define MMC_TYPE_MMC 0 /* MMC card */
|
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#define MMC_TYPE_SD 1 /* SD card */
|
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#define MMC_TYPE_SDIO 2 /* SDIO card */
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#define MMC_TYPE_SD_COMBO 3 /* SD combo (IO+mem) card */
|
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unsigned int state; /* (our) card state */
|
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#define MMC_STATE_PRESENT (1<<0) /* present in sysfs */
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#define MMC_STATE_READONLY (1<<1) /* card is read-only */
|
||||
#define MMC_STATE_BLOCKADDR (1<<2) /* card uses block-addressing */
|
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#define MMC_CARD_SDXC (1<<3) /* card is SDXC */
|
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#define MMC_CARD_REMOVED (1<<4) /* card has been removed */
|
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#define MMC_STATE_DOING_BKOPS (1<<5) /* card is doing BKOPS */
|
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#define MMC_STATE_SUSPENDED (1<<6) /* card is suspended */
|
||||
unsigned int quirks; /* card quirks */
|
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#define MMC_QUIRK_LENIENT_FN0 (1<<0) /* allow SDIO FN0 writes outside of the VS CCCR range */
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#define MMC_QUIRK_BLKSZ_FOR_BYTE_MODE (1<<1) /* use func->cur_blksize */
|
||||
/* for byte mode */
|
||||
#define MMC_QUIRK_NONSTD_SDIO (1<<2) /* non-standard SDIO card attached */
|
||||
/* (missing CIA registers) */
|
||||
#define MMC_QUIRK_BROKEN_CLK_GATING (1<<3) /* clock gating the sdio bus will make card fail */
|
||||
#define MMC_QUIRK_NONSTD_FUNC_IF (1<<4) /* SDIO card has nonstd function interfaces */
|
||||
#define MMC_QUIRK_DISABLE_CD (1<<5) /* disconnect CD/DAT[3] resistor */
|
||||
#define MMC_QUIRK_INAND_CMD38 (1<<6) /* iNAND devices have broken CMD38 */
|
||||
#define MMC_QUIRK_BLK_NO_CMD23 (1<<7) /* Avoid CMD23 for regular multiblock */
|
||||
#define MMC_QUIRK_BROKEN_BYTE_MODE_512 (1<<8) /* Avoid sending 512 bytes in */
|
||||
/* byte mode */
|
||||
#define MMC_QUIRK_LONG_READ_TIME (1<<9) /* Data read time > CSD says */
|
||||
#define MMC_QUIRK_SEC_ERASE_TRIM_BROKEN (1<<10) /* Skip secure for erase/trim */
|
||||
#define MMC_QUIRK_BROKEN_IRQ_POLLING (1<<11) /* Polling SDIO_CCCR_INTx could create a fake interrupt */
|
||||
|
||||
unsigned int erase_size; /* erase size in sectors */
|
||||
unsigned int erase_shift; /* if erase unit is power 2 */
|
||||
unsigned int pref_erase; /* in sectors */
|
||||
u8 erased_byte; /* value of erased bytes */
|
||||
|
||||
u32 raw_cid[4]; /* raw card CID */
|
||||
u32 raw_csd[4]; /* raw card CSD */
|
||||
u32 raw_scr[2]; /* raw card SCR */
|
||||
struct mmc_cid cid; /* card identification */
|
||||
struct mmc_csd csd; /* card specific */
|
||||
struct mmc_ext_csd ext_csd; /* mmc v4 extended card specific */
|
||||
struct sd_scr scr; /* extra SD information */
|
||||
struct sd_ssr ssr; /* yet more SD information */
|
||||
struct sd_switch_caps sw_caps; /* switch (CMD6) caps */
|
||||
|
||||
unsigned int sdio_funcs; /* number of SDIO functions */
|
||||
struct sdio_cccr cccr; /* common card info */
|
||||
struct sdio_cis cis; /* common tuple info */
|
||||
struct sdio_func *sdio_func[SDIO_MAX_FUNCS]; /* SDIO functions (devices) */
|
||||
struct sdio_func *sdio_single_irq; /* SDIO function when only one IRQ active */
|
||||
unsigned num_info; /* number of info strings */
|
||||
const char **info; /* info strings */
|
||||
struct sdio_func_tuple *tuples; /* unknown common tuples */
|
||||
|
||||
unsigned int sd_bus_speed; /* Bus Speed Mode set for the card */
|
||||
unsigned int mmc_avail_type; /* supported device type by both host and card */
|
||||
|
||||
struct dentry *debugfs_root;
|
||||
struct mmc_part part[MMC_NUM_PHY_PARTITION]; /* physical partitions */
|
||||
unsigned int nr_parts;
|
||||
u8 en_strobe_enhanced; /*enhanced strobe ctrl */
|
||||
};
|
||||
|
||||
/*
|
||||
* This function fill contents in mmc_part.
|
||||
*/
|
||||
static inline void mmc_part_add(struct mmc_card *card, unsigned int size,
|
||||
unsigned int part_cfg, char *name, int idx, bool ro,
|
||||
int area_type)
|
||||
{
|
||||
card->part[card->nr_parts].size = size;
|
||||
card->part[card->nr_parts].part_cfg = part_cfg;
|
||||
sprintf(card->part[card->nr_parts].name, name, idx);
|
||||
card->part[card->nr_parts].force_ro = ro;
|
||||
card->part[card->nr_parts].area_type = area_type;
|
||||
card->nr_parts++;
|
||||
}
|
||||
|
||||
static inline bool mmc_large_sector(struct mmc_card *card)
|
||||
{
|
||||
return card->ext_csd.data_sector_size == 4096;
|
||||
}
|
||||
|
||||
/*
|
||||
* The world is not perfect and supplies us with broken mmc/sdio devices.
|
||||
* For at least some of these bugs we need a work-around.
|
||||
*/
|
||||
|
||||
struct mmc_fixup {
|
||||
/* CID-specific fields. */
|
||||
const char *name;
|
||||
|
||||
/* Valid revision range */
|
||||
u64 rev_start, rev_end;
|
||||
|
||||
unsigned int manfid;
|
||||
unsigned short oemid;
|
||||
|
||||
/* SDIO-specfic fields. You can use SDIO_ANY_ID here of course */
|
||||
u16 cis_vendor, cis_device;
|
||||
|
||||
void (*vendor_fixup)(struct mmc_card *card, int data);
|
||||
int data;
|
||||
};
|
||||
|
||||
#define CID_MANFID_ANY (-1u)
|
||||
#define CID_OEMID_ANY ((unsigned short) -1)
|
||||
#define CID_NAME_ANY (NULL)
|
||||
|
||||
#define END_FIXUP { NULL }
|
||||
|
||||
#define _FIXUP_EXT(_name, _manfid, _oemid, _rev_start, _rev_end, \
|
||||
_cis_vendor, _cis_device, \
|
||||
_fixup, _data) \
|
||||
{ \
|
||||
.name = (_name), \
|
||||
.manfid = (_manfid), \
|
||||
.oemid = (_oemid), \
|
||||
.rev_start = (_rev_start), \
|
||||
.rev_end = (_rev_end), \
|
||||
.cis_vendor = (_cis_vendor), \
|
||||
.cis_device = (_cis_device), \
|
||||
.vendor_fixup = (_fixup), \
|
||||
.data = (_data), \
|
||||
}
|
||||
|
||||
#define MMC_FIXUP_REV(_name, _manfid, _oemid, _rev_start, _rev_end, \
|
||||
_fixup, _data) \
|
||||
_FIXUP_EXT(_name, _manfid, \
|
||||
_oemid, _rev_start, _rev_end, \
|
||||
SDIO_ANY_ID, SDIO_ANY_ID, \
|
||||
_fixup, _data) \
|
||||
|
||||
#define MMC_FIXUP(_name, _manfid, _oemid, _fixup, _data) \
|
||||
MMC_FIXUP_REV(_name, _manfid, _oemid, 0, -1ull, _fixup, _data)
|
||||
|
||||
#define SDIO_FIXUP(_vendor, _device, _fixup, _data) \
|
||||
_FIXUP_EXT(CID_NAME_ANY, CID_MANFID_ANY, \
|
||||
CID_OEMID_ANY, 0, -1ull, \
|
||||
_vendor, _device, \
|
||||
_fixup, _data) \
|
||||
|
||||
#define cid_rev(hwrev, fwrev, year, month) \
|
||||
(((u64) hwrev) << 40 | \
|
||||
((u64) fwrev) << 32 | \
|
||||
((u64) year) << 16 | \
|
||||
((u64) month))
|
||||
|
||||
#define cid_rev_card(card) \
|
||||
cid_rev(card->cid.hwrev, \
|
||||
card->cid.fwrev, \
|
||||
card->cid.year, \
|
||||
card->cid.month)
|
||||
|
||||
/*
|
||||
* Unconditionally quirk add/remove.
|
||||
*/
|
||||
|
||||
static inline void __maybe_unused add_quirk(struct mmc_card *card, int data)
|
||||
{
|
||||
card->quirks |= data;
|
||||
}
|
||||
|
||||
static inline void __maybe_unused remove_quirk(struct mmc_card *card, int data)
|
||||
{
|
||||
card->quirks &= ~data;
|
||||
}
|
||||
|
||||
#define mmc_card_mmc(c) ((c)->type == MMC_TYPE_MMC)
|
||||
#define mmc_card_sd(c) ((c)->type == MMC_TYPE_SD)
|
||||
#define mmc_card_sdio(c) ((c)->type == MMC_TYPE_SDIO)
|
||||
|
||||
#define mmc_card_present(c) ((c)->state & MMC_STATE_PRESENT)
|
||||
#define mmc_card_readonly(c) ((c)->state & MMC_STATE_READONLY)
|
||||
#define mmc_card_blockaddr(c) ((c)->state & MMC_STATE_BLOCKADDR)
|
||||
#define mmc_card_ext_capacity(c) ((c)->state & MMC_CARD_SDXC)
|
||||
#define mmc_card_removed(c) ((c) && ((c)->state & MMC_CARD_REMOVED))
|
||||
#define mmc_card_doing_bkops(c) ((c)->state & MMC_STATE_DOING_BKOPS)
|
||||
#define mmc_card_suspended(c) ((c)->state & MMC_STATE_SUSPENDED)
|
||||
|
||||
#define mmc_card_set_present(c) ((c)->state |= MMC_STATE_PRESENT)
|
||||
#define mmc_card_set_readonly(c) ((c)->state |= MMC_STATE_READONLY)
|
||||
#define mmc_card_set_blockaddr(c) ((c)->state |= MMC_STATE_BLOCKADDR)
|
||||
#define mmc_card_set_ext_capacity(c) ((c)->state |= MMC_CARD_SDXC)
|
||||
#define mmc_card_set_removed(c) ((c)->state |= MMC_CARD_REMOVED)
|
||||
#define mmc_card_set_doing_bkops(c) ((c)->state |= MMC_STATE_DOING_BKOPS)
|
||||
#define mmc_card_clr_doing_bkops(c) ((c)->state &= ~MMC_STATE_DOING_BKOPS)
|
||||
#define mmc_card_set_suspended(c) ((c)->state |= MMC_STATE_SUSPENDED)
|
||||
#define mmc_card_clr_suspended(c) ((c)->state &= ~MMC_STATE_SUSPENDED)
|
||||
|
||||
/*
|
||||
* Quirk add/remove for MMC products.
|
||||
*/
|
||||
|
||||
static inline void __maybe_unused add_quirk_mmc(struct mmc_card *card, int data)
|
||||
{
|
||||
if (mmc_card_mmc(card))
|
||||
card->quirks |= data;
|
||||
}
|
||||
|
||||
static inline void __maybe_unused remove_quirk_mmc(struct mmc_card *card,
|
||||
int data)
|
||||
{
|
||||
if (mmc_card_mmc(card))
|
||||
card->quirks &= ~data;
|
||||
}
|
||||
|
||||
/*
|
||||
* Quirk add/remove for SD products.
|
||||
*/
|
||||
|
||||
static inline void __maybe_unused add_quirk_sd(struct mmc_card *card, int data)
|
||||
{
|
||||
if (mmc_card_sd(card))
|
||||
card->quirks |= data;
|
||||
}
|
||||
|
||||
static inline void __maybe_unused remove_quirk_sd(struct mmc_card *card,
|
||||
int data)
|
||||
{
|
||||
if (mmc_card_sd(card))
|
||||
card->quirks &= ~data;
|
||||
}
|
||||
|
||||
static inline int mmc_card_lenient_fn0(const struct mmc_card *c)
|
||||
{
|
||||
return c->quirks & MMC_QUIRK_LENIENT_FN0;
|
||||
}
|
||||
|
||||
static inline int mmc_blksz_for_byte_mode(const struct mmc_card *c)
|
||||
{
|
||||
return c->quirks & MMC_QUIRK_BLKSZ_FOR_BYTE_MODE;
|
||||
}
|
||||
|
||||
static inline int mmc_card_disable_cd(const struct mmc_card *c)
|
||||
{
|
||||
return c->quirks & MMC_QUIRK_DISABLE_CD;
|
||||
}
|
||||
|
||||
static inline int mmc_card_nonstd_func_interface(const struct mmc_card *c)
|
||||
{
|
||||
return c->quirks & MMC_QUIRK_NONSTD_FUNC_IF;
|
||||
}
|
||||
|
||||
static inline int mmc_card_broken_byte_mode_512(const struct mmc_card *c)
|
||||
{
|
||||
return c->quirks & MMC_QUIRK_BROKEN_BYTE_MODE_512;
|
||||
}
|
||||
|
||||
static inline int mmc_card_long_read_time(const struct mmc_card *c)
|
||||
{
|
||||
return c->quirks & MMC_QUIRK_LONG_READ_TIME;
|
||||
}
|
||||
|
||||
static inline int mmc_card_broken_irq_polling(const struct mmc_card *c)
|
||||
{
|
||||
return c->quirks & MMC_QUIRK_BROKEN_IRQ_POLLING;
|
||||
}
|
||||
|
||||
#define mmc_card_name(c) ((c)->cid.prod_name)
|
||||
#define mmc_card_id(c) (dev_name(&(c)->dev))
|
||||
|
||||
#define mmc_dev_to_card(d) container_of(d, struct mmc_card, dev)
|
||||
|
||||
#define mmc_list_to_card(l) container_of(l, struct mmc_card, node)
|
||||
#define mmc_get_drvdata(c) dev_get_drvdata(&(c)->dev)
|
||||
#define mmc_set_drvdata(c,d) dev_set_drvdata(&(c)->dev, d)
|
||||
|
||||
/*
|
||||
* MMC device driver (e.g., Flash card, I/O card...)
|
||||
*/
|
||||
struct mmc_driver {
|
||||
struct device_driver drv;
|
||||
int (*probe)(struct mmc_card *);
|
||||
void (*remove)(struct mmc_card *);
|
||||
int (*suspend)(struct mmc_card *);
|
||||
int (*resume)(struct mmc_card *);
|
||||
void (*shutdown)(struct mmc_card *);
|
||||
};
|
||||
|
||||
extern int mmc_register_driver(struct mmc_driver *);
|
||||
extern void mmc_unregister_driver(struct mmc_driver *);
|
||||
|
||||
extern void mmc_fixup_device(struct mmc_card *card,
|
||||
const struct mmc_fixup *table);
|
||||
|
||||
#endif /* LINUX_MMC_CARD_H */
|
||||
217
include/linux/mmc/core.h
Normal file
217
include/linux/mmc/core.h
Normal file
|
|
@ -0,0 +1,217 @@
|
|||
/*
|
||||
* linux/include/linux/mmc/core.h
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef LINUX_MMC_CORE_H
|
||||
#define LINUX_MMC_CORE_H
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/completion.h>
|
||||
|
||||
struct request;
|
||||
struct mmc_data;
|
||||
struct mmc_request;
|
||||
|
||||
struct mmc_command {
|
||||
u32 opcode;
|
||||
u32 arg;
|
||||
#define MMC_CMD23_ARG_REL_WR (1 << 31)
|
||||
#define MMC_CMD23_ARG_PACKED ((0 << 31) | (1 << 30))
|
||||
#define MMC_CMD23_ARG_TAG_REQ (1 << 29)
|
||||
u32 resp[4];
|
||||
unsigned int flags; /* expected response type */
|
||||
#define MMC_RSP_PRESENT (1 << 0)
|
||||
#define MMC_RSP_136 (1 << 1) /* 136 bit response */
|
||||
#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
|
||||
#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
|
||||
#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
|
||||
|
||||
#define MMC_CMD_MASK (3 << 5) /* non-SPI command type */
|
||||
#define MMC_CMD_AC (0 << 5)
|
||||
#define MMC_CMD_ADTC (1 << 5)
|
||||
#define MMC_CMD_BC (2 << 5)
|
||||
#define MMC_CMD_BCR (3 << 5)
|
||||
|
||||
#define MMC_RSP_SPI_S1 (1 << 7) /* one status byte */
|
||||
#define MMC_RSP_SPI_S2 (1 << 8) /* second byte */
|
||||
#define MMC_RSP_SPI_B4 (1 << 9) /* four data bytes */
|
||||
#define MMC_RSP_SPI_BUSY (1 << 10) /* card may send busy */
|
||||
|
||||
/*
|
||||
* These are the native response types, and correspond to valid bit
|
||||
* patterns of the above flags. One additional valid pattern
|
||||
* is all zeros, which means we don't expect a response.
|
||||
*/
|
||||
#define MMC_RSP_NONE (0)
|
||||
#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
|
||||
#define MMC_RSP_R1B (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY)
|
||||
#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
|
||||
#define MMC_RSP_R3 (MMC_RSP_PRESENT)
|
||||
#define MMC_RSP_R4 (MMC_RSP_PRESENT)
|
||||
#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
|
||||
#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
|
||||
#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
|
||||
|
||||
#define mmc_resp_type(cmd) ((cmd)->flags & (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC|MMC_RSP_BUSY|MMC_RSP_OPCODE))
|
||||
|
||||
/*
|
||||
* These are the SPI response types for MMC, SD, and SDIO cards.
|
||||
* Commands return R1, with maybe more info. Zero is an error type;
|
||||
* callers must always provide the appropriate MMC_RSP_SPI_Rx flags.
|
||||
*/
|
||||
#define MMC_RSP_SPI_R1 (MMC_RSP_SPI_S1)
|
||||
#define MMC_RSP_SPI_R1B (MMC_RSP_SPI_S1|MMC_RSP_SPI_BUSY)
|
||||
#define MMC_RSP_SPI_R2 (MMC_RSP_SPI_S1|MMC_RSP_SPI_S2)
|
||||
#define MMC_RSP_SPI_R3 (MMC_RSP_SPI_S1|MMC_RSP_SPI_B4)
|
||||
#define MMC_RSP_SPI_R4 (MMC_RSP_SPI_S1|MMC_RSP_SPI_B4)
|
||||
#define MMC_RSP_SPI_R5 (MMC_RSP_SPI_S1|MMC_RSP_SPI_S2)
|
||||
#define MMC_RSP_SPI_R7 (MMC_RSP_SPI_S1|MMC_RSP_SPI_B4)
|
||||
|
||||
#define mmc_spi_resp_type(cmd) ((cmd)->flags & \
|
||||
(MMC_RSP_SPI_S1|MMC_RSP_SPI_BUSY|MMC_RSP_SPI_S2|MMC_RSP_SPI_B4))
|
||||
|
||||
/*
|
||||
* These are the command types.
|
||||
*/
|
||||
#define mmc_cmd_type(cmd) ((cmd)->flags & MMC_CMD_MASK)
|
||||
|
||||
unsigned int retries; /* max number of retries */
|
||||
unsigned int error; /* command error */
|
||||
|
||||
/*
|
||||
* Standard errno values are used for errors, but some have specific
|
||||
* meaning in the MMC layer:
|
||||
*
|
||||
* ETIMEDOUT Card took too long to respond
|
||||
* EILSEQ Basic format problem with the received or sent data
|
||||
* (e.g. CRC check failed, incorrect opcode in response
|
||||
* or bad end bit)
|
||||
* EINVAL Request cannot be performed because of restrictions
|
||||
* in hardware and/or the driver
|
||||
* ENOMEDIUM Host can determine that the slot is empty and is
|
||||
* actively failing requests
|
||||
*/
|
||||
|
||||
unsigned int cmd_timeout_ms; /* in milliseconds */
|
||||
unsigned int busy_timeout; /* busy detect timeout in ms */
|
||||
|
||||
/* Set this flag only for blocking sanitize request */
|
||||
bool sanitize_busy;
|
||||
|
||||
struct mmc_data *data; /* data segment associated with cmd */
|
||||
struct mmc_request *mrq; /* associated request */
|
||||
};
|
||||
|
||||
struct mmc_data {
|
||||
unsigned int timeout_ns; /* data timeout (in ns, max 80ms) */
|
||||
unsigned int timeout_clks; /* data timeout (in clocks) */
|
||||
unsigned int blksz; /* data block size */
|
||||
unsigned int blocks; /* number of blocks */
|
||||
unsigned int error; /* data error */
|
||||
unsigned int flags;
|
||||
|
||||
#define MMC_DATA_WRITE (1 << 8)
|
||||
#define MMC_DATA_READ (1 << 9)
|
||||
#define MMC_DATA_STREAM (1 << 10)
|
||||
|
||||
unsigned int bytes_xfered;
|
||||
|
||||
struct mmc_command *stop; /* stop command */
|
||||
struct mmc_request *mrq; /* associated request */
|
||||
|
||||
unsigned int sg_len; /* size of scatter list */
|
||||
struct scatterlist *sg; /* I/O scatter list */
|
||||
s32 host_cookie; /* host private data */
|
||||
};
|
||||
|
||||
struct mmc_host;
|
||||
struct mmc_request {
|
||||
struct mmc_command *sbc; /* SET_BLOCK_COUNT for multiblock */
|
||||
struct mmc_command *cmd;
|
||||
struct mmc_data *data;
|
||||
struct mmc_command *stop;
|
||||
|
||||
struct completion completion;
|
||||
void (*done)(struct mmc_request *);/* completion function */
|
||||
struct mmc_host *host;
|
||||
};
|
||||
|
||||
struct mmc_card;
|
||||
struct mmc_async_req;
|
||||
|
||||
extern int mmc_stop_bkops(struct mmc_card *);
|
||||
extern int mmc_read_bkops_status(struct mmc_card *);
|
||||
extern struct mmc_async_req *mmc_start_req(struct mmc_host *,
|
||||
struct mmc_async_req *, int *);
|
||||
extern int mmc_interrupt_hpi(struct mmc_card *);
|
||||
extern void mmc_wait_for_req(struct mmc_host *, struct mmc_request *);
|
||||
extern int mmc_wait_for_cmd(struct mmc_host *, struct mmc_command *, int);
|
||||
extern int mmc_app_cmd(struct mmc_host *, struct mmc_card *);
|
||||
extern int mmc_wait_for_app_cmd(struct mmc_host *, struct mmc_card *,
|
||||
struct mmc_command *, int);
|
||||
extern void mmc_start_bkops(struct mmc_card *card, bool from_exception);
|
||||
extern int __mmc_switch(struct mmc_card *, u8, u8, u8, unsigned int, bool,
|
||||
bool, bool);
|
||||
extern int mmc_switch(struct mmc_card *, u8, u8, u8, unsigned int);
|
||||
extern int mmc_send_ext_csd(struct mmc_card *card, u8 *ext_csd);
|
||||
|
||||
#define MMC_ERASE_ARG 0x00000000
|
||||
#define MMC_SECURE_ERASE_ARG 0x80000000
|
||||
#define MMC_TRIM_ARG 0x00000001
|
||||
#define MMC_DISCARD_ARG 0x00000003
|
||||
#define MMC_SECURE_TRIM1_ARG 0x80000001
|
||||
#define MMC_SECURE_TRIM2_ARG 0x80008000
|
||||
|
||||
#define MMC_SECURE_ARGS 0x80000000
|
||||
#define MMC_TRIM_ARGS 0x00008001
|
||||
|
||||
extern int mmc_erase(struct mmc_card *card, unsigned int from, unsigned int nr,
|
||||
unsigned int arg);
|
||||
extern int mmc_can_erase(struct mmc_card *card);
|
||||
extern int mmc_can_trim(struct mmc_card *card);
|
||||
extern int mmc_can_discard(struct mmc_card *card);
|
||||
extern int mmc_can_sanitize(struct mmc_card *card);
|
||||
extern int mmc_can_secure_erase_trim(struct mmc_card *card);
|
||||
extern int mmc_erase_group_aligned(struct mmc_card *card, unsigned int from,
|
||||
unsigned int nr);
|
||||
extern unsigned int mmc_calc_max_discard(struct mmc_card *card);
|
||||
|
||||
extern int mmc_set_blocklen(struct mmc_card *card, unsigned int blocklen);
|
||||
extern int mmc_set_blockcount(struct mmc_card *card, unsigned int blockcount,
|
||||
bool is_rel_write);
|
||||
extern int mmc_hw_reset(struct mmc_host *host);
|
||||
extern int mmc_hw_reset_check(struct mmc_host *host);
|
||||
extern int mmc_can_reset(struct mmc_card *card);
|
||||
|
||||
extern void mmc_set_data_timeout(struct mmc_data *, const struct mmc_card *);
|
||||
extern unsigned int mmc_align_data_size(struct mmc_card *, unsigned int);
|
||||
|
||||
extern int __mmc_claim_host(struct mmc_host *host, atomic_t *abort);
|
||||
extern void mmc_release_host(struct mmc_host *host);
|
||||
|
||||
extern void mmc_get_card(struct mmc_card *card);
|
||||
extern void mmc_put_card(struct mmc_card *card);
|
||||
|
||||
extern int mmc_flush_cache(struct mmc_card *);
|
||||
|
||||
extern int mmc_detect_card_removed(struct mmc_host *host);
|
||||
|
||||
/**
|
||||
* mmc_claim_host - exclusively claim a host
|
||||
* @host: mmc host to claim
|
||||
*
|
||||
* Claim a host for a set of operations.
|
||||
*/
|
||||
static inline void mmc_claim_host(struct mmc_host *host)
|
||||
{
|
||||
__mmc_claim_host(host, NULL);
|
||||
}
|
||||
|
||||
struct device_node;
|
||||
extern u32 mmc_vddrange_to_ocrmask(int vdd_min, int vdd_max);
|
||||
extern int mmc_of_parse_voltage(struct device_node *np, u32 *mask);
|
||||
|
||||
#endif /* LINUX_MMC_CORE_H */
|
||||
470
include/linux/mmc/dw_mmc.h
Normal file
470
include/linux/mmc/dw_mmc.h
Normal file
|
|
@ -0,0 +1,470 @@
|
|||
/*
|
||||
* Synopsys DesignWare Multimedia Card Interface driver
|
||||
* (Based on NXP driver for lpc 31xx)
|
||||
*
|
||||
* Copyright (C) 2009 NXP Semiconductors
|
||||
* Copyright (C) 2009, 2010 Imagination Technologies Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef LINUX_MMC_DW_MMC_H
|
||||
#define LINUX_MMC_DW_MMC_H
|
||||
|
||||
#include <linux/scatterlist.h>
|
||||
#include <linux/mmc/core.h>
|
||||
#include <linux/pm_qos.h>
|
||||
|
||||
#define MAX_MCI_SLOTS 2
|
||||
|
||||
enum dw_mci_state {
|
||||
STATE_IDLE = 0,
|
||||
STATE_SENDING_CMD,
|
||||
STATE_SENDING_DATA,
|
||||
STATE_DATA_BUSY,
|
||||
STATE_SENDING_STOP,
|
||||
STATE_DATA_ERROR,
|
||||
STATE_SENDING_CMD11,
|
||||
STATE_WAITING_CMD11_DONE,
|
||||
};
|
||||
|
||||
enum {
|
||||
EVENT_CMD_COMPLETE = 0,
|
||||
EVENT_XFER_COMPLETE,
|
||||
EVENT_DATA_COMPLETE,
|
||||
EVENT_DATA_ERROR,
|
||||
EVENT_XFER_ERROR
|
||||
};
|
||||
|
||||
struct mmc_data;
|
||||
|
||||
/**
|
||||
* struct dw_mci - MMC controller state shared between all slots
|
||||
* @lock: Spinlock protecting the queue and associated data.
|
||||
* @regs: Pointer to MMIO registers.
|
||||
* @sg: Scatterlist entry currently being processed by PIO code, if any.
|
||||
* @sg_miter: PIO mapping scatterlist iterator.
|
||||
* @cur_slot: The slot which is currently using the controller.
|
||||
* @mrq: The request currently being processed on @cur_slot,
|
||||
* or NULL if the controller is idle.
|
||||
* @cmd: The command currently being sent to the card, or NULL.
|
||||
* @data: The data currently being transferred, or NULL if no data
|
||||
* transfer is in progress.
|
||||
* @use_dma: Whether DMA channel is initialized or not.
|
||||
* @using_dma: Whether DMA is in use for the current transfer.
|
||||
* @dma_64bit_address: Whether DMA supports 64-bit address mode or not.
|
||||
* @sg_dma: Bus address of DMA buffer.
|
||||
* @sg_cpu: Virtual address of DMA buffer.
|
||||
* @dma_ops: Pointer to platform-specific DMA callbacks.
|
||||
* @cmd_status: Snapshot of SR taken upon completion of the current
|
||||
* command. Only valid when EVENT_CMD_COMPLETE is pending.
|
||||
* @data_status: Snapshot of SR taken upon completion of the current
|
||||
* data transfer. Only valid when EVENT_DATA_COMPLETE or
|
||||
* EVENT_DATA_ERROR is pending.
|
||||
* @stop_cmdr: Value to be loaded into CMDR when the stop command is
|
||||
* to be sent.
|
||||
* @dir_status: Direction of current transfer.
|
||||
* @tasklet: Tasklet running the request state machine.
|
||||
* @card_tasklet: Tasklet handling card detect.
|
||||
* @pending_events: Bitmask of events flagged by the interrupt handler
|
||||
* to be processed by the tasklet.
|
||||
* @completed_events: Bitmask of events which the state machine has
|
||||
* processed.
|
||||
* @state: Tasklet state.
|
||||
* @queue: List of slots waiting for access to the controller.
|
||||
* @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
|
||||
* rate and timeout calculations.
|
||||
* @current_speed: Configured rate of the controller.
|
||||
* @num_slots: Number of slots available.
|
||||
* @verid: Denote Version ID.
|
||||
* @data_offset: Set the offset of DATA register according to VERID.
|
||||
* @dev: Device associated with the MMC controller.
|
||||
* @pdata: Platform data associated with the MMC controller.
|
||||
* @drv_data: Driver specific data for identified variant of the controller
|
||||
* @priv: Implementation defined private data.
|
||||
* @biu_clk: Pointer to bus interface unit clock instance.
|
||||
* @ciu_clk: Pointer to card interface unit clock instance.
|
||||
* @slot: Slots sharing this MMC controller.
|
||||
* @fifo_depth: depth of FIFO.
|
||||
* @data_shift: log2 of FIFO item size.
|
||||
* @part_buf_start: Start index in part_buf.
|
||||
* @part_buf_count: Bytes of partial data in part_buf.
|
||||
* @part_buf: Simple buffer for partial fifo reads/writes.
|
||||
* @push_data: Pointer to FIFO push function.
|
||||
* @pull_data: Pointer to FIFO pull function.
|
||||
* @quirks: Set of quirks that apply to specific versions of the IP.
|
||||
* @irq_flags: The flags to be passed to request_irq.
|
||||
* @irq: The irq value to be passed to request_irq.
|
||||
*
|
||||
* Locking
|
||||
* =======
|
||||
*
|
||||
* @lock is a softirq-safe spinlock protecting @queue as well as
|
||||
* @cur_slot, @mrq and @state. These must always be updated
|
||||
* at the same time while holding @lock.
|
||||
*
|
||||
* The @mrq field of struct dw_mci_slot is also protected by @lock,
|
||||
* and must always be written at the same time as the slot is added to
|
||||
* @queue.
|
||||
*
|
||||
* @pending_events and @completed_events are accessed using atomic bit
|
||||
* operations, so they don't need any locking.
|
||||
*
|
||||
* None of the fields touched by the interrupt handler need any
|
||||
* locking. However, ordering is important: Before EVENT_DATA_ERROR or
|
||||
* EVENT_DATA_COMPLETE is set in @pending_events, all data-related
|
||||
* interrupts must be disabled and @data_status updated with a
|
||||
* snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
|
||||
* CMDRDY interrupt must be disabled and @cmd_status updated with a
|
||||
* snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
|
||||
* bytes_xfered field of @data must be written. This is ensured by
|
||||
* using barriers.
|
||||
*/
|
||||
struct dw_mci {
|
||||
spinlock_t lock;
|
||||
void __iomem *regs;
|
||||
unsigned int channel;
|
||||
|
||||
struct scatterlist *sg;
|
||||
struct sg_mapping_iter sg_miter;
|
||||
|
||||
struct dw_mci_slot *cur_slot;
|
||||
struct mmc_request *mrq;
|
||||
struct mmc_command *cmd;
|
||||
struct mmc_data *data;
|
||||
struct mmc_command stop_abort;
|
||||
unsigned int prev_blksz;
|
||||
unsigned char timing;
|
||||
struct workqueue_struct *card_workqueue;
|
||||
|
||||
/* DMA interface members*/
|
||||
int use_dma;
|
||||
int using_dma;
|
||||
int dma_64bit_address;
|
||||
|
||||
dma_addr_t sg_dma;
|
||||
void *sg_cpu;
|
||||
const struct dw_mci_dma_ops *dma_ops;
|
||||
#ifdef CONFIG_MMC_DW_IDMAC
|
||||
unsigned int ring_size;
|
||||
#else
|
||||
struct dw_mci_dma_data *dma_data;
|
||||
#endif
|
||||
unsigned int desc_sz;
|
||||
struct pm_qos_request pm_qos_int;
|
||||
u32 cmd_status;
|
||||
u32 data_status;
|
||||
u32 stop_cmdr;
|
||||
u32 dir_status;
|
||||
struct tasklet_struct tasklet;
|
||||
u32 tasklet_state;
|
||||
struct work_struct card_work;
|
||||
unsigned long pending_events;
|
||||
unsigned long completed_events;
|
||||
enum dw_mci_state state;
|
||||
struct list_head queue;
|
||||
|
||||
u32 bus_hz;
|
||||
u32 current_speed;
|
||||
u32 num_slots;
|
||||
u32 fifoth_val;
|
||||
u32 cd_rd_thr;
|
||||
u16 verid;
|
||||
u16 data_offset;
|
||||
struct device *dev;
|
||||
struct dw_mci_board *pdata;
|
||||
const struct dw_mci_drv_data *drv_data;
|
||||
void *priv;
|
||||
struct clk *biu_clk;
|
||||
struct clk *ciu_clk;
|
||||
struct clk *ciu_gate;
|
||||
atomic_t biu_clk_cnt;
|
||||
atomic_t ciu_clk_cnt;
|
||||
atomic_t biu_en_win;
|
||||
atomic_t ciu_en_win;
|
||||
struct dw_mci_slot *slot[MAX_MCI_SLOTS];
|
||||
|
||||
/* FIFO push and pull */
|
||||
int fifo_depth;
|
||||
int data_shift;
|
||||
u8 part_buf_start;
|
||||
u8 part_buf_count;
|
||||
union {
|
||||
u16 part_buf16;
|
||||
u32 part_buf32;
|
||||
u64 part_buf;
|
||||
};
|
||||
void (*push_data)(struct dw_mci *host, void *buf, int cnt);
|
||||
void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
|
||||
|
||||
/* Workaround flags */
|
||||
u32 quirks;
|
||||
|
||||
/* S/W reset timer */
|
||||
struct timer_list timer;
|
||||
|
||||
bool vqmmc_enabled;
|
||||
unsigned long irq_flags; /* IRQ flags */
|
||||
int irq;
|
||||
|
||||
/* Save request status */
|
||||
#define DW_MMC_REQ_IDLE 0
|
||||
#define DW_MMC_REQ_BUSY 1
|
||||
unsigned int req_state;
|
||||
struct dw_mci_debug_info *debug_info; /* debug info */
|
||||
|
||||
/* HWACG q-active ctrl check */
|
||||
unsigned int qactive_check;
|
||||
|
||||
/* Support system power mode */
|
||||
int idle_ip_index;
|
||||
|
||||
/* For argos */
|
||||
unsigned int transferred_cnt;
|
||||
|
||||
/* Sfr dump */
|
||||
struct dw_mci_sfe_ram_dump *sfr_dump;
|
||||
|
||||
#ifdef CONFIG_MMC_DW_EXYNOS_EMMC_POWERCTRL
|
||||
struct regulator *vemmc;
|
||||
struct regulator *vqemmc;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* DMA ops for Internal/External DMAC interface */
|
||||
struct dw_mci_dma_ops {
|
||||
/* DMA Ops */
|
||||
int (*init)(struct dw_mci *host);
|
||||
void (*start)(struct dw_mci *host, unsigned int sg_len);
|
||||
void (*complete)(struct dw_mci *host);
|
||||
void (*stop)(struct dw_mci *host);
|
||||
void (*reset)(struct dw_mci *host);
|
||||
void (*cleanup)(struct dw_mci *host);
|
||||
void (*exit)(struct dw_mci *host);
|
||||
};
|
||||
|
||||
/* IP Quirks/flags. */
|
||||
/* DTO fix for command transmission with IDMAC configured */
|
||||
#define DW_MCI_QUIRK_IDMAC_DTO BIT(0)
|
||||
/* delay needed between retries on some 2.11a implementations */
|
||||
#define DW_MCI_QUIRK_RETRY_DELAY BIT(1)
|
||||
/* High Speed Capable - Supports HS cards (up to 50MHz) */
|
||||
#define DW_MCI_QUIRK_HIGHSPEED BIT(2)
|
||||
/* Unreliable card detection */
|
||||
#define DW_MCI_QUIRK_BROKEN_CARD_DETECTION BIT(3)
|
||||
/* No write protect */
|
||||
#define DW_MCI_QUIRK_NO_WRITE_PROTECT BIT(4)
|
||||
/* No detect end bit during read */
|
||||
#define DW_MCI_QUIRK_NO_DETECT_EBIT BIT(5)
|
||||
/* Bypass the security management unit */
|
||||
#define DW_MCI_QUIRK_BYPASS_SMU BIT(6)
|
||||
/* Use fixed IO voltage */
|
||||
#define DW_MMC_QUIRK_FIXED_VOLTAGE BIT(7)
|
||||
/* Card init W/A HWACG ctrl */
|
||||
#define DW_MCI_QUIRK_HWACG_CTRL BIT(8)
|
||||
/* Enables ultra low power mode */
|
||||
#define DW_MCI_QUIRK_ENABLE_ULP BIT(9)
|
||||
/* Use the security management unit */
|
||||
#define DW_MCI_QUIRK_USE_SMU BIT(10)
|
||||
/* Switching transfer */
|
||||
#define DW_MCI_SW_TRANS BIT(11)
|
||||
|
||||
/* Slot level quirks */
|
||||
/* This slot has no write protect */
|
||||
#define DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT BIT(0)
|
||||
enum dw_mci_cd_types {
|
||||
DW_MCI_CD_INTERNAL = 1, /* use mmc internal CD line */
|
||||
DW_MCI_CD_EXTERNAL, /* use external callback */
|
||||
DW_MCI_CD_GPIO, /* use external gpio pin for CD line */
|
||||
DW_MCI_CD_NONE, /* no CD line, use polling to detect card */
|
||||
DW_MCI_CD_PERMANENT, /* no CD line, card permanently wired to host */
|
||||
};
|
||||
struct dma_pdata;
|
||||
|
||||
struct block_settings {
|
||||
unsigned short max_segs; /* see blk_queue_max_segments */
|
||||
unsigned int max_blk_size; /* maximum size of one mmc block */
|
||||
unsigned int max_blk_count; /* maximum number of blocks in one req*/
|
||||
unsigned int max_req_size; /* maximum number of bytes in one req*/
|
||||
unsigned int max_seg_size; /* see blk_queue_max_segment_size */
|
||||
};
|
||||
|
||||
/* Board platform data */
|
||||
struct dw_mci_board {
|
||||
u32 num_slots;
|
||||
|
||||
u32 quirks; /* Workaround / Quirk flags */
|
||||
unsigned int bus_hz; /* Clock speed at the cclk_in pad */
|
||||
|
||||
u32 caps; /* Capabilities */
|
||||
u32 caps2; /* More capabilities */
|
||||
u32 pm_caps; /* PM capabilities */
|
||||
/*
|
||||
* Override fifo depth. If 0, autodetect it from the FIFOTH register,
|
||||
* but note that this may not be reliable after a bootloader has used
|
||||
* it.
|
||||
*/
|
||||
unsigned int fifo_depth;
|
||||
|
||||
/* delay in mS before detecting cards after interrupt */
|
||||
u32 detect_delay_ms;
|
||||
|
||||
u8 clk_smpl;
|
||||
bool is_fine_tuned;
|
||||
bool tuned;
|
||||
bool extra_tuning;
|
||||
bool only_once_tune;
|
||||
|
||||
/* INT QOS khz */
|
||||
unsigned int qos_int_level;
|
||||
unsigned char io_mode;
|
||||
|
||||
enum dw_mci_cd_types cd_type;
|
||||
struct dw_mci_dma_ops *dma_ops;
|
||||
struct dma_pdata *data;
|
||||
struct block_settings *blk_settings;
|
||||
unsigned int sw_timeout;
|
||||
|
||||
/* DATA_TIMEOUT[31:11] of TMOUT */
|
||||
u32 data_timeout;
|
||||
u32 hto_timeout;
|
||||
bool use_gate_clock;
|
||||
bool use_biu_gate_clock;
|
||||
bool enable_cclk_on_suspend;
|
||||
bool on_suspend;
|
||||
|
||||
/* Number of descriptors */
|
||||
unsigned int desc_sz;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_MMC_DW_IDMAC
|
||||
#define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
|
||||
SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
|
||||
SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
|
||||
SDMMC_IDMAC_INT_TI)
|
||||
|
||||
#if defined(CONFIG_MMC_DW_FMP_DM_CRYPT) || defined(CONFIG_MMC_DW_FMP_ECRYPT_FS)
|
||||
struct idmac_desc_64addr {
|
||||
u32 des0; /* Control Descriptor */
|
||||
#define IDMAC_DES0_DIC BIT(1)
|
||||
#define IDMAC_DES0_LD BIT(2)
|
||||
#define IDMAC_DES0_FD BIT(3)
|
||||
#define IDMAC_DES0_CH BIT(4)
|
||||
#define IDMAC_DES0_ER BIT(5)
|
||||
#define IDMAC_DES0_CES BIT(30)
|
||||
#define IDMAC_DES0_OWN BIT(31)
|
||||
u32 des1; /* Reserved */
|
||||
#define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
|
||||
((d)->des2 = ((d)->des2 & 0x03ffe000) | ((s) & 0x1fff))
|
||||
u32 des2; /*Buffer sizes */
|
||||
#define IDMAC_DES2_FKL BIT(26)
|
||||
#define IDMAC_DES2_DKL BIT(27)
|
||||
#define IDMAC_SET_FAS(d, v) \
|
||||
((d)->des2 = ((d)->des2 & 0xcfffffff) | v << 28)
|
||||
#define IDMAC_SET_DAS(d, v) \
|
||||
((d)->des2 = ((d)->des2 & 0x3fffffff) | v << 30)
|
||||
u32 des3; /* Reserved */
|
||||
u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
|
||||
u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
|
||||
u32 des6; /* Lower 32-bits of Next Descriptor Address */
|
||||
u32 des7; /* Upper 32-bits of Next Descriptor Address */
|
||||
u32 des8; /* File IV 0 */
|
||||
u32 des9; /* File IV 1 */
|
||||
u32 des10; /* File IV 2 */
|
||||
u32 des11; /* File IV 3 */
|
||||
u32 des12; /* File EncKey 0 */
|
||||
u32 des13; /* File EncKey 1 */
|
||||
u32 des14; /* File EncKey 2 */
|
||||
u32 des15; /* File EncKey 3 */
|
||||
u32 des16; /* File EncKey 4 */
|
||||
u32 des17; /* File EncKey 5 */
|
||||
u32 des18; /* File EncKey 6 */
|
||||
u32 des19; /* File EncKey 7 */
|
||||
u32 des20; /* File TwKey 0 */
|
||||
u32 des21; /* File TwKey 1 */
|
||||
u32 des22; /* File TwKey 2 */
|
||||
u32 des23; /* File TwKey 3 */
|
||||
u32 des24; /* File TwKey 4 */
|
||||
u32 des25; /* File TwKey 5 */
|
||||
u32 des26; /* File TwKey 6 */
|
||||
u32 des27; /* File TwKey 7 */
|
||||
u32 des28; /* Disk IV 0 */
|
||||
u32 des29; /* Disk IV 1 */
|
||||
u32 des30; /* Disk IV 2 */
|
||||
u32 des31; /* Disk IV 3 */
|
||||
#define IDMAC_64ADDR_SET_DESC_CLEAR(d) \
|
||||
do { \
|
||||
(d)->des1 = 0; \
|
||||
(d)->des2 = 0; \
|
||||
(d)->des3 = 0; \
|
||||
} while(0)
|
||||
#define IDMAC_64ADDR_SET_DESC_ADDR(d, a) \
|
||||
do { \
|
||||
(d)->des6 = ((u32)(a) & 0xffffffff); \
|
||||
(d)->des7 = ((u32)((a) >> 32)); \
|
||||
} while(0)
|
||||
};
|
||||
#else
|
||||
struct idmac_desc_64addr {
|
||||
u32 des0; /* Control Descriptor */
|
||||
|
||||
u32 des1; /* Reserved */
|
||||
|
||||
u32 des2; /*Buffer sizes */
|
||||
#define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
|
||||
((d)->des2 = ((d)->des2 & 0x03ffe000) | ((s) & 0x1fff))
|
||||
|
||||
u32 des3; /* Reserved */
|
||||
|
||||
u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
|
||||
u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
|
||||
|
||||
u32 des6; /* Lower 32-bits of Next Descriptor Address */
|
||||
u32 des7; /* Upper 32-bits of Next Descriptor Address */
|
||||
#define IDMAC_64ADDR_SET_DESC_CLEAR(d) \
|
||||
do { \
|
||||
(d)->des1 = 0; \
|
||||
(d)->des2 = 0; \
|
||||
(d)->des3 = 0; \
|
||||
} while(0)
|
||||
#define IDMAC_64ADDR_SET_DESC_ADDR(d, a) \
|
||||
do { \
|
||||
(d)->des6 = ((u32)(a) & 0xffffffff); \
|
||||
(d)->des7 = ((u32)((a) >> 32)); \
|
||||
} while(0)
|
||||
};
|
||||
#endif
|
||||
|
||||
struct idmac_desc {
|
||||
u32 des0; /* Control Descriptor */
|
||||
#define IDMAC_DES0_DIC BIT(1)
|
||||
#define IDMAC_DES0_LD BIT(2)
|
||||
#define IDMAC_DES0_FD BIT(3)
|
||||
#define IDMAC_DES0_CH BIT(4)
|
||||
#define IDMAC_DES0_ER BIT(5)
|
||||
#define IDMAC_DES0_CES BIT(30)
|
||||
#define IDMAC_DES0_OWN BIT(31)
|
||||
|
||||
u32 des1; /* Buffer sizes */
|
||||
#define IDMAC_SET_BUFFER1_SIZE(d, s) \
|
||||
((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
|
||||
|
||||
u32 des2; /* buffer 1 physical address */
|
||||
|
||||
u32 des3; /* buffer 2 physical address */
|
||||
#define IDMAC_SET_DESC_ADDR(d, a) \
|
||||
do { \
|
||||
(d)->des3 = (u32)(a); \
|
||||
} while(0)
|
||||
};
|
||||
#endif /* CONFIG_MMC_DW_IDMAC */
|
||||
|
||||
/* FMP bypass/encrypt mode */
|
||||
#define CLEAR 0
|
||||
#define AES_CBC 1
|
||||
#define AES_XTS 2
|
||||
|
||||
#endif /* LINUX_MMC_DW_MMC_H */
|
||||
576
include/linux/mmc/host.h
Normal file
576
include/linux/mmc/host.h
Normal file
|
|
@ -0,0 +1,576 @@
|
|||
/*
|
||||
* linux/include/linux/mmc/host.h
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Host driver specific definitions.
|
||||
*/
|
||||
#ifndef LINUX_MMC_HOST_H
|
||||
#define LINUX_MMC_HOST_H
|
||||
|
||||
#include <linux/leds.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/fault-inject.h>
|
||||
#include <linux/wakelock.h>
|
||||
|
||||
#include <linux/mmc/core.h>
|
||||
#include <linux/mmc/card.h>
|
||||
#include <linux/mmc/pm.h>
|
||||
|
||||
#define MMC_DRIVER_TYPE_0 0 /* Default, x1 */
|
||||
#define MMC_DRIVER_TYPE_1 1 /* x1.5 */
|
||||
#define MMC_DRIVER_TYPE_2 2 /* x0.75 */
|
||||
#define MMC_DRIVER_TYPE_3 3 /* x0.5 */
|
||||
#define MMC_DRIVER_TYPE_4 4 /* x1.2 */
|
||||
#define MMC_DRIVER_TYPE_5 5 /* x2 */
|
||||
|
||||
struct mmc_ios {
|
||||
unsigned int clock; /* clock rate */
|
||||
unsigned short vdd;
|
||||
|
||||
/* vdd stores the bit number of the selected voltage range from below. */
|
||||
|
||||
unsigned char bus_mode; /* command output mode */
|
||||
|
||||
#define MMC_BUSMODE_OPENDRAIN 1
|
||||
#define MMC_BUSMODE_PUSHPULL 2
|
||||
|
||||
unsigned char chip_select; /* SPI chip select */
|
||||
|
||||
#define MMC_CS_DONTCARE 0
|
||||
#define MMC_CS_HIGH 1
|
||||
#define MMC_CS_LOW 2
|
||||
|
||||
unsigned char power_mode; /* power supply mode */
|
||||
|
||||
#define MMC_POWER_OFF 0
|
||||
#define MMC_POWER_UP 1
|
||||
#define MMC_POWER_ON 2
|
||||
#define MMC_POWER_UNDEFINED 3
|
||||
|
||||
unsigned char bus_width; /* data bus width */
|
||||
|
||||
#define MMC_BUS_WIDTH_1 0
|
||||
#define MMC_BUS_WIDTH_4 2
|
||||
#define MMC_BUS_WIDTH_8 3
|
||||
|
||||
unsigned char timing; /* timing specification used */
|
||||
|
||||
#define MMC_TIMING_LEGACY 0
|
||||
#define MMC_TIMING_MMC_HS 1
|
||||
#define MMC_TIMING_SD_HS 2
|
||||
#define MMC_TIMING_UHS_SDR12 3
|
||||
#define MMC_TIMING_UHS_SDR25 4
|
||||
#define MMC_TIMING_UHS_SDR50 5
|
||||
#define MMC_TIMING_UHS_SDR104 6
|
||||
#define MMC_TIMING_UHS_DDR50 7
|
||||
#define MMC_TIMING_MMC_DDR52 8
|
||||
#define MMC_TIMING_MMC_HS200 9
|
||||
#define MMC_TIMING_MMC_HS400 10
|
||||
#define MMC_TIMING_MMC_HS400_ES 11
|
||||
|
||||
unsigned char signal_voltage; /* signalling voltage (1.8V or 3.3V) */
|
||||
|
||||
#define MMC_SIGNAL_VOLTAGE_330 0
|
||||
#define MMC_SIGNAL_VOLTAGE_180 1
|
||||
#define MMC_SIGNAL_VOLTAGE_120 2
|
||||
|
||||
unsigned char drv_type; /* driver type (A, B, C, D) */
|
||||
|
||||
#define MMC_SET_DRIVER_TYPE_B 0
|
||||
#define MMC_SET_DRIVER_TYPE_A 1
|
||||
#define MMC_SET_DRIVER_TYPE_C 2
|
||||
#define MMC_SET_DRIVER_TYPE_D 3
|
||||
};
|
||||
|
||||
struct mmc_host_ops {
|
||||
/*
|
||||
* 'enable' is called when the host is claimed and 'disable' is called
|
||||
* when the host is released. 'enable' and 'disable' are deprecated.
|
||||
*/
|
||||
int (*enable)(struct mmc_host *host);
|
||||
int (*disable)(struct mmc_host *host);
|
||||
/*
|
||||
* It is optional for the host to implement pre_req and post_req in
|
||||
* order to support double buffering of requests (prepare one
|
||||
* request while another request is active).
|
||||
* pre_req() must always be followed by a post_req().
|
||||
* To undo a call made to pre_req(), call post_req() with
|
||||
* a nonzero err condition.
|
||||
*/
|
||||
void (*post_req)(struct mmc_host *host, struct mmc_request *req,
|
||||
int err);
|
||||
void (*pre_req)(struct mmc_host *host, struct mmc_request *req,
|
||||
bool is_first_req);
|
||||
void (*request)(struct mmc_host *host, struct mmc_request *req);
|
||||
/*
|
||||
* Avoid calling these three functions too often or in a "fast path",
|
||||
* since underlaying controller might implement them in an expensive
|
||||
* and/or slow way.
|
||||
*
|
||||
* Also note that these functions might sleep, so don't call them
|
||||
* in the atomic contexts!
|
||||
*
|
||||
* Return values for the get_ro callback should be:
|
||||
* 0 for a read/write card
|
||||
* 1 for a read-only card
|
||||
* -ENOSYS when not supported (equal to NULL callback)
|
||||
* or a negative errno value when something bad happened
|
||||
*
|
||||
* Return values for the get_cd callback should be:
|
||||
* 0 for a absent card
|
||||
* 1 for a present card
|
||||
* -ENOSYS when not supported (equal to NULL callback)
|
||||
* or a negative errno value when something bad happened
|
||||
*/
|
||||
void (*set_ios)(struct mmc_host *host, struct mmc_ios *ios);
|
||||
int (*get_ro)(struct mmc_host *host);
|
||||
int (*get_cd)(struct mmc_host *host);
|
||||
|
||||
void (*enable_sdio_irq)(struct mmc_host *host, int enable);
|
||||
|
||||
/* optional callback for HC quirks */
|
||||
void (*init_card)(struct mmc_host *host, struct mmc_card *card);
|
||||
|
||||
int (*start_signal_voltage_switch)(struct mmc_host *host, struct mmc_ios *ios);
|
||||
|
||||
/* Check if the card is pulling dat[0:3] low */
|
||||
int (*card_busy)(struct mmc_host *host);
|
||||
|
||||
/* The tuning command opcode value is different for SD and eMMC cards */
|
||||
int (*execute_tuning)(struct mmc_host *host, u32 opcode);
|
||||
|
||||
/* Prepare HS400 target operating frequency depending host driver */
|
||||
int (*prepare_hs400_tuning)(struct mmc_host *host, struct mmc_ios *ios);
|
||||
int (*select_drive_strength)(unsigned int max_dtr, int host_drv, int card_drv);
|
||||
void (*hw_reset)(struct mmc_host *host);
|
||||
void (*card_event)(struct mmc_host *host);
|
||||
|
||||
/*
|
||||
* Optional callback to support controllers with HW issues for multiple
|
||||
* I/O. Returns the number of supported blocks for the request.
|
||||
*/
|
||||
int (*multi_io_quirk)(struct mmc_card *card,
|
||||
unsigned int direction, int blk_size);
|
||||
void (*emmc_pwr)(struct mmc_host *mmc, unsigned int power_mode);
|
||||
};
|
||||
|
||||
struct mmc_card;
|
||||
struct device;
|
||||
|
||||
struct mmc_async_req {
|
||||
/* active mmc request */
|
||||
struct mmc_request *mrq;
|
||||
/*
|
||||
* Check error status of completed mmc request.
|
||||
* Returns 0 if success otherwise non zero.
|
||||
*/
|
||||
int (*err_check) (struct mmc_card *, struct mmc_async_req *);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct mmc_slot - MMC slot functions
|
||||
*
|
||||
* @cd_irq: MMC/SD-card slot hotplug detection IRQ or -EINVAL
|
||||
* @lock: protect the @handler_priv pointer
|
||||
* @handler_priv: MMC/SD-card slot context
|
||||
*
|
||||
* Some MMC/SD host controllers implement slot-functions like card and
|
||||
* write-protect detection natively. However, a large number of controllers
|
||||
* leave these functions to the CPU. This struct provides a hook to attach
|
||||
* such slot-function drivers.
|
||||
*/
|
||||
struct mmc_slot {
|
||||
int cd_irq;
|
||||
struct mutex lock;
|
||||
void *handler_priv;
|
||||
};
|
||||
|
||||
/**
|
||||
* mmc_context_info - synchronization details for mmc context
|
||||
* @is_done_rcv wake up reason was done request
|
||||
* @is_new_req wake up reason was new request
|
||||
* @is_waiting_last_req mmc context waiting for single running request
|
||||
* @wait wait queue
|
||||
* @lock lock to protect data fields
|
||||
*/
|
||||
struct mmc_context_info {
|
||||
bool is_done_rcv;
|
||||
bool is_new_req;
|
||||
bool is_waiting_last_req;
|
||||
wait_queue_head_t wait;
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
struct regulator;
|
||||
|
||||
struct mmc_supply {
|
||||
struct regulator *vmmc; /* Card power supply */
|
||||
struct regulator *vqmmc; /* Optional Vccq supply */
|
||||
};
|
||||
|
||||
struct mmc_host {
|
||||
struct device *parent;
|
||||
struct device class_dev;
|
||||
int index;
|
||||
const struct mmc_host_ops *ops;
|
||||
unsigned int f_min;
|
||||
unsigned int f_max;
|
||||
unsigned int f_init;
|
||||
u32 device_drv; /* device strength */
|
||||
u32 ocr_avail;
|
||||
u32 ocr_avail_sdio; /* SDIO-specific OCR */
|
||||
u32 ocr_avail_sd; /* SD-specific OCR */
|
||||
u32 ocr_avail_mmc; /* MMC-specific OCR */
|
||||
struct notifier_block pm_notify;
|
||||
u32 max_current_330;
|
||||
u32 max_current_300;
|
||||
u32 max_current_180;
|
||||
|
||||
#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
|
||||
#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
|
||||
#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
|
||||
#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
|
||||
#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
|
||||
#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
|
||||
#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
|
||||
#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
|
||||
#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
|
||||
#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
|
||||
#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
|
||||
#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
|
||||
#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
|
||||
#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
|
||||
#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
|
||||
#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
|
||||
#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
|
||||
|
||||
u32 caps; /* Host capabilities */
|
||||
|
||||
#define MMC_CAP_4_BIT_DATA (1 << 0) /* Can the host do 4 bit transfers */
|
||||
#define MMC_CAP_MMC_HIGHSPEED (1 << 1) /* Can do MMC high-speed timing */
|
||||
#define MMC_CAP_SD_HIGHSPEED (1 << 2) /* Can do SD high-speed timing */
|
||||
#define MMC_CAP_SDIO_IRQ (1 << 3) /* Can signal pending SDIO IRQs */
|
||||
#define MMC_CAP_SPI (1 << 4) /* Talks only SPI protocols */
|
||||
#define MMC_CAP_NEEDS_POLL (1 << 5) /* Needs polling for card-detection */
|
||||
#define MMC_CAP_8_BIT_DATA (1 << 6) /* Can the host do 8 bit transfers */
|
||||
#define MMC_CAP_AGGRESSIVE_PM (1 << 7) /* Suspend (e)MMC/SD at idle */
|
||||
#define MMC_CAP_NONREMOVABLE (1 << 8) /* Nonremovable e.g. eMMC */
|
||||
#define MMC_CAP_WAIT_WHILE_BUSY (1 << 9) /* Waits while card is busy */
|
||||
#define MMC_CAP_ERASE (1 << 10) /* Allow erase/trim commands */
|
||||
#define MMC_CAP_1_8V_DDR (1 << 11) /* can support */
|
||||
/* DDR mode at 1.8V */
|
||||
#define MMC_CAP_1_2V_DDR (1 << 12) /* can support */
|
||||
/* DDR mode at 1.2V */
|
||||
#define MMC_CAP_POWER_OFF_CARD (1 << 13) /* Can power off after boot */
|
||||
#define MMC_CAP_BUS_WIDTH_TEST (1 << 14) /* CMD14/CMD19 bus width ok */
|
||||
#define MMC_CAP_UHS_SDR12 (1 << 15) /* Host supports UHS SDR12 mode */
|
||||
#define MMC_CAP_UHS_SDR25 (1 << 16) /* Host supports UHS SDR25 mode */
|
||||
#define MMC_CAP_UHS_SDR50 (1 << 17) /* Host supports UHS SDR50 mode */
|
||||
#define MMC_CAP_UHS_SDR104 (1 << 18) /* Host supports UHS SDR104 mode */
|
||||
#define MMC_CAP_UHS_DDR50 (1 << 19) /* Host supports UHS DDR50 mode */
|
||||
#define MMC_CAP_RUNTIME_RESUME (1 << 20) /* Resume at runtime_resume. */
|
||||
#define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */
|
||||
#define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */
|
||||
#define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */
|
||||
#define MMC_CAP_CMD23 (1 << 30) /* CMD23 supported. */
|
||||
#define MMC_CAP_HW_RESET (1 << 31) /* Hardware reset */
|
||||
|
||||
u32 caps2; /* More host capabilities */
|
||||
|
||||
#define MMC_CAP2_BOOTPART_NOACC (1 << 0) /* Boot partition no access */
|
||||
#define MMC_CAP2_FULL_PWR_CYCLE (1 << 2) /* Can do full power cycle */
|
||||
#define MMC_CAP2_HS200_1_8V_SDR (1 << 5) /* can support */
|
||||
#define MMC_CAP2_HS200_1_2V_SDR (1 << 6) /* can support */
|
||||
#define MMC_CAP2_HS200 (MMC_CAP2_HS200_1_8V_SDR | \
|
||||
MMC_CAP2_HS200_1_2V_SDR)
|
||||
#define MMC_CAP2_HC_ERASE_SZ (1 << 9) /* High-capacity erase size */
|
||||
#define MMC_CAP2_CD_ACTIVE_HIGH (1 << 10) /* Card-detect signal active high */
|
||||
#define MMC_CAP2_RO_ACTIVE_HIGH (1 << 11) /* Write-protect signal active high */
|
||||
#define MMC_CAP2_PACKED_RD (1 << 12) /* Allow packed read */
|
||||
#define MMC_CAP2_PACKED_WR (1 << 13) /* Allow packed write */
|
||||
#define MMC_CAP2_PACKED_CMD (MMC_CAP2_PACKED_RD | \
|
||||
MMC_CAP2_PACKED_WR)
|
||||
#define MMC_CAP2_NO_PRESCAN_POWERUP (1 << 14) /* Don't power up before scan */
|
||||
#define MMC_CAP2_HS400_1_8V (1 << 15) /* Can support HS400 1.8V */
|
||||
#define MMC_CAP2_HS400_1_2V (1 << 16) /* Can support HS400 1.2V */
|
||||
#define MMC_CAP2_HS400 (MMC_CAP2_HS400_1_8V | \
|
||||
MMC_CAP2_HS400_1_2V)
|
||||
#define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17)
|
||||
#define MMC_CAP2_STROBE_ENHANCED (1 << 18) /* enhanced strobe */
|
||||
#define MMC_CAP2_SKIP_INIT_SCAN (1 << 19) /* skip init mmc scan */
|
||||
#define MMC_CAP2_PWR_SHUT_DOWN (1 << 20) /* emmc cntrl pwr in shutdown */
|
||||
#define MMC_CAP2_PWR_SUSPEND (1 << 21) /* emmc cntrl pwr in susepend */
|
||||
#define MMC_CAP2_DETECT_ON_ERR (1 << 22) /* On I/O err check card removal */
|
||||
mmc_pm_flag_t pm_caps; /* supported pm features */
|
||||
|
||||
#ifdef CONFIG_MMC_CLKGATE
|
||||
int clk_requests; /* internal reference counter */
|
||||
unsigned int clk_delay; /* number of MCI clk hold cycles */
|
||||
bool clk_gated; /* clock gated */
|
||||
struct delayed_work clk_gate_work; /* delayed clock gate */
|
||||
unsigned int clk_old; /* old clock value cache */
|
||||
spinlock_t clk_lock; /* lock for clk fields */
|
||||
struct mutex clk_gate_mutex; /* mutex for clock gating */
|
||||
struct device_attribute clkgate_delay_attr;
|
||||
unsigned long clkgate_delay;
|
||||
#endif
|
||||
|
||||
/* host specific block data */
|
||||
unsigned int max_seg_size; /* see blk_queue_max_segment_size */
|
||||
unsigned short max_segs; /* see blk_queue_max_segments */
|
||||
unsigned short unused;
|
||||
unsigned int max_req_size; /* maximum number of bytes in one req */
|
||||
unsigned int max_blk_size; /* maximum size of one mmc block */
|
||||
unsigned int max_blk_count; /* maximum number of blocks in one req */
|
||||
unsigned int max_busy_timeout; /* max busy timeout in ms */
|
||||
|
||||
/* private data */
|
||||
spinlock_t lock; /* lock for claim and bus ops */
|
||||
|
||||
struct mmc_ios ios; /* current io bus settings */
|
||||
|
||||
/* group bitfields together to minimize padding */
|
||||
unsigned int use_spi_crc:1;
|
||||
unsigned int claimed:1; /* host exclusively claimed */
|
||||
unsigned int bus_dead:1; /* bus has been released */
|
||||
#ifdef CONFIG_MMC_DEBUG
|
||||
unsigned int removed:1; /* host is being removed */
|
||||
#endif
|
||||
|
||||
int rescan_disable; /* disable card detection */
|
||||
int rescan_entered; /* used with nonremovable devices */
|
||||
|
||||
bool trigger_card_event; /* card_event necessary */
|
||||
|
||||
struct mmc_card *card; /* device attached to this host */
|
||||
|
||||
wait_queue_head_t wq;
|
||||
struct task_struct *claimer; /* task that has host claimed */
|
||||
int claim_cnt; /* "claim" nesting count */
|
||||
|
||||
struct delayed_work detect;
|
||||
struct wake_lock detect_wake_lock;
|
||||
const char *wlock_name;
|
||||
int detect_change; /* card detect flag */
|
||||
struct mmc_slot slot;
|
||||
|
||||
const struct mmc_bus_ops *bus_ops; /* current bus driver */
|
||||
unsigned int bus_refs; /* reference counter */
|
||||
|
||||
unsigned int bus_resume_flags;
|
||||
#define MMC_BUSRESUME_MANUAL_RESUME (1 << 0)
|
||||
#define MMC_BUSRESUME_NEEDS_RESUME (1 << 1)
|
||||
|
||||
unsigned int sdio_irqs;
|
||||
struct task_struct *sdio_irq_thread;
|
||||
bool sdio_irq_pending;
|
||||
atomic_t sdio_irq_thread_abort;
|
||||
|
||||
mmc_pm_flag_t pm_flags; /* requested pm features */
|
||||
|
||||
struct led_trigger *led; /* activity led */
|
||||
|
||||
#ifdef CONFIG_REGULATOR
|
||||
bool regulator_enabled; /* regulator state */
|
||||
#endif
|
||||
struct mmc_supply supply;
|
||||
|
||||
struct dentry *debugfs_root;
|
||||
|
||||
struct mmc_async_req *areq; /* active async req */
|
||||
struct mmc_context_info context_info; /* async synchronization info */
|
||||
|
||||
#ifdef CONFIG_FAIL_MMC_REQUEST
|
||||
struct fault_attr fail_mmc_request;
|
||||
#endif
|
||||
|
||||
unsigned int actual_clock; /* Actual HC clock rate */
|
||||
|
||||
unsigned int slotno; /* used for sdio acpi binding */
|
||||
|
||||
int dsr_req; /* DSR value is valid */
|
||||
u32 dsr; /* optional driver stage (DSR) value */
|
||||
|
||||
#ifdef CONFIG_MMC_EMBEDDED_SDIO
|
||||
struct {
|
||||
struct sdio_cis *cis;
|
||||
struct sdio_cccr *cccr;
|
||||
struct sdio_embedded_func *funcs;
|
||||
int num_funcs;
|
||||
} embedded_sdio_data;
|
||||
#endif
|
||||
|
||||
unsigned long private[0] ____cacheline_aligned;
|
||||
};
|
||||
|
||||
struct mmc_host *mmc_alloc_host(int extra, struct device *);
|
||||
int mmc_add_host(struct mmc_host *);
|
||||
void mmc_remove_host(struct mmc_host *);
|
||||
void mmc_free_host(struct mmc_host *);
|
||||
int mmc_of_parse(struct mmc_host *host);
|
||||
|
||||
#ifdef CONFIG_MMC_EMBEDDED_SDIO
|
||||
extern void mmc_set_embedded_sdio_data(struct mmc_host *host,
|
||||
struct sdio_cis *cis,
|
||||
struct sdio_cccr *cccr,
|
||||
struct sdio_embedded_func *funcs,
|
||||
int num_funcs);
|
||||
#endif
|
||||
|
||||
static inline void *mmc_priv(struct mmc_host *host)
|
||||
{
|
||||
return (void *)host->private;
|
||||
}
|
||||
|
||||
#define mmc_host_is_spi(host) ((host)->caps & MMC_CAP_SPI)
|
||||
|
||||
#define mmc_dev(x) ((x)->parent)
|
||||
#define mmc_classdev(x) (&(x)->class_dev)
|
||||
#define mmc_hostname(x) (dev_name(&(x)->class_dev))
|
||||
#define mmc_bus_needs_resume(host) ((host)->bus_resume_flags & MMC_BUSRESUME_NEEDS_RESUME)
|
||||
#define mmc_bus_manual_resume(host) ((host)->bus_resume_flags & MMC_BUSRESUME_MANUAL_RESUME)
|
||||
|
||||
static inline void mmc_set_bus_resume_policy(struct mmc_host *host, int manual)
|
||||
{
|
||||
if (manual) {
|
||||
host->bus_resume_flags |= MMC_BUSRESUME_MANUAL_RESUME;
|
||||
host->bus_resume_flags &= ~MMC_BUSRESUME_NEEDS_RESUME;
|
||||
} else
|
||||
host->bus_resume_flags &= ~MMC_BUSRESUME_MANUAL_RESUME;
|
||||
}
|
||||
|
||||
extern int mmc_resume_bus(struct mmc_host *host);
|
||||
|
||||
int mmc_power_save_host(struct mmc_host *host);
|
||||
int mmc_power_restore_host(struct mmc_host *host);
|
||||
|
||||
void mmc_detect_change(struct mmc_host *, unsigned long delay);
|
||||
void mmc_request_done(struct mmc_host *, struct mmc_request *);
|
||||
|
||||
static inline void mmc_signal_sdio_irq(struct mmc_host *host)
|
||||
{
|
||||
host->ops->enable_sdio_irq(host, 0);
|
||||
host->sdio_irq_pending = true;
|
||||
wake_up_process(host->sdio_irq_thread);
|
||||
}
|
||||
|
||||
void sdio_run_irqs(struct mmc_host *host);
|
||||
|
||||
#ifdef CONFIG_REGULATOR
|
||||
int mmc_regulator_get_ocrmask(struct regulator *supply);
|
||||
int mmc_regulator_set_ocr(struct mmc_host *mmc,
|
||||
struct regulator *supply,
|
||||
unsigned short vdd_bit);
|
||||
#else
|
||||
static inline int mmc_regulator_get_ocrmask(struct regulator *supply)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int mmc_regulator_set_ocr(struct mmc_host *mmc,
|
||||
struct regulator *supply,
|
||||
unsigned short vdd_bit)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int mmc_regulator_get_supply(struct mmc_host *mmc);
|
||||
|
||||
int mmc_pm_notify(struct notifier_block *notify_block, unsigned long, void *);
|
||||
|
||||
static inline int mmc_card_is_removable(struct mmc_host *host)
|
||||
{
|
||||
return !(host->caps & MMC_CAP_NONREMOVABLE);
|
||||
}
|
||||
|
||||
static inline int mmc_card_keep_power(struct mmc_host *host)
|
||||
{
|
||||
return host->pm_flags & MMC_PM_KEEP_POWER;
|
||||
}
|
||||
|
||||
static inline int mmc_card_wake_sdio_irq(struct mmc_host *host)
|
||||
{
|
||||
return host->pm_flags & MMC_PM_WAKE_SDIO_IRQ;
|
||||
}
|
||||
|
||||
static inline int mmc_host_cmd23(struct mmc_host *host)
|
||||
{
|
||||
return host->caps & MMC_CAP_CMD23;
|
||||
}
|
||||
|
||||
static inline int mmc_boot_partition_access(struct mmc_host *host)
|
||||
{
|
||||
return !(host->caps2 & MMC_CAP2_BOOTPART_NOACC);
|
||||
}
|
||||
|
||||
static inline int mmc_host_uhs(struct mmc_host *host)
|
||||
{
|
||||
return host->caps &
|
||||
(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
|
||||
MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 |
|
||||
MMC_CAP_UHS_DDR50);
|
||||
}
|
||||
|
||||
static inline int mmc_host_packed_wr(struct mmc_host *host)
|
||||
{
|
||||
return host->caps2 & MMC_CAP2_PACKED_WR;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MMC_CLKGATE
|
||||
void mmc_host_clk_hold(struct mmc_host *host);
|
||||
void mmc_host_clk_release(struct mmc_host *host);
|
||||
unsigned int mmc_host_clk_rate(struct mmc_host *host);
|
||||
|
||||
#else
|
||||
static inline void mmc_host_clk_hold(struct mmc_host *host)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void mmc_host_clk_release(struct mmc_host *host)
|
||||
{
|
||||
}
|
||||
|
||||
static inline unsigned int mmc_host_clk_rate(struct mmc_host *host)
|
||||
{
|
||||
return host->ios.clock;
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline int mmc_card_hs(struct mmc_card *card)
|
||||
{
|
||||
return card->host->ios.timing == MMC_TIMING_SD_HS ||
|
||||
card->host->ios.timing == MMC_TIMING_MMC_HS;
|
||||
}
|
||||
|
||||
static inline int mmc_card_uhs(struct mmc_card *card)
|
||||
{
|
||||
return card->host->ios.timing == MMC_TIMING_UHS_SDR12 ||
|
||||
card->host->ios.timing == MMC_TIMING_UHS_SDR25 ||
|
||||
card->host->ios.timing == MMC_TIMING_UHS_SDR50 ||
|
||||
card->host->ios.timing == MMC_TIMING_UHS_SDR104 ||
|
||||
card->host->ios.timing == MMC_TIMING_UHS_DDR50;
|
||||
}
|
||||
|
||||
static inline bool mmc_card_hs200(struct mmc_card *card)
|
||||
{
|
||||
return card->host->ios.timing == MMC_TIMING_MMC_HS200;
|
||||
}
|
||||
|
||||
static inline bool mmc_card_ddr52(struct mmc_card *card)
|
||||
{
|
||||
return card->host->ios.timing == MMC_TIMING_MMC_DDR52;
|
||||
}
|
||||
|
||||
static inline bool mmc_card_hs400(struct mmc_card *card)
|
||||
{
|
||||
return card->host->ios.timing == MMC_TIMING_MMC_HS400 ||
|
||||
card->host->ios.timing == MMC_TIMING_MMC_HS400_ES;
|
||||
}
|
||||
|
||||
#endif /* LINUX_MMC_HOST_H */
|
||||
459
include/linux/mmc/mmc.h
Normal file
459
include/linux/mmc/mmc.h
Normal file
|
|
@ -0,0 +1,459 @@
|
|||
/*
|
||||
* Header for MultiMediaCard (MMC)
|
||||
*
|
||||
* Copyright 2002 Hewlett-Packard Company
|
||||
*
|
||||
* Use consistent with the GNU GPL is permitted,
|
||||
* provided that this copyright notice is
|
||||
* preserved in its entirety in all copies and derived works.
|
||||
*
|
||||
* HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
|
||||
* AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
|
||||
* FITNESS FOR ANY PARTICULAR PURPOSE.
|
||||
*
|
||||
* Many thanks to Alessandro Rubini and Jonathan Corbet!
|
||||
*
|
||||
* Based strongly on code by:
|
||||
*
|
||||
* Author: Yong-iL Joh <tolkien@mizi.com>
|
||||
*
|
||||
* Author: Andrew Christian
|
||||
* 15 May 2002
|
||||
*/
|
||||
|
||||
#ifndef LINUX_MMC_MMC_H
|
||||
#define LINUX_MMC_MMC_H
|
||||
|
||||
/* Standard MMC commands (4.1) type argument response */
|
||||
/* class 1 */
|
||||
#define MMC_GO_IDLE_STATE 0 /* bc */
|
||||
#define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */
|
||||
#define MMC_ALL_SEND_CID 2 /* bcr R2 */
|
||||
#define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */
|
||||
#define MMC_SET_DSR 4 /* bc [31:16] RCA */
|
||||
#define MMC_SLEEP_AWAKE 5 /* ac [31:16] RCA 15:flg R1b */
|
||||
#define MMC_SWITCH 6 /* ac [31:0] See below R1b */
|
||||
#define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */
|
||||
#define MMC_SEND_EXT_CSD 8 /* adtc R1 */
|
||||
#define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */
|
||||
#define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */
|
||||
#define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */
|
||||
#define MMC_STOP_TRANSMISSION 12 /* ac R1b */
|
||||
#define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */
|
||||
#define MMC_BUS_TEST_R 14 /* adtc R1 */
|
||||
#define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */
|
||||
#define MMC_BUS_TEST_W 19 /* adtc R1 */
|
||||
#define MMC_SPI_READ_OCR 58 /* spi spi_R3 */
|
||||
#define MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */
|
||||
|
||||
/* class 2 */
|
||||
#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
|
||||
#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
|
||||
#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
|
||||
#define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */
|
||||
#define MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */
|
||||
|
||||
#define MMC_TUNING_BLK_PATTERN_4BIT_SIZE 64
|
||||
#define MMC_TUNING_BLK_PATTERN_8BIT_SIZE 128
|
||||
extern const u8 tuning_blk_pattern_4bit[MMC_TUNING_BLK_PATTERN_4BIT_SIZE];
|
||||
extern const u8 tuning_blk_pattern_8bit[MMC_TUNING_BLK_PATTERN_8BIT_SIZE];
|
||||
|
||||
/* class 3 */
|
||||
#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
|
||||
|
||||
/* class 4 */
|
||||
#define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */
|
||||
#define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */
|
||||
#define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */
|
||||
#define MMC_PROGRAM_CID 26 /* adtc R1 */
|
||||
#define MMC_PROGRAM_CSD 27 /* adtc R1 */
|
||||
|
||||
/* class 6 */
|
||||
#define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */
|
||||
#define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */
|
||||
#define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */
|
||||
|
||||
/* class 5 */
|
||||
#define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */
|
||||
#define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */
|
||||
#define MMC_ERASE 38 /* ac R1b */
|
||||
|
||||
/* class 9 */
|
||||
#define MMC_FAST_IO 39 /* ac <Complex> R4 */
|
||||
#define MMC_GO_IRQ_STATE 40 /* bcr R5 */
|
||||
|
||||
/* class 7 */
|
||||
#define MMC_LOCK_UNLOCK 42 /* adtc R1b */
|
||||
|
||||
/* class 8 */
|
||||
#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
|
||||
#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */
|
||||
|
||||
static inline bool mmc_op_multi(u32 opcode)
|
||||
{
|
||||
return opcode == MMC_WRITE_MULTIPLE_BLOCK ||
|
||||
opcode == MMC_READ_MULTIPLE_BLOCK;
|
||||
}
|
||||
|
||||
/*
|
||||
* MMC_SWITCH argument format:
|
||||
*
|
||||
* [31:26] Always 0
|
||||
* [25:24] Access Mode
|
||||
* [23:16] Location of target Byte in EXT_CSD
|
||||
* [15:08] Value Byte
|
||||
* [07:03] Always 0
|
||||
* [02:00] Command Set
|
||||
*/
|
||||
|
||||
/*
|
||||
MMC status in R1, for native mode (SPI bits are different)
|
||||
Type
|
||||
e : error bit
|
||||
s : status bit
|
||||
r : detected and set for the actual command response
|
||||
x : detected and set during command execution. the host must poll
|
||||
the card by sending status command in order to read these bits.
|
||||
Clear condition
|
||||
a : according to the card state
|
||||
b : always related to the previous command. Reception of
|
||||
a valid command will clear it (with a delay of one command)
|
||||
c : clear by read
|
||||
*/
|
||||
|
||||
#define R1_OUT_OF_RANGE (1 << 31) /* er, c */
|
||||
#define R1_ADDRESS_ERROR (1 << 30) /* erx, c */
|
||||
#define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */
|
||||
#define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */
|
||||
#define R1_ERASE_PARAM (1 << 27) /* ex, c */
|
||||
#define R1_WP_VIOLATION (1 << 26) /* erx, c */
|
||||
#define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */
|
||||
#define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */
|
||||
#define R1_COM_CRC_ERROR (1 << 23) /* er, b */
|
||||
#define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */
|
||||
#define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */
|
||||
#define R1_CC_ERROR (1 << 20) /* erx, c */
|
||||
#define R1_ERROR (1 << 19) /* erx, c */
|
||||
#define R1_UNDERRUN (1 << 18) /* ex, c */
|
||||
#define R1_OVERRUN (1 << 17) /* ex, c */
|
||||
#define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */
|
||||
#define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */
|
||||
#define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */
|
||||
#define R1_ERASE_RESET (1 << 13) /* sr, c */
|
||||
#define R1_STATUS(x) (x & 0xFFFFE000)
|
||||
#define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */
|
||||
#define R1_READY_FOR_DATA (1 << 8) /* sx, a */
|
||||
#define R1_SWITCH_ERROR (1 << 7) /* sx, c */
|
||||
#define R1_EXCEPTION_EVENT (1 << 6) /* sr, a */
|
||||
#define R1_APP_CMD (1 << 5) /* sr, c */
|
||||
|
||||
#define R1_STATE_IDLE 0
|
||||
#define R1_STATE_READY 1
|
||||
#define R1_STATE_IDENT 2
|
||||
#define R1_STATE_STBY 3
|
||||
#define R1_STATE_TRAN 4
|
||||
#define R1_STATE_DATA 5
|
||||
#define R1_STATE_RCV 6
|
||||
#define R1_STATE_PRG 7
|
||||
#define R1_STATE_DIS 8
|
||||
|
||||
/*
|
||||
* MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS
|
||||
* R1 is the low order byte; R2 is the next highest byte, when present.
|
||||
*/
|
||||
#define R1_SPI_IDLE (1 << 0)
|
||||
#define R1_SPI_ERASE_RESET (1 << 1)
|
||||
#define R1_SPI_ILLEGAL_COMMAND (1 << 2)
|
||||
#define R1_SPI_COM_CRC (1 << 3)
|
||||
#define R1_SPI_ERASE_SEQ (1 << 4)
|
||||
#define R1_SPI_ADDRESS (1 << 5)
|
||||
#define R1_SPI_PARAMETER (1 << 6)
|
||||
/* R1 bit 7 is always zero */
|
||||
#define R2_SPI_CARD_LOCKED (1 << 8)
|
||||
#define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */
|
||||
#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP
|
||||
#define R2_SPI_ERROR (1 << 10)
|
||||
#define R2_SPI_CC_ERROR (1 << 11)
|
||||
#define R2_SPI_CARD_ECC_ERROR (1 << 12)
|
||||
#define R2_SPI_WP_VIOLATION (1 << 13)
|
||||
#define R2_SPI_ERASE_PARAM (1 << 14)
|
||||
#define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */
|
||||
#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE
|
||||
|
||||
/* These are unpacked versions of the actual responses */
|
||||
|
||||
struct _mmc_csd {
|
||||
u8 csd_structure;
|
||||
u8 spec_vers;
|
||||
u8 taac;
|
||||
u8 nsac;
|
||||
u8 tran_speed;
|
||||
u16 ccc;
|
||||
u8 read_bl_len;
|
||||
u8 read_bl_partial;
|
||||
u8 write_blk_misalign;
|
||||
u8 read_blk_misalign;
|
||||
u8 dsr_imp;
|
||||
u16 c_size;
|
||||
u8 vdd_r_curr_min;
|
||||
u8 vdd_r_curr_max;
|
||||
u8 vdd_w_curr_min;
|
||||
u8 vdd_w_curr_max;
|
||||
u8 c_size_mult;
|
||||
union {
|
||||
struct { /* MMC system specification version 3.1 */
|
||||
u8 erase_grp_size;
|
||||
u8 erase_grp_mult;
|
||||
} v31;
|
||||
struct { /* MMC system specification version 2.2 */
|
||||
u8 sector_size;
|
||||
u8 erase_grp_size;
|
||||
} v22;
|
||||
} erase;
|
||||
u8 wp_grp_size;
|
||||
u8 wp_grp_enable;
|
||||
u8 default_ecc;
|
||||
u8 r2w_factor;
|
||||
u8 write_bl_len;
|
||||
u8 write_bl_partial;
|
||||
u8 file_format_grp;
|
||||
u8 copy;
|
||||
u8 perm_write_protect;
|
||||
u8 tmp_write_protect;
|
||||
u8 file_format;
|
||||
u8 ecc;
|
||||
};
|
||||
|
||||
/*
|
||||
* OCR bits are mostly in host.h
|
||||
*/
|
||||
#define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */
|
||||
|
||||
/*
|
||||
* Card Command Classes (CCC)
|
||||
*/
|
||||
#define CCC_BASIC (1<<0) /* (0) Basic protocol functions */
|
||||
/* (CMD0,1,2,3,4,7,9,10,12,13,15) */
|
||||
/* (and for SPI, CMD58,59) */
|
||||
#define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */
|
||||
/* (CMD11) */
|
||||
#define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */
|
||||
/* (CMD16,17,18) */
|
||||
#define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */
|
||||
/* (CMD20) */
|
||||
#define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */
|
||||
/* (CMD16,24,25,26,27) */
|
||||
#define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */
|
||||
/* (CMD32,33,34,35,36,37,38,39) */
|
||||
#define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */
|
||||
/* (CMD28,29,30) */
|
||||
#define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */
|
||||
/* (CMD16,CMD42) */
|
||||
#define CCC_APP_SPEC (1<<8) /* (8) Application specific */
|
||||
/* (CMD55,56,57,ACMD*) */
|
||||
#define CCC_IO_MODE (1<<9) /* (9) I/O mode */
|
||||
/* (CMD5,39,40,52,53) */
|
||||
#define CCC_SWITCH (1<<10) /* (10) High speed switch */
|
||||
/* (CMD6,34,35,36,37,50) */
|
||||
/* (11) Reserved */
|
||||
/* (CMD?) */
|
||||
|
||||
/*
|
||||
* CSD field definitions
|
||||
*/
|
||||
|
||||
#define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */
|
||||
#define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */
|
||||
#define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1 */
|
||||
#define CSD_STRUCT_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */
|
||||
|
||||
#define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */
|
||||
#define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */
|
||||
#define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */
|
||||
#define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 - 3.2 - 3.31 */
|
||||
#define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 - 4.1 */
|
||||
|
||||
/*
|
||||
* EXT_CSD fields
|
||||
*/
|
||||
|
||||
#define EXT_CSD_FLUSH_CACHE 32 /* W */
|
||||
#define EXT_CSD_CACHE_CTRL 33 /* R/W */
|
||||
#define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */
|
||||
#define EXT_CSD_PACKED_FAILURE_INDEX 35 /* RO */
|
||||
#define EXT_CSD_PACKED_CMD_STATUS 36 /* RO */
|
||||
#define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO, 2 bytes */
|
||||
#define EXT_CSD_EXP_EVENTS_CTRL 56 /* R/W, 2 bytes */
|
||||
#define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */
|
||||
#define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
|
||||
#define EXT_CSD_PARTITION_SETTING_COMPLETED 155 /* R/W */
|
||||
#define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */
|
||||
#define EXT_CSD_PARTITION_SUPPORT 160 /* RO */
|
||||
#define EXT_CSD_HPI_MGMT 161 /* R/W */
|
||||
#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
|
||||
#define EXT_CSD_BKOPS_EN 163 /* R/W */
|
||||
#define EXT_CSD_BKOPS_START 164 /* W */
|
||||
#define EXT_CSD_SANITIZE_START 165 /* W */
|
||||
#define EXT_CSD_WR_REL_PARAM 166 /* RO */
|
||||
#define EXT_CSD_RPMB_MULT 168 /* RO */
|
||||
#define EXT_CSD_BOOT_WP 173 /* R/W */
|
||||
#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
|
||||
#define EXT_CSD_PART_CONFIG 179 /* R/W */
|
||||
#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */
|
||||
#define EXT_CSD_BUS_WIDTH 183 /* R/W */
|
||||
#define EXT_CSD_STORBE_SUPPORT 184 /* R/W */
|
||||
#define EXT_CSD_HS_TIMING 185 /* R/W */
|
||||
#define EXT_CSD_POWER_CLASS 187 /* R/W */
|
||||
#define EXT_CSD_REV 192 /* RO */
|
||||
#define EXT_CSD_STRUCTURE 194 /* RO */
|
||||
#define EXT_CSD_CARD_TYPE 196 /* RO */
|
||||
#define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* RO */
|
||||
#define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
|
||||
#define EXT_CSD_PWR_CL_52_195 200 /* RO */
|
||||
#define EXT_CSD_PWR_CL_26_195 201 /* RO */
|
||||
#define EXT_CSD_PWR_CL_52_360 202 /* RO */
|
||||
#define EXT_CSD_PWR_CL_26_360 203 /* RO */
|
||||
#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
|
||||
#define EXT_CSD_S_A_TIMEOUT 217 /* RO */
|
||||
#define EXT_CSD_REL_WR_SEC_C 222 /* RO */
|
||||
#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
|
||||
#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */
|
||||
#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
|
||||
#define EXT_CSD_BOOT_MULT 226 /* RO */
|
||||
#define EXT_CSD_SEC_TRIM_MULT 229 /* RO */
|
||||
#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */
|
||||
#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
|
||||
#define EXT_CSD_TRIM_MULT 232 /* RO */
|
||||
#define EXT_CSD_PWR_CL_200_195 236 /* RO */
|
||||
#define EXT_CSD_PWR_CL_200_360 237 /* RO */
|
||||
#define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */
|
||||
#define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */
|
||||
#define EXT_CSD_BKOPS_STATUS 246 /* RO */
|
||||
#define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */
|
||||
#define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */
|
||||
#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */
|
||||
#define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */
|
||||
/* additional : eMMC v5.0 or later Only */
|
||||
#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYPE_B 269 /* RO */
|
||||
#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYPE_A 268 /* RO */
|
||||
#define EXT_CSD_PRE_EOL_INFO 267 /* RO */
|
||||
#define EXT_CSD_OPTIMAL_TRIM_UNIT_SIZE 264 /* RO */
|
||||
#define EXT_CSD_DEVICE_VERSION 262 /* RO, 2Byte */
|
||||
#define EXT_CSD_FIRMWARE_VERSION 254 /* RO, 8Byte */
|
||||
|
||||
/* additional : eMMC moviNAND VMX(PRE eMMC v5.0) device Only */
|
||||
#define EXT_CSD_PREv5_FIRMWARE_VERSION 259 /* RO */
|
||||
#define EXT_CSD_PREv5_CTRL_VERSION 258 /* RO */
|
||||
#define EXT_CSD_PREv5_OPT_ERASE_SIZE 257 /* RO */
|
||||
#define EXT_CSD_PREv5_OPT_WRITE_SIZE 256 /* RO */
|
||||
#define EXT_CSD_PREv5_PRE_EOL_INFO 255 /* RO */
|
||||
#define EXT_CSD_PREv5_LIFE_TIME_EST 254 /* RO */
|
||||
|
||||
#define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */
|
||||
#define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */
|
||||
#define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */
|
||||
#define EXT_CSD_MAX_PACKED_READS 501 /* RO */
|
||||
#define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
|
||||
#define EXT_CSD_HPI_FEATURES 503 /* RO */
|
||||
|
||||
/*
|
||||
* EXT_CSD field definitions
|
||||
*/
|
||||
|
||||
#define EXT_CSD_WR_REL_PARAM_EN (1<<2)
|
||||
|
||||
#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40)
|
||||
#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10)
|
||||
#define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04)
|
||||
#define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01)
|
||||
|
||||
#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7)
|
||||
#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1)
|
||||
#define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3)
|
||||
#define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4)
|
||||
|
||||
#define EXT_CSD_PART_SETTING_COMPLETED (0x1)
|
||||
#define EXT_CSD_PART_SUPPORT_PART_EN (0x1)
|
||||
|
||||
#define EXT_CSD_CMD_SET_NORMAL (1<<0)
|
||||
#define EXT_CSD_CMD_SET_SECURE (1<<1)
|
||||
#define EXT_CSD_CMD_SET_CPSECURE (1<<2)
|
||||
|
||||
#define EXT_CSD_CARD_TYPE_HS_26 (1<<0) /* Card can run at 26MHz */
|
||||
#define EXT_CSD_CARD_TYPE_HS_52 (1<<1) /* Card can run at 52MHz */
|
||||
#define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_HS_26 | \
|
||||
EXT_CSD_CARD_TYPE_HS_52)
|
||||
#define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */
|
||||
/* DDR mode @1.8V or 3V I/O */
|
||||
#define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */
|
||||
/* DDR mode @1.2V I/O */
|
||||
#define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
|
||||
| EXT_CSD_CARD_TYPE_DDR_1_2V)
|
||||
#define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */
|
||||
#define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz */
|
||||
/* SDR mode @1.2V I/O */
|
||||
#define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
|
||||
EXT_CSD_CARD_TYPE_HS200_1_2V)
|
||||
#define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz DDR, 1.8V */
|
||||
#define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */
|
||||
#define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \
|
||||
EXT_CSD_CARD_TYPE_HS400_1_2V)
|
||||
|
||||
#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
|
||||
#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
|
||||
#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
|
||||
#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
|
||||
#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
|
||||
#define EXT_CSD_STROBE_ENHANCED_EN (1<<7) /* Card in enhanced strobe mode */
|
||||
|
||||
#define EXT_CSD_TIMING_BC 0 /* Backwards compatility */
|
||||
#define EXT_CSD_TIMING_HS 1 /* High speed */
|
||||
#define EXT_CSD_TIMING_HS200 2 /* HS200 */
|
||||
#define EXT_CSD_TIMING_HS400 3 /* HS400 */
|
||||
|
||||
#define EXT_CSD_SEC_ER_EN BIT(0)
|
||||
#define EXT_CSD_SEC_BD_BLK_EN BIT(2)
|
||||
#define EXT_CSD_SEC_GB_CL_EN BIT(4)
|
||||
#define EXT_CSD_SEC_SANITIZE BIT(6) /* v4.5 only */
|
||||
|
||||
#define EXT_CSD_RST_N_EN_MASK 0x3
|
||||
#define EXT_CSD_RST_N_ENABLED 1 /* RST_n is enabled on card */
|
||||
|
||||
#define EXT_CSD_NO_POWER_NOTIFICATION 0
|
||||
#define EXT_CSD_POWER_ON 1
|
||||
#define EXT_CSD_POWER_OFF_SHORT 2
|
||||
#define EXT_CSD_POWER_OFF_LONG 3
|
||||
|
||||
#define EXT_CSD_PWR_CL_8BIT_MASK 0xF0 /* 8 bit PWR CLS */
|
||||
#define EXT_CSD_PWR_CL_4BIT_MASK 0x0F /* 8 bit PWR CLS */
|
||||
#define EXT_CSD_PWR_CL_8BIT_SHIFT 4
|
||||
#define EXT_CSD_PWR_CL_4BIT_SHIFT 0
|
||||
|
||||
#define EXT_CSD_PACKED_EVENT_EN BIT(3)
|
||||
|
||||
/*
|
||||
* EXCEPTION_EVENT_STATUS field
|
||||
*/
|
||||
#define EXT_CSD_URGENT_BKOPS BIT(0)
|
||||
#define EXT_CSD_DYNCAP_NEEDED BIT(1)
|
||||
#define EXT_CSD_SYSPOOL_EXHAUSTED BIT(2)
|
||||
#define EXT_CSD_PACKED_FAILURE BIT(3)
|
||||
|
||||
#define EXT_CSD_PACKED_GENERIC_ERROR BIT(0)
|
||||
#define EXT_CSD_PACKED_INDEXED_ERROR BIT(1)
|
||||
|
||||
/*
|
||||
* BKOPS status level
|
||||
*/
|
||||
#define EXT_CSD_BKOPS_LEVEL_2 0x2
|
||||
|
||||
/*
|
||||
* MMC_SWITCH access modes
|
||||
*/
|
||||
|
||||
#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
|
||||
#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */
|
||||
#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */
|
||||
#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
|
||||
|
||||
#endif /* LINUX_MMC_MMC_H */
|
||||
32
include/linux/mmc/pm.h
Normal file
32
include/linux/mmc/pm.h
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
/*
|
||||
* linux/include/linux/mmc/pm.h
|
||||
*
|
||||
* Author: Nicolas Pitre
|
||||
* Copyright: (C) 2009 Marvell Technology Group Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef LINUX_MMC_PM_H
|
||||
#define LINUX_MMC_PM_H
|
||||
|
||||
/*
|
||||
* These flags are used to describe power management features that
|
||||
* some cards (typically SDIO cards) might wish to benefit from when
|
||||
* the host system is being suspended. There are several layers of
|
||||
* abstractions involved, from the host controller driver, to the MMC core
|
||||
* code, to the SDIO core code, to finally get to the actual SDIO function
|
||||
* driver. This file is therefore used for common definitions shared across
|
||||
* all those layers.
|
||||
*/
|
||||
|
||||
typedef unsigned int mmc_pm_flag_t;
|
||||
|
||||
#define MMC_PM_KEEP_POWER (1 << 0) /* preserve card power during suspend */
|
||||
#define MMC_PM_WAKE_SDIO_IRQ (1 << 1) /* wake up host system on SDIO IRQ assertion */
|
||||
#define MMC_PM_IGNORE_PM_NOTIFY (1 << 2) /* ignore mmc pm notify */
|
||||
#define MMC_PM_SKIP_MMC_RESUME_INIT (1 << 3) /* preserve card power during suspend */
|
||||
|
||||
#endif /* LINUX_MMC_PM_H */
|
||||
94
include/linux/mmc/sd.h
Normal file
94
include/linux/mmc/sd.h
Normal file
|
|
@ -0,0 +1,94 @@
|
|||
/*
|
||||
* include/linux/mmc/sd.h
|
||||
*
|
||||
* Copyright (C) 2005-2007 Pierre Ossman, All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or (at
|
||||
* your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef LINUX_MMC_SD_H
|
||||
#define LINUX_MMC_SD_H
|
||||
|
||||
/* SD commands type argument response */
|
||||
/* class 0 */
|
||||
/* This is basically the same command as for MMC with some quirks. */
|
||||
#define SD_SEND_RELATIVE_ADDR 3 /* bcr R6 */
|
||||
#define SD_SEND_IF_COND 8 /* bcr [11:0] See below R7 */
|
||||
#define SD_SWITCH_VOLTAGE 11 /* ac R1 */
|
||||
|
||||
/* class 10 */
|
||||
#define SD_SWITCH 6 /* adtc [31:0] See below R1 */
|
||||
|
||||
/* class 5 */
|
||||
#define SD_ERASE_WR_BLK_START 32 /* ac [31:0] data addr R1 */
|
||||
#define SD_ERASE_WR_BLK_END 33 /* ac [31:0] data addr R1 */
|
||||
|
||||
/* Application commands */
|
||||
#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */
|
||||
#define SD_APP_SD_STATUS 13 /* adtc R1 */
|
||||
#define SD_APP_SEND_NUM_WR_BLKS 22 /* adtc R1 */
|
||||
#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */
|
||||
#define SD_APP_SEND_SCR 51 /* adtc R1 */
|
||||
|
||||
/* OCR bit definitions */
|
||||
#define SD_OCR_S18R (1 << 24) /* 1.8V switching request */
|
||||
#define SD_ROCR_S18A SD_OCR_S18R /* 1.8V switching accepted by card */
|
||||
#define SD_OCR_XPC (1 << 28) /* SDXC power control */
|
||||
#define SD_OCR_CCS (1 << 30) /* Card Capacity Status */
|
||||
|
||||
/*
|
||||
* SD_SWITCH argument format:
|
||||
*
|
||||
* [31] Check (0) or switch (1)
|
||||
* [30:24] Reserved (0)
|
||||
* [23:20] Function group 6
|
||||
* [19:16] Function group 5
|
||||
* [15:12] Function group 4
|
||||
* [11:8] Function group 3
|
||||
* [7:4] Function group 2
|
||||
* [3:0] Function group 1
|
||||
*/
|
||||
|
||||
/*
|
||||
* SD_SEND_IF_COND argument format:
|
||||
*
|
||||
* [31:12] Reserved (0)
|
||||
* [11:8] Host Voltage Supply Flags
|
||||
* [7:0] Check Pattern (0xAA)
|
||||
*/
|
||||
|
||||
/*
|
||||
* SCR field definitions
|
||||
*/
|
||||
|
||||
#define SCR_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.01 */
|
||||
#define SCR_SPEC_VER_1 1 /* Implements system specification 1.10 */
|
||||
#define SCR_SPEC_VER_2 2 /* Implements system specification 2.00-3.0X */
|
||||
|
||||
/*
|
||||
* SD bus widths
|
||||
*/
|
||||
#define SD_BUS_WIDTH_1 0
|
||||
#define SD_BUS_WIDTH_4 2
|
||||
|
||||
/*
|
||||
* SD_SWITCH mode
|
||||
*/
|
||||
#define SD_SWITCH_CHECK 0
|
||||
#define SD_SWITCH_SET 1
|
||||
|
||||
/*
|
||||
* SD_SWITCH function groups
|
||||
*/
|
||||
#define SD_SWITCH_GRP_ACCESS 0
|
||||
|
||||
/*
|
||||
* SD_SWITCH access modes
|
||||
*/
|
||||
#define SD_SWITCH_ACCESS_DEF 0
|
||||
#define SD_SWITCH_ACCESS_HS 1
|
||||
|
||||
#endif /* LINUX_MMC_SD_H */
|
||||
18
include/linux/mmc/sdhci-pci-data.h
Normal file
18
include/linux/mmc/sdhci-pci-data.h
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
#ifndef LINUX_MMC_SDHCI_PCI_DATA_H
|
||||
#define LINUX_MMC_SDHCI_PCI_DATA_H
|
||||
|
||||
struct pci_dev;
|
||||
|
||||
struct sdhci_pci_data {
|
||||
struct pci_dev *pdev;
|
||||
int slotno;
|
||||
int rst_n_gpio; /* Set to -EINVAL if unused */
|
||||
int cd_gpio; /* Set to -EINVAL if unused */
|
||||
int (*setup)(struct sdhci_pci_data *data);
|
||||
void (*cleanup)(struct sdhci_pci_data *data);
|
||||
};
|
||||
|
||||
extern struct sdhci_pci_data *(*sdhci_pci_get_data)(struct pci_dev *pdev,
|
||||
int slotno);
|
||||
|
||||
#endif
|
||||
34
include/linux/mmc/sdhci-spear.h
Normal file
34
include/linux/mmc/sdhci-spear.h
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* include/linux/mmc/sdhci-spear.h
|
||||
*
|
||||
* SDHCI declarations specific to ST SPEAr platform
|
||||
*
|
||||
* Copyright (C) 2010 ST Microelectronics
|
||||
* Viresh Kumar <viresh.linux@gmail.com>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#ifndef LINUX_MMC_SDHCI_SPEAR_H
|
||||
#define LINUX_MMC_SDHCI_SPEAR_H
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
/*
|
||||
* struct sdhci_plat_data: spear sdhci platform data structure
|
||||
*
|
||||
* card_int_gpio: gpio pin used for card detection
|
||||
*/
|
||||
struct sdhci_plat_data {
|
||||
int card_int_gpio;
|
||||
};
|
||||
|
||||
/* This function is used to set platform_data field of pdev->dev */
|
||||
static inline void
|
||||
sdhci_set_plat_data(struct platform_device *pdev, struct sdhci_plat_data *data)
|
||||
{
|
||||
pdev->dev.platform_data = data;
|
||||
}
|
||||
|
||||
#endif /* LINUX_MMC_SDHCI_SPEAR_H */
|
||||
193
include/linux/mmc/sdhci.h
Normal file
193
include/linux/mmc/sdhci.h
Normal file
|
|
@ -0,0 +1,193 @@
|
|||
/*
|
||||
* linux/include/linux/mmc/sdhci.h - Secure Digital Host Controller Interface
|
||||
*
|
||||
* Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or (at
|
||||
* your option) any later version.
|
||||
*/
|
||||
#ifndef LINUX_MMC_SDHCI_H
|
||||
#define LINUX_MMC_SDHCI_H
|
||||
|
||||
#include <linux/scatterlist.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mmc/host.h>
|
||||
|
||||
struct sdhci_host {
|
||||
/* Data set by hardware interface driver */
|
||||
const char *hw_name; /* Hardware bus name */
|
||||
|
||||
unsigned int quirks; /* Deviations from spec. */
|
||||
|
||||
/* Controller doesn't honor resets unless we touch the clock register */
|
||||
#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
|
||||
/* Controller has bad caps bits, but really supports DMA */
|
||||
#define SDHCI_QUIRK_FORCE_DMA (1<<1)
|
||||
/* Controller doesn't like to be reset when there is no card inserted. */
|
||||
#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
|
||||
/* Controller doesn't like clearing the power reg before a change */
|
||||
#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
|
||||
/* Controller has flaky internal state so reset it on each ios change */
|
||||
#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
|
||||
/* Controller has an unusable DMA engine */
|
||||
#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
|
||||
/* Controller has an unusable ADMA engine */
|
||||
#define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
|
||||
/* Controller can only DMA from 32-bit aligned addresses */
|
||||
#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
|
||||
/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
|
||||
#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
|
||||
/* Controller can only ADMA chunks that are a multiple of 32 bits */
|
||||
#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
|
||||
/* Controller needs to be reset after each request to stay stable */
|
||||
#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
|
||||
/* Controller needs voltage and power writes to happen separately */
|
||||
#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
|
||||
/* Controller provides an incorrect timeout value for transfers */
|
||||
#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
|
||||
/* Controller has an issue with buffer bits for small transfers */
|
||||
#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
|
||||
/* Controller does not provide transfer-complete interrupt when not busy */
|
||||
#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14)
|
||||
/* Controller has unreliable card detection */
|
||||
#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
|
||||
/* Controller reports inverted write-protect state */
|
||||
#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
|
||||
/* Controller does not like fast PIO transfers */
|
||||
#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
|
||||
/* Controller has to be forced to use block size of 2048 bytes */
|
||||
#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
|
||||
/* Controller cannot do multi-block transfers */
|
||||
#define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)
|
||||
/* Controller can only handle 1-bit data transfers */
|
||||
#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
|
||||
/* Controller needs 10ms delay between applying power and clock */
|
||||
#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
|
||||
/* Controller uses SDCLK instead of TMCLK for data timeouts */
|
||||
#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24)
|
||||
/* Controller reports wrong base clock capability */
|
||||
#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25)
|
||||
/* Controller cannot support End Attribute in NOP ADMA descriptor */
|
||||
#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26)
|
||||
/* Controller is missing device caps. Use caps provided by host */
|
||||
#define SDHCI_QUIRK_MISSING_CAPS (1<<27)
|
||||
/* Controller uses Auto CMD12 command to stop the transfer */
|
||||
#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28)
|
||||
/* Controller doesn't have HISPD bit field in HI-SPEED SD card */
|
||||
#define SDHCI_QUIRK_NO_HISPD_BIT (1<<29)
|
||||
/* Controller treats ADMA descriptors with length 0000h incorrectly */
|
||||
#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30)
|
||||
/* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
|
||||
#define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31)
|
||||
|
||||
unsigned int quirks2; /* More deviations from spec. */
|
||||
|
||||
#define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0)
|
||||
#define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1)
|
||||
/* The system physically doesn't support 1.8v, even if the host does */
|
||||
#define SDHCI_QUIRK2_NO_1_8_V (1<<2)
|
||||
#define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3)
|
||||
#define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4)
|
||||
/* Controller has a non-standard host control register */
|
||||
#define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5)
|
||||
/* Controller does not support HS200 */
|
||||
#define SDHCI_QUIRK2_BROKEN_HS200 (1<<6)
|
||||
/* Controller does not support DDR50 */
|
||||
#define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7)
|
||||
/* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
|
||||
#define SDHCI_QUIRK2_STOP_WITH_TC (1<<8)
|
||||
|
||||
int irq; /* Device IRQ */
|
||||
void __iomem *ioaddr; /* Mapped address */
|
||||
|
||||
const struct sdhci_ops *ops; /* Low level hw interface */
|
||||
|
||||
/* Internal data */
|
||||
struct mmc_host *mmc; /* MMC structure */
|
||||
u64 dma_mask; /* custom DMA mask */
|
||||
|
||||
#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
|
||||
struct led_classdev led; /* LED control */
|
||||
char led_name[32];
|
||||
#endif
|
||||
|
||||
spinlock_t lock; /* Mutex */
|
||||
|
||||
int flags; /* Host attributes */
|
||||
#define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */
|
||||
#define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
|
||||
#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
|
||||
#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
|
||||
#define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */
|
||||
#define SDHCI_NEEDS_RETUNING (1<<5) /* Host needs retuning */
|
||||
#define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */
|
||||
#define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */
|
||||
#define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */
|
||||
#define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */
|
||||
#define SDHCI_SDR104_NEEDS_TUNING (1<<10) /* SDR104/HS200 needs tuning */
|
||||
#define SDHCI_USING_RETUNING_TIMER (1<<11) /* Host is using a retuning timer for the card */
|
||||
|
||||
unsigned int version; /* SDHCI spec. version */
|
||||
|
||||
unsigned int max_clk; /* Max possible freq (MHz) */
|
||||
unsigned int timeout_clk; /* Timeout freq (KHz) */
|
||||
unsigned int clk_mul; /* Clock Muliplier value */
|
||||
|
||||
unsigned int clock; /* Current clock (MHz) */
|
||||
u8 pwr; /* Current voltage */
|
||||
|
||||
bool runtime_suspended; /* Host is runtime suspended */
|
||||
bool bus_on; /* Bus power prevents runtime suspend */
|
||||
bool preset_enabled; /* Preset is enabled */
|
||||
|
||||
struct mmc_request *mrq; /* Current request */
|
||||
struct mmc_command *cmd; /* Current command */
|
||||
struct mmc_data *data; /* Current data request */
|
||||
unsigned int data_early:1; /* Data finished before cmd */
|
||||
unsigned int busy_handle:1; /* Handling the order of Busy-end */
|
||||
|
||||
struct sg_mapping_iter sg_miter; /* SG state for PIO */
|
||||
unsigned int blocks; /* remaining PIO blocks */
|
||||
|
||||
int sg_count; /* Mapped sg entries */
|
||||
|
||||
u8 *adma_desc; /* ADMA descriptor table */
|
||||
u8 *align_buffer; /* Bounce buffer */
|
||||
|
||||
dma_addr_t adma_addr; /* Mapped ADMA descr. table */
|
||||
dma_addr_t align_addr; /* Mapped bounce buffer */
|
||||
|
||||
struct tasklet_struct finish_tasklet; /* Tasklet structures */
|
||||
|
||||
struct timer_list timer; /* Timer for timeouts */
|
||||
|
||||
u32 caps; /* Alternative CAPABILITY_0 */
|
||||
u32 caps1; /* Alternative CAPABILITY_1 */
|
||||
|
||||
unsigned int ocr_avail_sdio; /* OCR bit masks */
|
||||
unsigned int ocr_avail_sd;
|
||||
unsigned int ocr_avail_mmc;
|
||||
u32 ocr_mask; /* available voltages */
|
||||
|
||||
unsigned timing; /* Current timing */
|
||||
|
||||
u32 thread_isr;
|
||||
|
||||
/* cached registers */
|
||||
u32 ier;
|
||||
|
||||
wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
|
||||
unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
|
||||
|
||||
unsigned int tuning_count; /* Timer count for re-tuning */
|
||||
unsigned int tuning_mode; /* Re-tuning mode supported by host */
|
||||
#define SDHCI_TUNING_MODE_1 0
|
||||
struct timer_list tuning_timer; /* Timer for tuning */
|
||||
|
||||
unsigned long private[0] ____cacheline_aligned;
|
||||
};
|
||||
#endif /* LINUX_MMC_SDHCI_H */
|
||||
193
include/linux/mmc/sdio.h
Normal file
193
include/linux/mmc/sdio.h
Normal file
|
|
@ -0,0 +1,193 @@
|
|||
/*
|
||||
* include/linux/mmc/sdio.h
|
||||
*
|
||||
* Copyright 2006-2007 Pierre Ossman
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or (at
|
||||
* your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef LINUX_MMC_SDIO_H
|
||||
#define LINUX_MMC_SDIO_H
|
||||
|
||||
/* SDIO commands type argument response */
|
||||
#define SD_IO_SEND_OP_COND 5 /* bcr [23:0] OCR R4 */
|
||||
#define SD_IO_RW_DIRECT 52 /* ac [31:0] See below R5 */
|
||||
#define SD_IO_RW_EXTENDED 53 /* adtc [31:0] See below R5 */
|
||||
|
||||
/*
|
||||
* SD_IO_RW_DIRECT argument format:
|
||||
*
|
||||
* [31] R/W flag
|
||||
* [30:28] Function number
|
||||
* [27] RAW flag
|
||||
* [25:9] Register address
|
||||
* [7:0] Data
|
||||
*/
|
||||
|
||||
/*
|
||||
* SD_IO_RW_EXTENDED argument format:
|
||||
*
|
||||
* [31] R/W flag
|
||||
* [30:28] Function number
|
||||
* [27] Block mode
|
||||
* [26] Increment address
|
||||
* [25:9] Register address
|
||||
* [8:0] Byte/block count
|
||||
*/
|
||||
|
||||
#define R4_18V_PRESENT (1<<24)
|
||||
#define R4_MEMORY_PRESENT (1 << 27)
|
||||
|
||||
/*
|
||||
SDIO status in R5
|
||||
Type
|
||||
e : error bit
|
||||
s : status bit
|
||||
r : detected and set for the actual command response
|
||||
x : detected and set during command execution. the host must poll
|
||||
the card by sending status command in order to read these bits.
|
||||
Clear condition
|
||||
a : according to the card state
|
||||
b : always related to the previous command. Reception of
|
||||
a valid command will clear it (with a delay of one command)
|
||||
c : clear by read
|
||||
*/
|
||||
|
||||
#define R5_COM_CRC_ERROR (1 << 15) /* er, b */
|
||||
#define R5_ILLEGAL_COMMAND (1 << 14) /* er, b */
|
||||
#define R5_ERROR (1 << 11) /* erx, c */
|
||||
#define R5_FUNCTION_NUMBER (1 << 9) /* er, c */
|
||||
#define R5_OUT_OF_RANGE (1 << 8) /* er, c */
|
||||
#define R5_STATUS(x) (x & 0xCB00)
|
||||
#define R5_IO_CURRENT_STATE(x) ((x & 0x3000) >> 12) /* s, b */
|
||||
|
||||
/*
|
||||
* Card Common Control Registers (CCCR)
|
||||
*/
|
||||
|
||||
#define SDIO_CCCR_CCCR 0x00
|
||||
|
||||
#define SDIO_CCCR_REV_1_00 0 /* CCCR/FBR Version 1.00 */
|
||||
#define SDIO_CCCR_REV_1_10 1 /* CCCR/FBR Version 1.10 */
|
||||
#define SDIO_CCCR_REV_1_20 2 /* CCCR/FBR Version 1.20 */
|
||||
#define SDIO_CCCR_REV_3_00 3 /* CCCR/FBR Version 3.00 */
|
||||
|
||||
#define SDIO_SDIO_REV_1_00 0 /* SDIO Spec Version 1.00 */
|
||||
#define SDIO_SDIO_REV_1_10 1 /* SDIO Spec Version 1.10 */
|
||||
#define SDIO_SDIO_REV_1_20 2 /* SDIO Spec Version 1.20 */
|
||||
#define SDIO_SDIO_REV_2_00 3 /* SDIO Spec Version 2.00 */
|
||||
#define SDIO_SDIO_REV_3_00 4 /* SDIO Spec Version 3.00 */
|
||||
|
||||
#define SDIO_CCCR_SD 0x01
|
||||
|
||||
#define SDIO_SD_REV_1_01 0 /* SD Physical Spec Version 1.01 */
|
||||
#define SDIO_SD_REV_1_10 1 /* SD Physical Spec Version 1.10 */
|
||||
#define SDIO_SD_REV_2_00 2 /* SD Physical Spec Version 2.00 */
|
||||
#define SDIO_SD_REV_3_00 3 /* SD Physical Spev Version 3.00 */
|
||||
|
||||
#define SDIO_CCCR_IOEx 0x02
|
||||
#define SDIO_CCCR_IORx 0x03
|
||||
|
||||
#define SDIO_CCCR_IENx 0x04 /* Function/Master Interrupt Enable */
|
||||
#define SDIO_CCCR_INTx 0x05 /* Function Interrupt Pending */
|
||||
|
||||
#define SDIO_CCCR_ABORT 0x06 /* function abort/card reset */
|
||||
|
||||
#define SDIO_CCCR_IF 0x07 /* bus interface controls */
|
||||
|
||||
#define SDIO_BUS_WIDTH_MASK 0x03 /* data bus width setting */
|
||||
#define SDIO_BUS_WIDTH_1BIT 0x00
|
||||
#define SDIO_BUS_WIDTH_RESERVED 0x01
|
||||
#define SDIO_BUS_WIDTH_4BIT 0x02
|
||||
#define SDIO_BUS_ECSI 0x20 /* Enable continuous SPI interrupt */
|
||||
#define SDIO_BUS_SCSI 0x40 /* Support continuous SPI interrupt */
|
||||
|
||||
#define SDIO_BUS_ASYNC_INT 0x20
|
||||
|
||||
#define SDIO_BUS_CD_DISABLE 0x80 /* disable pull-up on DAT3 (pin 1) */
|
||||
|
||||
#define SDIO_CCCR_CAPS 0x08
|
||||
|
||||
#define SDIO_CCCR_CAP_SDC 0x01 /* can do CMD52 while data transfer */
|
||||
#define SDIO_CCCR_CAP_SMB 0x02 /* can do multi-block xfers (CMD53) */
|
||||
#define SDIO_CCCR_CAP_SRW 0x04 /* supports read-wait protocol */
|
||||
#define SDIO_CCCR_CAP_SBS 0x08 /* supports suspend/resume */
|
||||
#define SDIO_CCCR_CAP_S4MI 0x10 /* interrupt during 4-bit CMD53 */
|
||||
#define SDIO_CCCR_CAP_E4MI 0x20 /* enable ints during 4-bit CMD53 */
|
||||
#define SDIO_CCCR_CAP_LSC 0x40 /* low speed card */
|
||||
#define SDIO_CCCR_CAP_4BLS 0x80 /* 4 bit low speed card */
|
||||
|
||||
#define SDIO_CCCR_CIS 0x09 /* common CIS pointer (3 bytes) */
|
||||
|
||||
/* Following 4 regs are valid only if SBS is set */
|
||||
#define SDIO_CCCR_SUSPEND 0x0c
|
||||
#define SDIO_CCCR_SELx 0x0d
|
||||
#define SDIO_CCCR_EXECx 0x0e
|
||||
#define SDIO_CCCR_READYx 0x0f
|
||||
|
||||
#define SDIO_CCCR_BLKSIZE 0x10
|
||||
|
||||
#define SDIO_CCCR_POWER 0x12
|
||||
|
||||
#define SDIO_POWER_SMPC 0x01 /* Supports Master Power Control */
|
||||
#define SDIO_POWER_EMPC 0x02 /* Enable Master Power Control */
|
||||
|
||||
#define SDIO_CCCR_SPEED 0x13
|
||||
|
||||
#define SDIO_SPEED_SHS 0x01 /* Supports High-Speed mode */
|
||||
#define SDIO_SPEED_BSS_SHIFT 1
|
||||
#define SDIO_SPEED_BSS_MASK (7<<SDIO_SPEED_BSS_SHIFT)
|
||||
#define SDIO_SPEED_SDR12 (0<<SDIO_SPEED_BSS_SHIFT)
|
||||
#define SDIO_SPEED_SDR25 (1<<SDIO_SPEED_BSS_SHIFT)
|
||||
#define SDIO_SPEED_SDR50 (2<<SDIO_SPEED_BSS_SHIFT)
|
||||
#define SDIO_SPEED_SDR104 (3<<SDIO_SPEED_BSS_SHIFT)
|
||||
#define SDIO_SPEED_DDR50 (4<<SDIO_SPEED_BSS_SHIFT)
|
||||
#define SDIO_SPEED_EHS SDIO_SPEED_SDR25 /* Enable High-Speed */
|
||||
|
||||
#define SDIO_CCCR_UHS 0x14
|
||||
#define SDIO_UHS_SDR50 0x01
|
||||
#define SDIO_UHS_SDR104 0x02
|
||||
#define SDIO_UHS_DDR50 0x04
|
||||
|
||||
#define SDIO_CCCR_DRIVE_STRENGTH 0x15
|
||||
#define SDIO_SDTx_MASK 0x07
|
||||
#define SDIO_DRIVE_SDTA (1<<0)
|
||||
#define SDIO_DRIVE_SDTC (1<<1)
|
||||
#define SDIO_DRIVE_SDTD (1<<2)
|
||||
#define SDIO_DRIVE_DTSx_MASK 0x03
|
||||
#define SDIO_DRIVE_DTSx_SHIFT 4
|
||||
#define SDIO_DTSx_SET_TYPE_B (0 << SDIO_DRIVE_DTSx_SHIFT)
|
||||
#define SDIO_DTSx_SET_TYPE_A (1 << SDIO_DRIVE_DTSx_SHIFT)
|
||||
#define SDIO_DTSx_SET_TYPE_C (2 << SDIO_DRIVE_DTSx_SHIFT)
|
||||
#define SDIO_DTSx_SET_TYPE_D (3 << SDIO_DRIVE_DTSx_SHIFT)
|
||||
/*
|
||||
* Function Basic Registers (FBR)
|
||||
*/
|
||||
|
||||
#define SDIO_FBR_BASE(f) ((f) * 0x100) /* base of function f's FBRs */
|
||||
|
||||
#define SDIO_FBR_STD_IF 0x00
|
||||
|
||||
#define SDIO_FBR_SUPPORTS_CSA 0x40 /* supports Code Storage Area */
|
||||
#define SDIO_FBR_ENABLE_CSA 0x80 /* enable Code Storage Area */
|
||||
|
||||
#define SDIO_FBR_STD_IF_EXT 0x01
|
||||
|
||||
#define SDIO_FBR_POWER 0x02
|
||||
|
||||
#define SDIO_FBR_POWER_SPS 0x01 /* Supports Power Selection */
|
||||
#define SDIO_FBR_POWER_EPS 0x02 /* Enable (low) Power Selection */
|
||||
|
||||
#define SDIO_FBR_CIS 0x09 /* CIS pointer (3 bytes) */
|
||||
|
||||
|
||||
#define SDIO_FBR_CSA 0x0C /* CSA pointer (3 bytes) */
|
||||
|
||||
#define SDIO_FBR_CSA_DATA 0x0F
|
||||
|
||||
#define SDIO_FBR_BLKSIZE 0x10 /* block size (2 bytes) */
|
||||
|
||||
#endif /* LINUX_MMC_SDIO_H */
|
||||
174
include/linux/mmc/sdio_func.h
Executable file
174
include/linux/mmc/sdio_func.h
Executable file
|
|
@ -0,0 +1,174 @@
|
|||
/*
|
||||
* include/linux/mmc/sdio_func.h
|
||||
*
|
||||
* Copyright 2007-2008 Pierre Ossman
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or (at
|
||||
* your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef LINUX_MMC_SDIO_FUNC_H
|
||||
#define LINUX_MMC_SDIO_FUNC_H
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
|
||||
#include <linux/mmc/pm.h>
|
||||
|
||||
struct mmc_card;
|
||||
struct sdio_func;
|
||||
|
||||
typedef void (sdio_irq_handler_t)(struct sdio_func *);
|
||||
|
||||
/*
|
||||
* Structure used to hold embedded SDIO device data from platform layer
|
||||
*/
|
||||
struct sdio_embedded_func {
|
||||
uint8_t f_class;
|
||||
uint32_t f_maxblksize;
|
||||
};
|
||||
|
||||
/*
|
||||
* SDIO function CIS tuple (unknown to the core)
|
||||
*/
|
||||
struct sdio_func_tuple {
|
||||
struct sdio_func_tuple *next;
|
||||
unsigned char code;
|
||||
unsigned char size;
|
||||
unsigned char data[0];
|
||||
};
|
||||
|
||||
/*
|
||||
* SDIO function devices
|
||||
*/
|
||||
struct sdio_func {
|
||||
struct mmc_card *card; /* the card this device belongs to */
|
||||
struct device dev; /* the device */
|
||||
sdio_irq_handler_t *irq_handler; /* IRQ callback */
|
||||
unsigned int num; /* function number */
|
||||
|
||||
unsigned char class; /* standard interface class */
|
||||
unsigned short vendor; /* vendor id */
|
||||
unsigned short device; /* device id */
|
||||
|
||||
unsigned max_blksize; /* maximum block size */
|
||||
unsigned cur_blksize; /* current block size */
|
||||
|
||||
unsigned enable_timeout; /* max enable timeout in msec */
|
||||
|
||||
unsigned int state; /* function state */
|
||||
#define SDIO_STATE_PRESENT (1<<0) /* present in sysfs */
|
||||
|
||||
u8 tmpbuf[4]; /* DMA:able scratch buffer */
|
||||
|
||||
unsigned num_info; /* number of info strings */
|
||||
const char **info; /* info strings */
|
||||
|
||||
struct sdio_func_tuple *tuples;
|
||||
};
|
||||
|
||||
#define sdio_func_present(f) ((f)->state & SDIO_STATE_PRESENT)
|
||||
|
||||
#define sdio_func_set_present(f) ((f)->state |= SDIO_STATE_PRESENT)
|
||||
|
||||
#define sdio_func_id(f) (dev_name(&(f)->dev))
|
||||
|
||||
#define sdio_get_drvdata(f) dev_get_drvdata(&(f)->dev)
|
||||
#define sdio_set_drvdata(f,d) dev_set_drvdata(&(f)->dev, d)
|
||||
#define dev_to_sdio_func(d) container_of(d, struct sdio_func, dev)
|
||||
|
||||
/*
|
||||
* SDIO function device driver
|
||||
*/
|
||||
struct sdio_driver {
|
||||
char *name;
|
||||
const struct sdio_device_id *id_table;
|
||||
|
||||
int (*probe)(struct sdio_func *, const struct sdio_device_id *);
|
||||
void (*remove)(struct sdio_func *);
|
||||
|
||||
struct device_driver drv;
|
||||
};
|
||||
|
||||
#define to_sdio_driver(d) container_of(d, struct sdio_driver, drv)
|
||||
|
||||
/**
|
||||
* SDIO_DEVICE - macro used to describe a specific SDIO device
|
||||
* @vend: the 16 bit manufacturer code
|
||||
* @dev: the 16 bit function id
|
||||
*
|
||||
* This macro is used to create a struct sdio_device_id that matches a
|
||||
* specific device. The class field will be set to SDIO_ANY_ID.
|
||||
*/
|
||||
#define SDIO_DEVICE(vend,dev) \
|
||||
.class = SDIO_ANY_ID, \
|
||||
.vendor = (vend), .device = (dev)
|
||||
|
||||
/**
|
||||
* SDIO_DEVICE_CLASS - macro used to describe a specific SDIO device class
|
||||
* @dev_class: the 8 bit standard interface code
|
||||
*
|
||||
* This macro is used to create a struct sdio_device_id that matches a
|
||||
* specific standard SDIO function type. The vendor and device fields will
|
||||
* be set to SDIO_ANY_ID.
|
||||
*/
|
||||
#define SDIO_DEVICE_CLASS(dev_class) \
|
||||
.class = (dev_class), \
|
||||
.vendor = SDIO_ANY_ID, .device = SDIO_ANY_ID
|
||||
|
||||
extern int sdio_register_driver(struct sdio_driver *);
|
||||
extern void sdio_unregister_driver(struct sdio_driver *);
|
||||
|
||||
/*
|
||||
* SDIO I/O operations
|
||||
*/
|
||||
extern void sdio_claim_host(struct sdio_func *func);
|
||||
extern void sdio_release_host(struct sdio_func *func);
|
||||
|
||||
extern int sdio_enable_func(struct sdio_func *func);
|
||||
extern int sdio_disable_func(struct sdio_func *func);
|
||||
|
||||
extern int sdio_set_block_size(struct sdio_func *func, unsigned blksz);
|
||||
|
||||
extern int sdio_claim_irq(struct sdio_func *func, sdio_irq_handler_t *handler);
|
||||
extern int sdio_release_irq(struct sdio_func *func);
|
||||
|
||||
extern unsigned int sdio_align_size(struct sdio_func *func, unsigned int sz);
|
||||
|
||||
extern u8 sdio_readb(struct sdio_func *func, unsigned int addr, int *err_ret);
|
||||
extern u8 sdio_readb_ext(struct sdio_func *func, unsigned int addr, int *err_ret,
|
||||
unsigned in);
|
||||
extern u16 sdio_readw(struct sdio_func *func, unsigned int addr, int *err_ret);
|
||||
extern u32 sdio_readl(struct sdio_func *func, unsigned int addr, int *err_ret);
|
||||
|
||||
extern int sdio_memcpy_fromio(struct sdio_func *func, void *dst,
|
||||
unsigned int addr, int count);
|
||||
extern int sdio_readsb(struct sdio_func *func, void *dst,
|
||||
unsigned int addr, int count);
|
||||
|
||||
extern void sdio_writeb(struct sdio_func *func, u8 b,
|
||||
unsigned int addr, int *err_ret);
|
||||
extern void sdio_writew(struct sdio_func *func, u16 b,
|
||||
unsigned int addr, int *err_ret);
|
||||
extern void sdio_writel(struct sdio_func *func, u32 b,
|
||||
unsigned int addr, int *err_ret);
|
||||
|
||||
extern u8 sdio_writeb_readb(struct sdio_func *func, u8 write_byte,
|
||||
unsigned int addr, int *err_ret);
|
||||
|
||||
extern int sdio_memcpy_toio(struct sdio_func *func, unsigned int addr,
|
||||
void *src, int count);
|
||||
extern int sdio_writesb(struct sdio_func *func, unsigned int addr,
|
||||
void *src, int count);
|
||||
|
||||
extern unsigned char sdio_f0_readb(struct sdio_func *func,
|
||||
unsigned int addr, int *err_ret);
|
||||
extern void sdio_f0_writeb(struct sdio_func *func, unsigned char b,
|
||||
unsigned int addr, int *err_ret);
|
||||
|
||||
extern mmc_pm_flag_t sdio_get_host_pm_caps(struct sdio_func *func);
|
||||
extern int sdio_set_host_pm_flags(struct sdio_func *func, mmc_pm_flag_t flags);
|
||||
|
||||
#endif /* LINUX_MMC_SDIO_FUNC_H */
|
||||
57
include/linux/mmc/sdio_ids.h
Normal file
57
include/linux/mmc/sdio_ids.h
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/*
|
||||
* SDIO Classes, Interface Types, Manufacturer IDs, etc.
|
||||
*/
|
||||
|
||||
#ifndef LINUX_MMC_SDIO_IDS_H
|
||||
#define LINUX_MMC_SDIO_IDS_H
|
||||
|
||||
/*
|
||||
* Standard SDIO Function Interfaces
|
||||
*/
|
||||
|
||||
#define SDIO_CLASS_NONE 0x00 /* Not a SDIO standard interface */
|
||||
#define SDIO_CLASS_UART 0x01 /* standard UART interface */
|
||||
#define SDIO_CLASS_BT_A 0x02 /* Type-A BlueTooth std interface */
|
||||
#define SDIO_CLASS_BT_B 0x03 /* Type-B BlueTooth std interface */
|
||||
#define SDIO_CLASS_GPS 0x04 /* GPS standard interface */
|
||||
#define SDIO_CLASS_CAMERA 0x05 /* Camera standard interface */
|
||||
#define SDIO_CLASS_PHS 0x06 /* PHS standard interface */
|
||||
#define SDIO_CLASS_WLAN 0x07 /* WLAN interface */
|
||||
#define SDIO_CLASS_ATA 0x08 /* Embedded SDIO-ATA std interface */
|
||||
#define SDIO_CLASS_BT_AMP 0x09 /* Type-A Bluetooth AMP interface */
|
||||
|
||||
/*
|
||||
* Vendors and devices. Sort key: vendor first, device next.
|
||||
*/
|
||||
#define SDIO_VENDOR_ID_BROADCOM 0x02d0
|
||||
#define SDIO_DEVICE_ID_BROADCOM_43143 43143
|
||||
#define SDIO_DEVICE_ID_BROADCOM_43241 0x4324
|
||||
#define SDIO_DEVICE_ID_BROADCOM_4329 0x4329
|
||||
#define SDIO_DEVICE_ID_BROADCOM_4330 0x4330
|
||||
#define SDIO_DEVICE_ID_BROADCOM_4334 0x4334
|
||||
#define SDIO_DEVICE_ID_BROADCOM_4335_4339 0x4335
|
||||
#define SDIO_DEVICE_ID_BROADCOM_43362 43362
|
||||
#define SDIO_DEVICE_ID_BROADCOM_4354 0x4354
|
||||
|
||||
#define SDIO_VENDOR_ID_INTEL 0x0089
|
||||
#define SDIO_DEVICE_ID_INTEL_IWMC3200WIMAX 0x1402
|
||||
#define SDIO_DEVICE_ID_INTEL_IWMC3200WIFI 0x1403
|
||||
#define SDIO_DEVICE_ID_INTEL_IWMC3200TOP 0x1404
|
||||
#define SDIO_DEVICE_ID_INTEL_IWMC3200GPS 0x1405
|
||||
#define SDIO_DEVICE_ID_INTEL_IWMC3200BT 0x1406
|
||||
#define SDIO_DEVICE_ID_INTEL_IWMC3200WIMAX_2G5 0x1407
|
||||
|
||||
#define SDIO_VENDOR_ID_MARVELL 0x02df
|
||||
#define SDIO_DEVICE_ID_MARVELL_LIBERTAS 0x9103
|
||||
#define SDIO_DEVICE_ID_MARVELL_8688WLAN 0x9104
|
||||
#define SDIO_DEVICE_ID_MARVELL_8688BT 0x9105
|
||||
|
||||
#define SDIO_VENDOR_ID_SIANO 0x039a
|
||||
#define SDIO_DEVICE_ID_SIANO_NOVA_B0 0x0201
|
||||
#define SDIO_DEVICE_ID_SIANO_NICE 0x0202
|
||||
#define SDIO_DEVICE_ID_SIANO_VEGA_A0 0x0300
|
||||
#define SDIO_DEVICE_ID_SIANO_VENICE 0x0301
|
||||
#define SDIO_DEVICE_ID_SIANO_NOVA_A0 0x1100
|
||||
#define SDIO_DEVICE_ID_SIANO_STELLAR 0x5347
|
||||
|
||||
#endif /* LINUX_MMC_SDIO_IDS_H */
|
||||
218
include/linux/mmc/sh_mmcif.h
Normal file
218
include/linux/mmc/sh_mmcif.h
Normal file
|
|
@ -0,0 +1,218 @@
|
|||
/*
|
||||
* include/linux/mmc/sh_mmcif.h
|
||||
*
|
||||
* platform data for eMMC driver
|
||||
*
|
||||
* Copyright (C) 2010 Renesas Solutions Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef LINUX_MMC_SH_MMCIF_H
|
||||
#define LINUX_MMC_SH_MMCIF_H
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
/*
|
||||
* MMCIF : CE_CLK_CTRL [19:16]
|
||||
* 1000 : Peripheral clock / 512
|
||||
* 0111 : Peripheral clock / 256
|
||||
* 0110 : Peripheral clock / 128
|
||||
* 0101 : Peripheral clock / 64
|
||||
* 0100 : Peripheral clock / 32
|
||||
* 0011 : Peripheral clock / 16
|
||||
* 0010 : Peripheral clock / 8
|
||||
* 0001 : Peripheral clock / 4
|
||||
* 0000 : Peripheral clock / 2
|
||||
* 1111 : Peripheral clock (sup_pclk set '1')
|
||||
*/
|
||||
|
||||
struct sh_mmcif_plat_data {
|
||||
int (*get_cd)(struct platform_device *pdef);
|
||||
unsigned int slave_id_tx; /* embedded slave_id_[tr]x */
|
||||
unsigned int slave_id_rx;
|
||||
bool use_cd_gpio : 1;
|
||||
bool ccs_unsupported : 1;
|
||||
bool clk_ctrl2_present : 1;
|
||||
unsigned int cd_gpio;
|
||||
u8 sup_pclk; /* 1 :SH7757, 0: SH7724/SH7372 */
|
||||
unsigned long caps;
|
||||
u32 ocr;
|
||||
};
|
||||
|
||||
#define MMCIF_CE_CMD_SET 0x00000000
|
||||
#define MMCIF_CE_ARG 0x00000008
|
||||
#define MMCIF_CE_ARG_CMD12 0x0000000C
|
||||
#define MMCIF_CE_CMD_CTRL 0x00000010
|
||||
#define MMCIF_CE_BLOCK_SET 0x00000014
|
||||
#define MMCIF_CE_CLK_CTRL 0x00000018
|
||||
#define MMCIF_CE_BUF_ACC 0x0000001C
|
||||
#define MMCIF_CE_RESP3 0x00000020
|
||||
#define MMCIF_CE_RESP2 0x00000024
|
||||
#define MMCIF_CE_RESP1 0x00000028
|
||||
#define MMCIF_CE_RESP0 0x0000002C
|
||||
#define MMCIF_CE_RESP_CMD12 0x00000030
|
||||
#define MMCIF_CE_DATA 0x00000034
|
||||
#define MMCIF_CE_INT 0x00000040
|
||||
#define MMCIF_CE_INT_MASK 0x00000044
|
||||
#define MMCIF_CE_HOST_STS1 0x00000048
|
||||
#define MMCIF_CE_HOST_STS2 0x0000004C
|
||||
#define MMCIF_CE_CLK_CTRL2 0x00000070
|
||||
#define MMCIF_CE_VERSION 0x0000007C
|
||||
|
||||
/* CE_BUF_ACC */
|
||||
#define BUF_ACC_DMAWEN (1 << 25)
|
||||
#define BUF_ACC_DMAREN (1 << 24)
|
||||
#define BUF_ACC_BUSW_32 (0 << 17)
|
||||
#define BUF_ACC_BUSW_16 (1 << 17)
|
||||
#define BUF_ACC_ATYP (1 << 16)
|
||||
|
||||
/* CE_CLK_CTRL */
|
||||
#define CLK_ENABLE (1 << 24) /* 1: output mmc clock */
|
||||
#define CLK_CLEAR (0xf << 16)
|
||||
#define CLK_SUP_PCLK (0xf << 16)
|
||||
#define CLKDIV_4 (1 << 16) /* mmc clock frequency.
|
||||
* n: bus clock/(2^(n+1)) */
|
||||
#define CLKDIV_256 (7 << 16) /* mmc clock frequency. (see above) */
|
||||
#define SRSPTO_256 (2 << 12) /* resp timeout */
|
||||
#define SRBSYTO_29 (0xf << 8) /* resp busy timeout */
|
||||
#define SRWDTO_29 (0xf << 4) /* read/write timeout */
|
||||
#define SCCSTO_29 (0xf << 0) /* ccs timeout */
|
||||
|
||||
/* CE_VERSION */
|
||||
#define SOFT_RST_ON (1 << 31)
|
||||
#define SOFT_RST_OFF 0
|
||||
|
||||
static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
|
||||
{
|
||||
return __raw_readl(addr + reg);
|
||||
}
|
||||
|
||||
static inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
|
||||
{
|
||||
__raw_writel(val, addr + reg);
|
||||
}
|
||||
|
||||
#define SH_MMCIF_BBS 512 /* boot block size */
|
||||
|
||||
static inline void sh_mmcif_boot_cmd_send(void __iomem *base,
|
||||
unsigned long cmd, unsigned long arg)
|
||||
{
|
||||
sh_mmcif_writel(base, MMCIF_CE_INT, 0);
|
||||
sh_mmcif_writel(base, MMCIF_CE_ARG, arg);
|
||||
sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd);
|
||||
}
|
||||
|
||||
static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
|
||||
{
|
||||
unsigned long tmp;
|
||||
int cnt;
|
||||
|
||||
for (cnt = 0; cnt < 1000000; cnt++) {
|
||||
tmp = sh_mmcif_readl(base, MMCIF_CE_INT);
|
||||
if (tmp & mask) {
|
||||
sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
static inline int sh_mmcif_boot_cmd(void __iomem *base,
|
||||
unsigned long cmd, unsigned long arg)
|
||||
{
|
||||
sh_mmcif_boot_cmd_send(base, cmd, arg);
|
||||
return sh_mmcif_boot_cmd_poll(base, 0x00010000);
|
||||
}
|
||||
|
||||
static inline int sh_mmcif_boot_do_read_single(void __iomem *base,
|
||||
unsigned int block_nr,
|
||||
unsigned long *buf)
|
||||
{
|
||||
int k;
|
||||
|
||||
/* CMD13 - Status */
|
||||
sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000);
|
||||
|
||||
if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900)
|
||||
return -1;
|
||||
|
||||
/* CMD17 - Read */
|
||||
sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS);
|
||||
if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0)
|
||||
return -1;
|
||||
|
||||
for (k = 0; k < (SH_MMCIF_BBS / 4); k++)
|
||||
buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int sh_mmcif_boot_do_read(void __iomem *base,
|
||||
unsigned long first_block,
|
||||
unsigned long nr_blocks,
|
||||
void *buf)
|
||||
{
|
||||
unsigned long k;
|
||||
int ret = 0;
|
||||
|
||||
/* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
|
||||
sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
|
||||
CLK_ENABLE | CLKDIV_4 | SRSPTO_256 |
|
||||
SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
|
||||
|
||||
/* CMD9 - Get CSD */
|
||||
sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);
|
||||
|
||||
/* CMD7 - Select the card */
|
||||
sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);
|
||||
|
||||
/* CMD16 - Set the block size */
|
||||
sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS);
|
||||
|
||||
for (k = 0; !ret && k < nr_blocks; k++)
|
||||
ret = sh_mmcif_boot_do_read_single(base, first_block + k,
|
||||
buf + (k * SH_MMCIF_BBS));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline void sh_mmcif_boot_init(void __iomem *base)
|
||||
{
|
||||
/* reset */
|
||||
sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON);
|
||||
sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF);
|
||||
|
||||
/* byte swap */
|
||||
sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
|
||||
|
||||
/* Set block size in MMCIF hardware */
|
||||
sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
|
||||
|
||||
/* Enable the clock, set it to Bus clock/256 (about 325Khz). */
|
||||
sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
|
||||
CLK_ENABLE | CLKDIV_256 | SRSPTO_256 |
|
||||
SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
|
||||
|
||||
/* CMD0 */
|
||||
sh_mmcif_boot_cmd(base, 0x00000040, 0);
|
||||
|
||||
/* CMD1 - Get OCR */
|
||||
do {
|
||||
sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */
|
||||
} while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000)
|
||||
!= 0x80000000);
|
||||
|
||||
/* CMD2 - Get CID */
|
||||
sh_mmcif_boot_cmd(base, 0x02806040, 0);
|
||||
|
||||
/* CMD3 - Set card relative address */
|
||||
sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);
|
||||
}
|
||||
|
||||
#endif /* LINUX_MMC_SH_MMCIF_H */
|
||||
35
include/linux/mmc/sh_mobile_sdhi.h
Normal file
35
include/linux/mmc/sh_mobile_sdhi.h
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
#ifndef LINUX_MMC_SH_MOBILE_SDHI_H
|
||||
#define LINUX_MMC_SH_MOBILE_SDHI_H
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
struct platform_device;
|
||||
|
||||
#define SH_MOBILE_SDHI_IRQ_CARD_DETECT "card_detect"
|
||||
#define SH_MOBILE_SDHI_IRQ_SDCARD "sdcard"
|
||||
#define SH_MOBILE_SDHI_IRQ_SDIO "sdio"
|
||||
|
||||
/**
|
||||
* struct sh_mobile_sdhi_ops - SDHI driver callbacks
|
||||
* @cd_wakeup: trigger a card-detection run
|
||||
*/
|
||||
struct sh_mobile_sdhi_ops {
|
||||
void (*cd_wakeup)(const struct platform_device *pdev);
|
||||
};
|
||||
|
||||
struct sh_mobile_sdhi_info {
|
||||
int dma_slave_tx;
|
||||
int dma_slave_rx;
|
||||
unsigned long tmio_flags;
|
||||
unsigned long tmio_caps;
|
||||
unsigned long tmio_caps2;
|
||||
u32 tmio_ocr_mask; /* available MMC voltages */
|
||||
unsigned int cd_gpio;
|
||||
|
||||
/* callbacks for board specific setup code */
|
||||
int (*init)(struct platform_device *pdev,
|
||||
const struct sh_mobile_sdhi_ops *ops);
|
||||
void (*cleanup)(struct platform_device *pdev);
|
||||
};
|
||||
|
||||
#endif /* LINUX_MMC_SH_MOBILE_SDHI_H */
|
||||
34
include/linux/mmc/slot-gpio.h
Normal file
34
include/linux/mmc/slot-gpio.h
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* Generic GPIO card-detect helper header
|
||||
*
|
||||
* Copyright (C) 2011, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef MMC_SLOT_GPIO_H
|
||||
#define MMC_SLOT_GPIO_H
|
||||
|
||||
struct mmc_host;
|
||||
|
||||
int mmc_gpio_get_ro(struct mmc_host *host);
|
||||
int mmc_gpio_request_ro(struct mmc_host *host, unsigned int gpio);
|
||||
void mmc_gpio_free_ro(struct mmc_host *host);
|
||||
|
||||
int mmc_gpio_get_cd(struct mmc_host *host);
|
||||
int mmc_gpio_request_cd(struct mmc_host *host, unsigned int gpio,
|
||||
unsigned int debounce);
|
||||
void mmc_gpio_free_cd(struct mmc_host *host);
|
||||
|
||||
int mmc_gpiod_request_cd(struct mmc_host *host, const char *con_id,
|
||||
unsigned int idx, bool override_active_level,
|
||||
unsigned int debounce, bool *gpio_invert);
|
||||
int mmc_gpiod_request_ro(struct mmc_host *host, const char *con_id,
|
||||
unsigned int idx, bool override_active_level,
|
||||
unsigned int debounce, bool *gpio_invert);
|
||||
void mmc_gpiod_free_cd(struct mmc_host *host);
|
||||
void mmc_gpiod_request_cd_irq(struct mmc_host *host);
|
||||
|
||||
#endif
|
||||
66
include/linux/mmc/tmio.h
Normal file
66
include/linux/mmc/tmio.h
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* include/linux/mmc/tmio.h
|
||||
*
|
||||
* Copyright (C) 2007 Ian Molton
|
||||
* Copyright (C) 2004 Ian Molton
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Driver for the MMC / SD / SDIO cell found in:
|
||||
*
|
||||
* TC6393XB TC6391XB TC6387XB T7L66XB ASIC3
|
||||
*/
|
||||
#ifndef LINUX_MMC_TMIO_H
|
||||
#define LINUX_MMC_TMIO_H
|
||||
|
||||
#define CTL_SD_CMD 0x00
|
||||
#define CTL_ARG_REG 0x04
|
||||
#define CTL_STOP_INTERNAL_ACTION 0x08
|
||||
#define CTL_XFER_BLK_COUNT 0xa
|
||||
#define CTL_RESPONSE 0x0c
|
||||
#define CTL_STATUS 0x1c
|
||||
#define CTL_STATUS2 0x1e
|
||||
#define CTL_IRQ_MASK 0x20
|
||||
#define CTL_SD_CARD_CLK_CTL 0x24
|
||||
#define CTL_SD_XFER_LEN 0x26
|
||||
#define CTL_SD_MEM_CARD_OPT 0x28
|
||||
#define CTL_SD_ERROR_DETAIL_STATUS 0x2c
|
||||
#define CTL_SD_DATA_PORT 0x30
|
||||
#define CTL_TRANSACTION_CTL 0x34
|
||||
#define CTL_SDIO_STATUS 0x36
|
||||
#define CTL_SDIO_IRQ_MASK 0x38
|
||||
#define CTL_DMA_ENABLE 0xd8
|
||||
#define CTL_RESET_SD 0xe0
|
||||
#define CTL_VERSION 0xe2
|
||||
#define CTL_SDIO_REGS 0x100
|
||||
#define CTL_CLK_AND_WAIT_CTL 0x138
|
||||
#define CTL_RESET_SDIO 0x1e0
|
||||
|
||||
/* Definitions for values the CTRL_STATUS register can take. */
|
||||
#define TMIO_STAT_CMDRESPEND 0x00000001
|
||||
#define TMIO_STAT_DATAEND 0x00000004
|
||||
#define TMIO_STAT_CARD_REMOVE 0x00000008
|
||||
#define TMIO_STAT_CARD_INSERT 0x00000010
|
||||
#define TMIO_STAT_SIGSTATE 0x00000020
|
||||
#define TMIO_STAT_WRPROTECT 0x00000080
|
||||
#define TMIO_STAT_CARD_REMOVE_A 0x00000100
|
||||
#define TMIO_STAT_CARD_INSERT_A 0x00000200
|
||||
#define TMIO_STAT_SIGSTATE_A 0x00000400
|
||||
#define TMIO_STAT_CMD_IDX_ERR 0x00010000
|
||||
#define TMIO_STAT_CRCFAIL 0x00020000
|
||||
#define TMIO_STAT_STOPBIT_ERR 0x00040000
|
||||
#define TMIO_STAT_DATATIMEOUT 0x00080000
|
||||
#define TMIO_STAT_RXOVERFLOW 0x00100000
|
||||
#define TMIO_STAT_TXUNDERRUN 0x00200000
|
||||
#define TMIO_STAT_CMDTIMEOUT 0x00400000
|
||||
#define TMIO_STAT_RXRDY 0x01000000
|
||||
#define TMIO_STAT_TXRQ 0x02000000
|
||||
#define TMIO_STAT_ILL_FUNC 0x20000000
|
||||
#define TMIO_STAT_CMD_BUSY 0x40000000
|
||||
#define TMIO_STAT_ILL_ACCESS 0x80000000
|
||||
|
||||
#define TMIO_BBS 512 /* Boot block size */
|
||||
|
||||
#endif /* LINUX_MMC_TMIO_H */
|
||||
Loading…
Add table
Add a link
Reference in a new issue