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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
Fixed MTP to work with TWRP
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awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
203
include/linux/mtd/spi-nor.h
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203
include/linux/mtd/spi-nor.h
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/*
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __LINUX_MTD_SPI_NOR_H
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#define __LINUX_MTD_SPI_NOR_H
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/*
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* Note on opcode nomenclature: some opcodes have a format like
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* SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
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* of I/O lines used for the opcode, address, and data (respectively). The
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* FUNCTION has an optional suffix of '4', to represent an opcode which
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* requires a 4-byte (32-bit) address.
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*/
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/* Flash opcodes. */
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#define SPINOR_OP_WREN 0x06 /* Write enable */
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#define SPINOR_OP_RDSR 0x05 /* Read status register */
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#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
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#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
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#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
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#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */
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#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */
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#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
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#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
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#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
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#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
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#define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
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#define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
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#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
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#define SPINOR_OP_RDCR 0x35 /* Read configuration register */
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#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
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/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
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#define SPINOR_OP_READ4 0x13 /* Read data bytes (low frequency) */
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#define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */
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#define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */
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#define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */
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#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
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#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
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/* Used for SST flashes only. */
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#define SPINOR_OP_BP 0x02 /* Byte program */
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#define SPINOR_OP_WRDI 0x04 /* Write disable */
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#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
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/* Used for Macronix and Winbond flashes. */
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#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
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#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
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/* Used for Spansion flashes only. */
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#define SPINOR_OP_BRWR 0x17 /* Bank register write */
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/* Status Register bits. */
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#define SR_WIP 1 /* Write in progress */
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#define SR_WEL 2 /* Write enable latch */
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/* meaning of other SR_* bits may differ between vendors */
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#define SR_BP0 4 /* Block protect 0 */
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#define SR_BP1 8 /* Block protect 1 */
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#define SR_BP2 0x10 /* Block protect 2 */
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#define SR_SRWD 0x80 /* SR write protect */
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#define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
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/* Flag Status Register bits */
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#define FSR_READY 0x80
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/* Configuration Register bits. */
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#define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */
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enum read_mode {
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SPI_NOR_NORMAL = 0,
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SPI_NOR_FAST,
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SPI_NOR_DUAL,
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SPI_NOR_QUAD,
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};
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/**
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* struct spi_nor_xfer_cfg - Structure for defining a Serial Flash transfer
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* @wren: command for "Write Enable", or 0x00 for not required
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* @cmd: command for operation
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* @cmd_pins: number of pins to send @cmd (1, 2, 4)
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* @addr: address for operation
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* @addr_pins: number of pins to send @addr (1, 2, 4)
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* @addr_width: number of address bytes
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* (3,4, or 0 for address not required)
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* @mode: mode data
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* @mode_pins: number of pins to send @mode (1, 2, 4)
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* @mode_cycles: number of mode cycles (0 for mode not required)
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* @dummy_cycles: number of dummy cycles (0 for dummy not required)
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*/
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struct spi_nor_xfer_cfg {
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u8 wren;
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u8 cmd;
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u8 cmd_pins;
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u32 addr;
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u8 addr_pins;
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u8 addr_width;
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u8 mode;
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u8 mode_pins;
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u8 mode_cycles;
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u8 dummy_cycles;
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};
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#define SPI_NOR_MAX_CMD_SIZE 8
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enum spi_nor_ops {
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SPI_NOR_OPS_READ = 0,
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SPI_NOR_OPS_WRITE,
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SPI_NOR_OPS_ERASE,
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SPI_NOR_OPS_LOCK,
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SPI_NOR_OPS_UNLOCK,
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};
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/**
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* struct spi_nor - Structure for defining a the SPI NOR layer
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* @mtd: point to a mtd_info structure
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* @lock: the lock for the read/write/erase/lock/unlock operations
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* @dev: point to a spi device, or a spi nor controller device.
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* @page_size: the page size of the SPI NOR
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* @addr_width: number of address bytes
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* @erase_opcode: the opcode for erasing a sector
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* @read_opcode: the read opcode
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* @read_dummy: the dummy needed by the read operation
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* @program_opcode: the program opcode
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* @flash_read: the mode of the read
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* @sst_write_second: used by the SST write operation
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* @cfg: used by the read_xfer/write_xfer
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* @cmd_buf: used by the write_reg
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* @prepare: [OPTIONAL] do some preparations for the
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* read/write/erase/lock/unlock operations
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* @unprepare: [OPTIONAL] do some post work after the
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* read/write/erase/lock/unlock operations
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* @read_xfer: [OPTIONAL] the read fundamental primitive
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* @write_xfer: [OPTIONAL] the writefundamental primitive
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* @read_reg: [DRIVER-SPECIFIC] read out the register
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* @write_reg: [DRIVER-SPECIFIC] write data to the register
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* @read_id: [REPLACEABLE] read out the ID data, and find
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* the proper spi_device_id
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* @wait_till_ready: [REPLACEABLE] wait till the NOR becomes ready
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* @read: [DRIVER-SPECIFIC] read data from the SPI NOR
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* @write: [DRIVER-SPECIFIC] write data to the SPI NOR
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* @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
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* at the offset @offs
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* @priv: the private data
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*/
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struct spi_nor {
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struct mtd_info *mtd;
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struct mutex lock;
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struct device *dev;
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u32 page_size;
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u8 addr_width;
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u8 erase_opcode;
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u8 read_opcode;
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u8 read_dummy;
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u8 program_opcode;
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enum read_mode flash_read;
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bool sst_write_second;
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struct spi_nor_xfer_cfg cfg;
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u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
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int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
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void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
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int (*read_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
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u8 *buf, size_t len);
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int (*write_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
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u8 *buf, size_t len);
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int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
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int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
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int write_enable);
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const struct spi_device_id *(*read_id)(struct spi_nor *nor);
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int (*wait_till_ready)(struct spi_nor *nor);
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int (*read)(struct spi_nor *nor, loff_t from,
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size_t len, size_t *retlen, u_char *read_buf);
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void (*write)(struct spi_nor *nor, loff_t to,
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size_t len, size_t *retlen, const u_char *write_buf);
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int (*erase)(struct spi_nor *nor, loff_t offs);
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void *priv;
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};
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/**
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* spi_nor_scan() - scan the SPI NOR
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* @nor: the spi_nor structure
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* @name: the chip type name
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* @mode: the read mode supported by the driver
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*
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* The drivers can use this fuction to scan the SPI NOR.
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* In the scanning, it will try to get all the necessary information to
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* fill the mtd_info{} and the spi_nor{}.
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*
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* The chip type name can be provided through the @name parameter.
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*
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* Return: 0 for success, others for failure.
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*/
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int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode);
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#endif
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