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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
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204
include/linux/muic/max77804-muic.h Normal file
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/*
* max77804-muic.h - MUIC for the Maxim 77804
*
* Copyright (C) 2011 Samsung Electrnoics
* Seoyoung Jeong <seo0.jeong@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* This driver is based on max14577-muic.h
*
*/
#ifndef __MAX77804_MUIC_H__
#define __MAX77804_MUIC_H__
#define MUIC_DEV_NAME "muic-max77804"
/* max77804 muic register read/write related information defines. */
/* MAX77804 REGISTER ENABLE or DISABLE bit */
enum max77804_reg_bit_control {
MAX77804_DISABLE_BIT = 0,
MAX77804_ENABLE_BIT,
};
/* MAX77804 STATUS1 register */
#define STATUS1_ADC_SHIFT 0
#define STATUS1_ADCLOW_SHIFT 5
#define STATUS1_ADCERR_SHIFT 6
#define STATUS1_ADC1K_SHIFT 7
#define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
#define STATUS1_ADCLOW_MASK (0x1 << STATUS1_ADCLOW_SHIFT)
#define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
#define STATUS1_ADC1K_MASK (0x1 << STATUS1_ADC1K_SHIFT)
/* MAX77804 STATUS2 register */
#define STATUS2_CHGTYP_SHIFT 0
#define STATUS2_CHGDETRUN_SHIFT 3
#define STATUS2_DXOVP_SHIFT 5
#define STATUS2_VBVOLT_SHIFT 6
#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
#define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
#define STATUS2_DXOVP_MASK (0x1 << STATUS2_DXOVP_SHIFT)
#define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
/* MAX77804 CDETCTRL1 register */
#define CHGDETEN_SHIFT 0
#define CHGTYPM_SHIFT 1
#define DCHKTM_SHIFT 4
#define CHGDETEN_MASK (0x1 << CHGDETEN_SHIFT)
#define CHGTYPM_MASK (0x1 << CHGTYPM_SHIFT)
#define DCHKTM_MASK (0x1 << DCHKTM_SHIFT)
/* MAX77804 CONTROL1 register */
#define COMN1SW_SHIFT 0
#define COMP2SW_SHIFT 3
#define MICEN_SHIFT 6
#define IDBEN_SHIFT 7
#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
#define MICEN_MASK (0x1 << MICEN_SHIFT)
#define IDBEN_MASK (0x1 << IDBEN_SHIFT)
#define CLEAR_IDBEN_MICEN_MASK (COMN1SW_MASK | COMP2SW_MASK)
/* MAX77804 CONTROL2 register */
#define CTRL2_ADCLOWPWR_SHIFT 0
#define CTRL2_CPEN_SHIFT 2
#define CTRL2_ACCDET_SHIFT 5
#define CTRL2_ADCLOWPWR_MASK (0x1 << CTRL2_ADCLOWPWR_SHIFT)
#define CTRL2_CPEN_MASK (0x1 << CTRL2_CPEN_SHIFT)
#define CTRL2_ACCDET_MASK (0x1 << CTRL2_ACCDET_SHIFT)
#define CTRL2_CPEn1_LOWPWD0 ((MAX77804_ENABLE_BIT << CTRL2_CPEN_SHIFT) | \
(MAX77804_DISABLE_BIT << CTRL2_ADCLOWPWR_SHIFT))
#define CTRl2_CPEN0_LOWPWD1 ((MAX77804_DISABLE_BIT << CTRL2_CPEN_SHIFT) | \
(MAX77804_ENABLE_BIT << CTRL2_ADCLOWPWR_SHIFT))
/* MAX77804 CONTROL3 register */
#define CTRL3_JIGSET_SHIFT 0
#define CTRL3_BTLDSET_SHIFT 2
#define CTRL3_ADCDBSET_SHIFT 4
#define CTRL3_JIGSET_MASK (0x3 << CTRL3_JIGSET_SHIFT)
#define CTRL3_BTLDSET_MASK (0x3 << CTRL3_BTLDSET_SHIFT)
#define CTRL3_ADCDBSET_MASK (0x3 << CTRL3_ADCDBSET_SHIFT)
/* MAX77804 MUIC support for device tree */
struct of_max77804_muic_support {
bool notifier;
bool otg_dongle;
};
typedef enum {
VB_LOW = 0x00,
VB_HIGH = (0x1 << STATUS2_VBVOLT_SHIFT),
VB_DONTCARE = 0xff,
} vbvolt_t;
typedef enum {
CHGDETRUN_FALSE = 0x00,
CHGDETRUN_TRUE = (0x1 << STATUS2_CHGDETRUN_SHIFT),
CHGDETRUN_DONTCARE = 0xff,
} chgdetrun_t;
/* MAX77804 MUIC Output of USB Charger Detection */
typedef enum {
/* No Valid voltage at VB (Vvb < Vvbdet) */
CHGTYP_NO_VOLTAGE = 0x00,
/* Unknown (D+/D- does not present a valid USB charger signature) */
CHGTYP_USB = 0x01,
/* Charging Downstream Port */
CHGTYP_CDP = 0x02,
/* Dedicated Charger (D+/D- shorted) */
CHGTYP_DEDICATED_CHARGER = 0x03,
/* Special 500mA charger, max current 500mA */
CHGTYP_500MA = 0x04,
/* Special 1A charger, max current 1A */
CHGTYP_1A = 0x05,
/* Reserved for Future Use */
CHGTYP_RFU = 0x06,
/* Any charger type */
CHGTYP_ANY = 0xfd,
/* Don't care charger type */
CHGTYP_DONTCARE = 0xfe,
#if 0
/* Dead Battery Charging, max current 100mA */
CHGTYP_DB_100MA_CHARGER = 0x07,
CHGTYP_MAX,
CHGTYP_INIT,
CHGTYP_MIN = CHGTYP_NO_VOLTAGE
#endif
} chgtyp_t;
/* muic register value for COMN1, COMN2 in CTRL1 reg */
/*
* MAX77804 CONTROL1 register
* ID Bypass [7] / Mic En [6] / D+ [5:3] / D- [2:0]
* 0: ID Bypass Open / 1: IDB connect to UID
* 0: Mic En Open / 1: Mic connect to VB
* 000: Open / 001: USB / 010: Audio / 011: UART
*/
enum max77804_reg_ctrl1_val {
MAX77804_MUIC_CTRL1_ID_OPEN = 0x0,
MAX77804_MUIC_CTRL1_ID_BYPASS = 0x1,
MAX77804_MUIC_CTRL1_MIC_OPEN = 0x0,
MAX77804_MUIC_CTRL1_MIC_VB = 0x1,
MAX77804_MUIC_CTRL1_COM_OPEN = 0x00,
MAX77804_MUIC_CTRL1_COM_USB = 0x01,
MAX77804_MUIC_CTRL1_COM_AUDIO = 0x02,
MAX77804_MUIC_CTRL1_COM_UART = 0x03,
MAX77804_MUIC_CTRL1_COM_USB_CP = 0x04,
MAX77804_MUIC_CTRL1_COM_UART_CP = 0x05,
};
typedef enum {
CTRL1_OPEN = (MAX77804_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77804_MUIC_CTRL1_MIC_OPEN << MICEN_SHIFT) | \
(MAX77804_MUIC_CTRL1_COM_OPEN << COMP2SW_SHIFT) | \
(MAX77804_MUIC_CTRL1_COM_OPEN << COMN1SW_SHIFT),
CTRL1_USB = (MAX77804_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77804_MUIC_CTRL1_MIC_OPEN << MICEN_SHIFT) | \
(MAX77804_MUIC_CTRL1_COM_USB << COMP2SW_SHIFT) | \
(MAX77804_MUIC_CTRL1_COM_USB << COMN1SW_SHIFT),
CTRL1_AUDIO = (MAX77804_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77804_MUIC_CTRL1_MIC_OPEN << MICEN_SHIFT) | \
(MAX77804_MUIC_CTRL1_COM_AUDIO << COMP2SW_SHIFT) | \
(MAX77804_MUIC_CTRL1_COM_AUDIO << COMN1SW_SHIFT),
CTRL1_UART = (MAX77804_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77804_MUIC_CTRL1_MIC_OPEN << MICEN_SHIFT) | \
(MAX77804_MUIC_CTRL1_COM_UART << COMP2SW_SHIFT) | \
(MAX77804_MUIC_CTRL1_COM_UART << COMN1SW_SHIFT),
CTRL1_USB_CP = (MAX77804_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77804_MUIC_CTRL1_MIC_OPEN << MICEN_SHIFT) | \
(MAX77804_MUIC_CTRL1_COM_USB_CP << COMP2SW_SHIFT) | \
(MAX77804_MUIC_CTRL1_COM_USB_CP << COMN1SW_SHIFT),
CTRL1_UART_CP = (MAX77804_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77804_MUIC_CTRL1_MIC_OPEN << MICEN_SHIFT) | \
(MAX77804_MUIC_CTRL1_COM_UART_CP << COMP2SW_SHIFT) | \
(MAX77804_MUIC_CTRL1_COM_UART_CP << COMN1SW_SHIFT),
} max77804_reg_ctrl1_t;
enum max77804_muic_reg_init_value {
/* CTRL3 ADCDbSet register. Manual Ctrl of ADC debounc Time: 25ms */
REG_CONTROL3_VALUE = (0x20),
};
extern struct device *switch_device;
#endif /* __MAX77804_MUIC_H__ */

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/*
* max77804k-muic.h - MUIC for the Maxim 77804K
*
* Copyright (C) 2011 Samsung Electrnoics
* Seoyoung Jeong <seo0.jeong@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* This driver is based on max14577-muic.h
*
*/
#ifndef __MAX77804K_MUIC_H__
#define __MAX77804K_MUIC_H__
#define MUIC_DEV_NAME "muic-max77804k"
/* max77804k muic register read/write related information defines. */
/* MAX77804K REGISTER ENABLE or DISABLE bit */
enum max77804k_reg_bit_control {
MAX77804K_DISABLE_BIT = 0,
MAX77804K_ENABLE_BIT,
};
/* MAX77804K STATUS1 register */
#define STATUS1_ADC_SHIFT 0
#define STATUS1_ADCERR_SHIFT 6
#define STATUS1_ADC1K_SHIFT 7
#define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
#define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
#define STATUS1_ADC1K_MASK (0x1 << STATUS1_ADC1K_SHIFT)
/* MAX77804K STATUS2 register */
#define STATUS2_CHGTYP_SHIFT 0
#define STATUS2_CHGDETRUN_SHIFT 3
#define STATUS2_DCDTMR_SHIFT 4
#define STATUS2_DXOVP_SHIFT 5
#define STATUS2_VBVOLT_SHIFT 6
#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
#define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
#define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT)
#define STATUS2_DXOVP_MASK (0x1 << STATUS2_DXOVP_SHIFT)
#define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
/* MAX77804K CDETCTRL1 register */
#define CHGDETEN_SHIFT 0
#define CHGTYPM_SHIFT 1
#define CDDELAY_SHIFT 4
#define CHGDETEN_MASK (0x1 << CHGDETEN_SHIFT)
#define CHGTYPM_MASK (0x1 << CHGTYPM_SHIFT)
#define CDDELAY_MASK (0x1 << CDDELAY_SHIFT)
/* MAX77804K CONTROL1 register */
#define COMN1SW_SHIFT 0
#define COMP2SW_SHIFT 3
#define IDBEN_SHIFT 7
#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
#define IDBEN_MASK (0x1 << IDBEN_SHIFT)
#define CLEAR_IDBEN_RSVD_MASK (COMN1SW_MASK | COMP2SW_MASK)
/* MAX77804K CONTROL2 register */
#define CTRL2_LOWPWR_SHIFT 0
#define CTRL2_CPEN_SHIFT 2
#define CTRL2_ACCDET_SHIFT 5
#define CTRL2_LOWPWR_MASK (0x1 << CTRL2_LOWPWR_SHIFT)
#define CTRL2_CPEN_MASK (0x1 << CTRL2_CPEN_SHIFT)
#define CTRL2_ACCDET_MASK (0x1 << CTRL2_ACCDET_SHIFT)
#define CTRL2_CPEN1_LOWPWD0 ((MAX77804K_ENABLE_BIT << CTRL2_CPEN_SHIFT) | \
(MAX77804K_DISABLE_BIT << CTRL2_ADCLOWPWR_SHIFT))
#define CTRL2_CPEN0_LOWPWD1 ((MAX77804K_DISABLE_BIT << CTRL2_CPEN_SHIFT) | \
(MAX77804K_ENABLE_BIT << CTRL2_ADCLOWPWR_SHIFT))
/* MAX77804K CONTROL3 register */
#define CTRL3_JIGSET_SHIFT 0
#define CTRL3_JIGSET_MASK (0x3 << CTRL3_JIGSET_SHIFT)
/* MAX77804K CONTROL4 register */
#define CTRL4_ADCDBSET_SHIFT 0
#define CTRL4_ADCMODE_SHIFT 6
#define CTRL4_ADCDBSET_MASK (0x3 << CTRL4_ADCDBSET_SHIFT)
#define CTRL4_ADCMODE_MASK (0x3 << CTRL4_ADCMODE_SHIFT)
/* MAX77804K MUIC support for device tree */
struct of_max77804k_muic_support {
bool notifier;
bool otg_dongle;
};
typedef enum {
VB_LOW = 0x00,
VB_HIGH = (0x1 << STATUS2_VBVOLT_SHIFT),
VB_DONTCARE = 0xff,
} vbvolt_t;
typedef enum {
CHGDETRUN_FALSE = 0x00,
CHGDETRUN_TRUE = (0x1 << STATUS2_CHGDETRUN_SHIFT),
CHGDETRUN_DONTCARE = 0xff,
} chgdetrun_t;
/* MAX77804 MUIC Output of USB Charger Detection */
typedef enum {
/* No Valid voltage at VB (Vvb < Vvbdet) */
CHGTYP_NO_VOLTAGE = 0x00,
/* Unknown (D+/D- does not present a valid USB charger signature) */
CHGTYP_USB = 0x01,
/* Charging Downstream Port */
CHGTYP_CDP = 0x02,
/* Dedicated Charger (D+/D- shorted) */
CHGTYP_DEDICATED_CHARGER = 0x03,
/* Special 500mA charger, max current 500mA */
CHGTYP_500MA = 0x04,
/* Special 1A charger, max current 1A */
CHGTYP_1A = 0x05,
/* Special charger - 3.3V bias on D+/D- */
CHGTYP_SPECIAL_3_3V_CHARGER = 0x06,
/* Reserved */
CHGTYP_RFU = 0x07,
/* Any charger w/o USB */
CHGTYP_ANY_CHARGER = 0xfc,
/* Any charger type */
CHGTYP_ANY = 0xfd,
/* Don't care charger type */
CHGTYP_DONTCARE = 0xfe,
CHGTYP_MAX,
CHGTYP_INIT,
CHGTYP_MIN = CHGTYP_NO_VOLTAGE
} chgtyp_t;
/* muic register value for COMN1, COMN2 in CTRL1 reg */
/*
* MAX77804K CONTROL1 register
* ID Bypass [7] / Mic En [6] / D+ [5:3] / D- [2:0]
* 0: ID Bypass Open / 1: IDB connect to UID
* 0: Mic En Open / 1: Mic connect to VB
* 000: Open / 001: USB / 010: Audio / 011: UART
*/
enum max77804k_reg_ctrl1_val {
MAX77804K_MUIC_CTRL1_ID_OPEN = 0x0,
MAX77804K_MUIC_CTRL1_ID_BYPASS = 0x1,
MAX77804K_MUIC_CTRL1_COM_OPEN = 0x00,
MAX77804K_MUIC_CTRL1_COM_USB = 0x01,
MAX77804K_MUIC_CTRL1_COM_AUDIO = 0x02,
MAX77804K_MUIC_CTRL1_COM_UART = 0x03,
MAX77804K_MUIC_CTRL1_COM_USB_CP = 0x04,
MAX77804K_MUIC_CTRL1_COM_UART_CP = 0x05,
};
typedef enum {
CTRL1_OPEN = (MAX77804K_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77804K_MUIC_CTRL1_COM_OPEN << COMP2SW_SHIFT) | \
(MAX77804K_MUIC_CTRL1_COM_OPEN << COMN1SW_SHIFT),
CTRL1_USB = (MAX77804K_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77804K_MUIC_CTRL1_COM_USB << COMP2SW_SHIFT) | \
(MAX77804K_MUIC_CTRL1_COM_USB << COMN1SW_SHIFT),
CTRL1_AUDIO = (MAX77804K_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77804K_MUIC_CTRL1_COM_AUDIO << COMP2SW_SHIFT) | \
(MAX77804K_MUIC_CTRL1_COM_AUDIO << COMN1SW_SHIFT),
CTRL1_UART = (MAX77804K_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77804K_MUIC_CTRL1_COM_UART << COMP2SW_SHIFT) | \
(MAX77804K_MUIC_CTRL1_COM_UART << COMN1SW_SHIFT),
CTRL1_USB_CP = (MAX77804K_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77804K_MUIC_CTRL1_COM_USB_CP << COMP2SW_SHIFT) | \
(MAX77804K_MUIC_CTRL1_COM_USB_CP << COMN1SW_SHIFT),
CTRL1_UART_CP = (MAX77804K_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77804K_MUIC_CTRL1_COM_UART_CP << COMP2SW_SHIFT) | \
(MAX77804K_MUIC_CTRL1_COM_UART_CP << COMN1SW_SHIFT),
} max77804k_reg_ctrl1_t;
enum {
MAX77804K_MUIC_CTRL4_ADCMODE_ALWAYS_ON = 0x00,
MAX77804K_MUIC_CTRL4_ADCMODE_ALWAYS_ON_1M_MON = 0x01,
MAX77804K_MUIC_CTRL4_ADCMODE_ONE_SHOT = 0x02,
MAX77804K_MUIC_CTRL4_ADCMODE_2S_PULSE = 0x03
};
extern struct device *switch_device;
#endif /* __MAX77804K_MUIC_H__ */

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/*
* max77828-muic.h - MUIC for the Maxim 77828
*
* Copyright (C) 2011 Samsung Electrnoics
* Seoyoung Jeong <seo0.jeong@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* This driver is based on max14577-muic.h
*
*/
#ifndef __MAX77828_MUIC_H__
#define __MAX77828_MUIC_H__
#define MUIC_DEV_NAME "muic-max77828"
/* max77828 muic register read/write related information defines. */
/* MAX77828 REGISTER ENABLE or DISABLE bit */
enum max77828_reg_bit_control {
MAX77828_DISABLE_BIT = 0,
MAX77828_ENABLE_BIT,
};
/* MAX77828 STATUS1 register */
#define STATUS1_ADC_SHIFT 0
#define STATUS1_ADCERR_SHIFT 6
#define STATUS1_ADC1K_SHIFT 7
#define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
#define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
#define STATUS1_ADC1K_MASK (0x1 << STATUS1_ADC1K_SHIFT)
/* MAX77828 STATUS2 register */
#define STATUS2_CHGTYP_SHIFT 0
#define STATUS2_CHGDETRUN_SHIFT 3
#define STATUS2_DCDTMR_SHIFT 4
#define STATUS2_DXOVP_SHIFT 5
#define STATUS2_VBVOLT_SHIFT 6
#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
#define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
#define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT)
#define STATUS2_DXOVP_MASK (0x1 << STATUS2_DXOVP_SHIFT)
#define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
/* MAX77828 CDETCTRL1 register */
#define CHGDETEN_SHIFT 0
#define CHGTYPM_SHIFT 1
#define CDDELAY_SHIFT 4
#define CHGDETEN_MASK (0x1 << CHGDETEN_SHIFT)
#define CHGTYPM_MASK (0x1 << CHGTYPM_SHIFT)
#define CDDELAY_MASK (0x1 << CDDELAY_SHIFT)
/* MAX77828 CONTROL1 register */
#define COMN1SW_SHIFT 0
#define COMP2SW_SHIFT 3
#define IDBEN_SHIFT 7
#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
#define IDBEN_MASK (0x1 << IDBEN_SHIFT)
#define CLEAR_IDBEN_RSVD_MASK (COMN1SW_MASK | COMP2SW_MASK)
/* MAX77828 CONTROL2 register */
#define CTRL2_LOWPWR_SHIFT 0
#define CTRL2_CPEN_SHIFT 2
#define CTRL2_ACCDET_SHIFT 5
#define CTRL2_LOWPWR_MASK (0x1 << CTRL2_LOWPWR_SHIFT)
#define CTRL2_CPEN_MASK (0x1 << CTRL2_CPEN_SHIFT)
#define CTRL2_ACCDET_MASK (0x1 << CTRL2_ACCDET_SHIFT)
#define CTRL2_CPEN1_LOWPWD0 ((MAX77828_ENABLE_BIT << CTRL2_CPEN_SHIFT) | \
(MAX77828_DISABLE_BIT << CTRL2_ADCLOWPWR_SHIFT))
#define CTRL2_CPEN0_LOWPWD1 ((MAX77828_DISABLE_BIT << CTRL2_CPEN_SHIFT) | \
(MAX77828_ENABLE_BIT << CTRL2_ADCLOWPWR_SHIFT))
/* MAX77828 CONTROL3 register */
#define CTRL3_JIGSET_SHIFT 0
#define CTRL3_JIGSET_MASK (0x3 << CTRL3_JIGSET_SHIFT)
/* MAX77828 CONTROL4 register */
#define CTRL4_ADCDBSET_SHIFT 0
#define CTRL4_ADCMODE_SHIFT 6
#define CTRL4_ADCDBSET_MASK (0x3 << CTRL4_ADCDBSET_SHIFT)
#define CTRL4_ADCMODE_MASK (0x3 << CTRL4_ADCMODE_SHIFT)
/* MAX77828 MUIC support for device tree */
struct of_max77828_muic_support {
bool notifier;
bool otg_dongle;
};
typedef enum {
VB_LOW = 0x00,
VB_HIGH = (0x1 << STATUS2_VBVOLT_SHIFT),
VB_DONTCARE = 0xff,
} vbvolt_t;
typedef enum {
CHGDETRUN_FALSE = 0x00,
CHGDETRUN_TRUE = (0x1 << STATUS2_CHGDETRUN_SHIFT),
CHGDETRUN_DONTCARE = 0xff,
} chgdetrun_t;
/* MAX77804 MUIC Output of USB Charger Detection */
typedef enum {
/* No Valid voltage at VB (Vvb < Vvbdet) */
CHGTYP_NO_VOLTAGE = 0x00,
/* Unknown (D+/D- does not present a valid USB charger signature) */
CHGTYP_USB = 0x01,
/* Charging Downstream Port */
CHGTYP_CDP = 0x02,
/* Dedicated Charger (D+/D- shorted) */
CHGTYP_DEDICATED_CHARGER = 0x03,
/* Special 500mA charger, max current 500mA */
CHGTYP_500MA = 0x04,
/* Special 1A charger, max current 1A */
CHGTYP_1A = 0x05,
/* Special charger - 3.3V bias on D+/D- */
CHGTYP_SPECIAL_3_3V_CHARGER = 0x06,
/* Reserved */
CHGTYP_RFU = 0x07,
/* Any charger type */
CHGTYP_ANY = 0xfd,
/* Don't care charger type */
CHGTYP_DONTCARE = 0xfe,
CHGTYP_MAX,
CHGTYP_INIT,
CHGTYP_MIN = CHGTYP_NO_VOLTAGE
} chgtyp_t;
/* muic register value for COMN1, COMN2 in CTRL1 reg */
/*
* MAX77828 CONTROL1 register
* ID Bypass [7] / Mic En [6] / D+ [5:3] / D- [2:0]
* 0: ID Bypass Open / 1: IDB connect to UID
* 0: Mic En Open / 1: Mic connect to VB
* 000: Open / 001: USB / 010: Audio / 011: UART
*/
enum max77828_reg_ctrl1_val {
MAX77828_MUIC_CTRL1_ID_OPEN = 0x0,
MAX77828_MUIC_CTRL1_ID_BYPASS = 0x1,
MAX77828_MUIC_CTRL1_COM_OPEN = 0x00,
MAX77828_MUIC_CTRL1_COM_USB = 0x01,
MAX77828_MUIC_CTRL1_COM_AUDIO = 0x02,
MAX77828_MUIC_CTRL1_COM_UART = 0x03,
MAX77828_MUIC_CTRL1_COM_USB_CP = 0x04,
MAX77828_MUIC_CTRL1_COM_UART_CP = 0x05,
};
typedef enum {
CTRL1_OPEN = (MAX77828_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77828_MUIC_CTRL1_COM_OPEN << COMP2SW_SHIFT) | \
(MAX77828_MUIC_CTRL1_COM_OPEN << COMN1SW_SHIFT),
CTRL1_USB = (MAX77828_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77828_MUIC_CTRL1_COM_USB << COMP2SW_SHIFT) | \
(MAX77828_MUIC_CTRL1_COM_USB << COMN1SW_SHIFT),
CTRL1_AUDIO = (MAX77828_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77828_MUIC_CTRL1_COM_AUDIO << COMP2SW_SHIFT) | \
(MAX77828_MUIC_CTRL1_COM_AUDIO << COMN1SW_SHIFT),
CTRL1_UART = (MAX77828_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77828_MUIC_CTRL1_COM_UART << COMP2SW_SHIFT) | \
(MAX77828_MUIC_CTRL1_COM_UART << COMN1SW_SHIFT),
CTRL1_USB_CP = (MAX77828_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77828_MUIC_CTRL1_COM_USB_CP << COMP2SW_SHIFT) | \
(MAX77828_MUIC_CTRL1_COM_USB_CP << COMN1SW_SHIFT),
CTRL1_UART_CP = (MAX77828_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77828_MUIC_CTRL1_COM_UART_CP << COMP2SW_SHIFT) | \
(MAX77828_MUIC_CTRL1_COM_UART_CP << COMN1SW_SHIFT),
} max77828_reg_ctrl1_t;
extern struct device *switch_device;
#endif /* __MAX77828_MUIC_H__ */

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/*
* max77833-muic-hv-typedef.h - MUIC for the Maxim 77833
*
* Copyright (C) 2011 Samsung Electrnoics
* Seoyoung Jeong <seo0.jeong@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* This driver is based on max77833-muic.h
*
*/
#ifndef __MAX77833_MUIC_HV_TYPEDEF_H__
#define __MAX77833_MUIC_HV_TYPEDEF_H__
/* MUIC afc irq type */
typedef enum {
MUIC_AFC_IRQ_VDNMON = 0,
MUIC_AFC_IRQ_MRXRDY,
MUIC_AFC_IRQ_VBADC,
MUIC_AFC_IRQ_MPNACK,
MUIC_AFC_IRQ_DONTCARE = 0xff,
} muic_afc_irq_t;
/* muic chip specific internal data structure */
typedef struct max77833_muic_afc_data {
muic_attached_dev_t new_dev;
const char *afc_name;
muic_afc_irq_t afc_irq;
u8 hvcontrol1_dpdnvden;
u8 status3_vbadc;
u8 status3_vdnmon;
int function_num;
struct max77833_muic_afc_data *next;
} muic_afc_data_t;
#endif /* __MAX77833_MUIC_HV_TYPEDEF_H__ */

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/*
* max77833-muic-hv.h - MUIC for the Maxim 77833
*
* Copyright (C) 2015 Samsung Electrnoics
* Insun Choi <insun77.choi@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* This driver is based on max77833-muic.h
*
*/
#ifndef __MAX77833_MUIC_HV_H__
#define __MAX77833_MUIC_HV_H__
#define MUIC_HV_DEV_NAME "muic-max77833-hv"
#define HV_CMD_PASS 0
typedef enum max77833_muic_hv_set_value {
QC_SET_9V = 0x09,
FCHV_SET_9V = 0x46,
FCHV_SET_POWERPACK = 0x24,
} muic_hv_set_val;
typedef enum max77833_muic_hv_enable_value {
MPING_5TIMES = 0x00,
MPING_ALWAYS = 0x02,
} muic_hv_enable_val;
extern void max77833_muic_set_afc_ready(struct max77833_muic_data *muic_data, bool value);
extern void max77833_muic_hv_fchv_disable_set(struct max77833_muic_data *muic_data);
extern void max77833_muic_hv_qc_disable_set(struct max77833_muic_data *muic_data);
extern void max77833_muic_hv_qc_enable(struct max77833_muic_data *muic_data);
extern void max77833_muic_hv_qc_disable(struct max77833_muic_data *muic_data);
extern void max77833_muic_hv_qc_autoset(struct max77833_muic_data *muic_data, u8 val, u8 mask);
extern void max77833_muic_hv_fchv_enable(struct max77833_muic_data *muic_data, u8 val, u8 mask);
extern void max77833_muic_hv_fchv_disable(struct max77833_muic_data *muic_data);
extern void max77833_muic_hv_fchv_set(struct max77833_muic_data *muic_data, u8 val, u8 mask);
extern void max77833_muic_hv_fchv_capa_read(struct max77833_muic_data *muic_data);
extern void max77833_muic_hv_chgin_read(struct max77833_muic_data *muic_data);
#endif /* __MAX77833_MUIC_HV_H__ */

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/*
* max77833-muic.h - MUIC for the Maxim 77833
*
* Copyright (C) 2015 Samsung Electrnoics
* Insun Choi <insun77.choi@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* This driver is based on max14577-muic.h
*
*/
#ifndef __MAX77833_MUIC_H__
#define __MAX77833_MUIC_H__
#define MUIC_DEV_NAME "muic-max77833"
#define MUIC_PASS4 (0x05)
enum max77833_muic_command_rw {
COMMAND_READ = 0,
COMMAND_WRITE = 1,
};
typedef enum {
MAX77833_ADC_GND = 0x00,
MAX77833_ADC_1K = 0x10, /* 0x010000 1K ohm */
MAX77833_ADC_SEND_END = 0x11, /* 0x010001 2K ohm */
MAX77833_ADC_2_604K = 0x12, /* 0x010010 2.604K ohm */
MAX77833_ADC_3_208K = 0x13, /* 0x010011 3.208K ohm */
MAX77833_ADC_4_014K = 0x14, /* 0x010100 4.014K ohm */
MAX77833_ADC_4_820K = 0x15, /* 0x010101 4.820K ohm */
MAX77833_ADC_6_030K = 0x16, /* 0x010110 6.030K ohm */
MAX77833_ADC_8_030K = 0x17, /* 0x010111 8.030K ohm */
MAX77833_ADC_10_030K = 0x18, /* 0x011000 10.030K ohm */
MAX77833_ADC_12_030K = 0x19, /* 0x011001 12.030K ohm */
MAX77833_ADC_14_460K = 0x1a, /* 0x011010 14.460K ohm */
MAX77833_ADC_17_260K = 0x1b, /* 0x011011 17.260K ohm */
MAX77833_ADC_REMOTE_S11 = 0x1c, /* 0x011100 20.5K ohm */
MAX77833_ADC_REMOTE_S12 = 0x1d, /* 0x011101 24.07K ohm */
MAX77833_ADC_RESERVED_VZW = 0x1e, /* 0x011110 28.7K ohm */
MAX77833_ADC_INCOMPATIBLE_VZW = 0x1f, /* 0x011111 34K ohm */
MAX77833_ADC_SMARTDOCK = 0x20, /* 0x100000 40.2K ohm */
MAX77833_ADC_HMT = 0x21, /* 0x100001 49.9K ohm */
MAX77833_ADC_AUDIODOCK = 0x22, /* 0x100010 64.9K ohm */
MAX77833_ADC_USB_LANHUB = 0x23, /* 0x100011 80.07K ohm */
MAX77833_ADC_CHARGING_CABLE = 0x24, /* 0x100100 102K ohm */
MAX77833_ADC_UNIVERSAL_MMDOCK = 0x25, /* 0x100101 121K ohm */
MAX77833_ADC_UART_CABLE = 0x26, /* 0x100110 150K ohm */
MAX77833_ADC_CEA936ATYPE1_CHG = 0x27, /* 0x100111 200K ohm */
MAX77833_ADC_JIG_USB_OFF = 0x28, /* 0x101000 255K ohm */
MAX77833_ADC_JIG_USB_ON = 0x29, /* 0x101001 301K ohm */
MAX77833_ADC_DESKDOCK = 0x2a, /* 0x101010 365K ohm */
MAX77833_ADC_CEA936ATYPE2_CHG = 0x2b, /* 0x101011 442K ohm */
MAX77833_ADC_JIG_UART_OFF = 0x2c, /* 0x101100 523K ohm */
MAX77833_ADC_JIG_UART_ON = 0x2d, /* 0x101101 619K ohm */
MAX77833_ADC_AUDIOMODE_W_REMOTE = 0x2e, /* 0x101110 1000K ohm */
MAX77833_ADC_OPEN = 0x2f,
MAX77833_ADC_OPEN_219 = 0xfb, /* ADC open or 219.3K ohm */
MAX77833_ADC_219 = 0xfc, /* ADC open or 219.3K ohm */
MAX77833_ADC_UNDEFINED = 0xfd, /* Undefied range */
MAX77833_ADC_DONTCARE = 0xfe, /* ADC don't care for MHL */
MAX77833_ADC_ERROR = 0xff, /* ADC value read error */
} max77833_adc_t;
typedef enum max77833_muic_command_opcode {
COMMAND_CONFIG_READ = 0x01,
COMMAND_CONFIG_WRITE = 0x02,
COMMAND_SWITCH_READ = 0x03,
COMMAND_SWITCH_WRITE = 0x04,
COMMAND_SYSMSG_READ = 0x05,
COMMAND_CHGDET_READ = 0x12,
COMMAND_MONITOR_READ = 0x21,
COMMAND_MONITOR_WRITE = 0x22,
#if defined(CONFIG_HV_MUIC_MAX77833_AFC)
COMMAND_QC_DISABLE_READ = 0x31,
COMMAND_QC_ENABLE_READ = 0x32,
COMMAND_QC_AUTOSET_WRITE = 0x34,
COMMAND_AFC_DISABLE_READ = 0x41,
COMMAND_AFC_ENABLE_READ = 0x42,
COMMAND_AFC_SET_WRITE = 0x43,
COMMAND_AFC_CAPA_READ = 0x44,
#endif
COMMAND_CHGIN_READ = 0x51,
/* not cmd opcode, for notifier */
NOTI_ATTACH = 0xfa,
NOTI_DETACH = 0xfb,
NOTI_LOGICALLY_ATTACH = 0xfc,
NOTI_LOGICALLY_DETACH = 0xfd,
COMMAND_NONE = 0xff,
} muic_cmd_opcode;
#define CMD_Q_SIZE 8
typedef struct max77833_muic_command_data {
muic_cmd_opcode opcode;
u8 response;
u8 read_data;
u8 write_data;
u8 reg;
u8 val;
u8 mask;
muic_attached_dev_t noti_dev;
} muic_cmd_data;
typedef struct max77833_muic_command_node {
muic_cmd_data cmd_data;
struct max77833_muic_command_node *next;
} muic_cmd_node;
typedef struct max77833_muic_command_node* muic_cmd_node_p;
typedef struct max77833_muic_command_queue {
struct mutex command_mutex;
muic_cmd_node *front;
muic_cmd_node *rear;
muic_cmd_node tmp_cmd_node;
// int count;
} cmd_queue_t;
typedef struct max77833_muic_data muic_data_t;
/* muic chip specific internal data structure */
struct max77833_muic_data {
struct device *dev;
struct i2c_client *i2c; /* i2c addr: 0x4A; MUIC */
struct mutex muic_mutex;
struct mutex reset_mutex;
struct mutex command_mutex;
/* muic command data */
cmd_queue_t muic_cmd_queue;
/* model dependant mfd platform data */
struct max77833_platform_data *mfd_pdata;
int irq_idres;
int irq_chgtyp;
// int irq_chgtyprun;
int irq_sysmsg;
int irq_apcmdres;
/* model dependant muic platform data */
struct muic_platform_data *pdata;
/* muic current attached device */
muic_attached_dev_t attached_dev;
void *attached_func;
/* muic support vps list */
bool muic_support_list[ATTACHED_DEV_NUM];
bool is_muic_ready;
bool is_muic_reset;
u8 adcmode;
// bool ignore_adcerr; // CHECK ME!!!
/* check is otg test */
bool is_otg_test;
/* muic HV charger */
bool is_factory_start;
bool is_check_hv;
bool is_charger_ready;
u8 is_boot_dpdnvden;
/* muic status value */
u8 status1;
u8 status2;
u8 status3;
u8 status4;
u8 status5;
u8 status6;
};
/* max77833 muic register read/write related information defines. */
#define REG_NONE 0xff
#define REG_FULL_MASKING 0xff
/* MAX77833 REGISTER ENABLE or DISABLE bit */
enum max77833_reg_bit_control {
MAX77833_DISABLE_BIT = 0,
MAX77833_ENABLE_BIT,
};
/* MAX77833 STATUS1 register */
#define STATUS1_IDRES_SHIFT 0
#define STATUS1_IDRES_MASK (0xff << STATUS1_IDRES_SHIFT)
/* MAX77833 STATUS2 register */
#define STATUS2_CHGTYP_SHIFT 0
#define STATUS2_SPCHGTYP_SHIFT 3
#define STATUS2_CHGTYPRUN_SHIFT 7
#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
#define STATUS2_SPCHGTYP_MASK (0x7 << STATUS2_SPCHGTYP_SHIFT)
#define STATUS2_CHGTYPRUN_MASK (0x1 << STATUS2_CHGTYPRUN_SHIFT)
/* MAX77833 STATUS3 register - include ERROR message. */
#define STATUS3_SYSMSG_SHIFT 0
#define STATUS3_SYSMSG_MASK (0xff << STATUS3_SYSMSG_SHIFT)
/* MAX77833 DAT_IN register */
#define DAT_IN_SHIFT 0
#define DAT_IN_MASK (0xff << DAT_IN_SHIFT)
/* MAX77833 DAT_OUT register */
#define DAT_OUT_SHIFT 0
#define DAT_OUT_MASK (0xff << DAT_OUT_SHIFT)
/* MAX77833 CONFIG COMMAND */
#define JIGSET_SHIFT 0
#define SFOUT_SHIFT 2
#define IDMONEN_SHIFT 6
#define CHGDETEN_SHIFT 7
#define JIGSET_MASK (0x3 << JIGSET_SHIFT)
#define SFOUT_MASK (0x3 << SFOUT_SHIFT)
#define IDMONEN_MASK (0x1 << IDMONEN_SHIFT)
#define CHGDETEN_MASK (0x1 << CHGDETEN_SHIFT)
/* MAX77833 SWITCH COMMAND */
#define COMN1SW_SHIFT 0
#define COMP2SW_SHIFT 3
#define RCPS_SHIFT 6
#define IDBEN_SHIFT 7
#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
#define RCPS_MASK (0x1 << RCPS_SHIFT)
#define IDBEN_MASK (0x1 << IDBEN_SHIFT)
//#define CLEAR_IDBEN_RSVD_MASK (COMN1SW_MASK | COMP2SW_MASK) // ??
/* MAX77833 ID Monitor Config */
#define MODE_SHIFT 2
#define MODE_MASK (0x3 << MODE_SHIFT)
typedef enum {
CHGDET_ENABLE = 0xfc,
CHGDET_DISABLE = 0x7c,
} chgdetcon_t;
typedef enum {
CHGDETRUN_FALSE = 0x00,
CHGDETRUN_TRUE = (0x1 << STATUS2_CHGTYPRUN_SHIFT),
CHGDETRUN_DONTCARE = 0xff,
} chgdetrun_t;
/* MAX77833 MUIC Charger Type Detection Output Value */
typedef enum {
/* No Valid voltage at VB (Vvb < Vvbdet) */
CHGTYP_NO_VOLTAGE = 0x00,
/* Unknown (D+/D- does not present a valid USB charger signature) */
CHGTYP_USB = 0x01,
/* Charging Downstream Port */
CHGTYP_CDP = 0x02,
/* Dedicated Charger (D+/D- shorted) */
CHGTYP_DEDICATED_CHARGER = 0x03,
/* DCD Timeout, Open D+/D- */
CHGTYP_TIMEOUT_OPEN = 0x04,
/* Abort Vbus present but Charge Detection halted */
CHGTYP_HALT = 0x05,
/* Reserved for Future Use */
CHGTYP_RFU_1 = 0x06,
CHGTYP_RFU_2 = 0x07,
/* Any charger w/o USB */
CHGTYP_UNOFFICIAL_CHARGER = 0xfc,
/* Any charger type */
CHGTYP_ANY = 0xfd,
/* Don't care charger type */
CHGTYP_DONTCARE = 0xfe,
CHGTYP_MAX,
CHGTYP_INIT,
CHGTYP_MIN = CHGTYP_NO_VOLTAGE
} chgtyp_t;
/* MAX77833 MUIC Special Charger Type Detection Output value */
typedef enum {
SPCHGTYP_UNKNOWN = 0x00,
SPCHGTYP_SAMSUNG_2A = 0x01,
SPCHGTYP_APPLE_500MA = 0x02,
SPCHGTYP_APPLE_1A = 0x03,
SPCHGTYP_APPLE_2A = 0x04,
SPCHGTYP_APPLE_12W = 0x05,
SPCHGTYP_GENERIC_500MA = 0x06,
SPCHGTYP_RFU = 0x07,
} spchgtyp_t;
typedef enum {
PROCESS_ATTACH = 0,
PROCESS_LOGICALLY_DETACH,
PROCESS_NONE,
} process_t;
/* muic register value for COMN1, COMN2 in Switch command */
/*
* MAX77833 Switch command
* ID Bypass [7] / Mic En [6] / D+ [5:3] / D- [2:0]
* 0: ID Bypass Open / 1: IDB connect to UID
* 0: Mic En Open / 1: Mic connect to VB
* 111: Open / 001: USB / 010(enable),011(disable): Audio / 100: UART
*/
enum max77833_switch_command_val {
MAX77833_MUIC_SWITCH_CMD_ID_OPEN = 0x0,
MAX77833_MUIC_SWITCH_CMD_ID_BYPASS = 0x1,
MAX77833_MUIC_SWITCH_CMD_RCPS_DIS = 0x0,
MAX77833_MUIC_SWITCH_CMD_RCPS_EN = 0x1,
MAX77833_MUIC_SWITCH_CMD_COM_USB = 0x01,
MAX77833_MUIC_SWITCH_CMD_COM_AUDIO_ON = 0x02,
MAX77833_MUIC_SWITCH_CMD_COM_AUDIO_OFF = 0x03,
MAX77833_MUIC_SWITCH_CMD_COM_UART = 0x04,
MAX77833_MUIC_SWITCH_CMD_COM_USB_CP = 0x05,
MAX77833_MUIC_SWITCH_CMD_COM_UART_CP = 0x06,
MAX77833_MUIC_SWITCH_CMD_COM_OPEN = 0x07,
};
typedef enum {
COM_OPEN = (MAX77833_MUIC_SWITCH_CMD_ID_OPEN << IDBEN_SHIFT) | \
(MAX77833_MUIC_SWITCH_CMD_RCPS_DIS << RCPS_SHIFT) | \
(MAX77833_MUIC_SWITCH_CMD_COM_OPEN << COMP2SW_SHIFT) | \
(MAX77833_MUIC_SWITCH_CMD_COM_OPEN << COMN1SW_SHIFT),
COM_USB = (MAX77833_MUIC_SWITCH_CMD_ID_OPEN << IDBEN_SHIFT) | \
(MAX77833_MUIC_SWITCH_CMD_RCPS_DIS << RCPS_SHIFT) | \
(MAX77833_MUIC_SWITCH_CMD_COM_USB << COMP2SW_SHIFT) | \
(MAX77833_MUIC_SWITCH_CMD_COM_USB << COMN1SW_SHIFT),
#if 0
COM_AUDIO = (MAX77833_MUIC_SWITCH_CMD_ID_OPEN << IDBEN_SHIFT) | \
(MAX77833_MUIC_SWITCH_CMD_RCPS_DIS << RCPS_SHIFT) | \
(MAX77833_MUIC_SWITCH_CMD_COM_AUDIO_ON << COMP2SW_SHIFT) | \
(MAX77833_MUIC_SWITCH_CMD_COM_AUDIO_ON << COMN1SW_SHIFT),
#endif
COM_UART = (MAX77833_MUIC_SWITCH_CMD_ID_OPEN << IDBEN_SHIFT) | \
(MAX77833_MUIC_SWITCH_CMD_RCPS_DIS << RCPS_SHIFT) | \
(MAX77833_MUIC_SWITCH_CMD_COM_UART << COMP2SW_SHIFT) | \
(MAX77833_MUIC_SWITCH_CMD_COM_UART << COMN1SW_SHIFT),
COM_USB_CP = (MAX77833_MUIC_SWITCH_CMD_ID_OPEN << IDBEN_SHIFT) | \
(MAX77833_MUIC_SWITCH_CMD_RCPS_DIS << RCPS_SHIFT) | \
(MAX77833_MUIC_SWITCH_CMD_COM_USB_CP << COMP2SW_SHIFT) | \
(MAX77833_MUIC_SWITCH_CMD_COM_USB_CP << COMN1SW_SHIFT),
COM_UART_CP = (MAX77833_MUIC_SWITCH_CMD_ID_OPEN << IDBEN_SHIFT) | \
(MAX77833_MUIC_SWITCH_CMD_RCPS_DIS << RCPS_SHIFT) | \
(MAX77833_MUIC_SWITCH_CMD_COM_UART_CP << COMP2SW_SHIFT) | \
(MAX77833_MUIC_SWITCH_CMD_COM_UART_CP << COMN1SW_SHIFT),
COM_USB_DOCK = (MAX77833_MUIC_SWITCH_CMD_ID_OPEN << IDBEN_SHIFT) | \
/* (MAX77833_MUIC_SWITCH_CMD_RCPS_DIS << RCPS_SHIFT) | \ */
(MAX77833_MUIC_SWITCH_CMD_COM_USB << COMP2SW_SHIFT) | \
(MAX77833_MUIC_SWITCH_CMD_COM_USB << COMN1SW_SHIFT),
} max77833_switch_cmd_t;
enum {
MAX77833_MUIC_IDMODE_CONTINUOUS = 0x3,
MAX77833_MUIC_IDMODE_FACTORY_ONE_SHOT = 0x2,
MAX77833_MUIC_IDMODE_ONE_SHOT = 0x1,
MAX77833_MUIC_IDMODE_PULSE = 0x0,
MAX77833_MUIC_IDMODE_NONE = 0xf,
};
extern struct device *switch_device;
extern void init_muic_cmd_data(muic_cmd_data *cmd_data);
extern void enqueue_muic_cmd(cmd_queue_t *muic_cmd_queue, muic_cmd_data cmd_data);
#endif /* __MAX77833_MUIC_H__ */

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/*
* max77843-muic-hv-typedef.h - MUIC for the Maxim 77843
*
* Copyright (C) 2011 Samsung Electrnoics
* Seoyoung Jeong <seo0.jeong@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* This driver is based on max77843-muic.h
*
*/
#ifndef __MAX77843_MUIC_HV_TYPEDEF_H__
#define __MAX77843_MUIC_HV_TYPEDEF_H__
/* MUIC afc irq type */
typedef enum {
MUIC_AFC_IRQ_VDNMON = 0,
MUIC_AFC_IRQ_MRXRDY,
MUIC_AFC_IRQ_VBADC,
MUIC_AFC_IRQ_MPNACK,
MUIC_AFC_IRQ_DONTCARE = 0xff,
} muic_afc_irq_t;
/* muic chip specific internal data structure */
typedef struct max77843_muic_afc_data {
muic_attached_dev_t new_dev;
const char *afc_name;
muic_afc_irq_t afc_irq;
u8 hvcontrol1_dpdnvden;
u8 status3_vbadc;
u8 status3_vdnmon;
int function_num;
struct max77843_muic_afc_data *next;
} muic_afc_data_t;
#endif /* __MAX77843_MUIC_HV_TYPEDEF_H__ */

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/*
* max77843-muic-hv.h - MUIC for the Maxim 77843
*
* Copyright (C) 2011 Samsung Electrnoics
* Seoyoung Jeong <seo0.jeong@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* This driver is based on max77843-muic.h
*
*/
#ifndef __MAX77843_MUIC_HV_H__
#define __MAX77843_MUIC_HV_H__
#define MUIC_HV_DEV_NAME "muic-max77843-hv"
/* MAX77828 INTMASK3 register */
#define INTMASK3_VBADCM_SHIFT 0
#define INTMASK3_VDNMONM_SHIFT 1
#define INTMASK3_DNRESM_SHIFT 2
#define INTMASK3_MPNACKM_SHIFT 3
#define INTMASK3_MRXBUFOWM_SHIFT 4
#define INTMASK3_MRXTRFM_SHIFT 5
#define INTMASK3_MRXPERRM_SHIFT 6
#define INTMASK3_MRXRDYM_SHIFT 7
#define INTMASK3_VBADCM_MASK (MAX77843_ENABLE_BIT << INTMASK3_VBADCM_SHIFT)
#define INTMASK3_VDNMONM_MASK (MAX77843_ENABLE_BIT << INTMASK3_VDNMONM_SHIFT)
#define INTMASK3_DNRESM_MASK (MAX77843_ENABLE_BIT << INTMASK3_DNRESM_SHIFT)
#define INTMASK3_MPNACKM_MASK (MAX77843_ENABLE_BIT << INTMASK3_MPNACKM_SHIFT)
#define INTMASK3_MRXBUFOWM_MASK (MAX77843_ENABLE_BIT << INTMASK3_MRXBUFOWM_SHIFT)
#define INTMASK3_MRXTRFM_MASK (MAX77843_ENABLE_BIT << INTMASK3_MRXTRFM_SHIFT)
#define INTMASK3_MRXPERRM_MASK (MAX77843_ENABLE_BIT << INTMASK3_MRXPERRM_SHIFT)
#define INTMASK3_MRXRDYM_MASK (MAX77843_ENABLE_BIT << INTMASK3_MRXRDYM_SHIFT)
/* MAX77843 HVCONTROL1 register */
#define HVCONTROL1_DPDNVDEN_SHIFT 0
#define HVCONTROL1_DNVD_SHIFT 1
#define HVCONTROL1_DPVD_SHIFT 3
#define HVCONTROL1_VBUSADCEN_SHIFT 5
#define HVCONTROL1_DPDNVDEN_MASK (0x1 << HVCONTROL1_DPDNVDEN_SHIFT)
#define HVCONTROL1_DNVD_MASK (0x3 << HVCONTROL1_DNVD_SHIFT)
#define HVCONTROL1_DPVD_MASK (0x3 << HVCONTROL1_DPVD_SHIFT)
#define HVCONTROL1_VBUSADCEN_MASK (0x1 << HVCONTROL1_VBUSADCEN_SHIFT)
/* MAX77843 STATUS3 register */
#define STATUS3_VBADC_SHIFT 0
#define STATUS3_VDNMON_SHIFT 4
#define STATUS3_DNRES_SHIFT 5
#define STATUS3_MPNACK_SHIFT 6
#define STATUS3_VBADC_MASK (0xf << STATUS3_VBADC_SHIFT)
#define STATUS3_VDNMON_MASK (0x1 << STATUS3_VDNMON_SHIFT)
#define STATUS3_DNRES_MASK (0x1 << STATUS3_DNRES_SHIFT)
#define STATUS3_MPNACK_MASK (0x1 << STATUS3_MPNACK_SHIFT)
/* MAX77843 HVCONTROL2 register */
#define HVCONTROL2_HVDIGEN_SHIFT 0
#define HVCONTROL2_DP06EN_SHIFT 1
#define HVCONTROL2_DNRESEN_SHIFT 2
#define HVCONTROL2_MPING_SHIFT 3
#define HVCONTROL2_MTXEN_SHIFT 4
#define HVCONTROL2_MTXBUSRES_SHIFT 5
#define HVCONTROL2_MPNGENB_SHIFT 6
#define HVCONTROL2_HVDIGEN_MASK (0x1 << HVCONTROL2_HVDIGEN_SHIFT)
#define HVCONTROL2_DP06EN_MASK (0x1 << HVCONTROL2_DP06EN_SHIFT)
#define HVCONTROL2_DNRESEN_MASK (0x1 << HVCONTROL2_DNRESEN_SHIFT)
#define HVCONTROL2_MPING_MASK (0x1 << HVCONTROL2_MPING_SHIFT)
#define HVCONTROL2_MTXEN_MASK (0x1 << HVCONTROL2_MTXEN_SHIFT)
#define HVCONTROL2_MTXBUSRES_MASK (0x1 << HVCONTROL2_MTXBUSRES_SHIFT)
#define HVCONTROL2_MPNGENB_MASK (0x1 << HVCONTROL2_MPNGENB_SHIFT)
/* MAX77843 HVRXBYTE register */
#define HVRXBYTE_MAX 16
/* MAX77843 AFC charger W/A Check NUM */
#define AFC_CHARGER_WA_PING 3
typedef enum {
DPDNVDEN_DISABLE = 0x00,
DPDNVDEN_ENABLE = (0x1 << HVCONTROL1_DPDNVDEN_SHIFT),
DPDNVDEN_DONTCARE = 0xff,
} dpdnvden_t;
typedef enum {
VDNMON_LOW = 0x00,
VDNMON_HIGH = (0x1 << STATUS3_VDNMON_SHIFT),
VDNMON_DONTCARE = 0xff,
} vdnmon_t;
typedef enum {
VBADC_VBDET = 0x00,
VBADC_4V_5V = (0x1 << STATUS3_VBADC_SHIFT),
VBADC_5V_6V = (0x2 << STATUS3_VBADC_SHIFT),
VBADC_6V_7V = (0x3 << STATUS3_VBADC_SHIFT),
VBADC_7V_8V = (0x4 << STATUS3_VBADC_SHIFT),
VBADC_8V_9V = (0x5 << STATUS3_VBADC_SHIFT),
VBADC_9V_10V = (0x6 << STATUS3_VBADC_SHIFT),
VBADC_10V_12V = (0x7 << STATUS3_VBADC_SHIFT),
VBADC_12V_13V = (0x8 << STATUS3_VBADC_SHIFT),
VBADC_13V_14V = (0x9 << STATUS3_VBADC_SHIFT),
VBADC_14V_15V = (0xA << STATUS3_VBADC_SHIFT),
VBADC_15V_16V = (0xB << STATUS3_VBADC_SHIFT),
VBADC_16V_17V = (0xC << STATUS3_VBADC_SHIFT),
VBADC_17V_18V = (0xD << STATUS3_VBADC_SHIFT),
VBADC_18V_19V = (0xE << STATUS3_VBADC_SHIFT),
VBADC_19V = (0xF << STATUS3_VBADC_SHIFT),
VBADC_QC_5V = 0xeb,
VBADC_QC_9V = 0xec,
VBADC_QC_12V = 0xed,
VBADC_QC_20V = 0xee,
VBADC_AFC_5V = 0xfa,
VBADC_AFC_9V = 0xfb,
VBADC_AFC_ERR_V = 0xfc,
VBADC_AFC_ERR_V_NOT_0 = 0xfd,
VBADC_ANY = 0xfe,
VBADC_DONTCARE = 0xff,
} vbadc_t;
enum {
HV_SUPPORT_QC_5V = 5,
HV_SUPPORT_QC_9V = 9,
HV_SUPPORT_QC_12V = 12,
HV_SUPPORT_QC_20V = 20,
};
enum max77843_reg_hv_val {
MAX77843_MUIC_HVCONTROL1_DPVD_06 = (0x2 << HVCONTROL1_DPVD_SHIFT),
MAX77843_MUIC_HVCONTROL1_11 = (MAX77843_MUIC_HVCONTROL1_DPVD_06 | \
HVCONTROL1_DPDNVDEN_MASK),
MAX77843_MUIC_HVCONTROL1_31 = (HVCONTROL1_VBUSADCEN_MASK | \
MAX77843_MUIC_HVCONTROL1_DPVD_06 | \
HVCONTROL1_DPDNVDEN_MASK),
MAX77843_MUIC_HVCONTROL2_06 = (HVCONTROL2_DP06EN_MASK | HVCONTROL2_DNRESEN_MASK),
MAX77843_MUIC_HVCONTROL2_13 = (HVCONTROL2_MTXEN_MASK | HVCONTROL2_DP06EN_MASK | \
HVCONTROL2_HVDIGEN_MASK),
MAX77843_MUIC_HVCONTROL2_1B = (HVCONTROL2_HVDIGEN_MASK | HVCONTROL2_DP06EN_MASK | \
HVCONTROL2_MPING_MASK | HVCONTROL2_MTXEN_MASK),
MAX77843_MUIC_HVCONTROL2_1F = (HVCONTROL2_HVDIGEN_MASK | HVCONTROL2_DP06EN_MASK | \
HVCONTROL2_DNRESEN_MASK | HVCONTROL2_MPING_MASK | HVCONTROL2_MTXEN_MASK),
MAX77843_MUIC_HVCONTROL2_5B = (HVCONTROL2_HVDIGEN_MASK | HVCONTROL2_DP06EN_MASK | \
HVCONTROL2_MPING_MASK | HVCONTROL2_MTXEN_MASK | HVCONTROL2_MPNGENB_MASK),
MAX77843_MUIC_INTMASK3_FB = (INTMASK3_MRXRDYM_MASK | INTMASK3_MRXPERRM_MASK | \
INTMASK3_MRXTRFM_MASK | INTMASK3_MRXBUFOWM_MASK | \
INTMASK3_MPNACKM_MASK | INTMASK3_VDNMONM_MASK | \
INTMASK3_VBADCM_MASK),
};
extern bool muic_check_dev_ta(struct max77843_muic_data *muic_data);
extern bool muic_check_is_hv_dev(struct max77843_muic_data *muic_data);
extern muic_attached_dev_t hv_muic_check_id_err
(struct max77843_muic_data *muic_data, muic_attached_dev_t new_dev);
extern void max77843_hv_muic_reset_hvcontrol_reg(struct max77843_muic_data *muic_data);
#if defined(CONFIG_OF)
extern int of_max77843_hv_muic_dt(struct max77843_muic_data *muic_data);
#endif
extern int max77843_afc_muic_irq_init(struct max77843_muic_data *muic_data);
extern void max77843_hv_muic_free_irqs(struct max77843_muic_data *muic_data);
extern int max77843_muic_hv_update_reg(struct i2c_client *i2c,
const u8 reg, const u8 val, const u8 mask, const bool debug_en);
extern void max77843_muic_set_afc_ready(struct max77843_muic_data *muic_data, bool value);
extern void max77843_hv_muic_init_check_dpdnvden (struct max77843_muic_data *muic_data);
extern void max77843_hv_muic_init_detect(struct max77843_muic_data *muic_data);
extern void max77843_hv_muic_initialize(struct max77843_muic_data *muic_data);
extern void max77843_hv_muic_remove(struct max77843_muic_data *muic_data);
extern void max77843_hv_muic_remove_wo_free_irq(struct max77843_muic_data *muic_data);
extern void max77843_muic_set_adcmode_always(struct max77843_muic_data *muic_data);
#if !defined(CONFIG_SEC_FACTORY)
extern void max77843_muic_set_adcmode_oneshot(struct max77843_muic_data *muic_data);
#endif /* !CONFIG_SEC_FACTORY */
extern void max77843_hv_muic_adcmode_oneshot(struct max77843_muic_data *muic_data);
extern void max77843_muic_prepare_afc_charger(struct max77843_muic_data *muic_data);
extern bool max77843_muic_check_change_dev_afc_charger
(struct max77843_muic_data *muic_data, muic_attached_dev_t new_dev);
#endif /* __MAX77843_MUIC_HV_H__ */

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/*
* max77843-muic.h - MUIC for the Maxim 77843
*
* Copyright (C) 2011 Samsung Electrnoics
* Seoyoung Jeong <seo0.jeong@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* This driver is based on max14577-muic.h
*
*/
#ifndef __MAX77843_MUIC_H__
#define __MAX77843_MUIC_H__
#define MUIC_DEV_NAME "muic-max77843"
/* muic chip specific internal data structure */
struct max77843_muic_data {
struct device *dev;
struct i2c_client *i2c; /* i2c addr: 0x4A; MUIC */
struct mutex muic_mutex;
struct mutex reset_mutex;
/* model dependant mfd platform data */
struct max77843_platform_data *mfd_pdata;
int irq_adc1k;
int irq_adcerr;
int irq_adc;
int irq_chgtyp;
int irq_vbvolt;
int irq_vdnmon;
int irq_mrxrdy;
int irq_mpnack;
int irq_vbadc;
int irq_reset_acokbf;
/* model dependant muic platform data */
struct muic_platform_data *pdata;
/* muic current attached device */
muic_attached_dev_t attached_dev;
/* muic support vps list */
bool muic_support_list[ATTACHED_DEV_NUM];
bool is_muic_ready;
bool is_muic_reset;
bool ignore_adcerr;
/* check is otg test for jig uart off + vb */
bool is_otg_test;
bool is_factory_start;
bool is_afc_muic_ready;
bool is_afc_handshaking;
bool is_afc_muic_prepare;
bool is_charger_ready;
bool is_qc_vb_settle;
u8 is_boot_dpdnvden;
u8 tx_data;
bool is_mrxrdy;
int afc_count;
muic_afc_data_t afc_data;
u8 qc_hv;
struct delayed_work hv_muic_qc_vb_work;
/* muic status value */
u8 status1;
u8 status2;
u8 status3;
/* muic hvcontrol value */
u8 hvcontrol1;
u8 hvcontrol2;
};
/* max77843 muic register read/write related information defines. */
/* MAX77843 REGISTER ENABLE or DISABLE bit */
enum max77843_reg_bit_control {
MAX77843_DISABLE_BIT = 0,
MAX77843_ENABLE_BIT,
};
/* MAX77843 STATUS1 register */
#define STATUS1_ADC_SHIFT 0
#define STATUS1_ADCERR_SHIFT 6
#define STATUS1_ADC1K_SHIFT 7
#define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
#define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
#define STATUS1_ADC1K_MASK (0x1 << STATUS1_ADC1K_SHIFT)
/* MAX77843 STATUS2 register */
#define STATUS2_CHGTYP_SHIFT 0
#define STATUS2_CHGDETRUN_SHIFT 3
#define STATUS2_DCDTMR_SHIFT 4
#define STATUS2_DXOVP_SHIFT 5
#define STATUS2_VBVOLT_SHIFT 6
#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
#define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
#define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT)
#define STATUS2_DXOVP_MASK (0x1 << STATUS2_DXOVP_SHIFT)
#define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
/* MAX77843 CDETCTRL1 register */
#define CHGDETEN_SHIFT 0
#define CHGTYPM_SHIFT 1
#define CDDELAY_SHIFT 4
#define CHGDETEN_MASK (0x1 << CHGDETEN_SHIFT)
#define CHGTYPM_MASK (0x1 << CHGTYPM_SHIFT)
#define CDDELAY_MASK (0x1 << CDDELAY_SHIFT)
/* MAX77843 CONTROL1 register */
#define COMN1SW_SHIFT 0
#define COMP2SW_SHIFT 3
#define NOBCCOMP_SHIFT 6
#define IDBEN_SHIFT 7
#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
#define NOBCCOMP_MASK (0x1 << NOBCCOMP_SHIFT)
#define IDBEN_MASK (0x1 << IDBEN_SHIFT)
#define CLEAR_IDBEN_RSVD_MASK (COMN1SW_MASK | COMP2SW_MASK)
/* MAX77843 CONTROL2 register */
#define CTRL2_LOWPWR_SHIFT 0
#define CTRL2_CPEN_SHIFT 2
#define CTRL2_ACCDET_SHIFT 5
#define CTRL2_LOWPWR_MASK (0x1 << CTRL2_LOWPWR_SHIFT)
#define CTRL2_CPEN_MASK (0x1 << CTRL2_CPEN_SHIFT)
#define CTRL2_ACCDET_MASK (0x1 << CTRL2_ACCDET_SHIFT)
#define CTRL2_CPEN1_LOWPWD0 ((MAX77843_ENABLE_BIT << CTRL2_CPEN_SHIFT) | \
(MAX77843_DISABLE_BIT << CTRL2_ADCLOWPWR_SHIFT))
#define CTRL2_CPEN0_LOWPWD1 ((MAX77843_DISABLE_BIT << CTRL2_CPEN_SHIFT) | \
(MAX77843_ENABLE_BIT << CTRL2_ADCLOWPWR_SHIFT))
/* MAX77843 CONTROL3 register */
#define CTRL3_JIGSET_SHIFT 0
#define CTRL3_JIGSET_MASK (0x3 << CTRL3_JIGSET_SHIFT)
/* MAX77843 CONTROL4 register */
#define CTRL4_ADCDBSET_SHIFT 0
#define CTRL4_ADCMODE_SHIFT 6
#define CTRL4_ADCDBSET_MASK (0x3 << CTRL4_ADCDBSET_SHIFT)
#define CTRL4_ADCMODE_MASK (0x3 << CTRL4_ADCMODE_SHIFT)
typedef enum {
VB_LOW = 0x00,
VB_HIGH = (0x1 << STATUS2_VBVOLT_SHIFT),
VB_DONTCARE = 0xff,
} vbvolt_t;
typedef enum {
CHGDETRUN_FALSE = 0x00,
CHGDETRUN_TRUE = (0x1 << STATUS2_CHGDETRUN_SHIFT),
CHGDETRUN_DONTCARE = 0xff,
} chgdetrun_t;
/* MAX77843 MUIC Output of USB Charger Detection */
typedef enum {
/* No Valid voltage at VB (Vvb < Vvbdet) */
CHGTYP_NO_VOLTAGE = 0x00,
/* Unknown (D+/D- does not present a valid USB charger signature) */
CHGTYP_USB = 0x01,
/* Charging Downstream Port */
CHGTYP_CDP = 0x02,
/* Dedicated Charger (D+/D- shorted) */
CHGTYP_DEDICATED_CHARGER = 0x03,
/* Special 500mA charger, max current 500mA */
CHGTYP_500MA = 0x04,
/* Special 1A charger, max current 1A */
CHGTYP_1A = 0x05,
/* Special charger - 3.3V bias on D+/D- */
CHGTYP_SPECIAL_3_3V_CHARGER = 0x06,
/* Reserved */
CHGTYP_RFU = 0x07,
/* Any charger w/o USB */
CHGTYP_UNOFFICIAL_CHARGER = 0xfc,
/* Any charger type */
CHGTYP_ANY = 0xfd,
/* Don't care charger type */
CHGTYP_DONTCARE = 0xfe,
CHGTYP_MAX,
CHGTYP_INIT,
CHGTYP_MIN = CHGTYP_NO_VOLTAGE
} chgtyp_t;
typedef enum {
PROCESS_ATTACH = 0,
PROCESS_LOGICALLY_DETACH,
PROCESS_NONE,
} process_t;
/* muic register value for COMN1, COMN2 in CTRL1 reg */
/*
* MAX77843 CONTROL1 register
* ID Bypass [7] / Mic En [6] / D+ [5:3] / D- [2:0]
* 0: ID Bypass Open / 1: IDB connect to UID
* 0: Mic En Open / 1: Mic connect to VB
* 000: Open / 001: USB / 010: Audio / 011: UART
*/
enum max77843_reg_ctrl1_val {
MAX77843_MUIC_CTRL1_ID_OPEN = 0x0,
MAX77843_MUIC_CTRL1_ID_BYPASS = 0x1,
MAX77843_MUIC_CTRL1_NO_BC_COMP_OFF = 0x0,
MAX77843_MUIC_CTRL1_NO_BC_COMP_ON = 0x1,
MAX77843_MUIC_CTRL1_COM_OPEN = 0x00,
MAX77843_MUIC_CTRL1_COM_USB = 0x01,
MAX77843_MUIC_CTRL1_COM_AUDIO = 0x02,
MAX77843_MUIC_CTRL1_COM_UART = 0x03,
MAX77843_MUIC_CTRL1_COM_USB_CP = 0x04,
MAX77843_MUIC_CTRL1_COM_UART_CP = 0x05,
};
typedef enum {
CTRL1_OPEN = (MAX77843_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77843_MUIC_CTRL1_NO_BC_COMP_OFF << NOBCCOMP_SHIFT) | \
(MAX77843_MUIC_CTRL1_COM_OPEN << COMP2SW_SHIFT) | \
(MAX77843_MUIC_CTRL1_COM_OPEN << COMN1SW_SHIFT),
CTRL1_USB = (MAX77843_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77843_MUIC_CTRL1_NO_BC_COMP_OFF << NOBCCOMP_SHIFT) | \
(MAX77843_MUIC_CTRL1_COM_USB << COMP2SW_SHIFT) | \
(MAX77843_MUIC_CTRL1_COM_USB << COMN1SW_SHIFT),
CTRL1_AUDIO = (MAX77843_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77843_MUIC_CTRL1_NO_BC_COMP_OFF << NOBCCOMP_SHIFT) | \
(MAX77843_MUIC_CTRL1_COM_AUDIO << COMP2SW_SHIFT) | \
(MAX77843_MUIC_CTRL1_COM_AUDIO << COMN1SW_SHIFT),
CTRL1_UART = (MAX77843_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77843_MUIC_CTRL1_NO_BC_COMP_OFF << NOBCCOMP_SHIFT) | \
(MAX77843_MUIC_CTRL1_COM_UART << COMP2SW_SHIFT) | \
(MAX77843_MUIC_CTRL1_COM_UART << COMN1SW_SHIFT),
CTRL1_USB_CP = (MAX77843_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77843_MUIC_CTRL1_NO_BC_COMP_OFF << NOBCCOMP_SHIFT) | \
(MAX77843_MUIC_CTRL1_COM_USB_CP << COMP2SW_SHIFT) | \
(MAX77843_MUIC_CTRL1_COM_USB_CP << COMN1SW_SHIFT),
CTRL1_UART_CP = (MAX77843_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77843_MUIC_CTRL1_NO_BC_COMP_OFF << NOBCCOMP_SHIFT) | \
(MAX77843_MUIC_CTRL1_COM_UART_CP << COMP2SW_SHIFT) | \
(MAX77843_MUIC_CTRL1_COM_UART_CP << COMN1SW_SHIFT),
CTRL1_USB_DOCK = (MAX77843_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77843_MUIC_CTRL1_NO_BC_COMP_ON << NOBCCOMP_SHIFT) | \
(MAX77843_MUIC_CTRL1_COM_USB << COMP2SW_SHIFT) | \
(MAX77843_MUIC_CTRL1_COM_USB << COMN1SW_SHIFT),
} max77843_reg_ctrl1_t;
enum {
MAX77843_MUIC_CTRL4_ADCMODE_ALWAYS_ON = 0x00,
MAX77843_MUIC_CTRL4_ADCMODE_ALWAYS_ON_1M_MON = 0x01,
MAX77843_MUIC_CTRL4_ADCMODE_ONE_SHOT = 0x02,
MAX77843_MUIC_CTRL4_ADCMODE_2S_PULSE = 0x03
};
extern struct device *switch_device;
#endif /* __MAX77843_MUIC_H__ */

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/*
* max77888-muic.h - MUIC for the Maxim 77888
*
* Copyright (C) 2011 Samsung Electrnoics
* Seoyoung Jeong <seo0.jeong@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* This driver is based on max14577-muic.h
*
*/
#ifndef __MAX77888_MUIC_H__
#define __MAX77888_MUIC_H__
#define MUIC_DEV_NAME "muic-max77888"
/* max77888 muic register read/write related information defines. */
/* MAX77888 REGISTER ENABLE or DISABLE bit */
enum max77888_reg_bit_control {
MAX77888_DISABLE_BIT = 0,
MAX77888_ENABLE_BIT,
};
/* MAX77888 STATUS1 register */
#define STATUS1_ADC_SHIFT 0
#define STATUS1_ADCERR_SHIFT 6
#define STATUS1_ADC1K_SHIFT 7
#define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
#define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
#define STATUS1_ADC1K_MASK (0x1 << STATUS1_ADC1K_SHIFT)
/* MAX77888 STATUS2 register */
#define STATUS2_CHGTYP_SHIFT 0
#define STATUS2_CHGDETRUN_SHIFT 3
#define STATUS2_DCDTMR_SHIFT 4
#define STATUS2_DXOVP_SHIFT 5
#define STATUS2_VBVOLT_SHIFT 6
#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
#define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
#define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT)
#define STATUS2_DXOVP_MASK (0x1 << STATUS2_DXOVP_SHIFT)
#define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
/* MAX77888 CDETCTRL1 register */
#define CHGDETEN_SHIFT 0
#define CHGTYPM_SHIFT 1
#define CDDELAY_SHIFT 4
#define CHGDETEN_MASK (0x1 << CHGDETEN_SHIFT)
#define CHGTYPM_MASK (0x1 << CHGTYPM_SHIFT)
#define CDDELAY_MASK (0x1 << CDDELAY_SHIFT)
/* MAX77888 CONTROL1 register */
#define COMN1SW_SHIFT 0
#define COMP2SW_SHIFT 3
#define MICEN_SHIFT 6
#define IDBEN_SHIFT 7
#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
#define MICEN_MASK (0x1 << MICEN_SHIFT)
#define IDBEN_MASK (0x1 << IDBEN_SHIFT)
#define CLEAR_IDBEN_MICEN_MASK (COMN1SW_MASK | COMP2SW_MASK)
/* MAX77888 CONTROL2 register */
#define CTRL2_LOWPWR_SHIFT 0
#define CTRL2_CPEN_SHIFT 2
#define CTRL2_ACCDET_SHIFT 5
#define CTRL2_LOWPWR_MASK (0x1 << CTRL2_LOWPWR_SHIFT)
#define CTRL2_CPEN_MASK (0x1 << CTRL2_CPEN_SHIFT)
#define CTRL2_ACCDET_MASK (0x1 << CTRL2_ACCDET_SHIFT)
#define CTRL2_CPEN1_LOWPWD0 ((MAX77888_ENABLE_BIT << CTRL2_CPEN_SHIFT) | \
(MAX77888_DISABLE_BIT << CTRL2_ADCLOWPWR_SHIFT))
#define CTRL2_CPEN0_LOWPWD1 ((MAX77888_DISABLE_BIT << CTRL2_CPEN_SHIFT) | \
(MAX77888_ENABLE_BIT << CTRL2_ADCLOWPWR_SHIFT))
/* MAX77888 CONTROL3 register */
#define CTRL3_JIGSET_SHIFT 0
#define CTRL3_BOOTSET_SHIFT 2
#define CTRL3_JIGSET_MASK (0x3 << CTRL3_JIGSET_SHIFT)
#define CTRL3_BOOTSET_MASK (0x3 << CTRL3_BOOTSET_SHIFT)
/* MAX77888 CONTROL4 register */
#define CTRL4_ADCDBSET_SHIFT 0
#define CTRL4_USBAUTO_SHIFT 4
#define CTRL4_FACTAUTO_SHIFT 5
#define CTRL4_ADCMODE_SHIFT 6
#define CTRL4_ADCDBSET_MASK (0x3 << CTRL4_ADCDBSET_SHIFT)
#define CTRL4_USBAUTO_MASK (MAX77888_ENABLE_BIT << CTRL4_USBAUTO_SHIFT)
#define CTRL4_FACTAUTO_MASK (MAX77888_ENABLE_BIT << CTRL4_FACTAUTO_SHIFT)
#define CTRL4_ADCMODE_MASK (0x3 << CTRL4_ADCMODE_SHIFT)
typedef enum {
VB_LOW = 0x00,
VB_HIGH = (0x1 << STATUS2_VBVOLT_SHIFT),
VB_DONTCARE = 0xff,
} vbvolt_t;
typedef enum {
CHGDETRUN_FALSE = 0x00,
CHGDETRUN_TRUE = (0x1 << STATUS2_CHGDETRUN_SHIFT),
CHGDETRUN_DONTCARE = 0xff,
} chgdetrun_t;
/* MAX77888 MUIC Output of USB Charger Detection */
typedef enum {
/* No Valid voltage at VB (Vvb < Vvbdet) */
CHGTYP_NO_VOLTAGE = 0x00,
/* Unknown (D+/D- does not present a valid USB charger signature) */
CHGTYP_USB = 0x01,
/* Charging Downstream Port */
CHGTYP_CDP = 0x02,
/* Dedicated Charger (D+/D- shorted) */
CHGTYP_DEDICATED_CHARGER = 0x03,
/* Special 500mA charger, max current 500mA */
CHGTYP_500MA = 0x04,
/* Special 1A charger, max current 1A */
CHGTYP_1A = 0x05,
/* Special charger - 3.3V bias on D+/D- */
CHGTYP_SPECIAL_3_3V_CHARGER = 0x06,
/* Reserved */
CHGTYP_RFU = 0x07,
/* Any charger type */
CHGTYP_ANY = 0xfd,
/* Don't care charger type */
CHGTYP_DONTCARE = 0xfe,
CHGTYP_MAX,
CHGTYP_INIT,
CHGTYP_MIN = CHGTYP_NO_VOLTAGE
} chgtyp_t;
/* muic register value for COMN1, COMN2 in CTRL1 reg */
/*
* MAX77888 CONTROL1 register
* ID Bypass [7] / Mic En [6] / D+ [5:3] / D- [2:0]
* 0: ID Bypass Open / 1: IDB connect to UID
* 0: Mic En Open / 1: Mic connect to VB
* 000: Open / 001: USB / 010: Audio / 011: UART
*/
enum max77888_reg_ctrl1_val {
MAX77888_MUIC_CTRL1_ID_OPEN = 0x0,
MAX77888_MUIC_CTRL1_ID_BYPASS = 0x1,
MAX77888_MUIC_CTRL1_MIC_OPEN = 0x0,
MAX77888_MUIC_CTRL1_MIC_VB = 0x1,
MAX77888_MUIC_CTRL1_COM_OPEN = 0x00,
MAX77888_MUIC_CTRL1_COM_USB = 0x01,
MAX77888_MUIC_CTRL1_COM_AUDIO = 0x02,
MAX77888_MUIC_CTRL1_COM_UART = 0x03,
MAX77888_MUIC_CTRL1_COM_USB_CP = 0x04,
MAX77888_MUIC_CTRL1_COM_UART_CP = 0x05,
};
typedef enum {
CTRL1_OPEN = (MAX77888_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77888_MUIC_CTRL1_MIC_OPEN << MICEN_SHIFT) | \
(MAX77888_MUIC_CTRL1_COM_OPEN << COMP2SW_SHIFT) | \
(MAX77888_MUIC_CTRL1_COM_OPEN << COMN1SW_SHIFT),
CTRL1_USB = (MAX77888_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77888_MUIC_CTRL1_MIC_OPEN << MICEN_SHIFT) | \
(MAX77888_MUIC_CTRL1_COM_USB << COMP2SW_SHIFT) | \
(MAX77888_MUIC_CTRL1_COM_USB << COMN1SW_SHIFT),
CTRL1_AUDIO = (MAX77888_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77888_MUIC_CTRL1_MIC_OPEN << MICEN_SHIFT) | \
(MAX77888_MUIC_CTRL1_COM_AUDIO << COMP2SW_SHIFT) | \
(MAX77888_MUIC_CTRL1_COM_AUDIO << COMN1SW_SHIFT),
CTRL1_UART = (MAX77888_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77888_MUIC_CTRL1_MIC_OPEN << MICEN_SHIFT) | \
(MAX77888_MUIC_CTRL1_COM_UART << COMP2SW_SHIFT) | \
(MAX77888_MUIC_CTRL1_COM_UART << COMN1SW_SHIFT),
CTRL1_USB_CP = (MAX77888_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77888_MUIC_CTRL1_MIC_OPEN << MICEN_SHIFT) | \
(MAX77888_MUIC_CTRL1_COM_USB_CP << COMP2SW_SHIFT) | \
(MAX77888_MUIC_CTRL1_COM_USB_CP << COMN1SW_SHIFT),
CTRL1_UART_CP = (MAX77888_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77888_MUIC_CTRL1_MIC_OPEN << MICEN_SHIFT) | \
(MAX77888_MUIC_CTRL1_COM_UART_CP << COMP2SW_SHIFT) | \
(MAX77888_MUIC_CTRL1_COM_UART_CP << COMN1SW_SHIFT),
} max77888_reg_ctrl1_t;
extern struct device *switch_device;
#endif /* __MAX77888_MUIC_H__ */

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/*
* include/linux/muic/muic.h
*
* header file supporting MUIC common information
*
* Copyright (C) 2010 Samsung Electronics
* Seoyoung Jeong <seo0.jeong@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __MUIC_H__
#define __MUIC_H__
/* Status of IF PMIC chip (suspend and resume) */
enum {
MUIC_SUSPEND = 0,
MUIC_RESUME,
};
/* MUIC Interrupt */
enum {
MUIC_INTR_DETACH = 0,
MUIC_INTR_ATTACH
};
/* MUIC Dock Observer Callback parameter */
enum {
MUIC_DOCK_DETACHED = 0,
MUIC_DOCK_DESKDOCK = 1,
MUIC_DOCK_CARDOCK = 2,
MUIC_DOCK_AUDIODOCK = 101,
MUIC_DOCK_SMARTDOCK = 102,
MUIC_DOCK_HMT = 105,
};
/* MUIC Path */
enum {
MUIC_PATH_USB_AP = 0,
MUIC_PATH_USB_CP,
MUIC_PATH_UART_AP,
MUIC_PATH_UART_CP,
MUIC_PATH_OPEN,
MUIC_PATH_AUDIO,
};
#ifdef CONFIG_MUIC_HV_FORCE_LIMIT
enum {
HV_9V = 0,
HV_5V,
};
#endif
/* bootparam SWITCH_SEL */
enum {
SWITCH_SEL_USB_MASK = 0x1,
SWITCH_SEL_UART_MASK = 0x2,
SWITCH_SEL_RUSTPROOF_MASK = 0x8,
SWITCH_SEL_AFC_DISABLE_MASK = 0x100,
};
/* MUIC ADC table */
typedef enum {
ADC_GND = 0x00,
ADC_SEND_END = 0x01, /* 0x00001 2K ohm */
ADC_REMOTE_S11 = 0x0c, /* 0x01100 20.5K ohm */
ADC_REMOTE_S12 = 0x0d, /* 0x01101 24.07K ohm */
ADC_RESERVED_VZW = 0x0e, /* 0x01110 28.7K ohm */
ADC_INCOMPATIBLE_VZW = 0x0f, /* 0x01111 34K ohm */
ADC_SMARTDOCK = 0x10, /* 0x10000 40.2K ohm */
ADC_RDU_TA = 0x10, /* 0x10000 40.2K ohm */
ADC_HMT = 0x11, /* 0x10001 49.9K ohm */
ADC_AUDIODOCK = 0x12, /* 0x10010 64.9K ohm */
ADC_USB_LANHUB = 0x13, /* 0x10011 80.07K ohm */
ADC_CHARGING_CABLE = 0x14, /* 0x10100 102K ohm */
ADC_UNIVERSAL_MMDOCK = 0x15, /* 0x10101 121K ohm */
ADC_UART_CABLE = 0x16, /* 0x10110 150K ohm */
ADC_CEA936ATYPE1_CHG = 0x17, /* 0x10111 200K ohm */
ADC_JIG_USB_OFF = 0x18, /* 0x11000 255K ohm */
ADC_JIG_USB_ON = 0x19, /* 0x11001 301K ohm */
ADC_DESKDOCK = 0x1a, /* 0x11010 365K ohm */
ADC_CEA936ATYPE2_CHG = 0x1b, /* 0x11011 442K ohm */
ADC_JIG_UART_OFF = 0x1c, /* 0x11100 523K ohm */
ADC_JIG_UART_ON = 0x1d, /* 0x11101 619K ohm */
ADC_AUDIOMODE_W_REMOTE = 0x1e, /* 0x11110 1000K ohm */
ADC_OPEN = 0x1f,
ADC_OPEN_219 = 0xfb, /* ADC open or 219.3K ohm */
ADC_219 = 0xfc, /* ADC open or 219.3K ohm */
ADC_UNDEFINED = 0xfd, /* Undefied range */
ADC_DONTCARE = 0xfe, /* ADC don't care for MHL */
ADC_ERROR = 0xff, /* ADC value read error */
} muic_adc_t;
/* MUIC attached device type */
typedef enum {
ATTACHED_DEV_NONE_MUIC = 0,
ATTACHED_DEV_USB_MUIC,
ATTACHED_DEV_CDP_MUIC,
ATTACHED_DEV_OTG_MUIC,
ATTACHED_DEV_TA_MUIC,
ATTACHED_DEV_UNOFFICIAL_MUIC,
ATTACHED_DEV_UNOFFICIAL_TA_MUIC,
ATTACHED_DEV_UNOFFICIAL_ID_MUIC,
ATTACHED_DEV_UNOFFICIAL_ID_TA_MUIC,
ATTACHED_DEV_UNOFFICIAL_ID_ANY_MUIC,
ATTACHED_DEV_UNOFFICIAL_ID_USB_MUIC,
ATTACHED_DEV_UNOFFICIAL_ID_CDP_MUIC,
ATTACHED_DEV_UNDEFINED_CHARGING_MUIC,
ATTACHED_DEV_DESKDOCK_MUIC,
ATTACHED_DEV_UNKNOWN_VB_MUIC,
ATTACHED_DEV_DESKDOCK_VB_MUIC,
ATTACHED_DEV_CARDOCK_MUIC,
ATTACHED_DEV_JIG_UART_OFF_MUIC,
ATTACHED_DEV_JIG_UART_OFF_VB_MUIC, /* VBUS enabled */
ATTACHED_DEV_JIG_UART_OFF_VB_OTG_MUIC, /* for otg test */
ATTACHED_DEV_JIG_UART_OFF_VB_FG_MUIC, /* for fuelgauge test */
ATTACHED_DEV_JIG_UART_ON_MUIC,
ATTACHED_DEV_JIG_USB_OFF_MUIC,
ATTACHED_DEV_JIG_USB_ON_MUIC,
ATTACHED_DEV_SMARTDOCK_MUIC,
ATTACHED_DEV_SMARTDOCK_VB_MUIC,
ATTACHED_DEV_SMARTDOCK_TA_MUIC,
ATTACHED_DEV_SMARTDOCK_USB_MUIC,
ATTACHED_DEV_UNIVERSAL_MMDOCK_MUIC,
ATTACHED_DEV_AUDIODOCK_MUIC,
ATTACHED_DEV_MHL_MUIC,
ATTACHED_DEV_CHARGING_CABLE_MUIC,
ATTACHED_DEV_AFC_CHARGER_PREPARE_MUIC,
ATTACHED_DEV_AFC_CHARGER_PREPARE_DUPLI_MUIC,
ATTACHED_DEV_AFC_CHARGER_5V_MUIC,
ATTACHED_DEV_AFC_CHARGER_5V_DUPLI_MUIC,
ATTACHED_DEV_AFC_CHARGER_9V_MUIC,
ATTACHED_DEV_AFC_CHARGER_ERR_V_MUIC,
ATTACHED_DEV_AFC_CHARGER_ERR_V_DUPLI_MUIC,
ATTACHED_DEV_QC_CHARGER_PREPARE_MUIC,
ATTACHED_DEV_QC_CHARGER_5V_MUIC,
ATTACHED_DEV_QC_CHARGER_ERR_V_MUIC,
ATTACHED_DEV_QC_CHARGER_9V_MUIC,
ATTACHED_DEV_HV_ID_ERR_UNDEFINED_MUIC,
ATTACHED_DEV_HV_ID_ERR_UNSUPPORTED_MUIC,
ATTACHED_DEV_HV_ID_ERR_SUPPORTED_MUIC,
ATTACHED_DEV_HMT_MUIC,
ATTACHED_DEV_VZW_ACC_MUIC,
ATTACHED_DEV_VZW_INCOMPATIBLE_MUIC,
ATTACHED_DEV_USB_LANHUB_MUIC,
ATTACHED_DEV_TYPE2_CHG_MUIC,
ATTACHED_DEV_UNSUPPORTED_ID_MUIC,
ATTACHED_DEV_UNSUPPORTED_ID_VB_MUIC,
ATTACHED_DEV_UNDEFINED_RANGE_MUIC,
ATTACHED_DEV_RDU_TA_MUIC,
ATTACHED_DEV_UNKNOWN_MUIC,
ATTACHED_DEV_NUM,
} muic_attached_dev_t;
#ifdef CONFIG_MUIC_HV_FORCE_LIMIT
/* MUIC attached device type */
typedef enum {
SILENT_CHG_DONE = 0,
SILENT_CHG_CHANGING = 1,
SILENT_CHG_NUM,
} muic_silent_change_state_t;
#endif
/* muic common callback driver internal data structure
* that setted at muic-core.c file
*/
struct muic_platform_data {
int irq_gpio;
/* muic current USB/UART path */
int usb_path;
int uart_path;
int gpio_uart_sel;
bool rustproof_on;
bool afc_disable;
#ifdef CONFIG_MUIC_HV_FORCE_LIMIT
int hv_sel;
int silent_chg_change_state;
#endif
/* muic switch dev register function for DockObserver */
void (*init_switch_dev_cb) (void);
void (*cleanup_switch_dev_cb) (void);
/* muic GPIO control function */
int (*init_gpio_cb) (void);
int (*set_gpio_usb_sel) (int usb_path);
int (*set_gpio_uart_sel) (int uart_path);
int (*set_safeout) (int safeout_path);
/* muic path switch function for rustproof */
void (*set_path_switch_suspend) (struct device *dev);
void (*set_path_switch_resume) (struct device *dev);
/* for uart_sel */
int (*muic_set_path)(void *drv_data, int path);
};
extern int get_switch_sel(void);
extern struct device *switch_device;
extern struct muic_platform_data muic_pdata;
#endif /* __MUIC_H__ */

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/*
* Copyright (C) 2010 Samsung Electronics
* Hyoyoung Kim <hyway.kim@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __MUIC_AFC_H__
#define __MUIC_AFC_H__
#include <../drivers/muic/universal/muic-internal.h>
struct muic_data_t;
/* SM5705 AFC CTRL register */
#define AFCCTRL_DIS_AFC 5
#define AFCCTRL_VBUS_READ 3
#define AFCCTRL_DM_RESET 2
#define AFCCTRL_DP_RESET 1
#define AFCCTRL_ENAFC 0
int muic_check_afc_state(int state);
int muic_torch_prepare(int state);
void muic_init_afc_state(muic_data_t *pmuic);
#endif /* __MUIC_AFC_H__ */

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/*
* include/linux/muic/muic_notifier.h
*
* header file supporting MUIC notifier call chain information
*
* Copyright (C) 2010 Samsung Electronics
* Seung-Jin Hahn <sjin.hahn@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __MUIC_NOTIFIER_H__
#define __MUIC_NOTIFIER_H__
/* MUIC notifier call chain command */
typedef enum {
MUIC_NOTIFY_CMD_DETACH = 0,
MUIC_NOTIFY_CMD_ATTACH,
MUIC_NOTIFY_CMD_LOGICALLY_DETACH,
MUIC_NOTIFY_CMD_LOGICALLY_ATTACH,
} muic_notifier_cmd_t;
/* MUIC notifier call sequence,
* largest priority number device will be called first. */
typedef enum {
MUIC_NOTIFY_DEV_DOCK = 0,
MUIC_NOTIFY_DEV_MHL,
MUIC_NOTIFY_DEV_USB,
MUIC_NOTIFY_DEV_TSP,
MUIC_NOTIFY_DEV_CHARGER,
MUIC_NOTIFY_DEV_CPUIDLE,
MUIC_NOTIFY_DEV_CPUFREQ
} muic_notifier_device_t;
struct muic_notifier_struct {
muic_attached_dev_t attached_dev;
muic_notifier_cmd_t cmd;
struct blocking_notifier_head notifier_call_chain;
};
#define MUIC_NOTIFIER_BLOCK(name) \
struct notifier_block (name)
/* muic notifier init/notify function
* this function is for JUST MUIC device driver.
* DON'T use function anywhrer else!!
*/
extern void muic_notifier_attach_attached_dev(muic_attached_dev_t new_dev);
extern void muic_notifier_detach_attached_dev(muic_attached_dev_t cur_dev);
extern void muic_notifier_logically_attach_attached_dev(muic_attached_dev_t new_dev);
extern void muic_notifier_logically_detach_attached_dev(muic_attached_dev_t cur_dev);
/* muic notifier register/unregister API
* for used any where want to receive muic attached device attach/detach. */
extern int muic_notifier_register(struct notifier_block *nb,
notifier_fn_t notifier, muic_notifier_device_t listener);
extern int muic_notifier_unregister(struct notifier_block *nb);
#endif /* __MUIC_NOTIFIER_H__ */

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/*
* Copyright (C) 2016 Samsung Electronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __RT8973_H__
#define __RT8973_H__
#include <linux/muic/muic.h>
#include <linux/wakelock.h>
#define MUIC_DEV_NAME "muic-rt8973"
#define RT8973_IRQF_MODE (IRQF_TRIGGER_FALLING | IRQF_NO_SUSPEND)
enum rt8973_muic_reg {
RT8973_REG_CHIP_ID = 0x01,
RT8973_REG_CONTROL = 0x02,
RT8973_REG_INT1 = 0x03,
RT8973_REG_INT2 = 0x04,
RT8973_REG_INT_MASK1 = 0x05,
RT8973_REG_INT_MASK2 = 0x06,
RT8973_REG_ADC = 0x23,
RT8973_REG_DEVICE1 = 0x0A,
RT8973_REG_DEVICE2 = 0x0B,
RT8973_REG_MANUAL_SW1 = 0x13,
RT8973_REG_MANUAL_SW2 = 0x14,
RT8973_REG_RESET = 0x1B,
};
#define DCD_T_RETRY 2
/* RT8973 Control register */
#define CTRL_ADC_EN_SHIFT 7
#define CTRL_USBCHDEN_SHIFT 6
#define CTRL_CHG_TYP_SHIFT 5
#define CTRL_SWITCH_OPEN_SHIFT 4
/* CTRL bit 3 is deprecated */
#define CTRL_AUTO_CONFIG_SHIFT 2
/* CTRL bit 1 is RSVD */
#define CTRL_INT_MASK_SHIFT 0
#define CTRL_ADC_EN_MASK (0x1 << CTRL_ADC_EN_SHIFT)
#define CTRL_USBCHDEN_MASK (0x1 << CTRL_USBCHDEN_SHIFT)
#define CTRL_CHG_TYP_MASK (0x1 << CTRL_CHG_TYP_SHIFT)
#define CTRL_SWITCH_OPEN_MASK (0x1 << CTRL_SWITCH_OPEN_SHIFT)
#define CTRL_AUTO_CONFIG_MASK (0x1 << CTRL_AUTO_CONFIG_SHIFT)
#define CTRL_INT_MASK_MASK (0x1 << CTRL_INT_MASK_SHIFT)
#define CTRL_MASK (CTRL_INT_MASK_MASK | CTRL_AUTO_CONFIG_MASK |\
CTRL_CHG_TYP_MASK | CTRL_USBCHDEN_MASK | CTRL_ADC_EN_MASK)
/* RT8973 Interrupt 1 register */
#define INT_OTP_SHIFT 7
#define INT_ADC_CHG_SHIFT 6
#define INT_CONNECT_SHIFT 5
#define INT_OVP_SHIFT 4
#define INT_DCD_T_SHIFT 3
#define INT_CHG_DET_SHIFT 2
#define INT_DETACH_SHIFT 1
#define INT_ATTACH_SHIFT 0
#define INT_OTP_MASK (0x1 << INT_OTP_SHIFT)
#define INT_ADC_CHG_MASK (0x1 << INT_ADC_CHG_SHIFT)
#define INT_CONNECT_MASK (0x1 << INT_CONNECT_SHIFT)
#define INT_OVP_MASK (0x1 << INT_OVP_SHIFT)
#define INT_DCD_T_MASK (0x1 << INT_DCD_T_SHIFT)
#define INT_CHG_DET_MASK (0x1 << INT_CHG_DET_SHIFT)
#define INT_DETACH_MASK (0x1 << INT_DETACH_SHIFT)
#define INT_ATTACH_MASK (0x1 << INT_ATTACH_SHIFT)
/* RT8973 Interrupt 2 register */
#define INT_OVP_OCP_SHIFT 7
#define INT_OCP_SHIFT 6
#define INT_OCP_LATCH_SHIFT 5
#define INT_OVP_FET_SHIFT 4
#define INT_OTP_FET_SHIFT 3
#define INT_POR_SHIFT 2
#define INT_UVLO_SHIFT 1
/* INT2 bit 0 is RSVD */
#define INT_OVP_OCP_MASK (0x1 << INT_OVP_OCP_SHIFT)
#define INT_OCP_MASK (0x1 << INT_OCP_SHIFT)
#define INT_OCP_LATCH_MASK (0x1 << INT_OCP_LATCH_SHIFT)
#define INT_OVP_FET_MASK (0x1 << INT_OVP_FET_SHIFT)
#define INT_OTP_FET_MASK (0x1 << INT_OTP_FET_SHIFT)
#define INT_POR_MASK (0x1 << INT_POR_SHIFT)
#define INT_UVLO_MASK (0x1 << INT_UVLO_SHIFT)
/* RT8973 ADC register */
#define ADC_ADC_SHIFT 0
#define ADC_ADC_MASK (0x1f << ADC_ADC_SHIFT)
/* RT8973 DEVICE1 register */
#define RT8973_DEVICE1_OTG 0x01
#define RT8973_DEVICE1_SDP (0x1 << 2)
#define RT8973_DEVICE1_UART (0x1 << 3)
#define RT8973_DEVICE1_CDPORT (0x1 << 5)
#define RT8973_DEVICE1_DCPORT (0x1 << 6)
#define RT8973_USB_TYPES (RT8973_DEVICE1_OTG | RT8973_DEVICE1_SDP | RT8973_DEVICE1_CDPORT)
#define RT8973_CHG_TYPES (RT8973_DEVICE1_DCPORT | RT8973_DEVICE1_CDPORT)
/* RT8973 DEVICE2 register */
#define RT8973_DEVICE2_JIG_USB_ON 0x01
#define RT8973_DEVICE2_JIG_USB_OFF (0x1 << 1)
#define RT8973_DEVICE2_JIG_UART_ON (0x1 << 2)
#define RT8973_DEVICE2_JIG_UART_OFF (0x1 << 3)
#define RT8973_DEVICE2_UNKNOWN (0x1 << 7)
#define RT8973_JIG_USB_TYPES (RT8973_DEVICE2_JIG_USB_ON | RT8973_DEVICE2_JIG_USB_OFF)
#define RT8973_JIG_UART_TYPES (RT8973_DEVICE2_JIG_UART_OFF)
/*
* Manual Switch
* D- [7:5] / D+ [4:2]
* 000: Open all / 001: USB / 011: UART
* 00: Vbus to Open / 01: Vbus to Charger / 10: Vbus to MIC / 11: Vbus to VBout
*/
#define MANUAL_SW1_DN_SHIFT 5
#define MANUAL_SW1_DP_SHIFT 2
#define MANUAL_SW_DM_DP_MASK 0xFC
/* bit 1 and bit 0 are RSVD */
#define MANUAL_SW1_D_OPEN (0x0)
#define MANUAL_SW1_D_USB (0x1)
/* RT8973 does not have audio path */
#define MANUAL_SW1_D_UART (0x3)
enum rt8973_switch_sel_val {
SM5502_SWITCH_SEL_1st_BIT_USB = (0x1 << 0),
SM5502_SWITCH_SEL_2nd_BIT_UART = (0x1 << 1),
};
enum rt8973_reg_manual_sw1_value {
MANSW1_OPEN = (MANUAL_SW1_D_OPEN << MANUAL_SW1_DN_SHIFT) | \
(MANUAL_SW1_D_OPEN << MANUAL_SW1_DP_SHIFT),
MANSW1_USB = (MANUAL_SW1_D_USB << MANUAL_SW1_DN_SHIFT) | \
(MANUAL_SW1_D_USB << MANUAL_SW1_DP_SHIFT),
MANSW1_UART = (MANUAL_SW1_D_UART << MANUAL_SW1_DN_SHIFT) | \
(MANUAL_SW1_D_UART << MANUAL_SW1_DP_SHIFT),
};
typedef enum {
JIG_USB_BOOT_OFF,
JIG_USB_BOOT_ON,
JIG_UART_BOOT_OFF,
JIG_UART_BOOT_ON,
} jig_type_t;
struct rt8973_status {
int cable_type;
int id_adc;
uint8_t irq_flags[2];
uint8_t device_reg[2];
/* Processed useful status
* Compare previous and current regs
* to get this information */
union {
struct {
uint32_t vbus_status:1;
uint32_t accessory_status:1;
uint32_t ocp_status:1;
uint32_t ovp_status:1;
uint32_t otp_status:1;
uint32_t adc_chg_status:1;
uint32_t cable_chg_status:1;
uint32_t otg_status:1;
uint32_t dcdt_status:1;
uint32_t usb_connect:1;
uint32_t uart_connect:1;
uint32_t jig_connect:1;
uint32_t l200k_usb_connect:1;
uint32_t dock_status:1;
};
uint32_t status;
};
};
/* muic chip specific internal data structure
* that setted at muic-xxxx.c file
*/
struct rt8973_muic_data {
struct device *dev;
struct i2c_client *i2c; /* i2c addr: 0x4A; MUIC */
struct mutex muic_mutex;
/* muic common callback driver internal data */
struct sec_switch_data *switch_data;
/* model dependant muic platform data */
struct muic_platform_data *pdata;
/* muic support vps list */
bool muic_support_list[ATTACHED_DEV_NUM];
/* muic current attached device */
muic_attached_dev_t attached_dev;
/* muic Device ID */
u8 muic_vendor; /* Vendor ID */
u8 muic_version; /* Version ID */
bool is_usb_ready;
bool is_factory_start;
bool is_rustproof;
bool is_otg_test;
bool vbus_ignore;
/* W/A waiting for the charger ic */
bool suspended;
bool need_to_noti;
/* RT8973 specific*/
struct delayed_work dwork;
struct wake_lock muic_wake_lock;
struct rt8973_status prev_status;
struct rt8973_status curr_status;
int dcdt_retry_count;
int rev_id;
};
extern unsigned int system_rev;
#endif /* __RT8973_H__ */

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/*
* Copyright (C) 2010 Samsung Electronics
* Hyoyoung Kim <hyway.kim@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __S2MM001_H__
#define __S2MM001_H__
#include <linux/muic/muic.h>
#include <linux/wakelock.h>
#define MUIC_DEV_NAME "muic-s2mm001"
/* s2mm001 muic register read/write related information defines. */
/* Slave addr = 0x4A: MUIC */
/* S2MM001 I2C registers */
enum s2mm001_muic_reg {
S2MM001_MUIC_REG_DEVID = 0x01,
S2MM001_MUIC_REG_CTRL = 0x02,
S2MM001_MUIC_REG_INT1 = 0x03,
S2MM001_MUIC_REG_INT2 = 0x04,
S2MM001_MUIC_REG_INTMASK1 = 0x05,
S2MM001_MUIC_REG_INTMASK2 = 0x06,
S2MM001_MUIC_REG_ADC = 0x07,
S2MM001_MUIC_REG_TIMING1 = 0x08,
S2MM001_MUIC_REG_TIMING2 = 0x09,
/* unused registers */
S2MM001_MUIC_REG_DEV_T1 = 0x0a,
S2MM001_MUIC_REG_DEV_T2 = 0x0b,
S2MM001_MUIC_REG_MANSW1 = 0x13,
S2MM001_MUIC_REG_MANSW2 = 0x14,
S2MM001_MUIC_REG_DEV_T3 = 0x15,
S2MM001_MUIC_REG_RESET = 0x1B,
S2MM001_MUIC_REG_TIMING3 = 0x20,
S2MM001_MUIC_REG_OCP = 0x22,
S2MM001_MUIC_REG_CTRL2 = 0x23,
S2MM001_MUIC_REG_END,
};
/* S2MM001 REGISTER ENABLE or DISABLE bit */
#define S2MM001_ENABLE_BIT 1
#define S2MM001_DISABLE_BIT 0
/* S2MM001 Control register */
#define CTRL_SWITCH_OPEN_SHIFT 4
#define CTRL_RAW_DATA_SHIFT 3
#define CTRL_MANUAL_SW_SHIFT 2
#define CTRL_WAIT_SHIFT 1
#define CTRL_INT_MASK_SHIFT 0
#define CTRL_SWITCH_OPEN_MASK (0x1 << CTRL_SWITCH_OPEN_SHIFT)
#define CTRL_RAW_DATA_MASK (0x1 << CTRL_RAW_DATA_SHIFT)
#define CTRL_MANUAL_SW_MASK (0x1 << CTRL_MANUAL_SW_SHIFT)
#define CTRL_WAIT_MASK (0x1 << CTRL_WAIT_SHIFT)
#define CTRL_INT_MASK_MASK (0x1 << CTRL_INT_MASK_SHIFT)
#define CTRL_MASK (CTRL_SWITCH_OPEN_MASK | CTRL_RAW_DATA_MASK | \
/*CTRL_MANUAL_SW_MASK |*/ CTRL_WAIT_MASK | \
CTRL_INT_MASK_MASK)
/* S2MM001 Interrupt 1 register */
#define INT_OVP_EN_SHIFT 5
#define INT_LKR_SHIFT 4
#define INT_LKP_SHIFT 3
#define INT_KP_SHIFT 2
#define INT_DETACH_SHIFT 1
#define INT_ATTACH_SHIFT 0
#define INT_OVP_EN_MASK (0x1 << INT_OVP_EN_SHIFT)
#define INT_LKR_MASK (0x1 << INT_LKR_SHIFT)
#define INT_LKP_MASK (0x1 << INT_LKP_SHIFT)
#define INT_KP_MASK (0x1 << INT_KP_SHIFT)
#define INT_DETACH_MASK (0x1 << INT_DETACH_SHIFT)
#define INT_ATTACH_MASK (0x1 << INT_ATTACH_SHIFT)
/* S2MM001 Interrupt 2 register */
#define INT_ADC_CHANGE_SHIFT 2
#define INT_RSRV_ATTACH_SHIFT 1
#define INT_CHG_DET_SHIFT 0
#define INT_ADC_CHANGE_MASK (0x1 << INT_ADC_CHANGE_SHIFT)
#define INT_RSRV_ATTACH_MASK (0x1 << INT_RSRV_ATTACH_SHIFT)
#define INT_CHG_DET_MASK (0x1 << INT_CHG_DET_SHIFT)
/* S2MM001 ADC register */
#define ADC_ADC_SHIFT 0
#define ADC_ADC_MASK (0x1f << ADC_ADC_SHIFT)
/* S2MM001 Timing Set 1 & 2 register Timing table */
#define OCP_TIME_DELAY_1MS (0x00)
#define OCP_TIME_DELAY_2MS (0x01)
#define OCP_TIME_DELAY_4MS (0x02)
#define OCP_TIME_DELAY_8MS (0x03)
#define OCP_TIME_DELAY_12MS (0x04)
#define OCP_TIME_DELAY_16MS (0x05)
#define KEY_PRESS_TIME_100MS (0x00)
#define KEY_PRESS_TIME_200MS (0x10)
#define KEY_PRESS_TIME_300MS (0x20)
#define KEY_PRESS_TIME_700MS (0x60)
#define LONGKEY_PRESS_TIME_300MS (0x00)
#define LONGKEY_PRESS_TIME_500MS (0x02)
#define LONGKEY_PRESS_TIME_1000MS (0x07)
#define LONGKEY_PRESS_TIME_1500MS (0x0C)
#define SWITCHING_WAIT_TIME_10MS (0x00)
#define SWITCHING_WAIT_TIME_210MS (0xa0)
/* S2MM001 Device Type 1 register */
#define DEV_TYPE1_USB_OTG (0x1 << 7)
#define DEV_TYPE1_DEDICATED_CHG (0x1 << 6)
#define DEV_TYPE1_CDP (0x1 << 5)
#define DEV_TYPE1_T1_T2_CHG (0x1 << 4)
#define DEV_TYPE1_UART (0x1 << 3)
#define DEV_TYPE1_USB (0x1 << 2)
#define DEV_TYPE1_AUDIO_2 (0x1 << 1)
#define DEV_TYPE1_AUDIO_1 (0x1 << 0)
#define DEV_TYPE1_USB_TYPES (DEV_TYPE1_USB_OTG | DEV_TYPE1_CDP | \
DEV_TYPE1_USB)
#define DEV_TYPE1_CHG_TYPES (DEV_TYPE1_DEDICATED_CHG | DEV_TYPE1_CDP)
/* S2MM001 Device Type 2 register */
#define DEV_TYPE2_AV (0x1 << 6)
#define DEV_TYPE2_TTY (0x1 << 5)
#define DEV_TYPE2_PPD (0x1 << 4)
#define DEV_TYPE2_JIG_UART_OFF (0x1 << 3)
#define DEV_TYPE2_JIG_UART_ON (0x1 << 2)
#define DEV_TYPE2_JIG_USB_OFF (0x1 << 1)
#define DEV_TYPE2_JIG_USB_ON (0x1 << 0)
#define DEV_TYPE2_JIG_USB_TYPES (DEV_TYPE2_JIG_USB_OFF | \
DEV_TYPE2_JIG_USB_ON)
#define DEV_TYPE2_JIG_UART_TYPES (DEV_TYPE2_JIG_UART_OFF)
#define DEV_TYPE2_JIG_TYPES (DEV_TYPE2_JIG_UART_TYPES | \
DEV_TYPE2_JIG_USB_TYPES)
/* S2MM001 Device Type 3 register */
#define DEV_TYPE3_U200_CHG (0x1 << 6)
#define DEV_TYPE3_APPLE_CHG (0x1 << 5)
#define DEV_TYPE3_AV_WITH_VBUS (0x1 << 4)
#define DEV_TYPE3_NO_STD_CHG (0x1 << 2)
#define DEV_TYPE3_MHL (0x1 << 0)
#define DEV_TYPE3_CHG_TYPE (DEV_TYPE3_U200_CHG | DEV_TYPE3_NO_STD_CHG | \
DEV_TYPE3_APPLE_CHG)
/* S2MM001_MUIC_REG_DEV_T3 register */
#define RSVD1_VBUS (0x1 << 1)
/* S2MM001_MUIC_REG_CTRL2 register */
#define RSVD3_CHGPUMP_nEN (0x1 << 0)
/*
* Manual Switch
* D- [7:5] / D+ [4:2] / CHARGER[1] / OTGEN[0]
* 000: Open all / 001: USB / 010: AUDIO / 011: UART / 100: V_AUDIO
* 00: Vbus to Open / 01: Vbus to Charger / 10: Vbus to MIC / 11: Vbus to VBout
*/
#define MANUAL_SW1_DM_SHIFT 5
#define MANUAL_SW1_DP_SHIFT 2
#define MANUAL_SW1_VBUS_SHIFT 0
#define MANUAL_SW1_D_OPEN (0x0)
#define MANUAL_SW1_D_USB (0x1)
#define MANUAL_SW1_D_AUDIO (0x2)
#define MANUAL_SW1_D_UART (0x3)
#define MANUAL_SW1_V_OPEN (0x0)
#define MANUAL_SW1_V_CHARGER (0x2)
#define MANUAL_SW1_V_OTGEN (0x1)
enum s2mm001_switch_sel_val {
S2MM001_SWITCH_SEL_1st_BIT_USB = (0x1 << 0),
S2MM001_SWITCH_SEL_2nd_BIT_UART = (0x1 << 1),
};
enum s2mm001_reg_manual_sw1_value {
MANSW1_OPEN = (MANUAL_SW1_D_OPEN << MANUAL_SW1_DM_SHIFT) |
(MANUAL_SW1_D_OPEN << MANUAL_SW1_DP_SHIFT) |
(MANUAL_SW1_V_OPEN << MANUAL_SW1_VBUS_SHIFT),
MANSW1_OPEN_WITH_V_BUS = (MANUAL_SW1_D_OPEN << MANUAL_SW1_DM_SHIFT) |
(MANUAL_SW1_D_OPEN << MANUAL_SW1_DP_SHIFT) |
(MANUAL_SW1_V_CHARGER << MANUAL_SW1_VBUS_SHIFT),
MANSW1_USB = (MANUAL_SW1_D_USB << MANUAL_SW1_DM_SHIFT) |
(MANUAL_SW1_D_USB << MANUAL_SW1_DP_SHIFT) |
(MANUAL_SW1_V_CHARGER << MANUAL_SW1_VBUS_SHIFT),
MANSW1_AUDIO = (MANUAL_SW1_D_AUDIO << MANUAL_SW1_DM_SHIFT) |
(MANUAL_SW1_D_AUDIO << MANUAL_SW1_DP_SHIFT) |
(MANUAL_SW1_V_CHARGER << MANUAL_SW1_VBUS_SHIFT),
MANSW1_UART = (MANUAL_SW1_D_UART << MANUAL_SW1_DM_SHIFT) |
(MANUAL_SW1_D_UART << MANUAL_SW1_DP_SHIFT) |
(MANUAL_SW1_V_CHARGER << MANUAL_SW1_VBUS_SHIFT),
MANSW1_OPEN_RUSTPROOF = (MANUAL_SW1_D_OPEN << MANUAL_SW1_DM_SHIFT) |
(MANUAL_SW1_D_UART << MANUAL_SW1_DP_SHIFT) |
(MANUAL_SW1_V_CHARGER << MANUAL_SW1_VBUS_SHIFT),
};
enum s2mm001_muic_reg_init_value {
REG_INTMASK1_VALUE = (0xDC),
REG_INTMASK2_VALUE = (0xA0),
REG_INTMASK2_VBUS = (0x02),
REG_TIMING1_VALUE = (OCP_TIME_DELAY_4MS |
KEY_PRESS_TIME_100MS),
};
/* muic chip specific internal data structure
* that setted at muic-xxxx.c file
*/
struct s2mm001_muic_data {
struct device *dev;
struct i2c_client *i2c; /* i2c addr: 0x4A; MUIC */
struct mutex muic_mutex;
/* muic common callback driver internal data */
struct sec_switch_data *switch_data;
/* model dependant muic platform data */
struct muic_platform_data *pdata;
/* muic support vps list */
bool muic_support_list[ATTACHED_DEV_NUM];
/* muic current attached device */
muic_attached_dev_t attached_dev;
/* muic Device ID */
u8 muic_vendor; /* Vendor ID */
u8 muic_version; /* Version ID */
bool is_usb_ready;
bool is_factory_start;
bool is_rustproof;
struct delayed_work init_work;
struct delayed_work usb_work;
};
extern struct device *switch_device;
extern unsigned int system_rev;
extern struct muic_platform_data muic_pdata;
#endif /* __S2MM001_H__ */

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/*
* Copyright (C) 2015 Samsung Electronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __S2MU005_MUIC_H__
#define __S2MU005_MUIC_H__
#include <linux/muic/muic.h>
#define MUIC_DEV_NAME "muic-s2mu005"
/* s2mu005 muic register read/write related information defines. */
/* S2MU005 Control register */
#define CTRL_SWITCH_OPEN_SHIFT 4
#define CTRL_RAW_DATA_SHIFT 3
#define CTRL_MANUAL_SW_SHIFT 2
#define CTRL_WAIT_SHIFT 1
#define CTRL_INT_MASK_SHIFT 0
#define CTRL_SWITCH_OPEN_MASK (0x1 << CTRL_SWITCH_OPEN_SHIFT)
#define CTRL_RAW_DATA_MASK (0x1 << CTRL_RAW_DATA_SHIFT)
#define CTRL_MANUAL_SW_MASK (0x1 << CTRL_MANUAL_SW_SHIFT)
#define CTRL_WAIT_MASK (0x1 << CTRL_WAIT_SHIFT)
#define CTRL_INT_MASK_MASK (0x1 << CTRL_INT_MASK_SHIFT)
#ifdef CONFIG_MUIC_S2MU005_ENABLE_AUTOSW
#define CTRL_MASK (CTRL_SWITCH_OPEN_MASK | \
CTRL_MANUAL_SW_MASK | CTRL_WAIT_MASK | \
CTRL_INT_MASK_MASK)
#else
#define CTRL_MASK (CTRL_SWITCH_OPEN_MASK | \
CTRL_WAIT_MASK | CTRL_INT_MASK_MASK)
#endif
/* S2MU005 MUIC Interrupt 1 register */
#define INT_RID_CHG_SHIFT 5
#define INT_LKR_SHIFT 4
#define INT_LKP_SHIFT 3
#define INT_KP_SHIFT 2
#define INT_DETACH_SHIFT 1
#define INT_ATTACH_SHIFT 0
#define INT_RID_CHG_MASK (0x1 << INT_OVP_EN_SHIFT)
#define INT_LKR_MASK (0x1 << INT_LKR_SHIFT)
#define INT_LKP_MASK (0x1 << INT_LKP_SHIFT)
#define INT_KP_MASK (0x1 << INT_KP_SHIFT)
#define INT_DETACH_MASK (0x1 << INT_DETACH_SHIFT)
#define INT_ATTACH_MASK (0x1 << INT_ATTACH_SHIFT)
/* S2MU005 MUIC Interrupt 2 register */
#define INT_ADC_CHANGE_SHIFT 2
#define INT_RSRV_ATTACH_SHIFT 1
#define INT_CHG_DET_SHIFT 0
#define INT_ADC_CHANGE_MASK (0x1 << INT_ADC_CHANGE_SHIFT)
#define INT_RSRV_ATTACH_MASK (0x1 << INT_RSRV_ATTACH_SHIFT)
#define INT_VBUS_ON_MASK (0x1 << INT_CHG_DET_SHIFT)
/* S2MU005 ADC register */
#define ADC_MASK (0x1f)
#define ADC_CONVERSION_MASK (0x1 << 7)
/* S2MU005 Timing Set 1 & 2 register Timing table */
#define KEY_PRESS_TIME_100MS (0x00)
#define KEY_PRESS_TIME_200MS (0x10)
#define KEY_PRESS_TIME_300MS (0x20)
#define KEY_PRESS_TIME_700MS (0x60)
#define LONGKEY_PRESS_TIME_300MS (0x00)
#define LONGKEY_PRESS_TIME_500MS (0x02)
#define LONGKEY_PRESS_TIME_1000MS (0x07)
#define LONGKEY_PRESS_TIME_1500MS (0x0C)
#define SWITCHING_WAIT_TIME_10MS (0x00)
#define SWITCHING_WAIT_TIME_210MS (0xa0)
/* S2MU005 MUIC Device Type 1 register */
#define DEV_TYPE1_USB_OTG (0x1 << 7)
#define DEV_TYPE1_DEDICATED_CHG (0x1 << 6)
#define DEV_TYPE1_CDP (0x1 << 5)
#define DEV_TYPE1_T1_T2_CHG (0x1 << 4)
#define DEV_TYPE1_UART (0x1 << 3)
#define DEV_TYPE1_USB (0x1 << 2)
#define DEV_TYPE1_AUDIO_2 (0x1 << 1)
#define DEV_TYPE1_AUDIO_1 (0x1 << 0)
#define DEV_TYPE1_USB_TYPES (DEV_TYPE1_USB_OTG | DEV_TYPE1_CDP | DEV_TYPE1_USB)
#define DEV_TYPE1_CHG_TYPES (DEV_TYPE1_DEDICATED_CHG | DEV_TYPE1_CDP)
/* S2MU005 MUIC Device Type 2 register */
#define DEV_TYPE2_SDP_1P8S (0x1 << 7)
#define DEV_TYPE2_AV (0x1 << 6)
#define DEV_TYPE2_TTY (0x1 << 5)
#define DEV_TYPE2_PPD (0x1 << 4)
#define DEV_TYPE2_JIG_UART_OFF (0x1 << 3)
#define DEV_TYPE2_JIG_UART_ON (0x1 << 2)
#define DEV_TYPE2_JIG_USB_OFF (0x1 << 1)
#define DEV_TYPE2_JIG_USB_ON (0x1 << 0)
#define DEV_TYPE2_JIG_USB_TYPES (DEV_TYPE2_JIG_USB_OFF | DEV_TYPE2_JIG_USB_ON)
#define DEV_TYPE2_JIG_UART_TYPES (DEV_TYPE2_JIG_UART_OFF)
#define DEV_TYPE2_JIG_TYPES (DEV_TYPE2_JIG_UART_TYPES | DEV_TYPE2_JIG_USB_TYPES)
/* S2MU005 MUIC Device Type 3 register */
#define DEV_TYPE3_U200_CHG (0x1 << 7)
#define DEV_TYPE3_AV_WITH_VBUS (0x1 << 4)
#define DEV_TYPE3_VBUS_R255 (0x1 << 1)
#define DEV_TYPE3_MHL (0x1 << 0)
#define DEV_TYPE3_CHG_TYPE (DEV_TYPE3_U200_CHG | DEV_TYPE3_VBUS_R255)
/* S2MU005 MUIC APPLE Device Type register */
#define DEV_TYPE_APPLE_APPLE0P5A_CHG (0x1 << 7)
#define DEV_TYPE_APPLE_APPLE1A_CHG (0x1 << 6)
#define DEV_TYPE_APPLE_APPLE2A_CHG (0x1 << 5)
#define DEV_TYPE_APPLE_APPLE2P4A_CHG (0x1 << 4)
#define DEV_TYPE_APPLE_SDP_DCD_OUT (0x1 << 3)
#define DEV_TYPE_APPLE_RID_WAKEUP (0x1 << 2)
#define DEV_TYPE_APPLE_VBUS_WAKEUP (0x1 << 1)
#define DEV_TYPE_APPLE_BCV1P2_OR_OPEN (0x1 << 0)
/* S2MU005 MUIC CHG Type register */
#define CHG_TYPE_VBUS_R255 (0x1 << 7)
#define DEV_TYPE_U200 (0x1 << 4)
#define DEV_TYPE_SDP_1P8S (0x1 << 3)
#define DEV_TYPE_USB (0x1 << 2)
#define DEV_TYPE_CDPCHG (0x1 << 1)
#define DEV_TYPE_DCPCHG (0x1 << 0)
#define DEV_TYPE_CHG_TYPE (CHG_TYPE_VBUS_R255 | DEV_TYPE_U200 | DEV_TYPE_SDP_1P8S)
#define MANUAL_SW_JIG_EN (0x1 << 0)
/*
* Manual Switch
* D- [7:5] / D+ [4:2] / CHARGER[1] / OTGEN[0]
* 000: Open all / 001: USB / 010: AUDIO / 011: UART / 100: V_AUDIO
* 00: Vbus to Open / 01: Vbus to Charger / 10: Vbus to MIC / 11: Vbus to VBout
*/
#define MANUAL_SW_DM_SHIFT 5
#define MANUAL_SW_DP_SHIFT 2
#define MANUAL_SW_CHG_SHIFT 1
#define MANUAL_SW_DM_DP_MASK 0xFC
#define MANUAL_SW_OPEN (0x0)
#define MANUAL_SW_USB (0x1 << MANUAL_SW_DM_SHIFT | 0x1 << MANUAL_SW_DP_SHIFT)
#define MANUAL_SW_UART (0x2 << MANUAL_SW_DM_SHIFT | 0x2 << MANUAL_SW_DP_SHIFT)
#define MANUAL_SW_UART2 (0x3 << MANUAL_SW_DM_SHIFT | 0x3 << MANUAL_SW_DP_SHIFT)
#define MANUAL_SW_AUDIO (0x0 << MANUAL_SW_DM_SHIFT | 0x0 << MANUAL_SW_DP_SHIFT) /* Not Used */
#define MANUAL_SW_OTGEN (0x1)
#define MANUAL_SW_CHARGER (0x1 << MANUAL_SW_CHG_SHIFT)
enum s2mu005_reg_manual_sw_value {
MANSW_OPEN = (MANUAL_SW_OPEN),
MANSW_OPEN_WITH_VBUS = (MANUAL_SW_CHARGER),
MANSW_USB = (MANUAL_SW_USB | MANUAL_SW_CHARGER),
MANSW_AUDIO = (MANUAL_SW_AUDIO | MANUAL_SW_CHARGER), /* Not Used */
MANSW_OTG = (MANUAL_SW_USB | MANUAL_SW_OTGEN),
MANSW_UART = (MANUAL_SW_UART | MANUAL_SW_CHARGER),
MANSW_OPEN_RUSTPROOF = (MANUAL_SW_OPEN | MANUAL_SW_CHARGER),
};
/* muic chip specific internal data structure
* that setted at muic-xxxx.c file
*/
struct s2mu005_muic_data {
struct device *dev;
struct i2c_client *i2c; /* i2c addr: 0x7A; MUIC */
struct mutex muic_mutex;
/* model dependant mfd platform data */
struct s2mu005_platform_data *mfd_pdata;
int irq_attach;
int irq_detach;
int irq_rid_chg;
int irq_vbus_on;
int irq_rsvd_attach;
int irq_adc_change;
int irq_av_charge;
int irq_vbus_off;
/* muic common callback driver internal data */
struct sec_switch_data *switch_data;
/* model dependant muic platform data */
struct muic_platform_data *pdata;
/* muic support vps list */
bool muic_support_list[ATTACHED_DEV_NUM];
/* muic current attached device */
muic_attached_dev_t attached_dev;
/* muic Device ID */
u8 muic_vendor; /* Vendor ID */
u8 muic_version; /* Version ID */
bool is_usb_ready;
bool is_factory_start;
bool is_rustproof;
bool is_otg_test;
#if !defined(CONFIG_MUIC_S2MU005_ENABLE_AUTOSW)
bool is_jig_on;
#endif
/* W/A waiting for the charger ic */
bool suspended;
bool need_to_noti;
struct workqueue_struct *muic_wqueue;
int rev_id;
};
extern struct device *switch_device;
extern unsigned int system_rev;
extern struct muic_platform_data muic_pdata;
#endif /* __S2MU005_MUIC_H__ */

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/*
* Copyright (C) 2016 Samsung Electronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __SM5504_H__
#define __SM5504_H__
#include <linux/muic/muic.h>
#define MUIC_DEV_NAME "muic-sm5504"
/* SM5504 MUIC registers */
enum {
SM5504_MUIC_REG_DEV_ID = 0x01,
SM5504_MUIC_REG_CTRL = 0x02,
SM5504_MUIC_REG_INT1 = 0x03,
SM5504_MUIC_REG_INT2 = 0x04,
SM5504_MUIC_REG_INT_MASK1 = 0x05,
SM5504_MUIC_REG_INT_MASK2 = 0x06,
SM5504_MUIC_REG_ADC = 0x07,
SM5504_MUIC_REG_DEV_TYPE1 = 0x0A,
SM5504_MUIC_REG_DEV_TYPE2 = 0x0B,
SM5504_MUIC_REG_MAN_SW1 = 0x13,
SM5504_MUIC_REG_MAN_SW2 = 0x14,
SM5504_MUIC_REG_RESET = 0x1B,
SM5504_MUIC_REG_CHG = 0x24,
SM5504_MUIC_REG_SET = 0x20,
SM5504_MUIC_REG_END,
};
/* CONTROL : REG_CTRL */
#define ADC_EN (1 << 7)
#define USBCHDEN (1 << 6)
#define CHGTYP (1 << 5)
#define SWITCH_OPEN (1 << 4)
#define MANUAL_SWITCH (1 << 2)
#define MASK_INT (1 << 0)
#define CTRL_INIT (ADC_EN | USBCHDEN | CHGTYP | MANUAL_SWITCH)
#define RESET_DEFAULT (ADC_EN | USBCHDEN | CHGTYP | MANUAL_SWITCH | MASK_INT)
/* INTERRUPT 1 : REG_INT1 */
#define ADC_CHG (1 << 6)
#define CONNECT (1 << 5)
#define OVP (1 << 4)
#define DCD_OUT (1 << 3)
#define CHGDET (1 << 2)
#define DETACH (1 << 1)
#define ATTACH (1 << 0)
/* INTERRUPT 2 : REG_INT2 */
#define OVP_OCP (1 << 7)
#define OCP (1 << 6)
#define OCP_LATCH (1 << 5)
#define OVP_FET (1 << 4)
#define POR (1 << 2)
#define UVLO (1 << 1) /* vbus */
#define RID_CHARGER (1 << 0)
#define INT_UVLO_MASK UVLO
/* INTMASK 1 : REG_INT1_MASK */
#define ADC_CHG_M (1 << 6)
#define CONNECT_M (1 << 5)
#define OVP_M (1 << 4)
#define DCD_OUT_M (1 << 3)
#define CHGDET_M (1 << 2)
#define DETACH_M (1 << 1)
#define ATTACH_M (1 << 0)
#define INTMASK1_INIT (ADC_CHG_M | CONNECT_M | OVP_M | DCD_OUT_M | CHGDET_M)
#define INTMASK1_CHGDET (CHGDET_M)
/* INTMASK 2 : REG_INT2_MASK */
#define OVP_OCP_M (1 << 7)
#define OCP_M (1 << 6)
#define OCP_LATCH_M (1 << 5)
#define OVP_FET_M (1 << 4)
#define POR_M (1 << 2)
#define UVLO_M (1 << 1)
#define RID_CHARGER_M (1 << 0)
#define INTMASK2_INIT (0x80)
//#define INTMASK2_INIT (OVP_OCP_M | POR_M | !UVLO_M | RID_CHARGER_M)
/* ADC : REG_ADC */
#define ADC_MASK (0x1F)
/* DEVICE TYPE 1 : REG_DEV_T1 */
#define DEV_DCP (1 << 6) /* Max 1.5A */
#define DEV_CDP (1 << 5) /* Max 1.5A with Data */
#define DEV_CARKIT_T1 (1 << 4)
#define DEV_UART (1 << 3)
#define DEV_SDP (1 << 2) /* Max 500mA with Data */
#define DEV_OTG (1 << 0)
#define DEV_CHARGER (DEV_DEDICATED_CHG | DEV_USB_CHG)
#define SM5504_DEV_OTG (DEV_OTG)
#define SM5504_DEV_SDP (DEV_SDP)
#define SM5504_DEV_UART (DEV_UART)
#define SM5504_DEV_CDP (DEV_CDP)
#define SM5504_DEV_DCP (DEV_DCP)
/* DEVICE TYPE 2 : REG_DEV_T2 */
#define DEV_UNKNOWN (1 << 7)
#define DEV_JIG_UART_OFF (1 << 3)
#define DEV_JIG_UART_ON (1 << 2)
#define DEV_JIG_USB_OFF (1 << 1)
#define DEV_JIG_USB_ON (1 << 0)
#define DEV_JIG_ALL (DEV_JIG_UART_OFF | DEV_JIG_UART_ON | DEV_JIG_USB_OFF | DEV_JIG_USB_ON)
#define DEV_JIG_WAKEUP (DEV_JIG_UART_OFF | DEV_JIG_UART_ON | DEV_JIG_USB_ON)
#define SM5504_DEV_JIG_USB_ON (DEV_JIG_USB_ON)
#define SM5504_DEV_JIG_USB_OFF (DEV_JIG_USB_OFF)
#define SM5504_DEV_JIG_UART_ON (DEV_JIG_UART_ON)
#define SM5504_DEV_JIG_UART_OFF (DEV_JIG_UART_OFF)
#define SM5504_DEV_JIG_UNKNOWN (DEV_UNKNOWN)
/* MANUAL SWITCH 1 : REG_MANSW1
* D- [7:5] / D+ [4:2]
* 000: Open all / 001: USB / 011: UART
*/
#define DM_SHIFT (5)
#define DP_SHIFT (2)
#define COM_OPEM (0 << DM_SHIFT) | (0 << DP_SHIFT)
#define COM_TO_USB (1 << DM_SHIFT) | (1 << DP_SHIFT) /* 0010 0100 */
#define COM_TO_AUDIO (2 << DM_SHIFT) | (2 << DP_SHIFT)
#define COM_TO_UART (3 << DM_SHIFT) | (3 << DP_SHIFT) /* 0110 1100 */
#define MANUAL_SW1_MASK (0xFC)
/* MANUAL SWITCH 2 : REG_MANSW2 */
#define BOOT_SW (1 << 3)
#define JIG_ON (1 << 2)
#define VBUS_FET_ONOFF (1 << 0)
/* RESET : REG_RESET */
#define IC_RESET (1 << 0)
/* Setting Register */
#define VBUS_300MS (0x06)
#define VBUS_140MS (0x0E)
/* muic chip specific internal data structure
* that setted at muic-xxxx.c file
*/
struct sm5504_muic_data {
struct device *dev;
struct i2c_client *i2c; /* i2c addr: 0x4A; MUIC */
struct mutex muic_mutex;
/* muic common callback driver internal data */
struct sec_switch_data *switch_data;
/* model dependancy muic platform data */
struct muic_platform_data *pdata;
/* muic support vps list */
bool muic_support_list[ATTACHED_DEV_NUM];
/* muic current attached device */
muic_attached_dev_t attached_dev;
/* muic Device ID */
u8 muic_vendor; /* Vendor ID */
u8 muic_version; /* Version ID */
bool is_usb_ready;
bool is_factory_start;
bool is_rustproof;
bool is_otg_test;
bool vbus_ignore;
/* W/A waiting for the charger ic */
bool suspended;
bool need_to_noti;
struct wake_lock muic_wake_lock;
int rev_id;
// OTG enable W/A for JAVA Rev03 board
u8 otg_en;
int vbvolt;
};
extern struct device *switch_device;
extern struct muic_platform_data muic_pdata;
#endif /* __SM5504_H__ */

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/*
* Copyright (C) 2010 Samsung Electronics
* Seung-Jin Hahn <sjin.hahn@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __TSU6721_H__
#define __TSU6721_H__
#include <linux/muic/muic.h>
#define MUIC_DEV_NAME "muic-tsu6721"
/* tsu6721 muic register read/write related information defines. */
/* Slave addr = 0x4A: MUIC */
/* TSU6721 I2C registers */
enum tsu6721_muic_reg {
TSU6721_MUIC_REG_DEVID = 0x01,
TSU6721_MUIC_REG_CTRL = 0x02,
TSU6721_MUIC_REG_INT1 = 0x03,
TSU6721_MUIC_REG_INT2 = 0x04,
TSU6721_MUIC_REG_INTMASK1 = 0x05,
TSU6721_MUIC_REG_INTMASK2 = 0x06,
TSU6721_MUIC_REG_ADC = 0x07,
/* unused registers */
#if 0
TSU6721_MUIC_REG_TIMING1 = 0x08,
TSU6721_MUIC_REG_TIMING2 = 0x09,
#endif
TSU6721_MUIC_REG_DEV_T1 = 0x0a,
TSU6721_MUIC_REG_DEV_T2 = 0x0b,
/* unused registers */
#if 0
TSU6721_MUIC_REG_BUTTON1 = 0x0c,
TSU6721_MUIC_REG_BUTTON2 = 0x0d,
TSU6721_MUIC_REG_CK_STATUS = 0x0e,
TSU6721_MUIC_REG_CK_INT1 = 0x0f,
TSU6721_MUIC_REG_CK_INT2 = 0x10,
TSU6721_MUIC_REG_CK_INTMASK1 = 0x11,
TSU6721_MUIC_REG_CK_INTMASK2 = 0x12,
#endif
TSU6721_MUIC_REG_MANSW1 = 0x13,
TSU6721_MUIC_REG_MANSW2 = 0x14,
TSU6721_MUIC_REG_DEV_T3 = 0x15,
TSU6721_MUIC_REG_RESET = 0x1B,
TSU6721_MUIC_REG_TIMER_SET = 0x20,
TSU6721_MUIC_REG_OCL_OCP_SET1 = 0x21,
TSU6721_MUIC_REG_OCL_OCP_SET2 = 0x22,
TSU6721_MUIC_REG_DEV_T4 = 0x23,
TSU6721_MUIC_REG_END,
};
/* TSU6721 REGISTER ENABLE or DISABLE bit */
#define TSU6721_ENABLE_BIT 1
#define TSU6721_DISABLE_BIT 0
/* TSU6721 Control register */
#define CTRL_SWITCH_OPEN_SHIFT 4
#define CTRL_RAW_DATA_SHIFT 3
#define CTRL_MANUAL_SW_SHIFT 2
#define CTRL_WAIT_SHIFT 1
#define CTRL_INT_MASK_SHIFT 0
#define CTRL_SWITCH_OPEN_MASK (0x1 << CTRL_SWITCH_OPEN_SHIFT)
#define CTRL_RAW_DATA_MASK (0x1 << CTRL_RAW_DATA_SHIFT)
#define CTRL_MANUAL_SW_MASK (0x1 << CTRL_MANUAL_SW_SHIFT)
#define CTRL_WAIT_MASK (0x1 << CTRL_WAIT_SHIFT)
#define CTRL_INT_MASK_MASK (0x1 << CTRL_INT_MASK_SHIFT)
#define CTRL_MASK (CTRL_SWITCH_OPEN_MASK | CTRL_RAW_DATA_MASK | \
CTRL_MANUAL_SW_MASK | CTRL_WAIT_MASK | \
CTRL_INT_MASK_MASK)
/* TSU6721 Interrupt 1 register */
#define INT_OVP_EN_SHIFT 5
#define INT_LKR_SHIFT 4
#define INT_LKP_SHIFT 3
#define INT_KP_SHIFT 2
#define INT_DETACH_SHIFT 1
#define INT_ATTACH_SHIFT 0
#define INT_OVP_EN_MASK (0x1 << INT_OVP_EN_SHIFT)
#define INT_LKR_MASK (0x1 << INT_LKR_SHIFT)
#define INT_LKP_MASK (0x1 << INT_LKP_SHIFT)
#define INT_KP_MASK (0x1 << INT_KP_SHIFT)
#define INT_DETACH_MASK (0x1 << INT_DETACH_SHIFT)
#define INT_ATTACH_MASK (0x1 << INT_ATTACH_SHIFT)
/* TSU6721 Interrupt 2 register */
#define INT_ADC_CHANGE_SHIFT 2
#define INT_RSRV_ATTACH_SHIFT 1
#define INT_AV_CHARGING_SHIFT 0
#define INT_ADC_CHANGE_MASK (0x1 << INT_ADC_CHANGE_SHIFT)
#define INT_RSRV_ATTACH_MASK (0x1 << INT_RSRV_ATTACH_SHIFT)
#define INT_AV_CHARGING_MASK (0x1 << INT_AV_CHARGING_SHIFT)
/* TSU6721 ADC register */
#define ADC_ADC_SHIFT 0
#define ADC_ADC_MASK (0x1f << ADC_ADC_SHIFT)
/* TSU6721 Timing Set 1 & 2 register Timing table */
#define ADC_DETECT_TIME_50MS (0x00)
#define ADC_DETECT_TIME_100MS (0x01)
#define ADC_DETECT_TIME_150MS (0x02)
#define ADC_DETECT_TIME_200MS (0x03)
#define ADC_DETECT_TIME_300MS (0x04)
#define ADC_DETECT_TIME_400MS (0x05)
#define ADC_DETECT_TIME_500MS (0x06)
#define ADC_DETECT_TIME_600MS (0x07)
#define ADC_DETECT_TIME_700MS (0x08)
#define ADC_DETECT_TIME_800MS (0x09)
#define ADC_DETECT_TIME_900MS (0x0a)
#define ADC_DETECT_TIME_1000MS (0x0b)
#define KEY_PRESS_TIME_100MS (0x00)
#define KEY_PRESS_TIME_200MS (0x10)
#define KEY_PRESS_TIME_300MS (0x20)
#define KEY_PRESS_TIME_700MS (0x60)
#define LONGKEY_PRESS_TIME_300MS (0x00)
#define LONGKEY_PRESS_TIME_500MS (0x02)
#define LONGKEY_PRESS_TIME_1000MS (0x07)
#define LONGKEY_PRESS_TIME_1500MS (0x0C)
#define SWITCHING_WAIT_TIME_10MS (0x00)
#define SWITCHING_WAIT_TIME_210MS (0xa0)
/* TSU6721 Device Type 1 register */
#define DEV_TYPE1_USB_OTG (0x1 << 7)
#define DEV_TYPE1_DEDICATED_CHG (0x1 << 6)
#define DEV_TYPE1_CDP (0x1 << 5)
#define DEV_TYPE1_T1_T2_CHG (0x1 << 4)
#define DEV_TYPE1_UART (0x1 << 3)
#define DEV_TYPE1_USB (0x1 << 2)
#define DEV_TYPE1_AUDIO_2 (0x1 << 1)
#define DEV_TYPE1_AUDIO_1 (0x1 << 0)
#define DEV_TYPE1_USB_TYPES (DEV_TYPE1_USB_OTG | DEV_TYPE1_CDP | \
DEV_TYPE1_USB)
#define DEV_TYPE1_CHG_TYPES (DEV_TYPE1_DEDICATED_CHG | DEV_TYPE1_CDP)
/* TSU6721 Device Type 2 register */
#define DEV_TYPE2_AV (0x1 << 6)
#define DEV_TYPE2_TTY (0x1 << 5)
#define DEV_TYPE2_PPD (0x1 << 4)
#define DEV_TYPE2_JIG_UART_OFF (0x1 << 3)
#define DEV_TYPE2_JIG_UART_ON (0x1 << 2)
#define DEV_TYPE2_JIG_USB_OFF (0x1 << 1)
#define DEV_TYPE2_JIG_USB_ON (0x1 << 0)
#define DEV_TYPE2_JIG_USB_TYPES (DEV_TYPE2_JIG_USB_OFF | \
DEV_TYPE2_JIG_USB_ON)
#define DEV_TYPE2_JIG_UART_TYPES (DEV_TYPE2_JIG_UART_OFF)
#define DEV_TYPE2_JIG_TYPES (DEV_TYPE2_JIG_UART_TYPES | \
DEV_TYPE2_JIG_USB_TYPES)
/* TSU6721 Device Type 3 register */
#define DEV_TYPE3_VIDEO (0x1 << 7)
#define DEV_TYPE3_U200_CHG (0x1 << 6)
#define DEV_TYPE3_APPLE_CHG (0x1 << 5)
#define DEV_TYPE3_AV_WITH_VBUS (0x1 << 4)
#define DEV_TYPE3_NON_STANDART_CHG (0x1 << 2)
#define DEV_TYPE3_VBVOLT (0x1 << 1)
#define DEV_TYPE3_MHL (0x1 << 0)
#define DEV_TYPE3_CHG_TYPE (DEV_TYPE3_U200_CHG | DEV_TYPE3_APPLE_CHG | \
DEV_TYPE3_NON_STANDART_CHG)
/*
* Manual Switch : Manual S/W 1
* D- [7:5] / D+ [4:2] / Vbus [1:0]
* 000: Open all / 001: USB / 010: AUDIO / 011: UART / 100: V_AUDIO
* 00: Vbus to Open / 01: Vbus to Charger / 10: Vbus to MIC / 11: Vbus to Open
* Just for FSA9485
*/
#define MANUAL_SW1_DM_SHIFT 5
#define MANUAL_SW1_DP_SHIFT 2
#define MANUAL_SW1_VBUS_SHIFT 0
#define MANUAL_SW1_D_OPEN (0x0)
#define MANUAL_SW1_D_USB (0x1)
#define MANUAL_SW1_D_AUDIO (0x2)
#define MANUAL_SW1_D_UART (0x3)
#define MANUAL_SW1_V_OPEN (0x0)
#define MANUAL_SW1_V_CHARGER (0x1)
#define MANUAL_SW1_V_MIC (0x2)
enum tsu6721_switch_sel_val {
TSU6721_SWITCH_SEL_1st_BIT_USB = (0x1 << 0),
TSU6721_SWITCH_SEL_2nd_BIT_UART = (0x1 << 1),
};
enum tsu6721_reg_manual_sw1_value {
MANSW1_OPEN = (MANUAL_SW1_D_OPEN << MANUAL_SW1_DM_SHIFT) | \
(MANUAL_SW1_D_OPEN << MANUAL_SW1_DP_SHIFT) | \
(MANUAL_SW1_V_OPEN << MANUAL_SW1_VBUS_SHIFT),
MANSW1_OPEN_WITH_V_BUS = (MANUAL_SW1_D_OPEN << MANUAL_SW1_DM_SHIFT) | \
(MANUAL_SW1_D_OPEN << MANUAL_SW1_DP_SHIFT) | \
(MANUAL_SW1_V_CHARGER << MANUAL_SW1_VBUS_SHIFT),
MANSW1_USB = (MANUAL_SW1_D_USB << MANUAL_SW1_DM_SHIFT) | \
(MANUAL_SW1_D_USB << MANUAL_SW1_DP_SHIFT) | \
(MANUAL_SW1_V_CHARGER << MANUAL_SW1_VBUS_SHIFT),
MANSW1_AUDIO = (MANUAL_SW1_D_AUDIO << MANUAL_SW1_DM_SHIFT) | \
(MANUAL_SW1_D_AUDIO << MANUAL_SW1_DP_SHIFT) | \
(MANUAL_SW1_V_OPEN << MANUAL_SW1_VBUS_SHIFT),
MANSW1_UART = (MANUAL_SW1_D_UART << MANUAL_SW1_DM_SHIFT) | \
(MANUAL_SW1_D_UART << MANUAL_SW1_DP_SHIFT) | \
(MANUAL_SW1_V_OPEN << MANUAL_SW1_VBUS_SHIFT),
};
/*
* Manual Switch : Manual S/W 2
*/
#define MANUAL_SW2_ISET_SHIFT 4
#define MANUAL_SW2_ISET_OFF 0
#define MANUAL_SW2_ISET_ON 1
enum tsu6721_reg_manual_sw2_value {
MANSW2_CHARGER_ON = (MANUAL_SW2_ISET_ON << MANUAL_SW2_ISET_SHIFT),
MANSW2_CHARGER_OFF = (MANUAL_SW2_ISET_OFF << MANUAL_SW2_ISET_SHIFT),
};
enum tsu6721_muic_reg_init_value {
REG_INTMASK1_VALUE = (0x5c),
REG_INTMASK2_VALUE = (0xb8),
REG_TIMING1_VALUE = (ADC_DETECT_TIME_50MS | \
KEY_PRESS_TIME_100MS),
REG_TIMING2_VALUE = (LONGKEY_PRESS_TIME_300MS | \
SWITCHING_WAIT_TIME_10MS),
};
/* muic chip specific internal data structure
* that setted at muic-xxxx.c file
*/
struct tsu6721_muic_data {
struct device *dev;
struct i2c_client *i2c; /* i2c addr: 0x4A; MUIC */
struct mutex muic_mutex;
/* muic common callback driver internal data */
struct sec_switch_data *switch_data;
/* model dependant muic platform data */
struct muic_platform_data *pdata;
/* muic current attached device */
muic_attached_dev_t attached_dev;
/* muic Device ID */
u8 muic_vendor; /* Vendor ID */
u8 muic_version; /* Version ID */
bool is_usb_ready;
bool is_factory_start;
struct delayed_work init_work;
struct delayed_work usb_work;
};
extern struct device *switch_device;
extern struct muic_platform_data muic_pdata;
#endif /* __TSU6721_H__ */