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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
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Fixed MTP to work with TWRP
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awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
273
include/linux/muic/tsu6721.h
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273
include/linux/muic/tsu6721.h
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/*
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* Copyright (C) 2010 Samsung Electronics
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* Seung-Jin Hahn <sjin.hahn@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#ifndef __TSU6721_H__
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#define __TSU6721_H__
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#include <linux/muic/muic.h>
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#define MUIC_DEV_NAME "muic-tsu6721"
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/* tsu6721 muic register read/write related information defines. */
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/* Slave addr = 0x4A: MUIC */
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/* TSU6721 I2C registers */
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enum tsu6721_muic_reg {
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TSU6721_MUIC_REG_DEVID = 0x01,
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TSU6721_MUIC_REG_CTRL = 0x02,
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TSU6721_MUIC_REG_INT1 = 0x03,
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TSU6721_MUIC_REG_INT2 = 0x04,
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TSU6721_MUIC_REG_INTMASK1 = 0x05,
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TSU6721_MUIC_REG_INTMASK2 = 0x06,
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TSU6721_MUIC_REG_ADC = 0x07,
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/* unused registers */
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#if 0
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TSU6721_MUIC_REG_TIMING1 = 0x08,
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TSU6721_MUIC_REG_TIMING2 = 0x09,
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#endif
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TSU6721_MUIC_REG_DEV_T1 = 0x0a,
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TSU6721_MUIC_REG_DEV_T2 = 0x0b,
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/* unused registers */
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#if 0
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TSU6721_MUIC_REG_BUTTON1 = 0x0c,
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TSU6721_MUIC_REG_BUTTON2 = 0x0d,
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TSU6721_MUIC_REG_CK_STATUS = 0x0e,
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TSU6721_MUIC_REG_CK_INT1 = 0x0f,
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TSU6721_MUIC_REG_CK_INT2 = 0x10,
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TSU6721_MUIC_REG_CK_INTMASK1 = 0x11,
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TSU6721_MUIC_REG_CK_INTMASK2 = 0x12,
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#endif
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TSU6721_MUIC_REG_MANSW1 = 0x13,
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TSU6721_MUIC_REG_MANSW2 = 0x14,
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TSU6721_MUIC_REG_DEV_T3 = 0x15,
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TSU6721_MUIC_REG_RESET = 0x1B,
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TSU6721_MUIC_REG_TIMER_SET = 0x20,
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TSU6721_MUIC_REG_OCL_OCP_SET1 = 0x21,
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TSU6721_MUIC_REG_OCL_OCP_SET2 = 0x22,
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TSU6721_MUIC_REG_DEV_T4 = 0x23,
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TSU6721_MUIC_REG_END,
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};
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/* TSU6721 REGISTER ENABLE or DISABLE bit */
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#define TSU6721_ENABLE_BIT 1
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#define TSU6721_DISABLE_BIT 0
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/* TSU6721 Control register */
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#define CTRL_SWITCH_OPEN_SHIFT 4
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#define CTRL_RAW_DATA_SHIFT 3
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#define CTRL_MANUAL_SW_SHIFT 2
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#define CTRL_WAIT_SHIFT 1
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#define CTRL_INT_MASK_SHIFT 0
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#define CTRL_SWITCH_OPEN_MASK (0x1 << CTRL_SWITCH_OPEN_SHIFT)
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#define CTRL_RAW_DATA_MASK (0x1 << CTRL_RAW_DATA_SHIFT)
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#define CTRL_MANUAL_SW_MASK (0x1 << CTRL_MANUAL_SW_SHIFT)
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#define CTRL_WAIT_MASK (0x1 << CTRL_WAIT_SHIFT)
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#define CTRL_INT_MASK_MASK (0x1 << CTRL_INT_MASK_SHIFT)
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#define CTRL_MASK (CTRL_SWITCH_OPEN_MASK | CTRL_RAW_DATA_MASK | \
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CTRL_MANUAL_SW_MASK | CTRL_WAIT_MASK | \
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CTRL_INT_MASK_MASK)
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/* TSU6721 Interrupt 1 register */
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#define INT_OVP_EN_SHIFT 5
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#define INT_LKR_SHIFT 4
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#define INT_LKP_SHIFT 3
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#define INT_KP_SHIFT 2
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#define INT_DETACH_SHIFT 1
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#define INT_ATTACH_SHIFT 0
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#define INT_OVP_EN_MASK (0x1 << INT_OVP_EN_SHIFT)
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#define INT_LKR_MASK (0x1 << INT_LKR_SHIFT)
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#define INT_LKP_MASK (0x1 << INT_LKP_SHIFT)
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#define INT_KP_MASK (0x1 << INT_KP_SHIFT)
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#define INT_DETACH_MASK (0x1 << INT_DETACH_SHIFT)
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#define INT_ATTACH_MASK (0x1 << INT_ATTACH_SHIFT)
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/* TSU6721 Interrupt 2 register */
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#define INT_ADC_CHANGE_SHIFT 2
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#define INT_RSRV_ATTACH_SHIFT 1
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#define INT_AV_CHARGING_SHIFT 0
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#define INT_ADC_CHANGE_MASK (0x1 << INT_ADC_CHANGE_SHIFT)
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#define INT_RSRV_ATTACH_MASK (0x1 << INT_RSRV_ATTACH_SHIFT)
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#define INT_AV_CHARGING_MASK (0x1 << INT_AV_CHARGING_SHIFT)
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/* TSU6721 ADC register */
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#define ADC_ADC_SHIFT 0
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#define ADC_ADC_MASK (0x1f << ADC_ADC_SHIFT)
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/* TSU6721 Timing Set 1 & 2 register Timing table */
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#define ADC_DETECT_TIME_50MS (0x00)
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#define ADC_DETECT_TIME_100MS (0x01)
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#define ADC_DETECT_TIME_150MS (0x02)
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#define ADC_DETECT_TIME_200MS (0x03)
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#define ADC_DETECT_TIME_300MS (0x04)
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#define ADC_DETECT_TIME_400MS (0x05)
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#define ADC_DETECT_TIME_500MS (0x06)
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#define ADC_DETECT_TIME_600MS (0x07)
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#define ADC_DETECT_TIME_700MS (0x08)
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#define ADC_DETECT_TIME_800MS (0x09)
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#define ADC_DETECT_TIME_900MS (0x0a)
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#define ADC_DETECT_TIME_1000MS (0x0b)
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#define KEY_PRESS_TIME_100MS (0x00)
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#define KEY_PRESS_TIME_200MS (0x10)
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#define KEY_PRESS_TIME_300MS (0x20)
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#define KEY_PRESS_TIME_700MS (0x60)
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#define LONGKEY_PRESS_TIME_300MS (0x00)
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#define LONGKEY_PRESS_TIME_500MS (0x02)
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#define LONGKEY_PRESS_TIME_1000MS (0x07)
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#define LONGKEY_PRESS_TIME_1500MS (0x0C)
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#define SWITCHING_WAIT_TIME_10MS (0x00)
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#define SWITCHING_WAIT_TIME_210MS (0xa0)
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/* TSU6721 Device Type 1 register */
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#define DEV_TYPE1_USB_OTG (0x1 << 7)
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#define DEV_TYPE1_DEDICATED_CHG (0x1 << 6)
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#define DEV_TYPE1_CDP (0x1 << 5)
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#define DEV_TYPE1_T1_T2_CHG (0x1 << 4)
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#define DEV_TYPE1_UART (0x1 << 3)
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#define DEV_TYPE1_USB (0x1 << 2)
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#define DEV_TYPE1_AUDIO_2 (0x1 << 1)
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#define DEV_TYPE1_AUDIO_1 (0x1 << 0)
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#define DEV_TYPE1_USB_TYPES (DEV_TYPE1_USB_OTG | DEV_TYPE1_CDP | \
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DEV_TYPE1_USB)
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#define DEV_TYPE1_CHG_TYPES (DEV_TYPE1_DEDICATED_CHG | DEV_TYPE1_CDP)
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/* TSU6721 Device Type 2 register */
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#define DEV_TYPE2_AV (0x1 << 6)
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#define DEV_TYPE2_TTY (0x1 << 5)
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#define DEV_TYPE2_PPD (0x1 << 4)
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#define DEV_TYPE2_JIG_UART_OFF (0x1 << 3)
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#define DEV_TYPE2_JIG_UART_ON (0x1 << 2)
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#define DEV_TYPE2_JIG_USB_OFF (0x1 << 1)
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#define DEV_TYPE2_JIG_USB_ON (0x1 << 0)
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#define DEV_TYPE2_JIG_USB_TYPES (DEV_TYPE2_JIG_USB_OFF | \
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DEV_TYPE2_JIG_USB_ON)
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#define DEV_TYPE2_JIG_UART_TYPES (DEV_TYPE2_JIG_UART_OFF)
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#define DEV_TYPE2_JIG_TYPES (DEV_TYPE2_JIG_UART_TYPES | \
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DEV_TYPE2_JIG_USB_TYPES)
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/* TSU6721 Device Type 3 register */
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#define DEV_TYPE3_VIDEO (0x1 << 7)
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#define DEV_TYPE3_U200_CHG (0x1 << 6)
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#define DEV_TYPE3_APPLE_CHG (0x1 << 5)
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#define DEV_TYPE3_AV_WITH_VBUS (0x1 << 4)
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#define DEV_TYPE3_NON_STANDART_CHG (0x1 << 2)
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#define DEV_TYPE3_VBVOLT (0x1 << 1)
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#define DEV_TYPE3_MHL (0x1 << 0)
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#define DEV_TYPE3_CHG_TYPE (DEV_TYPE3_U200_CHG | DEV_TYPE3_APPLE_CHG | \
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DEV_TYPE3_NON_STANDART_CHG)
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/*
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* Manual Switch : Manual S/W 1
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* D- [7:5] / D+ [4:2] / Vbus [1:0]
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* 000: Open all / 001: USB / 010: AUDIO / 011: UART / 100: V_AUDIO
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* 00: Vbus to Open / 01: Vbus to Charger / 10: Vbus to MIC / 11: Vbus to Open
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* Just for FSA9485
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*/
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#define MANUAL_SW1_DM_SHIFT 5
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#define MANUAL_SW1_DP_SHIFT 2
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#define MANUAL_SW1_VBUS_SHIFT 0
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#define MANUAL_SW1_D_OPEN (0x0)
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#define MANUAL_SW1_D_USB (0x1)
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#define MANUAL_SW1_D_AUDIO (0x2)
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#define MANUAL_SW1_D_UART (0x3)
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#define MANUAL_SW1_V_OPEN (0x0)
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#define MANUAL_SW1_V_CHARGER (0x1)
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#define MANUAL_SW1_V_MIC (0x2)
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enum tsu6721_switch_sel_val {
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TSU6721_SWITCH_SEL_1st_BIT_USB = (0x1 << 0),
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TSU6721_SWITCH_SEL_2nd_BIT_UART = (0x1 << 1),
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};
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enum tsu6721_reg_manual_sw1_value {
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MANSW1_OPEN = (MANUAL_SW1_D_OPEN << MANUAL_SW1_DM_SHIFT) | \
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(MANUAL_SW1_D_OPEN << MANUAL_SW1_DP_SHIFT) | \
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(MANUAL_SW1_V_OPEN << MANUAL_SW1_VBUS_SHIFT),
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MANSW1_OPEN_WITH_V_BUS = (MANUAL_SW1_D_OPEN << MANUAL_SW1_DM_SHIFT) | \
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(MANUAL_SW1_D_OPEN << MANUAL_SW1_DP_SHIFT) | \
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(MANUAL_SW1_V_CHARGER << MANUAL_SW1_VBUS_SHIFT),
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MANSW1_USB = (MANUAL_SW1_D_USB << MANUAL_SW1_DM_SHIFT) | \
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(MANUAL_SW1_D_USB << MANUAL_SW1_DP_SHIFT) | \
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(MANUAL_SW1_V_CHARGER << MANUAL_SW1_VBUS_SHIFT),
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MANSW1_AUDIO = (MANUAL_SW1_D_AUDIO << MANUAL_SW1_DM_SHIFT) | \
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(MANUAL_SW1_D_AUDIO << MANUAL_SW1_DP_SHIFT) | \
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(MANUAL_SW1_V_OPEN << MANUAL_SW1_VBUS_SHIFT),
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MANSW1_UART = (MANUAL_SW1_D_UART << MANUAL_SW1_DM_SHIFT) | \
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(MANUAL_SW1_D_UART << MANUAL_SW1_DP_SHIFT) | \
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(MANUAL_SW1_V_OPEN << MANUAL_SW1_VBUS_SHIFT),
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};
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/*
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* Manual Switch : Manual S/W 2
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*/
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#define MANUAL_SW2_ISET_SHIFT 4
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#define MANUAL_SW2_ISET_OFF 0
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#define MANUAL_SW2_ISET_ON 1
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enum tsu6721_reg_manual_sw2_value {
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MANSW2_CHARGER_ON = (MANUAL_SW2_ISET_ON << MANUAL_SW2_ISET_SHIFT),
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MANSW2_CHARGER_OFF = (MANUAL_SW2_ISET_OFF << MANUAL_SW2_ISET_SHIFT),
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};
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enum tsu6721_muic_reg_init_value {
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REG_INTMASK1_VALUE = (0x5c),
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REG_INTMASK2_VALUE = (0xb8),
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REG_TIMING1_VALUE = (ADC_DETECT_TIME_50MS | \
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KEY_PRESS_TIME_100MS),
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REG_TIMING2_VALUE = (LONGKEY_PRESS_TIME_300MS | \
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SWITCHING_WAIT_TIME_10MS),
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};
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/* muic chip specific internal data structure
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* that setted at muic-xxxx.c file
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*/
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struct tsu6721_muic_data {
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struct device *dev;
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struct i2c_client *i2c; /* i2c addr: 0x4A; MUIC */
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struct mutex muic_mutex;
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/* muic common callback driver internal data */
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struct sec_switch_data *switch_data;
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/* model dependant muic platform data */
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struct muic_platform_data *pdata;
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/* muic current attached device */
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muic_attached_dev_t attached_dev;
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/* muic Device ID */
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u8 muic_vendor; /* Vendor ID */
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u8 muic_version; /* Version ID */
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bool is_usb_ready;
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bool is_factory_start;
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struct delayed_work init_work;
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struct delayed_work usb_work;
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};
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extern struct device *switch_device;
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extern struct muic_platform_data muic_pdata;
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#endif /* __TSU6721_H__ */
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