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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
commit f6dfaef42e
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24
include/linux/spi/ad7877.h Normal file
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/* linux/spi/ad7877.h */
/* Touchscreen characteristics vary between boards and models. The
* platform_data for the device's "struct device" holds this information.
*
* It's OK if the min/max values are zero.
*/
struct ad7877_platform_data {
u16 model; /* 7877 */
u16 vref_delay_usecs; /* 0 for external vref; etc */
u16 x_plate_ohms;
u16 y_plate_ohms;
u16 x_min, x_max;
u16 y_min, y_max;
u16 pressure_min, pressure_max;
u8 stopacq_polarity; /* 1 = Active HIGH, 0 = Active LOW */
u8 first_conversion_delay; /* 0 = 0.5us, 1 = 128us, 2 = 1ms, 3 = 8ms */
u8 acquisition_time; /* 0 = 2us, 1 = 4us, 2 = 8us, 3 = 16us */
u8 averaging; /* 0 = 1, 1 = 4, 2 = 8, 3 = 16 */
u8 pen_down_acc_interval; /* 0 = covert once, 1 = every 0.5 ms,
2 = ever 1 ms, 3 = every 8 ms,*/
};

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include/linux/spi/ad7879.h Normal file
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/* linux/spi/ad7879.h */
/* Touchscreen characteristics vary between boards and models. The
* platform_data for the device's "struct device" holds this information.
*
* It's OK if the min/max values are zero.
*/
struct ad7879_platform_data {
u16 model; /* 7879 */
u16 x_plate_ohms;
u16 x_min, x_max;
u16 y_min, y_max;
u16 pressure_min, pressure_max;
bool swap_xy; /* swap x and y axes */
/* [0..255] 0=OFF Starts at 1=550us and goes
* all the way to 9.440ms in steps of 35us.
*/
u8 pen_down_acc_interval;
/* [0..15] Starts at 0=128us and goes all the
* way to 4.096ms in steps of 128us.
*/
u8 first_conversion_delay;
/* [0..3] 0 = 2us, 1 = 4us, 2 = 8us, 3 = 16us */
u8 acquisition_time;
/* [0..3] Average X middle samples 0 = 2, 1 = 4, 2 = 8, 3 = 16 */
u8 averaging;
/* [0..3] Perform X measurements 0 = OFF,
* 1 = 4, 2 = 8, 3 = 16 (median > averaging)
*/
u8 median;
/* 1 = AUX/VBAT/GPIO export GPIO to gpiolib
* requires CONFIG_GPIOLIB
*/
bool gpio_export;
/* identifies the first GPIO number handled by this chip;
* or, if negative, requests dynamic ID allocation.
*/
s32 gpio_base;
};

254
include/linux/spi/adi_spi3.h Normal file
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/*
* Analog Devices SPI3 controller driver
*
* Copyright (c) 2014 Analog Devices Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _ADI_SPI3_H_
#define _ADI_SPI3_H_
#include <linux/types.h>
/* SPI_CONTROL */
#define SPI_CTL_EN 0x00000001 /* Enable */
#define SPI_CTL_MSTR 0x00000002 /* Master/Slave */
#define SPI_CTL_PSSE 0x00000004 /* controls modf error in master mode */
#define SPI_CTL_ODM 0x00000008 /* Open Drain Mode */
#define SPI_CTL_CPHA 0x00000010 /* Clock Phase */
#define SPI_CTL_CPOL 0x00000020 /* Clock Polarity */
#define SPI_CTL_ASSEL 0x00000040 /* Slave Select Pin Control */
#define SPI_CTL_SELST 0x00000080 /* Slave Select Polarity in-between transfers */
#define SPI_CTL_EMISO 0x00000100 /* Enable MISO */
#define SPI_CTL_SIZE 0x00000600 /* Word Transfer Size */
#define SPI_CTL_SIZE08 0x00000000 /* SIZE: 8 bits */
#define SPI_CTL_SIZE16 0x00000200 /* SIZE: 16 bits */
#define SPI_CTL_SIZE32 0x00000400 /* SIZE: 32 bits */
#define SPI_CTL_LSBF 0x00001000 /* LSB First */
#define SPI_CTL_FCEN 0x00002000 /* Flow-Control Enable */
#define SPI_CTL_FCCH 0x00004000 /* Flow-Control Channel Selection */
#define SPI_CTL_FCPL 0x00008000 /* Flow-Control Polarity */
#define SPI_CTL_FCWM 0x00030000 /* Flow-Control Water-Mark */
#define SPI_CTL_FIFO0 0x00000000 /* FCWM: TFIFO empty or RFIFO Full */
#define SPI_CTL_FIFO1 0x00010000 /* FCWM: TFIFO 75% or more empty or RFIFO 75% or more full */
#define SPI_CTL_FIFO2 0x00020000 /* FCWM: TFIFO 50% or more empty or RFIFO 50% or more full */
#define SPI_CTL_FMODE 0x00040000 /* Fast-mode Enable */
#define SPI_CTL_MIOM 0x00300000 /* Multiple I/O Mode */
#define SPI_CTL_MIO_DIS 0x00000000 /* MIOM: Disable */
#define SPI_CTL_MIO_DUAL 0x00100000 /* MIOM: Enable DIOM (Dual I/O Mode) */
#define SPI_CTL_MIO_QUAD 0x00200000 /* MIOM: Enable QUAD (Quad SPI Mode) */
#define SPI_CTL_SOSI 0x00400000 /* Start on MOSI */
/* SPI_RX_CONTROL */
#define SPI_RXCTL_REN 0x00000001 /* Receive Channel Enable */
#define SPI_RXCTL_RTI 0x00000004 /* Receive Transfer Initiate */
#define SPI_RXCTL_RWCEN 0x00000008 /* Receive Word Counter Enable */
#define SPI_RXCTL_RDR 0x00000070 /* Receive Data Request */
#define SPI_RXCTL_RDR_DIS 0x00000000 /* RDR: Disabled */
#define SPI_RXCTL_RDR_NE 0x00000010 /* RDR: RFIFO not empty */
#define SPI_RXCTL_RDR_25 0x00000020 /* RDR: RFIFO 25% full */
#define SPI_RXCTL_RDR_50 0x00000030 /* RDR: RFIFO 50% full */
#define SPI_RXCTL_RDR_75 0x00000040 /* RDR: RFIFO 75% full */
#define SPI_RXCTL_RDR_FULL 0x00000050 /* RDR: RFIFO full */
#define SPI_RXCTL_RDO 0x00000100 /* Receive Data Over-Run */
#define SPI_RXCTL_RRWM 0x00003000 /* FIFO Regular Water-Mark */
#define SPI_RXCTL_RWM_0 0x00000000 /* RRWM: RFIFO Empty */
#define SPI_RXCTL_RWM_25 0x00001000 /* RRWM: RFIFO 25% full */
#define SPI_RXCTL_RWM_50 0x00002000 /* RRWM: RFIFO 50% full */
#define SPI_RXCTL_RWM_75 0x00003000 /* RRWM: RFIFO 75% full */
#define SPI_RXCTL_RUWM 0x00070000 /* FIFO Urgent Water-Mark */
#define SPI_RXCTL_UWM_DIS 0x00000000 /* RUWM: Disabled */
#define SPI_RXCTL_UWM_25 0x00010000 /* RUWM: RFIFO 25% full */
#define SPI_RXCTL_UWM_50 0x00020000 /* RUWM: RFIFO 50% full */
#define SPI_RXCTL_UWM_75 0x00030000 /* RUWM: RFIFO 75% full */
#define SPI_RXCTL_UWM_FULL 0x00040000 /* RUWM: RFIFO full */
/* SPI_TX_CONTROL */
#define SPI_TXCTL_TEN 0x00000001 /* Transmit Channel Enable */
#define SPI_TXCTL_TTI 0x00000004 /* Transmit Transfer Initiate */
#define SPI_TXCTL_TWCEN 0x00000008 /* Transmit Word Counter Enable */
#define SPI_TXCTL_TDR 0x00000070 /* Transmit Data Request */
#define SPI_TXCTL_TDR_DIS 0x00000000 /* TDR: Disabled */
#define SPI_TXCTL_TDR_NF 0x00000010 /* TDR: TFIFO not full */
#define SPI_TXCTL_TDR_25 0x00000020 /* TDR: TFIFO 25% empty */
#define SPI_TXCTL_TDR_50 0x00000030 /* TDR: TFIFO 50% empty */
#define SPI_TXCTL_TDR_75 0x00000040 /* TDR: TFIFO 75% empty */
#define SPI_TXCTL_TDR_EMPTY 0x00000050 /* TDR: TFIFO empty */
#define SPI_TXCTL_TDU 0x00000100 /* Transmit Data Under-Run */
#define SPI_TXCTL_TRWM 0x00003000 /* FIFO Regular Water-Mark */
#define SPI_TXCTL_RWM_FULL 0x00000000 /* TRWM: TFIFO full */
#define SPI_TXCTL_RWM_25 0x00001000 /* TRWM: TFIFO 25% empty */
#define SPI_TXCTL_RWM_50 0x00002000 /* TRWM: TFIFO 50% empty */
#define SPI_TXCTL_RWM_75 0x00003000 /* TRWM: TFIFO 75% empty */
#define SPI_TXCTL_TUWM 0x00070000 /* FIFO Urgent Water-Mark */
#define SPI_TXCTL_UWM_DIS 0x00000000 /* TUWM: Disabled */
#define SPI_TXCTL_UWM_25 0x00010000 /* TUWM: TFIFO 25% empty */
#define SPI_TXCTL_UWM_50 0x00020000 /* TUWM: TFIFO 50% empty */
#define SPI_TXCTL_UWM_75 0x00030000 /* TUWM: TFIFO 75% empty */
#define SPI_TXCTL_UWM_EMPTY 0x00040000 /* TUWM: TFIFO empty */
/* SPI_CLOCK */
#define SPI_CLK_BAUD 0x0000FFFF /* Baud Rate */
/* SPI_DELAY */
#define SPI_DLY_STOP 0x000000FF /* Transfer delay time in multiples of SCK period */
#define SPI_DLY_LEADX 0x00000100 /* Extended (1 SCK) LEAD Control */
#define SPI_DLY_LAGX 0x00000200 /* Extended (1 SCK) LAG control */
/* SPI_SSEL */
#define SPI_SLVSEL_SSE1 0x00000002 /* SPISSEL1 Enable */
#define SPI_SLVSEL_SSE2 0x00000004 /* SPISSEL2 Enable */
#define SPI_SLVSEL_SSE3 0x00000008 /* SPISSEL3 Enable */
#define SPI_SLVSEL_SSE4 0x00000010 /* SPISSEL4 Enable */
#define SPI_SLVSEL_SSE5 0x00000020 /* SPISSEL5 Enable */
#define SPI_SLVSEL_SSE6 0x00000040 /* SPISSEL6 Enable */
#define SPI_SLVSEL_SSE7 0x00000080 /* SPISSEL7 Enable */
#define SPI_SLVSEL_SSEL1 0x00000200 /* SPISSEL1 Value */
#define SPI_SLVSEL_SSEL2 0x00000400 /* SPISSEL2 Value */
#define SPI_SLVSEL_SSEL3 0x00000800 /* SPISSEL3 Value */
#define SPI_SLVSEL_SSEL4 0x00001000 /* SPISSEL4 Value */
#define SPI_SLVSEL_SSEL5 0x00002000 /* SPISSEL5 Value */
#define SPI_SLVSEL_SSEL6 0x00004000 /* SPISSEL6 Value */
#define SPI_SLVSEL_SSEL7 0x00008000 /* SPISSEL7 Value */
/* SPI_RWC */
#define SPI_RWC_VALUE 0x0000FFFF /* Received Word-Count */
/* SPI_RWCR */
#define SPI_RWCR_VALUE 0x0000FFFF /* Received Word-Count Reload */
/* SPI_TWC */
#define SPI_TWC_VALUE 0x0000FFFF /* Transmitted Word-Count */
/* SPI_TWCR */
#define SPI_TWCR_VALUE 0x0000FFFF /* Transmitted Word-Count Reload */
/* SPI_IMASK */
#define SPI_IMSK_RUWM 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */
#define SPI_IMSK_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */
#define SPI_IMSK_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */
#define SPI_IMSK_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */
#define SPI_IMSK_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */
#define SPI_IMSK_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */
#define SPI_IMSK_RSM 0x00000100 /* Receive Start Interrupt Mask */
#define SPI_IMSK_TSM 0x00000200 /* Transmit Start Interrupt Mask */
#define SPI_IMSK_RFM 0x00000400 /* Receive Finish Interrupt Mask */
#define SPI_IMSK_TFM 0x00000800 /* Transmit Finish Interrupt Mask */
/* SPI_IMASKCL */
#define SPI_IMSK_CLR_RUW 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */
#define SPI_IMSK_CLR_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */
#define SPI_IMSK_CLR_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */
#define SPI_IMSK_CLR_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */
#define SPI_IMSK_CLR_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */
#define SPI_IMSK_CLR_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */
#define SPI_IMSK_CLR_RSM 0x00000100 /* Receive Start Interrupt Mask */
#define SPI_IMSK_CLR_TSM 0x00000200 /* Transmit Start Interrupt Mask */
#define SPI_IMSK_CLR_RFM 0x00000400 /* Receive Finish Interrupt Mask */
#define SPI_IMSK_CLR_TFM 0x00000800 /* Transmit Finish Interrupt Mask */
/* SPI_IMASKST */
#define SPI_IMSK_SET_RUWM 0x00000002 /* Receive Urgent Water-Mark Interrupt Mask */
#define SPI_IMSK_SET_TUWM 0x00000004 /* Transmit Urgent Water-Mark Interrupt Mask */
#define SPI_IMSK_SET_ROM 0x00000010 /* Receive Over-Run Error Interrupt Mask */
#define SPI_IMSK_SET_TUM 0x00000020 /* Transmit Under-Run Error Interrupt Mask */
#define SPI_IMSK_SET_TCM 0x00000040 /* Transmit Collision Error Interrupt Mask */
#define SPI_IMSK_SET_MFM 0x00000080 /* Mode Fault Error Interrupt Mask */
#define SPI_IMSK_SET_RSM 0x00000100 /* Receive Start Interrupt Mask */
#define SPI_IMSK_SET_TSM 0x00000200 /* Transmit Start Interrupt Mask */
#define SPI_IMSK_SET_RFM 0x00000400 /* Receive Finish Interrupt Mask */
#define SPI_IMSK_SET_TFM 0x00000800 /* Transmit Finish Interrupt Mask */
/* SPI_STATUS */
#define SPI_STAT_SPIF 0x00000001 /* SPI Finished */
#define SPI_STAT_RUWM 0x00000002 /* Receive Urgent Water-Mark Breached */
#define SPI_STAT_TUWM 0x00000004 /* Transmit Urgent Water-Mark Breached */
#define SPI_STAT_ROE 0x00000010 /* Receive Over-Run Error Indication */
#define SPI_STAT_TUE 0x00000020 /* Transmit Under-Run Error Indication */
#define SPI_STAT_TCE 0x00000040 /* Transmit Collision Error Indication */
#define SPI_STAT_MODF 0x00000080 /* Mode Fault Error Indication */
#define SPI_STAT_RS 0x00000100 /* Receive Start Indication */
#define SPI_STAT_TS 0x00000200 /* Transmit Start Indication */
#define SPI_STAT_RF 0x00000400 /* Receive Finish Indication */
#define SPI_STAT_TF 0x00000800 /* Transmit Finish Indication */
#define SPI_STAT_RFS 0x00007000 /* SPI_RFIFO status */
#define SPI_STAT_RFIFO_EMPTY 0x00000000 /* RFS: RFIFO Empty */
#define SPI_STAT_RFIFO_25 0x00001000 /* RFS: RFIFO 25% Full */
#define SPI_STAT_RFIFO_50 0x00002000 /* RFS: RFIFO 50% Full */
#define SPI_STAT_RFIFO_75 0x00003000 /* RFS: RFIFO 75% Full */
#define SPI_STAT_RFIFO_FULL 0x00004000 /* RFS: RFIFO Full */
#define SPI_STAT_TFS 0x00070000 /* SPI_TFIFO status */
#define SPI_STAT_TFIFO_FULL 0x00000000 /* TFS: TFIFO full */
#define SPI_STAT_TFIFO_25 0x00010000 /* TFS: TFIFO 25% empty */
#define SPI_STAT_TFIFO_50 0x00020000 /* TFS: TFIFO 50% empty */
#define SPI_STAT_TFIFO_75 0x00030000 /* TFS: TFIFO 75% empty */
#define SPI_STAT_TFIFO_EMPTY 0x00040000 /* TFS: TFIFO empty */
#define SPI_STAT_FCS 0x00100000 /* Flow-Control Stall Indication */
#define SPI_STAT_RFE 0x00400000 /* SPI_RFIFO Empty */
#define SPI_STAT_TFF 0x00800000 /* SPI_TFIFO Full */
/* SPI_ILAT */
#define SPI_ILAT_RUWMI 0x00000002 /* Receive Urgent Water Mark Interrupt */
#define SPI_ILAT_TUWMI 0x00000004 /* Transmit Urgent Water Mark Interrupt */
#define SPI_ILAT_ROI 0x00000010 /* Receive Over-Run Error Indication */
#define SPI_ILAT_TUI 0x00000020 /* Transmit Under-Run Error Indication */
#define SPI_ILAT_TCI 0x00000040 /* Transmit Collision Error Indication */
#define SPI_ILAT_MFI 0x00000080 /* Mode Fault Error Indication */
#define SPI_ILAT_RSI 0x00000100 /* Receive Start Indication */
#define SPI_ILAT_TSI 0x00000200 /* Transmit Start Indication */
#define SPI_ILAT_RFI 0x00000400 /* Receive Finish Indication */
#define SPI_ILAT_TFI 0x00000800 /* Transmit Finish Indication */
/* SPI_ILATCL */
#define SPI_ILAT_CLR_RUWMI 0x00000002 /* Receive Urgent Water Mark Interrupt */
#define SPI_ILAT_CLR_TUWMI 0x00000004 /* Transmit Urgent Water Mark Interrupt */
#define SPI_ILAT_CLR_ROI 0x00000010 /* Receive Over-Run Error Indication */
#define SPI_ILAT_CLR_TUI 0x00000020 /* Transmit Under-Run Error Indication */
#define SPI_ILAT_CLR_TCI 0x00000040 /* Transmit Collision Error Indication */
#define SPI_ILAT_CLR_MFI 0x00000080 /* Mode Fault Error Indication */
#define SPI_ILAT_CLR_RSI 0x00000100 /* Receive Start Indication */
#define SPI_ILAT_CLR_TSI 0x00000200 /* Transmit Start Indication */
#define SPI_ILAT_CLR_RFI 0x00000400 /* Receive Finish Indication */
#define SPI_ILAT_CLR_TFI 0x00000800 /* Transmit Finish Indication */
/*
* adi spi3 registers layout
*/
struct adi_spi_regs {
u32 revid;
u32 control;
u32 rx_control;
u32 tx_control;
u32 clock;
u32 delay;
u32 ssel;
u32 rwc;
u32 rwcr;
u32 twc;
u32 twcr;
u32 reserved0;
u32 emask;
u32 emaskcl;
u32 emaskst;
u32 reserved1;
u32 status;
u32 elat;
u32 elatcl;
u32 reserved2;
u32 rfifo;
u32 reserved3;
u32 tfifo;
};
#define MAX_CTRL_CS 8 /* cs in spi controller */
/* device.platform_data for SSP controller devices */
struct adi_spi3_master {
u16 num_chipselect;
u16 pin_req[7];
};
/* spi_board_info.controller_data for SPI slave devices,
* copied to spi_device.platform_data ... mostly for dma tuning
*/
struct adi_spi3_chip {
u32 control;
u16 cs_chg_udelay; /* Some devices require 16-bit delays */
u32 tx_dummy_val; /* tx value for rx only transfer */
bool enable_dma;
};
#endif /* _ADI_SPI3_H_ */

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include/linux/spi/ads7846.h Normal file
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/* linux/spi/ads7846.h */
/* Touchscreen characteristics vary between boards and models. The
* platform_data for the device's "struct device" holds this information.
*
* It's OK if the min/max values are zero.
*/
enum ads7846_filter {
ADS7846_FILTER_OK,
ADS7846_FILTER_REPEAT,
ADS7846_FILTER_IGNORE,
};
struct ads7846_platform_data {
u16 model; /* 7843, 7845, 7846, 7873. */
u16 vref_delay_usecs; /* 0 for external vref; etc */
u16 vref_mv; /* external vref value, milliVolts
* ads7846: if 0, use internal vref */
bool keep_vref_on; /* set to keep vref on for differential
* measurements as well */
bool swap_xy; /* swap x and y axes */
/* Settling time of the analog signals; a function of Vcc and the
* capacitance on the X/Y drivers. If set to non-zero, two samples
* are taken with settle_delay us apart, and the second one is used.
* ~150 uSec with 0.01uF caps.
*/
u16 settle_delay_usecs;
/* If set to non-zero, after samples are taken this delay is applied
* and penirq is rechecked, to help avoid false events. This value
* is affected by the material used to build the touch layer.
*/
u16 penirq_recheck_delay_usecs;
u16 x_plate_ohms;
u16 y_plate_ohms;
u16 x_min, x_max;
u16 y_min, y_max;
u16 pressure_min, pressure_max;
u16 debounce_max; /* max number of additional readings
* per sample */
u16 debounce_tol; /* tolerance used for filtering */
u16 debounce_rep; /* additional consecutive good readings
* required after the first two */
int gpio_pendown; /* the GPIO used to decide the pendown
* state if get_pendown_state == NULL */
int gpio_pendown_debounce; /* platform specific debounce time for
* the gpio_pendown */
int (*get_pendown_state)(void);
int (*filter_init) (const struct ads7846_platform_data *pdata,
void **filter_data);
int (*filter) (void *filter_data, int data_idx, int *val);
void (*filter_cleanup)(void *filter_data);
void (*wait_for_sync)(void);
bool wakeup;
unsigned long irq_flags;
};

25
include/linux/spi/at73c213.h Normal file
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/*
* Board-specific data used to set up AT73c213 audio DAC driver.
*/
#ifndef __LINUX_SPI_AT73C213_H
#define __LINUX_SPI_AT73C213_H
/**
* at73c213_board_info - how the external DAC is wired to the device.
*
* @ssc_id: SSC platform_driver id the DAC shall use to stream the audio.
* @dac_clk: the external clock used to provide master clock to the DAC.
* @shortname: a short discription for the DAC, seen by userspace tools.
*
* This struct contains the configuration of the hardware connection to the
* external DAC. The DAC needs a master clock and a I2S audio stream. It also
* provides a name which is used to identify it in userspace tools.
*/
struct at73c213_board_info {
int ssc_id;
struct clk *dac_clk;
char shortname[32];
};
#endif /* __LINUX_SPI_AT73C213_H */

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include/linux/spi/at86rf230.h Normal file
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/*
* AT86RF230/RF231 driver
*
* Copyright (C) 2009-2012 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2
* as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Written by:
* Dmitry Eremin-Solenikov <dmitry.baryshkov@siemens.com>
*/
#ifndef AT86RF230_H
#define AT86RF230_H
struct at86rf230_platform_data {
int rstn;
int slp_tr;
int dig2;
};
#endif

26
include/linux/spi/cc2520.h Normal file
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/* Header file for cc2520 radio driver
*
* Copyright (C) 2014 Varka Bhadram <varkab@cdac.in>
* Md.Jamal Mohiuddin <mjmohiuddin@cdac.in>
* P Sowjanya <sowjanyap@cdac.in>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __CC2520_H
#define __CC2520_H
struct cc2520_platform_data {
int fifo;
int fifop;
int cca;
int sfd;
int reset;
int vreg;
};
#endif

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include/linux/spi/corgi_lcd.h Normal file
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#ifndef __LINUX_SPI_CORGI_LCD_H
#define __LINUX_SPI_CORGI_LCD_H
#define CORGI_LCD_MODE_QVGA 1
#define CORGI_LCD_MODE_VGA 2
struct corgi_lcd_platform_data {
int init_mode;
int max_intensity;
int default_intensity;
int limit_mask;
int gpio_backlight_on; /* -1 if n/a */
int gpio_backlight_cont; /* -1 if n/a */
void (*notify)(int intensity);
void (*kick_battery)(void);
};
#endif /* __LINUX_SPI_CORGI_LCD_H */

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include/linux/spi/ds1305.h Normal file
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#ifndef __LINUX_SPI_DS1305_H
#define __LINUX_SPI_DS1305_H
/*
* One-time configuration for ds1305 and ds1306 RTC chips.
*
* Put a pointer to this in spi_board_info.platform_data if you want to
* be sure that Linux (re)initializes this as needed ... after losing
* backup power, and potentially on the first boot.
*/
struct ds1305_platform_data {
/* Trickle charge configuration: it's OK to leave out the MAGIC
* bitmask; mask in either DS1 or DS2, and then one of 2K/4k/8K.
*/
#define DS1305_TRICKLE_MAGIC 0xa0
#define DS1305_TRICKLE_DS2 0x08 /* two diodes */
#define DS1305_TRICKLE_DS1 0x04 /* one diode */
#define DS1305_TRICKLE_2K 0x01 /* 2 KOhm resistance */
#define DS1305_TRICKLE_4K 0x02 /* 4 KOhm resistance */
#define DS1305_TRICKLE_8K 0x03 /* 8 KOhm resistance */
u8 trickle;
/* set only on ds1306 parts */
bool is_ds1306;
/* ds1306 only: enable 1 Hz output */
bool en_1hz;
/* REVISIT: the driver currently expects nINT0 to be wired
* as the alarm IRQ. ALM1 may also need to be set up ...
*/
};
#endif /* __LINUX_SPI_DS1305_H */

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include/linux/spi/eeprom.h Normal file
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#ifndef __LINUX_SPI_EEPROM_H
#define __LINUX_SPI_EEPROM_H
#include <linux/memory.h>
/*
* Put one of these structures in platform_data for SPI EEPROMS handled
* by the "at25" driver. On SPI, most EEPROMS understand the same core
* command set. If you need to support EEPROMs that don't yet fit, add
* flags to support those protocol options. These values all come from
* the chip datasheets.
*/
struct spi_eeprom {
u32 byte_len;
char name[10];
u16 page_size; /* for writes */
u16 flags;
#define EE_ADDR1 0x0001 /* 8 bit addrs */
#define EE_ADDR2 0x0002 /* 16 bit addrs */
#define EE_ADDR3 0x0004 /* 24 bit addrs */
#define EE_READONLY 0x0008 /* disallow writes */
/*
* Certain EEPROMS have a size that is larger than the number of address
* bytes would allow (e.g. like M95040 from ST that has 512 Byte size
* but uses only one address byte (A0 to A7) for addressing.) For
* the extra address bit (A8, A16 or A24) bit 3 of the instruction byte
* is used. This instruction bit is normally defined as don't care for
* other AT25 like chips.
*/
#define EE_INSTR_BIT3_IS_ADDR 0x0010
/* for exporting this chip's data to other kernel code */
void (*setup)(struct memory_accessor *mem, void *context);
void *context;
};
#endif /* __LINUX_SPI_EEPROM_H */

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#ifndef LINUX_SPI_FLASH_H
#define LINUX_SPI_FLASH_H
struct mtd_partition;
/**
* struct flash_platform_data: board-specific flash data
* @name: optional flash device name (eg, as used with mtdparts=)
* @parts: optional array of mtd_partitions for static partitioning
* @nr_parts: number of mtd_partitions for static partitoning
* @type: optional flash device type (e.g. m25p80 vs m25p64), for use
* with chips that can't be queried for JEDEC or other IDs
*
* Board init code (in arch/.../mach-xxx/board-yyy.c files) can
* provide information about SPI flash parts (such as DataFlash) to
* help set up the device and its appropriate default partitioning.
*
* Note that for DataFlash, sizes for pages, blocks, and sectors are
* rarely powers of two; and partitions should be sector-aligned.
*/
struct flash_platform_data {
char *name;
struct mtd_partition *parts;
unsigned int nr_parts;
char *type;
/* we'll likely add more ... use JEDEC IDs, etc */
};
#endif

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#ifndef LINUX_IFX_MODEM_H
#define LINUX_IFX_MODEM_H
struct ifx_modem_platform_data {
unsigned short rst_out; /* modem reset out */
unsigned short pwr_on; /* power on */
unsigned short rst_pmu; /* reset modem */
unsigned short tx_pwr; /* modem power threshold */
unsigned short srdy; /* SRDY */
unsigned short mrdy; /* MRDY */
unsigned char modem_type; /* Modem type */
unsigned long max_hz; /* max SPI frequency */
unsigned short use_dma:1; /* spi protocol driver supplies
dma-able addrs */
};
#define IFX_MODEM_6160 1
#define IFX_MODEM_6260 2
#endif

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/*
* l4f00242t03.h -- Platform glue for Epson L4F00242T03 LCD
*
* Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
* Based on Marek Vasut work in lms283gf05.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _INCLUDE_LINUX_SPI_L4F00242T03_H_
#define _INCLUDE_LINUX_SPI_L4F00242T03_H_
struct l4f00242t03_pdata {
unsigned int reset_gpio;
unsigned int data_enable_gpio;
};
#endif /* _INCLUDE_LINUX_SPI_L4F00242T03_H_ */

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/*
* board-specific data for the libertas_spi driver.
*
* Copyright 2008 Analog Devices Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or (at
* your option) any later version.
*/
#ifndef _LIBERTAS_SPI_H_
#define _LIBERTAS_SPI_H_
struct spi_device;
struct libertas_spi_platform_data {
/* There are two ways to read data from the WLAN module's SPI
* interface. Setting 0 or 1 here controls which one is used.
*
* Usually you want to set use_dummy_writes = 1.
* However, if that doesn't work or if you are using a slow SPI clock
* speed, you may want to use 0 here. */
u16 use_dummy_writes;
/* Board specific setup/teardown */
int (*setup)(struct spi_device *spi);
int (*teardown)(struct spi_device *spi);
};
#endif

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/*
* lms283gf05.h - Platform glue for Samsung LMS283GF05 LCD
*
* Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _INCLUDE_LINUX_SPI_LMS283GF05_H_
#define _INCLUDE_LINUX_SPI_LMS283GF05_H_
struct lms283gf05_pdata {
unsigned long reset_gpio;
bool reset_inverted;
};
#endif /* _INCLUDE_LINUX_SPI_LMS283GF05_H_ */

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#ifndef LINUX_SPI_MAX7301_H
#define LINUX_SPI_MAX7301_H
#include <linux/gpio.h>
/*
* Some registers must be read back to modify.
* To save time we cache them here in memory
*/
struct max7301 {
struct mutex lock;
u8 port_config[8]; /* field 0 is unused */
u32 out_level; /* cached output levels */
u32 input_pullup_active;
struct gpio_chip chip;
struct device *dev;
int (*write)(struct device *dev, unsigned int reg, unsigned int val);
int (*read)(struct device *dev, unsigned int reg);
};
struct max7301_platform_data {
/* number assigned to the first GPIO */
unsigned base;
/*
* bitmask controlling the pullup configuration,
*
* _note_ the 4 lowest bits are unused, because the first 4
* ports of the controller are not used, too.
*/
u32 input_pullup_active;
};
extern int __max730x_remove(struct device *dev);
extern int __max730x_probe(struct max7301 *ts);
#endif

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#ifndef LINUX_SPI_MC33880_H
#define LINUX_SPI_MC33880_H
struct mc33880_platform_data {
/* number assigned to the first GPIO */
unsigned base;
};
#endif

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/* FIXME driver should be able to handle IRQs... */
struct mcp23s08_chip_info {
bool is_present; /* true if populated */
unsigned pullups; /* BIT(x) means enable pullup x */
};
struct mcp23s08_platform_data {
/* For mcp23s08, up to 4 slaves (numbered 0..3) can share one SPI
* chipselect, each providing 1 gpio_chip instance with 8 gpios.
* For mpc23s17, up to 8 slaves (numbered 0..7) can share one SPI
* chipselect, each providing 1 gpio_chip (port A + port B) with
* 16 gpios.
*/
struct mcp23s08_chip_info chip[8];
/* "base" is the number of the first GPIO. Dynamic assignment is
* not currently supported, and even if there are gaps in chip
* addressing the GPIO numbers are sequential .. so for example
* if only slaves 0 and 3 are present, their GPIOs range from
* base to base+15 (or base+31 for s17 variant).
*/
unsigned base;
/* Marks the device as a interrupt controller.
* NOTE: The interrupt functionality is only supported for i2c
* versions of the chips. The spi chips can also do the interrupts,
* but this is not supported by the linux driver yet.
*/
bool irq_controller;
/* Sets the mirror flag in the IOCON register. Devices
* with two interrupt outputs (these are the devices ending with 17 and
* those that have 16 IOs) have two IO banks: IO 0-7 form bank 1 and
* IO 8-15 are bank 2. These chips have two different interrupt outputs:
* One for bank 1 and another for bank 2. If irq-mirror is set, both
* interrupts are generated regardless of the bank that an input change
* occurred on. If it is not set, the interrupt are only generated for
* the bank they belong to.
* On devices with only one interrupt output this property is useless.
*/
bool mirror;
};

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#ifndef __LINUX_SPI_MMC_SPI_H
#define __LINUX_SPI_MMC_SPI_H
#include <linux/spi/spi.h>
#include <linux/interrupt.h>
struct device;
struct mmc_host;
#define MMC_SPI_USE_CD_GPIO (1 << 0)
#define MMC_SPI_USE_RO_GPIO (1 << 1)
#define MMC_SPI_CD_GPIO_ACTIVE_LOW (1 << 2)
#define MMC_SPI_RO_GPIO_ACTIVE_LOW (1 << 3)
/* Put this in platform_data of a device being used to manage an MMC/SD
* card slot. (Modeled after PXA mmc glue; see that for usage examples.)
*
* REVISIT This is not a spi-specific notion. Any card slot should be
* able to handle it. If the MMC core doesn't adopt this kind of notion,
* switch the "struct device *" parameters over to "struct spi_device *".
*/
struct mmc_spi_platform_data {
/* driver activation and (optional) card detect irq hookup */
int (*init)(struct device *,
irqreturn_t (*)(int, void *),
void *);
void (*exit)(struct device *, void *);
/*
* Card Detect and Read Only GPIOs. To enable debouncing on the card
* detect GPIO, set the cd_debounce to the debounce time in
* microseconds.
*/
unsigned int flags;
unsigned int cd_gpio;
unsigned int cd_debounce;
unsigned int ro_gpio;
/* Capabilities to pass into mmc core (e.g. MMC_CAP_NEEDS_POLL). */
unsigned long caps;
unsigned long caps2;
/* how long to debounce card detect, in msecs */
u16 detect_delay;
/* power management */
u16 powerup_msecs; /* delay of up to 250 msec */
u32 ocr_mask; /* available voltages */
void (*setpower)(struct device *, unsigned int maskval);
};
#ifdef CONFIG_OF
extern struct mmc_spi_platform_data *mmc_spi_get_pdata(struct spi_device *spi);
extern void mmc_spi_put_pdata(struct spi_device *spi);
#else
static inline struct mmc_spi_platform_data *
mmc_spi_get_pdata(struct spi_device *spi)
{
return spi->dev.platform_data;
}
static inline void mmc_spi_put_pdata(struct spi_device *spi) {}
#endif /* CONFIG_OF */
#endif /* __LINUX_SPI_MMC_SPI_H */

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/*
* include/linux/spi/mxs-spi.h
*
* Freescale i.MX233/i.MX28 SPI controller register definition
*
* Copyright 2008 Embedded Alley Solutions, Inc.
* Copyright 2009-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#ifndef __LINUX_SPI_MXS_SPI_H__
#define __LINUX_SPI_MXS_SPI_H__
#include <linux/dmaengine.h>
#define ssp_is_old(host) ((host)->devid == IMX23_SSP)
/* SSP registers */
#define HW_SSP_CTRL0 0x000
#define BM_SSP_CTRL0_RUN (1 << 29)
#define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28)
#define BM_SSP_CTRL0_LOCK_CS (1 << 27)
#define BM_SSP_CTRL0_IGNORE_CRC (1 << 26)
#define BM_SSP_CTRL0_READ (1 << 25)
#define BM_SSP_CTRL0_DATA_XFER (1 << 24)
#define BP_SSP_CTRL0_BUS_WIDTH 22
#define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
#define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
#define BM_SSP_CTRL0_WAIT_FOR_CMD (1 << 20)
#define BM_SSP_CTRL0_LONG_RESP (1 << 19)
#define BM_SSP_CTRL0_GET_RESP (1 << 17)
#define BM_SSP_CTRL0_ENABLE (1 << 16)
#define BP_SSP_CTRL0_XFER_COUNT 0
#define BM_SSP_CTRL0_XFER_COUNT 0xffff
#define HW_SSP_CMD0 0x010
#define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
#define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22)
#define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21)
#define BM_SSP_CMD0_APPEND_8CYC (1 << 20)
#define BP_SSP_CMD0_BLOCK_SIZE 16
#define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
#define BP_SSP_CMD0_BLOCK_COUNT 8
#define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
#define BP_SSP_CMD0_CMD 0
#define BM_SSP_CMD0_CMD 0xff
#define HW_SSP_CMD1 0x020
#define HW_SSP_XFER_SIZE 0x030
#define HW_SSP_BLOCK_SIZE 0x040
#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT 4
#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4)
#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE 0
#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE 0xf
#define HW_SSP_TIMING(h) (ssp_is_old(h) ? 0x050 : 0x070)
#define BP_SSP_TIMING_TIMEOUT 16
#define BM_SSP_TIMING_TIMEOUT (0xffff << 16)
#define BP_SSP_TIMING_CLOCK_DIVIDE 8
#define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8)
#define BF_SSP_TIMING_CLOCK_DIVIDE(v) \
(((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE)
#define BP_SSP_TIMING_CLOCK_RATE 0
#define BM_SSP_TIMING_CLOCK_RATE 0xff
#define BF_SSP_TIMING_CLOCK_RATE(v) \
(((v) << 0) & BM_SSP_TIMING_CLOCK_RATE)
#define HW_SSP_CTRL1(h) (ssp_is_old(h) ? 0x060 : 0x080)
#define BM_SSP_CTRL1_SDIO_IRQ (1 << 31)
#define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30)
#define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28)
#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27)
#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26)
#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24)
#define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23)
#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22)
#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21)
#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20)
#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17)
#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16)
#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15)
#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14)
#define BM_SSP_CTRL1_DMA_ENABLE (1 << 13)
#define BM_SSP_CTRL1_PHASE (1 << 10)
#define BM_SSP_CTRL1_POLARITY (1 << 9)
#define BP_SSP_CTRL1_WORD_LENGTH 4
#define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4)
#define BF_SSP_CTRL1_WORD_LENGTH(v) \
(((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH)
#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS 0x3
#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS 0x7
#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS 0xF
#define BP_SSP_CTRL1_SSP_MODE 0
#define BM_SSP_CTRL1_SSP_MODE 0xf
#define BF_SSP_CTRL1_SSP_MODE(v) \
(((v) << 0) & BM_SSP_CTRL1_SSP_MODE)
#define BV_SSP_CTRL1_SSP_MODE__SPI 0x0
#define BV_SSP_CTRL1_SSP_MODE__SSI 0x1
#define BV_SSP_CTRL1_SSP_MODE__SD_MMC 0x3
#define BV_SSP_CTRL1_SSP_MODE__MS 0x4
#define HW_SSP_DATA(h) (ssp_is_old(h) ? 0x070 : 0x090)
#define HW_SSP_SDRESP0(h) (ssp_is_old(h) ? 0x080 : 0x0a0)
#define HW_SSP_SDRESP1(h) (ssp_is_old(h) ? 0x090 : 0x0b0)
#define HW_SSP_SDRESP2(h) (ssp_is_old(h) ? 0x0a0 : 0x0c0)
#define HW_SSP_SDRESP3(h) (ssp_is_old(h) ? 0x0b0 : 0x0d0)
#define HW_SSP_STATUS(h) (ssp_is_old(h) ? 0x0c0 : 0x100)
#define BM_SSP_STATUS_CARD_DETECT (1 << 28)
#define BM_SSP_STATUS_SDIO_IRQ (1 << 17)
#define BM_SSP_STATUS_FIFO_EMPTY (1 << 5)
#define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field)
#define SSP_PIO_NUM 3
enum mxs_ssp_id {
IMX23_SSP,
IMX28_SSP,
};
struct mxs_ssp {
struct device *dev;
void __iomem *base;
struct clk *clk;
unsigned int clk_rate;
enum mxs_ssp_id devid;
struct dma_chan *dmach;
unsigned int dma_dir;
enum dma_transfer_direction slave_dirn;
u32 ssp_pio_words[SSP_PIO_NUM];
};
void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp, unsigned int rate);
#endif /* __LINUX_SPI_MXS_SPI_H__ */

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/*
* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __linux_pxa2xx_spi_h
#define __linux_pxa2xx_spi_h
#include <linux/pxa2xx_ssp.h>
#define PXA2XX_CS_ASSERT (0x01)
#define PXA2XX_CS_DEASSERT (0x02)
struct dma_chan;
/* device.platform_data for SSP controller devices */
struct pxa2xx_spi_master {
u32 clock_enable;
u16 num_chipselect;
u8 enable_dma;
/* DMA engine specific config */
bool (*dma_filter)(struct dma_chan *chan, void *param);
void *tx_param;
void *rx_param;
/* For non-PXA arches */
struct ssp_device ssp;
};
/* spi_board_info.controller_data for SPI slave devices,
* copied to spi_device.platform_data ... mostly for dma tuning
*/
struct pxa2xx_spi_chip {
u8 tx_threshold;
u8 tx_hi_threshold;
u8 rx_threshold;
u8 dma_burst_size;
u32 timeout;
u8 enable_loopback;
int gpio_cs;
void (*cs_control)(u32 command);
};
#if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP)
#include <linux/clk.h>
#include <mach/dma.h>
extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info);
#endif
#endif

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/*
* Renesas SPI driver
*
* Copyright (C) 2012 Renesas Solutions Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*
*/
#ifndef __LINUX_SPI_RENESAS_SPI_H__
#define __LINUX_SPI_RENESAS_SPI_H__
struct rspi_plat_data {
unsigned int dma_tx_id;
unsigned int dma_rx_id;
u16 num_chipselect;
};
#endif

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/*
* Copyright (c) 2006 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - SPI Controller platform_device info
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_SPI_S3C24XX_H
#define __LINUX_SPI_S3C24XX_H __FILE__
struct s3c2410_spi_info {
int pin_cs; /* simple gpio cs */
unsigned int num_cs; /* total chipselects */
int bus_num; /* bus number to use. */
unsigned int use_fiq:1; /* use fiq */
void (*gpio_setup)(struct s3c2410_spi_info *spi, int enable);
void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol);
};
extern int s3c24xx_set_fiq(unsigned int irq, bool on);
#endif /* __LINUX_SPI_S3C24XX_H */

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/*
* Copyright (C) 2011 Kuninori Morimoto
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef SH_HSPI_H
#define SH_HSPI_H
struct sh_hspi_info {
};
#endif

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#ifndef __SPI_SH_MSIOF_H__
#define __SPI_SH_MSIOF_H__
struct sh_msiof_spi_info {
int tx_fifo_override;
int rx_fifo_override;
u16 num_chipselect;
unsigned int dma_tx_id;
unsigned int dma_rx_id;
};
#endif /* __SPI_SH_MSIOF_H__ */

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#ifndef __SPI_BITBANG_H
#define __SPI_BITBANG_H
#include <linux/workqueue.h>
struct spi_bitbang {
spinlock_t lock;
u8 busy;
u8 use_dma;
u8 flags; /* extra spi->mode support */
struct spi_master *master;
/* setup_transfer() changes clock and/or wordsize to match settings
* for this transfer; zeroes restore defaults from spi_device.
*/
int (*setup_transfer)(struct spi_device *spi,
struct spi_transfer *t);
void (*chipselect)(struct spi_device *spi, int is_on);
#define BITBANG_CS_ACTIVE 1 /* normally nCS, active low */
#define BITBANG_CS_INACTIVE 0
/* txrx_bufs() may handle dma mapping for transfers that don't
* already have one (transfer.{tx,rx}_dma is zero), or use PIO
*/
int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t);
/* txrx_word[SPI_MODE_*]() just looks like a shift register */
u32 (*txrx_word[4])(struct spi_device *spi,
unsigned nsecs,
u32 word, u8 bits);
};
/* you can call these default bitbang->master methods from your custom
* methods, if you like.
*/
extern int spi_bitbang_setup(struct spi_device *spi);
extern void spi_bitbang_cleanup(struct spi_device *spi);
extern int spi_bitbang_setup_transfer(struct spi_device *spi,
struct spi_transfer *t);
/* start or stop queue processing */
extern int spi_bitbang_start(struct spi_bitbang *spi);
extern void spi_bitbang_stop(struct spi_bitbang *spi);
#endif /* __SPI_BITBANG_H */

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#ifndef __LINUX_SPI_GPIO_H
#define __LINUX_SPI_GPIO_H
/*
* For each bitbanged SPI bus, set up a platform_device node with:
* - name "spi_gpio"
* - id the same as the SPI bus number it implements
* - dev.platform data pointing to a struct spi_gpio_platform_data
*
* Or, see the driver code for information about speedups that are
* possible on platforms that support inlined access for GPIOs (no
* spi_gpio_platform_data is used).
*
* Use spi_board_info with these busses in the usual way, being sure
* that the controller_data being the GPIO used for each device's
* chipselect:
*
* static struct spi_board_info ... [] = {
* ...
* // this slave uses GPIO 42 for its chipselect
* .controller_data = (void *) 42,
* ...
* // this one uses GPIO 86 for its chipselect
* .controller_data = (void *) 86,
* ...
* };
*
* If chipselect is not used (there's only one device on the bus), assign
* SPI_GPIO_NO_CHIPSELECT to the controller_data:
* .controller_data = (void *) SPI_GPIO_NO_CHIPSELECT;
*
* If the MISO or MOSI pin is not available then it should be set to
* SPI_GPIO_NO_MISO or SPI_GPIO_NO_MOSI.
*
* If the bitbanged bus is later switched to a "native" controller,
* that platform_device and controller_data should be removed.
*/
#define SPI_GPIO_NO_CHIPSELECT ((unsigned long)-1l)
#define SPI_GPIO_NO_MISO ((unsigned long)-1l)
#define SPI_GPIO_NO_MOSI ((unsigned long)-1l)
/**
* struct spi_gpio_platform_data - parameter for bitbanged SPI master
* @sck: number of the GPIO used for clock output
* @mosi: number of the GPIO used for Master Output, Slave In (MOSI) data
* @miso: number of the GPIO used for Master Input, Slave Output (MISO) data
* @num_chipselect: how many slaves to allow
*
* All GPIO signals used with the SPI bus managed through this driver
* (chipselects, MOSI, MISO, SCK) must be configured as GPIOs, instead
* of some alternate function.
*
* It can be convenient to use this driver with pins that have alternate
* functions associated with a "native" SPI controller if a driver for that
* controller is not available, or is missing important functionality.
*
* On platforms which can do so, configure MISO with a weak pullup unless
* there's an external pullup on that signal. That saves power by avoiding
* floating signals. (A weak pulldown would save power too, but many
* drivers expect to see all-ones data as the no slave "response".)
*/
struct spi_gpio_platform_data {
unsigned sck;
unsigned long mosi;
unsigned long miso;
u16 num_chipselect;
};
#endif /* __LINUX_SPI_GPIO_H */

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#ifndef _LINUX_SPI_SPI_OC_TINY_H
#define _LINUX_SPI_SPI_OC_TINY_H
/**
* struct tiny_spi_platform_data - platform data of the OpenCores tiny SPI
* @freq: input clock freq to the core.
* @baudwidth: baud rate divider width of the core.
* @gpio_cs_count: number of gpio pins used for chipselect.
* @gpio_cs: array of gpio pins used for chipselect.
*
* freq and baudwidth are used only if the divider is programmable.
*/
struct tiny_spi_platform_data {
unsigned int freq;
unsigned int baudwidth;
unsigned int gpio_cs_count;
int *gpio_cs;
};
#endif /* _LINUX_SPI_SPI_OC_TINY_H */

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#ifndef __TDO24M_H__
#define __TDO24M_H__
enum tdo24m_model {
TDO24M,
TDO35S,
};
struct tdo24m_platform_data {
enum tdo24m_model model;
};
#endif /* __TDO24M_H__ */

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/*
* tle62x0.h - platform glue to Infineon TLE62x0 driver chips
*
* Copyright 2007 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
struct tle62x0_pdata {
unsigned int init_state;
unsigned int gpio_count;
};

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include/linux/spi/tsc2005.h Normal file
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/*
* This file is part of TSC2005 touchscreen driver
*
* Copyright (C) 2009-2010 Nokia Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef _LINUX_SPI_TSC2005_H
#define _LINUX_SPI_TSC2005_H
#include <linux/types.h>
struct tsc2005_platform_data {
int ts_pressure_max;
int ts_pressure_fudge;
int ts_x_max;
int ts_x_fudge;
int ts_y_max;
int ts_y_fudge;
int ts_x_plate_ohm;
unsigned int esd_timeout_ms;
void (*set_reset)(bool enable);
};
#endif

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#ifndef __LINUX_SPI_XILINX_SPI_H
#define __LINUX_SPI_XILINX_SPI_H
/**
* struct xspi_platform_data - Platform data of the Xilinx SPI driver
* @num_chipselect: Number of chip select by the IP.
* @little_endian: If registers should be accessed little endian or not.
* @bits_per_word: Number of bits per word.
* @devices: Devices to add when the driver is probed.
* @num_devices: Number of devices in the devices array.
*/
struct xspi_platform_data {
u16 num_chipselect;
u8 bits_per_word;
struct spi_board_info *devices;
u8 num_devices;
};
#endif /* __LINUX_SPI_XILINX_SPI_H */