mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-07 08:48:05 -04:00
Fixed MTP to work with TWRP
This commit is contained in:
awab228
commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
48
include/soc/samsung/acpm_ipc_ctrl.h
Normal file
48
include/soc/samsung/acpm_ipc_ctrl.h
Normal file
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@ -0,0 +1,48 @@
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#ifndef __ACPM_IPC_CTRL_H__
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#define __ACPM_IPC_CTRL_H__
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typedef void (*ipc_callback)(unsigned int *cmd, unsigned int size);
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struct ipc_config {
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unsigned int *cmd;
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unsigned int *indirection;
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unsigned int indirection_size;
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bool responce;
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};
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#define ACPM_IPC_PROTOCOL_OWN (31)
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#define ACPM_IPC_PROTOCOL_RSP (30)
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#define ACPM_IPC_PROTOCOL_INDIRECTION (29)
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#define ACPM_IPC_PROTOCOL_ID (26)
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#define ACPM_IPC_PROTOCOL_IDX (0x7 << ACPM_IPC_PROTOCOL_ID)
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#define ACPM_IPC_PROTOCOL_DP_A (25)
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#define ACPM_IPC_PROTOCOL_DP_D (24)
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#define ACPM_IPC_PROTOCOL_DP_CMD (0x3 << ACPM_IPC_PROTOCOL_DP_D)
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#define ACPM_IPC_PROTOCOL_TEST (23)
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#define ACPM_IPC_PROTOCOL_STOP (22)
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#ifdef CONFIG_EXYNOS_ACPM
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unsigned int acpm_ipc_request_channel(struct device_node *np, ipc_callback handler,
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unsigned int *id, unsigned int *size);
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unsigned int acpm_ipc_release_channel(unsigned int channel_id);
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int acpm_ipc_send_data(unsigned int channel_id, struct ipc_config *cfg);
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#else
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inline unsigned int acpm_ipc_request_channel(struct device_node *np, ipc_callback handler,
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unsigned int *id, unsigned int *size, bool polling)
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{
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return 0;
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}
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inline unsigned int acpm_ipc_release_channel(unsigned int channel_id)
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{
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return 0;
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}
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inline int acpm_ipc_send_data(unsigned int channel_id, struct ipc_config *cfg)
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{
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return 0;
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}
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#endif
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#endif
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189
include/soc/samsung/asv-exynos.h
Normal file
189
include/soc/samsung/asv-exynos.h
Normal file
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@ -0,0 +1,189 @@
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/* linux/arch/arm64/mach-exynos/include/mach/asv.h
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*
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* copyright (c) 2014 samsung electronics co., ltd.
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* http://www.samsung.com/
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*
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* EXYNOS - Adaptive Support Voltage Source File
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*
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* this program is free software; you can redistribute it and/or modify
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* it under the terms of the gnu general public license version 2 as
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* published by the free software foundation.
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*/
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#ifndef __ASM_ARCH_NEW_ASV_H
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#define __ASM_ARCH_NEW_ASV_H __FILE__
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#include <linux/io.h>
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#define ASV_GRP_NR(_id) _id##_ASV_GRP_NR
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#define DVFS_LEVEL_NR(_id) _id##_DVFS_LEVEL_NR
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#define MAX_VOLT(_id) _id##_MAX_VOLT
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#define MAX_VOLT_VER(_id, _ver) _id##_MAX_VOLT_##_ver
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#define ABB_X060 0
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#define ABB_X065 1
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#define ABB_X070 2
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#define ABB_X075 3
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#define ABB_X080 4
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#define ABB_X085 5
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#define ABB_X090 6
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#define ABB_X095 7
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#define ABB_X100 8
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#define ABB_X105 9
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#define ABB_X110 10
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#define ABB_X115 11
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#define ABB_X120 12
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#define ABB_X125 13
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#define ABB_X130 14
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#define ABB_X135 15
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#define ABB_X140 16
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#define ABB_X145 17
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#define ABB_X150 18
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#define ABB_X155 19
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#define ABB_X160 20
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#define ABB_BYPASS 255
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#define ABB_INIT (0x80000080)
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#define ABB_INIT_BYPASS (0x80000000)
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#define MAX_ASV_GRP_NR 16
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#define MAX_ASV_SUB_GRP_NR 3
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static inline void set_abb(void __iomem *target_reg, unsigned int target_value)
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{
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unsigned int tmp;
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if (target_value == ABB_BYPASS)
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tmp = ABB_INIT_BYPASS;
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else
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tmp = (ABB_INIT | target_value);
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__raw_writel(tmp , target_reg);
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}
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enum asv_type_id {
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ID_CL1,
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ID_CL0,
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ID_INT,
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ID_MIF,
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ID_G3D,
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ID_ISP,
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ASV_TYPE_END,
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};
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/* define Struct for ASV common */
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struct asv_common {
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char lot_name[5];
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unsigned int ids_value;
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unsigned int hpm_value;
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unsigned int (*init)(void);
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unsigned int (*regist_asv_member)(void);
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struct asv_common_ops_cal *ops_cal;
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};
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/* operation for CAL */
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struct asv_ops_cal {
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u32 (*get_vol)(u32, s32 eLvl);
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u32 (*get_freq)(u32 id, s32 eLvl);
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u32 (*get_abb)(u32 id, s32 eLvl);
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u32 (*get_rcc)(u32 id, s32 eLvl);
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bool (*get_use_abb)(u32 id);
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void (*set_abb)(u32 id, u32 eAbb);
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u32 (*set_rcc)(u32 id, s32 level, u32 rcc);
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u32 (*get_group)(u32 id, s32 level);
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u32 (*get_sub_grp_idx)(u32 id, s32 level);
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};
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struct asv_common_ops_cal {
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u32 (*get_max_volt)(u32 id);
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s32 (*get_min_lv)(u32 id);
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void (*init)(void);
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u32 (*get_table_ver)(void);
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bool (*is_fused_sp_gr)(void);
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u32 (*get_asv_gr)(void);
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u32 (*get_ids)(void);
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u32 (*get_hpm)(void);
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void (*set_rcc_limit_info)(void);
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};
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struct asv_freq_table {
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unsigned int asv_freq;
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unsigned int asv_value;
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};
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struct asv_grp_table {
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unsigned int asv_sub_idx;
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unsigned int asv_grp;
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};
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/* define struct for information of each ASV type */
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struct asv_info {
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struct list_head node;
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enum asv_type_id asv_type;
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const char *name;
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struct asv_ops *ops;
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unsigned int asv_group_nr;
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unsigned int dvfs_level_nr;
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unsigned int result_asv_grp;
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unsigned int max_volt_value;
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struct asv_freq_table *asv_volt;
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struct asv_freq_table *asv_abb;
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struct asv_freq_table *asv_rcc;
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struct abb_common *abb_info;
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struct asv_ops_cal *ops_cal;
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struct asv_grp_table *asv_sub_grp;
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};
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/* Struct for ABB function */
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struct abb_common {
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unsigned int target_abb;
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void (*set_target_abb)(struct asv_info *asv_inform);
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};
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/* Operation for ASV*/
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struct asv_ops {
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unsigned int (*get_asv_group)(struct asv_common *asv_comm);
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void (*set_asv_info)(struct asv_info *asv_inform,
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bool show_value);
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unsigned int (*get_asv_sub_group)(struct asv_info *asv_inform,
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unsigned int lv);
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void (*set_rcc_info)(struct asv_info *asv_inform);
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};
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/* define function for common asv */
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extern void add_asv_member(struct asv_info *exynos_asv_info);
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extern struct asv_info *asv_get(enum asv_type_id exynos_asv_type_id);
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#if defined (CONFIG_EXYNOS_ASV)
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extern unsigned int get_match_volt(enum asv_type_id target_type, unsigned int target_freq);
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/* define function for initialize of SoC */
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extern int exynos_init_asv(struct asv_common *asv_info);
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extern unsigned int exynos_get_table_ver(void);
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extern void exynos_set_ema(enum asv_type_id type, unsigned int volt);
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extern unsigned int exynos_get_asv_info(int id);
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extern unsigned int get_sub_grp_match_asv_grp(enum asv_type_id target_type, unsigned int lv);
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#else
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static inline int get_match_volt(enum asv_type_id target_type, unsigned int target_freq){return 0;}
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static inline int exynos_init_asv(struct asv_common *asv_info){return 0;}
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static inline unsigned int exynos_get_table_ver(void){return 0;}
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static inline void exynos_set_ema(enum asv_type_id type, unsigned int volt){};
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static inline unsigned int exynos_get_asv_info(int id){return 0;};
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extern inline unsigned int get_sub_grp_match_asv_grp(enum asv_type_id target_type, unsigned int lv){return 0;}
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#endif
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#if defined (CONFIG_EXYNOS_ASV_DYNAMIC_ABB)
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extern unsigned int get_match_abb(enum asv_type_id target_type, unsigned int target_freq);
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extern unsigned int set_match_abb(enum asv_type_id target_type, unsigned int target_abb);
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extern bool is_set_abb_first(enum asv_type_id target_type, unsigned int old_freq, unsigned int target_freq);
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#else
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static inline unsigned int get_match_abb(enum asv_type_id target_type, unsigned int target_freq)
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{return ABB_BYPASS;}
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static inline unsigned int set_match_abb(enum asv_type_id target_type, unsigned int target_abb)
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{return 0;}
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static inline bool is_set_abb_first(enum asv_type_id target_type, unsigned int old_freq, unsigned int target_freq)
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{return false;}
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#endif
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#ifdef CONFIG_EXYNOS_ASV_SUPPORT_RCC
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extern void set_rcc_info(void);
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#else
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static inline void set_rcc_info(void){};
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#endif
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#endif /* __ASM_ARCH_NEW_ASV_H */
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38
include/soc/samsung/bcm.h
Normal file
38
include/soc/samsung/bcm.h
Normal file
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@ -0,0 +1,38 @@
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/*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
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* the Free Software Foundation; either version 2 of the License, or
|
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* (at your option) any later version.
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*/
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#ifndef __EXYNOS_BCM_H_
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#define __EXYNOS_BCM_H_
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struct bcm_info;
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struct output_data {
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int index;
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u32 rd0;
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u32 rd1;
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u32 rd2;
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u32 rd3;
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u32 rd4;
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u64 rd5;
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};
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#if defined(CONFIG_EXYNOS_BCM)
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int bcm_pd_sync(struct bcm_info *, bool);
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struct output_data *bcm_start(const int *);
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struct output_data *bcm_stop(const int *);
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#else
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#define bcm_pd_sync(a, b) do {} while (0)
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#define bcm_start(a) do {} while (0)
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#define bcm_stop(a) do {} while (0)
|
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#endif
|
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|
||||
#endif
|
||||
140
include/soc/samsung/bts.h
Normal file
140
include/soc/samsung/bts.h
Normal file
|
|
@ -0,0 +1,140 @@
|
|||
/*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __EXYNOS_BTS_H_
|
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#define __EXYNOS_BTS_H_
|
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|
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#if defined(CONFIG_EXYNOS8890_BTS)
|
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#define CAM_FACTOR 3
|
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#define MIF_UTIL 50
|
||||
#define MIF_UTIL2 55
|
||||
#define MIF_DECODING 828000 // TBD
|
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#define MIF_ENCODING 1068000 // TBD
|
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#define INT_UTIL 70
|
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#define BUS_WIDTH 16
|
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#define SIZE_FACTOR(a) a = ((a) * 16 / 10)
|
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#define FULLHD_SRC 1920 * 1080
|
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#elif defined(CONFIG_EXYNOS7420_BTS) || defined(CONFIG_EXYNOS7890_BTS)
|
||||
#define DECON_NOCNT 10
|
||||
#define VPP_ROT 4
|
||||
#define CAM_FACTOR 3
|
||||
#define MIF_UTIL 50
|
||||
#define MIF_UTIL2 60
|
||||
#define MIF_UPPER_UTIL 44
|
||||
#define MIF_DECODING 828000
|
||||
#define MIF_ENCODING 1068000
|
||||
#define INT_UTIL 65
|
||||
#define NO_CNT_TH 100
|
||||
#define BUS_WIDTH 16
|
||||
#define SIZE_FACTOR(a) a = ((a) * 16 / 10)
|
||||
#define FULLHD_SRC 1920 * 1080
|
||||
#else
|
||||
#define FULLHD_SRC 1920 * 1080
|
||||
#endif
|
||||
|
||||
enum bts_media_type {
|
||||
TYPE_DECON_INT,
|
||||
TYPE_DECON_EXT,
|
||||
TYPE_VPP0,
|
||||
TYPE_VPP1,
|
||||
TYPE_VPP2,
|
||||
TYPE_VPP3,
|
||||
TYPE_VPP4,
|
||||
TYPE_VPP5,
|
||||
TYPE_VPP6,
|
||||
TYPE_VPP7,
|
||||
TYPE_VPP8,
|
||||
TYPE_CAM,
|
||||
TYPE_YUV,
|
||||
TYPE_UD_ENC,
|
||||
TYPE_UD_DEC,
|
||||
TYPE_SPDMA,
|
||||
};
|
||||
|
||||
enum vpp_bw_type {
|
||||
BW_DEFAULT,
|
||||
BW_ROT,
|
||||
BW_FULLHD_ROT,
|
||||
};
|
||||
|
||||
#if defined(CONFIG_EXYNOS8890_BTS) || defined(CONFIG_EXYNOS7870_BTS) \
|
||||
||defined(CONFIG_EXYNOS7570_BTS)
|
||||
void exynos_update_media_scenario(enum bts_media_type media_type,
|
||||
unsigned int bw, int bw_type);
|
||||
#else
|
||||
#define exynos_update_media_scenario(a, b, c) do {} while (0)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_EXYNOS7420_BTS) || defined(CONFIG_EXYNOS7890_BTS)
|
||||
void exynos7_update_media_scenario(enum bts_media_type media_type,
|
||||
unsigned int bw, int bw_type);
|
||||
int exynos7_update_bts_param(int target_idx, int work);
|
||||
int exynos7_bts_register_notifier(struct notifier_block *nb);
|
||||
int exynos7_bts_unregister_notifier(struct notifier_block *nb);
|
||||
#elif defined(CONFIG_EXYNOS7870_BTS)
|
||||
int exynos_update_bts_param(int target_idx, int work);
|
||||
int exynos_bts_register_notifier(struct notifier_block *nb);
|
||||
int exynos_bts_unregister_notifier(struct notifier_block *nb);
|
||||
#else
|
||||
#define exynos7_update_media_scenario(a, b, c) do {} while (0)
|
||||
#define exynos7_update_bts_param(a, b) do {} while (0)
|
||||
#define exynos7_bts_register_notifier(a) do {} while (0)
|
||||
#define exynos7_bts_unregister_notifier(a) do {} while (0)
|
||||
#define exynos_update_bts_param(a, b) do {} while (0)
|
||||
#define exynos_bts_register_notifier(a) do {} while (0)
|
||||
#define exynos_bts_unregister_notifier(a, b) do {} while (0)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_EXYNOS5430_BTS) || defined(CONFIG_EXYNOS5422_BTS) \
|
||||
|| defined(CONFIG_EXYNOS5433_BTS)|| defined(CONFIG_EXYNOS7420_BTS) \
|
||||
|| defined(CONFIG_EXYNOS7890_BTS) || defined(CONFIG_EXYNOS8890_BTS) \
|
||||
|| defined(CONFIG_EXYNOS7870_BTS) || defined(CONFIG_EXYNOS7570_BTS)
|
||||
void bts_initialize(const char *pd_name, bool on);
|
||||
#else
|
||||
#define bts_initialize(a, b) do {} while (0)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_EXYNOS7420_BTS) || defined(CONFIG_EXYNOS7890_BTS)
|
||||
void exynos7_bts_show_mo_status(void);
|
||||
#else
|
||||
#define exynos7_bts_show_mo_status() do {} while (0)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_EXYNOS5430_BTS)
|
||||
void exynos5_bts_show_mo_status(void);
|
||||
#else
|
||||
#define exynos5_bts_show_mo_status() do { } while (0)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_EXYNOS5430_BTS) || defined(CONFIG_EXYNOS5433_BTS)
|
||||
void bts_otf_initialize(unsigned int id, bool on);
|
||||
#else
|
||||
#define bts_otf_initialize(a, b) do {} while (0)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_EXYNOS5422_BTS) || defined(CONFIG_EXYNOS5433_BTS) \
|
||||
|| defined(CONFIG_EXYNOS7420_BTS) || defined(CONFIG_EXYNOS7890_BTS) \
|
||||
|| defined(CONFIG_EXYNOS8890_BTS) || defined(CONFIG_EXYNOS7870_BTS) \
|
||||
|| defined(CONFIG_EXYNOS7570_BTS)
|
||||
enum bts_scen_type {
|
||||
TYPE_MFC_UD_ENCODING = 0,
|
||||
TYPE_MFC_UD_DECODING,
|
||||
TYPE_LAYERS,
|
||||
TYPE_G3D_FREQ,
|
||||
TYPE_G3D_SCENARIO,
|
||||
TYPE_CAM_BNS,
|
||||
};
|
||||
|
||||
void bts_scen_update(enum bts_scen_type type, unsigned int val);
|
||||
#else
|
||||
#define bts_scen_update(a, b) do {} while(0)
|
||||
#endif
|
||||
|
||||
#endif
|
||||
188
include/soc/samsung/cpufreq.h
Normal file
188
include/soc/samsung/cpufreq.h
Normal file
|
|
@ -0,0 +1,188 @@
|
|||
/* linux/arch/arm64/mach-exynos/include/mach/cpufreq.h
|
||||
*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS - CPUFreq support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_CPUFREQ_H
|
||||
#define __ARCH_CPUFREQ_H __FILE__
|
||||
|
||||
#include <linux/notifier.h>
|
||||
|
||||
/*
|
||||
* Common definitions and structures
|
||||
*/
|
||||
#define APLL_FREQ(f, a0, a1, a2, a3, a4, a5, a6, a7, b0, b1, b2, m, p, s) \
|
||||
{ \
|
||||
.freq = (f) * 1000, \
|
||||
.clk_div_cpu0 = ((a0) | (a1) << 4 | (a2) << 8 | (a3) << 12 | \
|
||||
(a4) << 16 | (a5) << 20 | (a6) << 24 | (a7) << 28), \
|
||||
.clk_div_cpu1 = (b0 << 0 | b1 << 4 | b2 << 8), \
|
||||
.mps = ((m) << 16 | (p) << 8 | (s)), \
|
||||
}
|
||||
|
||||
/* APLL Macro for Atlas Frequency in ISTOR */
|
||||
#define APLL_ATLAS_FREQ(f, a0, a1, a2, a3, a4, a5, b0, b1, b2, m, p, s) \
|
||||
{ \
|
||||
.freq = (f) * 1000, \
|
||||
.clk_div_cpu0 = ((a0) | (a1) << 4 | (a2) << 8 | (a3) << 12 | \
|
||||
(a4) << 20 | (a5) << 26), \
|
||||
.clk_div_cpu1 = (b0 << 0 | b1 << 4 | b2 << 8), \
|
||||
.mps = ((m) << 16 | (p) << 8 | (s)), \
|
||||
}
|
||||
|
||||
enum cpufreq_level_index {
|
||||
L0, L1, L2, L3, L4,
|
||||
L5, L6, L7, L8, L9,
|
||||
L10, L11, L12, L13, L14,
|
||||
L15, L16, L17, L18, L19,
|
||||
L20, L21, L22, L23, L24,
|
||||
};
|
||||
|
||||
struct apll_freq {
|
||||
unsigned int freq;
|
||||
u32 clk_div_cpu0;
|
||||
u32 clk_div_cpu1;
|
||||
u32 mps;
|
||||
};
|
||||
|
||||
struct exynos_dvfs_info {
|
||||
unsigned long mpll_freq_khz;
|
||||
unsigned int pll_safe_idx;
|
||||
unsigned int max_idx_num;
|
||||
unsigned int max_support_idx;
|
||||
unsigned int min_support_idx;
|
||||
unsigned int cluster_num;
|
||||
unsigned int reboot_limit_freq;
|
||||
unsigned int boost_freq; /* use only KFC when enable HMP */
|
||||
unsigned int boot_freq;
|
||||
unsigned int boot_min_qos;
|
||||
unsigned int boot_max_qos;
|
||||
unsigned int boot_lock_time;
|
||||
unsigned int resume_freq;
|
||||
int boot_freq_idx;
|
||||
int *bus_table;
|
||||
int regulator_max_support_volt;
|
||||
bool blocked;
|
||||
unsigned int en_ema;
|
||||
unsigned int en_smpl;
|
||||
unsigned int cur_volt;
|
||||
struct clk *cpu_clk;
|
||||
unsigned int *volt_table;
|
||||
unsigned int *abb_table;
|
||||
const unsigned int *max_op_freqs;
|
||||
struct cpufreq_frequency_table *freq_table;
|
||||
struct regulator *regulator;
|
||||
void (*set_freq)(unsigned int, unsigned int);
|
||||
unsigned int (*get_freq)(void);
|
||||
void (*set_ema)(unsigned int);
|
||||
bool (*need_apll_change)(unsigned int, unsigned int);
|
||||
bool (*is_alive)(void);
|
||||
void (*set_int_skew)(int);
|
||||
int (*check_smpl)(void);
|
||||
void (*clear_smpl)(void);
|
||||
int (*init_smpl)(void);
|
||||
};
|
||||
|
||||
struct cpufreq_clkdiv {
|
||||
unsigned int index;
|
||||
unsigned int clkdiv0;
|
||||
unsigned int clkdiv1;
|
||||
};
|
||||
|
||||
struct cpufreq_dvfs_table {
|
||||
u32 index;
|
||||
u32 frequency;
|
||||
u32 voltage;
|
||||
s32 bus_qos_lock;
|
||||
};
|
||||
|
||||
/*
|
||||
* common interfaces for IPA
|
||||
*/
|
||||
/* interfaces for IPA */
|
||||
#if defined(CONFIG_ARM_EXYNOS_MP_CPUFREQ) || defined(CONFIG_ARM_EXYNOS_CPUFREQ)
|
||||
void exynos_set_max_freq(int max_freq, unsigned int cpu);
|
||||
void ipa_set_clamp(int cpu, unsigned int clamp_freq, unsigned int gov_target);
|
||||
#else
|
||||
static inline void exynos_set_max_freq(int max_freq, unsigned int cpu) {}
|
||||
static inline void ipa_set_clamp(int cpu, unsigned int clamp_freq, unsigned int gov_target) {}
|
||||
#endif
|
||||
|
||||
/* interface for THERMAL */
|
||||
extern void exynos_thermal_throttle(void);
|
||||
extern void exynos_thermal_unthrottle(void);
|
||||
|
||||
/*
|
||||
* CPUFREQ init events and notifiers
|
||||
*/
|
||||
#define CPUFREQ_INIT_COMPLETE 0x0001
|
||||
|
||||
#if defined(CONFIG_ARM_EXYNOS_MP_CPUFREQ) || defined(CONFIG_ARM_EXYNOS_CPUFREQ)
|
||||
extern int exynos_cpufreq_init_register_notifier(struct notifier_block *nb);
|
||||
extern int exynos_cpufreq_init_unregister_notifier(struct notifier_block *nb);
|
||||
#else
|
||||
static inline int exynos_cpufreq_init_register_notifier(struct notifier_block *nb)
|
||||
{return 0;}
|
||||
static inline int exynos_cpufreq_init_unregister_notifier(struct notifier_block *nb)
|
||||
{return 0;}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARM_EXYNOS_MP_CPUFREQ)
|
||||
extern int exynos_cpufreq_smpl_warn_notify_call_chain(void);
|
||||
#else
|
||||
static inline int exynos_cpufreq_smpl_warn_notify_call_chain(void){return 0;}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_FREQ)
|
||||
#if defined(CONFIG_ARM_EXYNOS_SC_CPUFREQ)
|
||||
extern int exynos_sc_cpufreq_cal_init(struct exynos_dvfs_info *);
|
||||
#endif
|
||||
extern int exynos_cpufreq_cluster0_init(struct exynos_dvfs_info *);
|
||||
extern int exynos_cpufreq_cluster1_init(struct exynos_dvfs_info *);
|
||||
typedef enum {
|
||||
CL_ZERO,
|
||||
CL_ONE,
|
||||
CL_END,
|
||||
} cluster_type;
|
||||
extern int exynos_cpufreq_regulator_register_notifier(cluster_type cluster);
|
||||
|
||||
#define COLD_VOLT_OFFSET 25000
|
||||
#define LIMIT_COLD_VOLTAGE 1350000
|
||||
#define MIN_COLD_VOLTAGE 950000
|
||||
#define NR_CLUST0_CPUS 4
|
||||
#define NR_CLUST1_CPUS 4
|
||||
#define CL0_POLICY_CPU 0
|
||||
#define CL1_POLICY_CPU 4
|
||||
|
||||
#define ENABLE_MIN_COLD 0
|
||||
|
||||
enum op_state {
|
||||
NORMAL, /* Operation : Normal */
|
||||
SUSPEND, /* Direct API will be blocked in this state */
|
||||
RESUME, /* Re-enabling DVFS using direct API after resume */
|
||||
};
|
||||
|
||||
/*
|
||||
* Keep frequency value for counterpart cluster DVFS
|
||||
* cur, min, max : Frequency (KHz),
|
||||
* c_id : Counter cluster with booting cluster, if booting cluster is
|
||||
* A15, c_id will be A7.
|
||||
*/
|
||||
struct cpu_info_alter {
|
||||
unsigned int cur;
|
||||
unsigned int min;
|
||||
unsigned int max;
|
||||
cluster_type boot_cluster;
|
||||
cluster_type c_id;
|
||||
};
|
||||
|
||||
extern cluster_type exynos_boot_cluster;
|
||||
#endif
|
||||
#endif /* __ARCH_CPUFREQ_H */
|
||||
106
include/soc/samsung/devfreq.h
Normal file
106
include/soc/samsung/devfreq.h
Normal file
|
|
@ -0,0 +1,106 @@
|
|||
/* linux/arch/arm64/mach-exynos/include/mach/devfreq.h
|
||||
*
|
||||
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef __EXYNOS_DEVFREQ_H_
|
||||
#define __EXYNOS_DEVFREQ_H_
|
||||
enum devfreq_media_type {
|
||||
TYPE_FIMC_LITE,
|
||||
TYPE_MIXER,
|
||||
#ifdef CONFIG_ARM_EXYNOS5422_BUS_DEVFREQ
|
||||
TYPE_FIMD1,
|
||||
#else
|
||||
TYPE_DECON,
|
||||
#endif
|
||||
#if defined(CONFIG_ARM_EXYNOS5422_BUS_DEVFREQ) || defined(CONFIG_ARM_EXYNOS5433_BUS_DEVFREQ) \
|
||||
|| defined(CONFIG_ARM_EXYNOS7420_BUS_DEVFREQ)
|
||||
TYPE_UD_ENCODING,
|
||||
TYPE_UD_DECODING,
|
||||
#endif
|
||||
TYPE_TV,
|
||||
TYPE_GSCL_LOCAL,
|
||||
TYPE_RESOLUTION,
|
||||
#if defined(CONFIG_ARM_EXYNOS7420_BUS_DEVFREQ)
|
||||
TYPE_VPP_ROTATION0,
|
||||
TYPE_VPP_ROTATION1,
|
||||
TYPE_VPP_ROTATION2,
|
||||
TYPE_VPP_ROTATION3,
|
||||
TYPE_VPP_SCALE_DOWN0,
|
||||
TYPE_VPP_SCALE_DOWN1,
|
||||
TYPE_VPP_SCALE_DOWN2,
|
||||
TYPE_VPP_SCALE_DOWN3,
|
||||
#endif
|
||||
};
|
||||
|
||||
enum devfreq_media_resolution {
|
||||
RESOLUTION_HD,
|
||||
RESOLUTION_FULLHD,
|
||||
RESOLUTION_WQHD,
|
||||
RESOLUTION_WQXGA,
|
||||
};
|
||||
|
||||
enum devfreq_layer_count {
|
||||
NUM_LAYER_0,
|
||||
NUM_LAYER_1,
|
||||
NUM_LAYER_2,
|
||||
NUM_LAYER_3,
|
||||
NUM_LAYER_4,
|
||||
NUM_LAYER_5,
|
||||
NUM_LAYER_6,
|
||||
};
|
||||
|
||||
#if defined(CONFIG_ARM_EXYNOS5430_BUS_DEVFREQ) || defined(CONFIG_ARM_EXYNOS5433_BUS_DEVFREQ)
|
||||
void exynos5_update_media_layers(enum devfreq_media_type media_type, unsigned int value);
|
||||
void exynos5_int_notify_power_status(const char* pd_name, unsigned int turn_on);
|
||||
void exynos5_isp_notify_power_status(const char* pd_name, unsigned int turn_on);
|
||||
void exynos5_disp_notify_power_status(const char* pd_name, unsigned int turn_on);
|
||||
unsigned long exynos5_devfreq_get_mif_freq(void);
|
||||
int exynos5_devfreq_get_mif_level(void);
|
||||
#elif defined(CONFIG_ARM_EXYNOS7420_BUS_DEVFREQ) || defined(CONFIG_ARM_EXYNOS7890_BUS_DEVFREQ)
|
||||
#define exynos7_update_media_layers(a, b) do {} while (0)
|
||||
void exynos7_int_notify_power_status(const char* pd_name, unsigned int turn_on);
|
||||
void exynos7_isp_notify_power_status(const char* pd_name, unsigned int turn_on);
|
||||
void exynos7_disp_notify_power_status(const char* pd_name, unsigned int turn_on);
|
||||
unsigned long vpp_get_int_freq(unsigned long freq);
|
||||
#elif defined(CONFIG_ARM_EXYNOS7580_BUS_DEVFREQ)
|
||||
void exynos7_int_notify_power_status(const char* pd_name, unsigned int turn_on);
|
||||
void exynos7_isp_notify_power_status(const char* pd_name, unsigned int turn_on);
|
||||
void exynos7_mif_notify_power_status(const char* pd_name, unsigned int turn_on);
|
||||
#define vpp_get_int_freq(a) do {} while (0)
|
||||
#elif defined(CONFIG_ARM_EXYNOS8890_BUS_DEVFREQ)
|
||||
#define vpp_get_int_freq(a) 0
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARM_EXYNOS5433_BUS_DEVFREQ)
|
||||
#include <linux/notifier.h>
|
||||
int exynos_mif_add_notifier(struct notifier_block *nb);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARM_EXYNOS5430_BUS_DEVFREQ) || defined(CONFIG_ARM_EXYNOS5433_BUS_DEVFREQ)
|
||||
extern int exynos5_mif_thermal_add_notifier(struct notifier_block *n);
|
||||
#else
|
||||
static inline int exynos5_mif_thermal_add_notifier(struct notifier_block *n)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARM_EXYNOS5422_BUS_DEVFREQ
|
||||
enum devfreq_transition {
|
||||
MIF_DEVFREQ_PRECHANGE,
|
||||
MIF_DEVFREQ_POSTCHANGE,
|
||||
MIF_DEVFREQ_EN_MONITORING,
|
||||
MIF_DEVFREQ_DIS_MONITORING,
|
||||
};
|
||||
|
||||
void exynos5_int_nocp_resume(void);
|
||||
void exynos5_mif_transition_disable(bool disable);
|
||||
void exynos5_update_media_layers(enum devfreq_media_type media_type, unsigned int value);
|
||||
#endif /* CONFIG_ARM_EXYNOS5422_BUS_DEVFREQ */
|
||||
|
||||
#endif
|
||||
384
include/soc/samsung/ect_parser.h
Normal file
384
include/soc/samsung/ect_parser.h
Normal file
|
|
@ -0,0 +1,384 @@
|
|||
/* arch/arm64/mach-exynos/include/mach/apm-exynos.h
|
||||
*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* AP Parameter definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ECT_PARSER_H
|
||||
#define __ECT_PARSER_H __FILE__
|
||||
|
||||
#include <linux/slab.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/errno.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/stat.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/debugfs.h>
|
||||
|
||||
#define BLOCK_HEADER "HEADER"
|
||||
|
||||
#define BLOCK_AP_THERMAL "THERMAL"
|
||||
#define BLOCK_MIF_THERMAL "MR4"
|
||||
#define BLOCK_DVFS "DVFS"
|
||||
#define BLOCK_ASV "ASV"
|
||||
#define BLOCK_TIMING_PARAM "TIMING"
|
||||
#define BLOCK_RCC "RCC"
|
||||
#define BLOCK_PLL "PLL"
|
||||
#define BLOCK_MARGIN "MARGIN"
|
||||
#define BLOCK_MINLOCK "MINLOCK"
|
||||
#define BLOCK_GEN_PARAM "GEN"
|
||||
#define BLOCK_BIN "BIN"
|
||||
|
||||
#define SYSFS_NODE_HEADER "header"
|
||||
#define SYSFS_NODE_AP_THERMAL "ap_thermal"
|
||||
#define SYSFS_NODE_MIF_THERMAL "mr4"
|
||||
#define SYSFS_NODE_DVFS "dvfs_table"
|
||||
#define SYSFS_NODE_ASV "asv_table"
|
||||
#define SYSFS_NODE_TIMING_PARAM "mif_timing_parameter"
|
||||
#define SYSFS_NODE_RCC "rcc_table"
|
||||
#define SYSFS_NODE_PLL "pll_list"
|
||||
#define SYSFS_NODE_MARGIN "margin_table"
|
||||
#define SYSFS_NODE_MINLOCK "minlock_table"
|
||||
#define SYSFS_NODE_GEN_PARAM "general_parameter"
|
||||
#define SYSFS_NODE_BIN "binary"
|
||||
|
||||
#define PMIC_VOLTAGE_STEP (6250)
|
||||
|
||||
struct ect_header
|
||||
{
|
||||
char sign[4];
|
||||
char version[4];
|
||||
unsigned int total_size;
|
||||
int num_of_header;
|
||||
};
|
||||
|
||||
struct ect_dvfs_level
|
||||
{
|
||||
unsigned int level;
|
||||
int level_en;
|
||||
};
|
||||
|
||||
struct ect_dvfs_domain
|
||||
{
|
||||
char *domain_name;
|
||||
unsigned int domain_offset;
|
||||
|
||||
unsigned int max_frequency;
|
||||
unsigned int min_frequency;
|
||||
int boot_level_idx;
|
||||
int resume_level_idx;
|
||||
int num_of_clock;
|
||||
int num_of_level;
|
||||
char **list_clock;
|
||||
struct ect_dvfs_level *list_level;
|
||||
unsigned int *list_dvfs_value;
|
||||
};
|
||||
|
||||
struct ect_dvfs_header
|
||||
{
|
||||
int parser_version;
|
||||
char version[4];
|
||||
int num_of_domain;
|
||||
|
||||
struct ect_dvfs_domain *domain_list;
|
||||
};
|
||||
|
||||
struct ect_pll_frequency
|
||||
{
|
||||
unsigned int frequency;
|
||||
unsigned int p;
|
||||
unsigned int m;
|
||||
unsigned int s;
|
||||
unsigned int k;
|
||||
};
|
||||
|
||||
struct ect_pll
|
||||
{
|
||||
char *pll_name;
|
||||
unsigned int pll_offset;
|
||||
|
||||
unsigned int type_pll;
|
||||
int num_of_frequency;
|
||||
struct ect_pll_frequency *frequency_list;
|
||||
};
|
||||
|
||||
struct ect_pll_header
|
||||
{
|
||||
int parser_version;
|
||||
char version[4];
|
||||
int num_of_pll;
|
||||
|
||||
struct ect_pll *pll_list;
|
||||
};
|
||||
|
||||
struct ect_voltage_table
|
||||
{
|
||||
int table_version;
|
||||
int boot_level_idx;
|
||||
int resume_level_idx;
|
||||
int *level_en;
|
||||
unsigned int *voltages;
|
||||
unsigned char *voltages_step;
|
||||
unsigned int volt_step;
|
||||
};
|
||||
|
||||
struct ect_voltage_domain
|
||||
{
|
||||
char *domain_name;
|
||||
unsigned int domain_offset;
|
||||
|
||||
int num_of_group;
|
||||
int num_of_level;
|
||||
int num_of_table;
|
||||
unsigned int *level_list;
|
||||
struct ect_voltage_table *table_list;
|
||||
};
|
||||
|
||||
struct ect_voltage_header
|
||||
{
|
||||
int parser_version;
|
||||
char version[4];
|
||||
int num_of_domain;
|
||||
|
||||
struct ect_voltage_domain *domain_list;
|
||||
};
|
||||
|
||||
struct ect_rcc_table
|
||||
{
|
||||
int table_version;
|
||||
|
||||
unsigned int *rcc;
|
||||
unsigned char *rcc_compact;
|
||||
};
|
||||
|
||||
struct ect_rcc_domain
|
||||
{
|
||||
char *domain_name;
|
||||
unsigned int domain_offset;
|
||||
|
||||
int num_of_group;
|
||||
int num_of_level;
|
||||
int num_of_table;
|
||||
unsigned int *level_list;
|
||||
struct ect_rcc_table *table_list;
|
||||
};
|
||||
|
||||
struct ect_rcc_header
|
||||
{
|
||||
int parser_version;
|
||||
char version[4];
|
||||
int num_of_domain;
|
||||
|
||||
struct ect_rcc_domain *domain_list;
|
||||
};
|
||||
|
||||
struct ect_mif_thermal_level
|
||||
{
|
||||
int mr4_level;
|
||||
unsigned int max_frequency;
|
||||
unsigned int min_frequency;
|
||||
unsigned int refresh_rate_value;
|
||||
unsigned int polling_period;
|
||||
unsigned int sw_trip;
|
||||
};
|
||||
|
||||
struct ect_mif_thermal_header
|
||||
{
|
||||
int parser_version;
|
||||
char version[4];
|
||||
int num_of_level;
|
||||
|
||||
struct ect_mif_thermal_level *level;
|
||||
};
|
||||
|
||||
struct ect_ap_thermal_range
|
||||
{
|
||||
unsigned int lower_bound_temperature;
|
||||
unsigned int upper_bound_temperature;
|
||||
unsigned int max_frequency;
|
||||
unsigned int sw_trip;
|
||||
unsigned int flag;
|
||||
};
|
||||
|
||||
struct ect_ap_thermal_function
|
||||
{
|
||||
char *function_name;
|
||||
unsigned int function_offset;
|
||||
|
||||
int num_of_range;
|
||||
struct ect_ap_thermal_range *range_list;
|
||||
};
|
||||
|
||||
struct ect_ap_thermal_header
|
||||
{
|
||||
int parser_version;
|
||||
char version[4];
|
||||
int num_of_function;
|
||||
|
||||
struct ect_ap_thermal_function *function_list;
|
||||
};
|
||||
|
||||
struct ect_margin_domain
|
||||
{
|
||||
char *domain_name;
|
||||
unsigned int domain_offset;
|
||||
|
||||
int num_of_group;
|
||||
int num_of_level;
|
||||
unsigned int *offset;
|
||||
unsigned char *offset_compact;
|
||||
unsigned int volt_step;
|
||||
};
|
||||
|
||||
struct ect_margin_header
|
||||
{
|
||||
int parser_version;
|
||||
char version[4];
|
||||
int num_of_domain;
|
||||
|
||||
struct ect_margin_domain *domain_list;
|
||||
};
|
||||
|
||||
struct ect_timing_param_size
|
||||
{
|
||||
unsigned int memory_size;
|
||||
unsigned int offset
|
||||
;
|
||||
int num_of_timing_param;
|
||||
int num_of_level;
|
||||
unsigned int *timing_parameter;
|
||||
};
|
||||
|
||||
struct ect_timing_param_header
|
||||
{
|
||||
int parser_version;
|
||||
char version[4];
|
||||
int num_of_size;
|
||||
|
||||
struct ect_timing_param_size *size_list;
|
||||
};
|
||||
|
||||
struct ect_minlock_frequency
|
||||
{
|
||||
unsigned int main_frequencies;
|
||||
unsigned int sub_frequencies;
|
||||
};
|
||||
|
||||
struct ect_minlock_domain
|
||||
{
|
||||
char *domain_name;
|
||||
unsigned int domain_offset;
|
||||
|
||||
int num_of_level;
|
||||
struct ect_minlock_frequency *level;
|
||||
};
|
||||
|
||||
struct ect_minlock_header
|
||||
{
|
||||
int parser_version;
|
||||
char version[4];
|
||||
int num_of_domain;
|
||||
|
||||
struct ect_minlock_domain *domain_list;
|
||||
};
|
||||
|
||||
struct ect_gen_param_table
|
||||
{
|
||||
char *table_name;
|
||||
unsigned int offset;
|
||||
|
||||
int num_of_col;
|
||||
int num_of_row;
|
||||
unsigned int *parameter;
|
||||
};
|
||||
|
||||
struct ect_gen_param_header
|
||||
{
|
||||
int parser_version;
|
||||
char version[4];
|
||||
int num_of_table;
|
||||
|
||||
struct ect_gen_param_table *table_list;
|
||||
};
|
||||
|
||||
struct ect_bin
|
||||
{
|
||||
char *binary_name;
|
||||
unsigned int offset;
|
||||
|
||||
int binary_size;
|
||||
void *ptr;
|
||||
};
|
||||
|
||||
struct ect_bin_header
|
||||
{
|
||||
int parser_version;
|
||||
char version[4];
|
||||
int num_of_binary;
|
||||
|
||||
struct ect_bin *binary_list;
|
||||
};
|
||||
|
||||
struct ect_info
|
||||
{
|
||||
char *block_name;
|
||||
int block_name_length;
|
||||
int (*parser)(void *address, struct ect_info *info);
|
||||
int (*dump)(struct seq_file *s, void *data);
|
||||
struct file_operations dump_ops;
|
||||
char *dump_node_name;
|
||||
void *block_handle;
|
||||
int block_precedence;
|
||||
};
|
||||
|
||||
#if defined(CONFIG_ECT)
|
||||
void ect_init(phys_addr_t address, phys_addr_t size);
|
||||
int ect_parse_binary_header(void);
|
||||
void* ect_get_block(char *block_name);
|
||||
struct ect_dvfs_domain *ect_dvfs_get_domain(void *block, char *domain_name);
|
||||
struct ect_pll *ect_pll_get_pll(void *block, char *pll_name);
|
||||
struct ect_voltage_domain *ect_asv_get_domain(void *block, char *domain_name);
|
||||
struct ect_rcc_domain *ect_rcc_get_domain(void *block, char *domain_name);
|
||||
struct ect_mif_thermal_level *ect_mif_thermal_get_level(void *block, int mr4_level);
|
||||
struct ect_ap_thermal_function *ect_ap_thermal_get_function(void *block, char *function_name);
|
||||
struct ect_margin_domain *ect_margin_get_domain(void *block, char *domain_name);
|
||||
struct ect_timing_param_size *ect_timing_param_get_size(void *block, int size);
|
||||
struct ect_minlock_domain *ect_minlock_get_domain(void *block, char *domain_name);
|
||||
struct ect_gen_param_table *ect_gen_param_get_table(void *block, char *table_name);
|
||||
struct ect_bin *ect_binary_get_bin(void *block, char *binary_name);
|
||||
|
||||
void ect_init_map_io(void);
|
||||
|
||||
int ect_strcmp(char *src1, char *src2);
|
||||
|
||||
#else
|
||||
|
||||
static inline void ect_init(phys_addr_t address, phys_addr_t size) {}
|
||||
static inline int ect_parse_binary_header(void) { return 0; }
|
||||
static inline void* ect_get_block(char *block_name) { return NULL; }
|
||||
static inline struct ect_dvfs_domain *ect_dvfs_get_domain(void *block, char *domain_name) { return NULL; }
|
||||
static inline struct ect_pll *ect_pll_get_pll(void *block, char *pll_name) { return NULL; }
|
||||
static inline struct ect_voltage_domain *ect_asv_get_domain(void *block, char *domain_name) { return NULL; }
|
||||
static inline struct ect_rcc_domain *ect_rcc_get_domain(void *block, char *domain_name) { return NULL; }
|
||||
static inline struct ect_mif_thermal_level *ect_mif_thermal_get_level(void *block, int mr4_level) { return NULL; }
|
||||
static inline struct ect_ap_thermal_function *ect_ap_thermal_get_function(void *block, char *function_name) { return NULL; }
|
||||
static inline struct ect_margin_domain *ect_margin_get_domain(void *block, char *domain_name) { return NULL; }
|
||||
static inline struct ect_timing_param_size *ect_timing_param_get_size(void *block, int size) { return NULL; }
|
||||
static inline struct ect_minlock_domain *ect_minlock_get_domain(void *block, char *domain_name) { return NULL; }
|
||||
static inline struct ect_gen_param_table *ect_gen_param_get_table(void *block, char *table_name) { return NULL; }
|
||||
static inline struct ect_bin *ect_binary_get_bin(void *block, char *binary_name) { return NULL; }
|
||||
|
||||
static inline void ect_init_map_io(void) {}
|
||||
|
||||
static inline int ect_strcmp(char *src1, char *src2) { return -1; }
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
19
include/soc/samsung/exynos-cpu_hotplug.h
Normal file
19
include/soc/samsung/exynos-cpu_hotplug.h
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* EXYNOS - CPU Hotplug support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __EXYNOS_CPU_HOTPLUG_H
|
||||
#define __EXYNOS_CPU_HOTPLUG_H __FILE__
|
||||
|
||||
struct kobject *exynos_cpu_hotplug_kobj(void);
|
||||
bool exynos_cpu_hotplug_enabled(void);
|
||||
|
||||
#endif /* __EXYNOS_CPU_HOTPLUG_H */
|
||||
|
||||
14
include/soc/samsung/exynos-devfreq-dep.h
Normal file
14
include/soc/samsung/exynos-devfreq-dep.h
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
/* linux/arch/arm64/mach-exynos/include/mach/exynos-devfreq-dep.h
|
||||
*
|
||||
* Copyright (c) 2015 Samsung Electronics Co., Ltd
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation
|
||||
*/
|
||||
|
||||
#ifndef __EXYNOS_DEVFREQ_DEP_H_
|
||||
#define __EXYNOS_DEVFREQ_DEP_H_
|
||||
|
||||
#endif /* __EXYNOS_DEVFREQ_DEP_H_ */
|
||||
232
include/soc/samsung/exynos-devfreq.h
Normal file
232
include/soc/samsung/exynos-devfreq.h
Normal file
|
|
@ -0,0 +1,232 @@
|
|||
/* linux/arch/arm64/mach-exynos/include/mach/exynos-devfreq.h
|
||||
*
|
||||
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef __EXYNOS_DEVFREQ_H_
|
||||
#define __EXYNOS_DEVFREQ_H_
|
||||
|
||||
#include <linux/devfreq.h>
|
||||
#include <linux/pm_qos.h>
|
||||
#include <linux/clk.h>
|
||||
#include <soc/samsung/exynos-devfreq-dep.h>
|
||||
|
||||
#define EXYNOS_DEVFREQ_MODULE_NAME "exynos-devfreq"
|
||||
#define VOLT_STEP 25000
|
||||
|
||||
enum exynos_devfreq_type {
|
||||
DEVFREQ_MIF = 0,
|
||||
DEVFREQ_INT,
|
||||
DEVFREQ_DISP,
|
||||
DEVFREQ_CAM,
|
||||
DEVFREQ_TYPE_END
|
||||
};
|
||||
|
||||
enum exynos_devfreq_gov_type {
|
||||
SIMPLE_INTERACTIVE = 0,
|
||||
GOV_TYPE_END
|
||||
};
|
||||
|
||||
/* "Utlization Monitor" type */
|
||||
enum UM_TYPE {
|
||||
UM_MIF = 0,
|
||||
UM_INT,
|
||||
NONE_UM
|
||||
};
|
||||
|
||||
enum volt_order_type {
|
||||
KEEP_SET_VOLT = 0,
|
||||
PRE_SET_VOLT,
|
||||
POST_SET_VOLT
|
||||
};
|
||||
|
||||
enum exynos_devfreq_lv_index {
|
||||
DEV_LV0 = 0,
|
||||
DEV_LV1,
|
||||
DEV_LV2,
|
||||
DEV_LV3,
|
||||
DEV_LV4,
|
||||
DEV_LV5,
|
||||
DEV_LV6,
|
||||
DEV_LV7,
|
||||
DEV_LV8,
|
||||
DEV_LV9,
|
||||
DEV_LV10,
|
||||
DEV_LV11,
|
||||
DEV_LV12,
|
||||
DEV_LV13,
|
||||
DEV_LV14,
|
||||
DEV_LV15,
|
||||
DEV_LV16,
|
||||
DEV_LV17,
|
||||
DEV_LV18,
|
||||
DEV_LV19,
|
||||
DEV_LV20,
|
||||
DEV_LV_END,
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
APL_EXYNOS_FREQ = 0,
|
||||
ATL_EXYNOS_FREQ,
|
||||
INT_EXYNOS_FREQ,
|
||||
MIF_EXYNOS_FREQ,
|
||||
ISP_EXYNOS_FREQ,
|
||||
DISP_EXYNOS_FREQ,
|
||||
};
|
||||
|
||||
struct exynos_devfreq_opp_table {
|
||||
u32 idx;
|
||||
u32 freq;
|
||||
u32 volt;
|
||||
};
|
||||
|
||||
struct exynos_devfreq_data;
|
||||
struct um_exynos;
|
||||
|
||||
struct exynos_devfreq_ops {
|
||||
int (*init)(struct exynos_devfreq_data *);
|
||||
int (*exit)(struct exynos_devfreq_data *);
|
||||
int (*init_freq_table)(struct exynos_devfreq_data *);
|
||||
int (*get_volt_table)(struct device *, u32, struct exynos_devfreq_opp_table *);
|
||||
int (*um_register)(struct exynos_devfreq_data *);
|
||||
int (*um_unregister)(struct exynos_devfreq_data *);
|
||||
int (*pm_suspend_prepare)(struct exynos_devfreq_data *);
|
||||
int (*pm_post_suspend)(struct exynos_devfreq_data *);
|
||||
int (*suspend)(struct exynos_devfreq_data *);
|
||||
int (*resume)(struct exynos_devfreq_data *);
|
||||
int (*reboot)(struct exynos_devfreq_data *);
|
||||
int (*get_switch_voltage)(struct device *, u32, u32, u32, u32, u32 *);
|
||||
void (*set_voltage_prepare)(struct exynos_devfreq_data *);
|
||||
void (*set_voltage_post)(struct exynos_devfreq_data *);
|
||||
int (*get_switch_freq)(struct device *, u32, u32, u32 *);
|
||||
int (*get_freq)(struct device *, u32 *, struct clk *);
|
||||
int (*set_freq)(struct device *, u32, struct clk *);
|
||||
int (*set_freq_prepare)(struct exynos_devfreq_data *);
|
||||
int (*set_freq_post)(struct exynos_devfreq_data *);
|
||||
int (*change_to_switch_freq)(struct device *, struct clk *, u32, u32, u32 *);
|
||||
int (*restore_from_switch_freq)(struct device *, struct clk *, u32, u32);
|
||||
int (*get_dev_status)(struct exynos_devfreq_data *);
|
||||
int (*cl_dvfs_start)(struct device *);
|
||||
int (*cl_dvfs_stop)(struct device *, u32);
|
||||
int (*cmu_dump)(struct exynos_devfreq_data *);
|
||||
};
|
||||
|
||||
struct um_addr {
|
||||
void __iomem *base;
|
||||
};
|
||||
|
||||
struct um_exynos {
|
||||
struct list_head node;
|
||||
struct um_addr *um_list;
|
||||
unsigned int um_count;
|
||||
u64 val_ccnt;
|
||||
u64 val_pmcnt;
|
||||
enum UM_TYPE type;
|
||||
};
|
||||
|
||||
struct exynos_devfreq_data {
|
||||
struct device *dev;
|
||||
struct devfreq *devfreq;
|
||||
struct mutex lock;
|
||||
struct clk *clk;
|
||||
struct clk *sw_clk;
|
||||
|
||||
bool devfreq_disabled;
|
||||
|
||||
enum exynos_devfreq_type devfreq_type;
|
||||
|
||||
struct exynos_devfreq_opp_table opp_list[DEV_LV_END];
|
||||
|
||||
u32 default_qos;
|
||||
|
||||
bool use_get_dev;
|
||||
u32 max_state;
|
||||
struct devfreq_dev_profile devfreq_profile;
|
||||
|
||||
enum exynos_devfreq_gov_type gov_type;
|
||||
const char *governor_name;
|
||||
u32 cal_qos_max;
|
||||
void *governor_data;
|
||||
#if IS_ENABLED(CONFIG_DEVFREQ_GOV_SIMPLE_INTERACTIVE)
|
||||
struct devfreq_simple_interactive_data simple_interactive_data;
|
||||
#endif
|
||||
s32 old_idx;
|
||||
s32 new_idx;
|
||||
u32 old_freq;
|
||||
u32 new_freq;
|
||||
u32 min_freq;
|
||||
u32 max_freq;
|
||||
u32 reboot_freq;
|
||||
|
||||
u32 old_volt;
|
||||
u32 new_volt;
|
||||
u32 volt_offset;
|
||||
u32 cold_volt_offset;
|
||||
u32 limit_cold_volt;
|
||||
u32 min_cold_volt;
|
||||
u32 reg_max_volt;
|
||||
bool use_regulator;
|
||||
bool use_pd_off;
|
||||
const char *regulator_name;
|
||||
struct regulator *vdd;
|
||||
struct mutex regulator_lock;
|
||||
|
||||
u32 pm_qos_class;
|
||||
u32 pm_qos_class_max;
|
||||
struct pm_qos_request sys_pm_qos_min;
|
||||
#ifdef CONFIG_ARM_EXYNOS_DEVFREQ_DEBUG
|
||||
struct pm_qos_request debug_pm_qos_min;
|
||||
struct pm_qos_request debug_pm_qos_max;
|
||||
#endif
|
||||
struct pm_qos_request default_pm_qos_min;
|
||||
struct pm_qos_request default_pm_qos_max;
|
||||
struct pm_qos_request boot_pm_qos;
|
||||
u32 boot_qos_timeout;
|
||||
|
||||
u32 um_base[16];
|
||||
struct devfreq_notifier_block *um_nb;
|
||||
struct um_exynos um_data;
|
||||
bool use_um;
|
||||
u32 last_monitor_period;
|
||||
u64 last_monitor_jiffies;
|
||||
u32 last_um_usage_rate;
|
||||
|
||||
bool use_tmu;
|
||||
struct notifier_block tmu_notifier;
|
||||
struct notifier_block reboot_notifier;
|
||||
struct notifier_block pm_notifier;
|
||||
|
||||
u32 ess_flag;
|
||||
|
||||
bool use_cl_dvfs;
|
||||
|
||||
s32 target_delay;
|
||||
s32 setfreq_delay;
|
||||
|
||||
bool use_switch_clk;
|
||||
u32 switch_freq;
|
||||
u32 switch_volt;
|
||||
|
||||
void *private_data;
|
||||
struct exynos_devfreq_ops ops;
|
||||
};
|
||||
|
||||
int register_exynos_devfreq_init_prepare(enum exynos_devfreq_type type,
|
||||
int (*func)(struct exynos_devfreq_data *));
|
||||
s32 exynos_devfreq_get_opp_idx(struct exynos_devfreq_opp_table *table,
|
||||
unsigned int size, u32 freq);
|
||||
#if defined(CONFIG_ARM_EXYNOS_DEVFREQ)
|
||||
int exynos_devfreq_sync_voltage(enum exynos_devfreq_type type, bool turn_on);
|
||||
#else
|
||||
static inline
|
||||
int exynos_devfreq_sync_voltage(enum exynos_devfreq_type type, bool turn_on)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
#endif /* __EXYNOS_DEVFREQ_H_ */
|
||||
92
include/soc/samsung/exynos-pd.h
Normal file
92
include/soc/samsung/exynos-pd.h
Normal file
|
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* Exynos PM domain support.
|
||||
*
|
||||
* Copyright (c) 2016 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Implementation of Exynos specific power domain control which is used in
|
||||
* conjunction with runtime-pm. Support for both device-tree and non-device-tree
|
||||
* based power domain support is included.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef __EXYNOS_PD_H
|
||||
#define __EXYNOS_PD_H __FILE__
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_domain.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/mutex.h>
|
||||
|
||||
#include <linux/mfd/samsung/core.h>
|
||||
#include <soc/samsung/bcm.h>
|
||||
|
||||
#include "../../../drivers/soc/samsung/pwrcal/pwrcal.h"
|
||||
|
||||
#include <soc/samsung/exynos-powermode.h>
|
||||
#include <soc/samsung/exynos-pm.h>
|
||||
#include <soc/samsung/exynos-devfreq.h>
|
||||
#include <soc/samsung/bts.h>
|
||||
|
||||
#define EXYNOS_PD_PREFIX "EXYNOS-PD: "
|
||||
#define EXYNOS_PD_DBG_PREFIX "EXYNOS-PD-DBG: "
|
||||
|
||||
#ifndef pr_fmt
|
||||
#define pr_fmt(fmt) fmt
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_EXYNOS_PM_DOMAIN_DEBUG
|
||||
#define DEBUG_PRINT_INFO(fmt, ...) printk(PM_DOMAIN_PREFIX pr_fmt(fmt), ##__VA_ARGS__)
|
||||
#else
|
||||
#define DEBUG_PRINT_INFO(fmt, ...)
|
||||
#endif
|
||||
|
||||
/* In Exynos, the number of MAX_POWER_DOMAIN is less than 15 */
|
||||
#define MAX_PARENT_POWER_DOMAIN 15
|
||||
|
||||
struct exynos_pm_domain;
|
||||
|
||||
struct exynos_pm_domain {
|
||||
struct generic_pm_domain genpd;
|
||||
char *name;
|
||||
unsigned int cal_pdid;
|
||||
struct device_node *of_node;
|
||||
int (*pd_control)(unsigned int cal_id, int on);
|
||||
int (*check_status)(struct exynos_pm_domain *pd);
|
||||
unsigned int bts;
|
||||
int devfreq_index;
|
||||
struct mutex access_lock;
|
||||
int idle_ip_index;
|
||||
#if defined(CONFIG_EXYNOS_BCM)
|
||||
struct bcm_info *bcm;
|
||||
#endif
|
||||
bool check_cp_status;
|
||||
};
|
||||
|
||||
struct exynos_pd_dbg_info {
|
||||
struct device *dev;
|
||||
#ifdef CONFIG_DEBUG_FS
|
||||
struct dentry *d;
|
||||
struct file_operations fops;
|
||||
#endif
|
||||
};
|
||||
|
||||
#ifdef CONFIG_EXYNOS_PD
|
||||
struct exynos_pm_domain *exynos_pd_lookup_name(const char *domain_name);
|
||||
#else
|
||||
static inline struct exynos_pm_domain *exynos_pd_lookup_name(const char *domain_name)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __EXYNOS_PD_H */
|
||||
85
include/soc/samsung/exynos-pm.h
Normal file
85
include/soc/samsung/exynos-pm.h
Normal file
|
|
@ -0,0 +1,85 @@
|
|||
/* linux/arm/arm/mach-exynos/include/mach/regs-clock.h
|
||||
*
|
||||
* Copyright (C) 2013 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS5 - Header file for exynos pm support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __EXYNOS_PM_H
|
||||
#define __EXYNOS_PM_H
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/notifier.h>
|
||||
|
||||
/*
|
||||
* Event codes for PM states
|
||||
*/
|
||||
enum exynos_pm_event {
|
||||
/* CPU is entering the LPA state */
|
||||
LPA_ENTER,
|
||||
|
||||
/* CPU failed to enter the LPA state */
|
||||
LPA_ENTER_FAIL,
|
||||
|
||||
/* CPU is exiting the LPA state */
|
||||
LPA_EXIT,
|
||||
|
||||
/* CPU is entering the SICD state */
|
||||
SICD_ENTER,
|
||||
|
||||
/* CPU is exiting the SICD state */
|
||||
SICD_EXIT,
|
||||
|
||||
/* Dummy power mode for uart */
|
||||
SICD_AUD_ENTER,
|
||||
SICD_AUD_EXIT,
|
||||
};
|
||||
|
||||
#define EXYNOS_PM_PREFIX "EXYNOS-PM:"
|
||||
|
||||
bool is_test_cp_call_set(void);
|
||||
|
||||
#ifdef CONFIG_CPU_IDLE
|
||||
int exynos_pm_register_notifier(struct notifier_block *nb);
|
||||
int exynos_pm_unregister_notifier(struct notifier_block *nb);
|
||||
int exynos_pm_lpa_enter(void);
|
||||
int exynos_pm_lpa_exit(void);
|
||||
int exynos_pm_sicd_enter(void);
|
||||
int exynos_pm_sicd_exit(void);
|
||||
#else
|
||||
static inline int exynos_pm_register_notifier(struct notifier_block *nb)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int exynos_pm_unregister_notifier(struct notifier_block *nb)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int exynos_pm_lpa_enter(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int exynos_pm_lpa_exit(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int exynos_pm_sicd_enter(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline int exynos_pm_sicd_exit(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
#endif /* __EXYNOS_PM_H */
|
||||
45
include/soc/samsung/exynos-pmu.h
Normal file
45
include/soc/samsung/exynos-pmu.h
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* EXYNOS - PMU(Power Management Unit) support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __EXYNOS_PMU_H
|
||||
#define __EXYNOS_PMU_H __FILE__
|
||||
|
||||
/**
|
||||
* struct exynos_cpu_power_ops
|
||||
*
|
||||
* CPU power control operations
|
||||
*
|
||||
* @power_up : Set cpu configuration register
|
||||
* @power_down : Clear cpu configuration register
|
||||
* @power_state : Show cpu status. Return true if cpu power on, otherwise return false.
|
||||
*/
|
||||
struct exynos_cpu_power_ops {
|
||||
void (*power_up)(unsigned int cpu);
|
||||
void (*power_down)(unsigned int cpu);
|
||||
int (*power_state)(unsigned int cpu);
|
||||
void (*cluster_up)(unsigned int cluster);
|
||||
void (*cluster_down)(unsigned int cluster);
|
||||
int (*cluster_state)(unsigned int cluster);
|
||||
int (*l2_state)(unsigned int cluster);
|
||||
int (*noncpu_state)(unsigned int cluster);
|
||||
};
|
||||
extern struct exynos_cpu_power_ops exynos_cpu;
|
||||
|
||||
/**
|
||||
* The APIs to control the PMU
|
||||
*/
|
||||
int exynos_pmu_read(unsigned int offset, unsigned int *val);
|
||||
int exynos_pmu_write(unsigned int offset, unsigned int val);
|
||||
int exynos_pmu_update(unsigned int offset, unsigned int mask, unsigned int val);
|
||||
|
||||
int exynos_check_cp_status(void);
|
||||
|
||||
#endif /* __EXYNOS_PMU_H */
|
||||
145
include/soc/samsung/exynos-powermode.h
Normal file
145
include/soc/samsung/exynos-powermode.h
Normal file
|
|
@ -0,0 +1,145 @@
|
|||
/*
|
||||
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* EXYNOS - PMU(Power Management Unit) support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __EXYNOS_POWERMODE_H
|
||||
#define __EXYNOS_POWERMODE_H __FILE__
|
||||
|
||||
#if defined(CONFIG_PMUCAL_MOD)
|
||||
#include "../../../drivers/soc/samsung/pwrcal/pmucal_mod/pmucal_system.h"
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_PMUCAL_MOD)
|
||||
/**
|
||||
* System power down mode
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS7570)
|
||||
enum sys_powerdown {
|
||||
SYS_SICD,
|
||||
SYS_AFTR,
|
||||
SYS_STOP,
|
||||
SYS_LPD,
|
||||
SYS_LPA,
|
||||
SYS_DSTOP,
|
||||
SYS_SLEEP,
|
||||
NUM_SYS_POWERDOWN,
|
||||
};
|
||||
#else
|
||||
enum sys_powerdown {
|
||||
SYS_SICD,
|
||||
#if !defined(CONFIG_SOC_EXYNOS7870)
|
||||
SYS_SICD_CPD,
|
||||
#endif
|
||||
SYS_AFTR,
|
||||
SYS_STOP,
|
||||
#if !defined(CONFIG_SOC_EXYNOS7870)
|
||||
SYS_DSTOP,
|
||||
#endif
|
||||
SYS_LPD,
|
||||
#if !defined(CONFIG_SOC_EXYNOS7870)
|
||||
SYS_ALPA,
|
||||
#endif
|
||||
SYS_SLEEP,
|
||||
NUM_SYS_POWERDOWN,
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
||||
extern void exynos_prepare_sys_powerdown(enum sys_powerdown mode, bool is_suspend);
|
||||
extern void exynos_wakeup_sys_powerdown(enum sys_powerdown mode, bool early_wakeup);
|
||||
extern int determine_lpm(void);
|
||||
|
||||
/**
|
||||
* Functions for cpuidle driver
|
||||
*/
|
||||
extern int enter_c2(unsigned int cpu, int index);
|
||||
extern void wakeup_from_c2(unsigned int cpu, int early_wakeup);
|
||||
|
||||
/**
|
||||
* Cluster power down blocker
|
||||
*/
|
||||
extern void block_cpd(void);
|
||||
extern void release_cpd(void);
|
||||
|
||||
/**
|
||||
* Checking cluster idle state
|
||||
*/
|
||||
extern int check_cluster_idle_state(unsigned int cpu);
|
||||
|
||||
/**
|
||||
IDLE_IP control
|
||||
*/
|
||||
#define IDLE_IP_REG_SIZE 32
|
||||
#define IDLE_IP_MAX_INDEX 127
|
||||
#define IDLE_IP_FIX_INDEX_COUNT 2
|
||||
#define IDLE_IP_MAX_CONFIGURABLE_INDEX (IDLE_IP_MAX_INDEX - IDLE_IP_FIX_INDEX_COUNT)
|
||||
|
||||
|
||||
#ifdef CONFIG_CPU_IDLE
|
||||
void exynos_update_ip_idle_status(int index, int idle);
|
||||
int exynos_get_idle_ip_index(const char *name);
|
||||
void exynos_get_idle_ip_list(char *(*idle_ip_list)[IDLE_IP_REG_SIZE]);
|
||||
#else
|
||||
static inline void exynos_update_ip_idle_status(int index, int idle)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
static inline int exynos_get_idle_ip_index(const char *name)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void exynos_get_idle_ip_list(char *(*idle_ip_list)[IDLE_IP_REG_SIZE])
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
enum exynos_idle_ip {
|
||||
IDLE_IP0,
|
||||
IDLE_IP1,
|
||||
IDLE_IP2,
|
||||
IDLE_IP3,
|
||||
NUM_IDLE_IP,
|
||||
};
|
||||
|
||||
#define MAX_CLUSTER 2
|
||||
|
||||
/**
|
||||
IDLE_IP control
|
||||
*/
|
||||
#define for_each_idle_ip(num) \
|
||||
for ((num) = 0; (num) < NUM_IDLE_IP; (num)++)
|
||||
|
||||
#define for_each_syspower_mode(mode) \
|
||||
for ((mode) = 0; (mode) < NUM_SYS_POWERDOWN; (mode)++)
|
||||
|
||||
#define for_each_cluster(id) \
|
||||
for ((id) = 0; (id) < MAX_CLUSTER; (id)++)
|
||||
|
||||
/**
|
||||
* external driver APIs
|
||||
*/
|
||||
#ifdef CONFIG_SERIAL_SAMSUNG
|
||||
extern void s3c24xx_serial_fifo_wait(void);
|
||||
#else
|
||||
static inline void s3c24xx_serial_fifo_wait(void) { }
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PINCTRL_EXYNOS
|
||||
extern u64 exynos_get_eint_wake_mask(void);
|
||||
#else
|
||||
static inline u64 exynos_get_eint_wake_mask(void) { return 0xffffffffL; }
|
||||
#endif
|
||||
|
||||
#define EXYNOS_SS_SICD_INDEX ('S' + 'I' + 'C' + 'D') /* 291 */
|
||||
#endif /* __EXYNOS_POWERMODE_H */
|
||||
751
include/soc/samsung/map.h
Normal file
751
include/soc/samsung/map.h
Normal file
|
|
@ -0,0 +1,751 @@
|
|||
/* linux/arch/arm/mach-exynos/include/mach/map.h
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* EXYNOS4 - Memory map definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MAP_H
|
||||
#define __ASM_ARCH_MAP_H __FILE__
|
||||
|
||||
#include <plat/map-base.h>
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS5433) || defined(CONFIG_SOC_EXYNOS7420) \
|
||||
|| defined(CONFIG_SOC_EXYNOS7890) || defined(CONFIG_SOC_EXYNOS8890)
|
||||
/*
|
||||
* The virtual and physical address of UART is aligned to 1MiB boundary usally.
|
||||
* However, the Exynos7410's UART physical address is alignd to 64KB boundary.
|
||||
* So, the virtual address needs to re-set to 64KB align boundary.
|
||||
*/
|
||||
#undef S3C_VA_UART
|
||||
#define S3C_VA_UART S3C_ADDR(0x01010000)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
|
||||
* So need to define it, and here is to avoid redefinition warning.
|
||||
*/
|
||||
#define S3C_UART_OFFSET (0x10000)
|
||||
|
||||
#include <plat/map-s5p.h>
|
||||
|
||||
#define EXYNOS5_PA_SYSREG 0x10050000
|
||||
#define EXYNOS5_PA_SYSRAM 0x02020000
|
||||
#define EXYNOS7_PA_SYSRAM 0x02100000
|
||||
#define EXYNOS7410_PA_SYSRAM_NS 0x0207F000
|
||||
#define EXYNOS5433_PA_SYSRAM_NS 0x0207B000
|
||||
#define EXYNOS7420_PA_SYSRAM_NS 0x02157000
|
||||
#define EXYNOS7890_PA_SYSRAM_NS 0x02159000
|
||||
#define EXYNOS7580_PA_SYSRAM_NS 0x0206E000
|
||||
#define EXYNOS8890_PA_SYSRAM_NS 0x0207A000
|
||||
|
||||
#define EXYNOS8890_PA_SYSRAM_ALIVE 0x020C5000
|
||||
|
||||
#define EXYNOS4_PA_FIMC0 0x11800000
|
||||
#define EXYNOS4_PA_FIMC1 0x11810000
|
||||
#define EXYNOS4_PA_FIMC2 0x11820000
|
||||
#define EXYNOS4_PA_FIMC3 0x11830000
|
||||
|
||||
#define EXYNOS4_PA_JPEG 0x11840000
|
||||
|
||||
/* x = 0...1 */
|
||||
#define EXYNOS4_PA_FIMC_LITE(x) (0x12390000 + ((x) * 0x10000))
|
||||
|
||||
#define EXYNOS4_PA_G2D 0x12800000
|
||||
|
||||
#define EXYNOS_PA_AUDSS_INTMEM 0x03000000
|
||||
#define EXYNOS_PA_AUDSS_COMMBOX 0x03820000
|
||||
#define EXYNOS_PA_AUDSS 0x03810000
|
||||
#define EXYNOS4_PA_I2S0 0x03830000
|
||||
#define EXYNOS4_PA_I2S1 0xE3100000
|
||||
#define EXYNOS4_PA_I2S2 0xE2A00000
|
||||
#define EXYNOS5_PA_LPASS 0x11400000
|
||||
|
||||
#define EXYNOS4_PA_PCM0 0x03840000
|
||||
#define EXYNOS4_PA_PCM1 0x13980000
|
||||
#define EXYNOS4_PA_PCM2 0x13990000
|
||||
|
||||
#define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
|
||||
|
||||
#define EXYNOS4_PA_ONENAND 0x0C000000
|
||||
#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
|
||||
|
||||
#define EXYNOS_PA_CHIPID 0x10000000
|
||||
#define EXYNOS_PA_CHIPID2 0x10004000
|
||||
#define EXYNOS_PA_CHIPID3 0x105D0000
|
||||
#define EXYNOS_PA_CHIPID4 0x11810000
|
||||
#define EXYNOS_PA_CHIPID5 0x105C0000
|
||||
#define EXYNOS_PA_CHIPID6 0x101E0000
|
||||
|
||||
#define EXYNOS4_PA_SYSCON 0x10010000
|
||||
#define EXYNOS5_PA_SYSCON 0x10050100
|
||||
|
||||
#define EXYNOS4_PA_PMU 0x10020000
|
||||
#define EXYNOS5_PA_PMU 0x10040000
|
||||
#define EXYNOS5433_PA_PMU 0x105C0000
|
||||
|
||||
#define EXYNOS7420_PA_PMU 0x105C0000
|
||||
#define EXYNOS7420_PA_PMU_LPI_APOLLO 0x11920000
|
||||
#define EXYNOS7420_PA_PMU_LPI_ATLAS 0x11820000
|
||||
#define EXYNOS7420_PA_PMU_LPI_AUD 0x114D0000
|
||||
#define EXYNOS7420_PA_PMU_LPI_BUS0 0x13420000
|
||||
#define EXYNOS7420_PA_PMU_LPI_BUS1 0x14820000
|
||||
#define EXYNOS7420_PA_PMU_LPI_CAM0 0x120E0000
|
||||
#define EXYNOS7420_PA_PMU_LPI_CAM1 0x145E0000
|
||||
#define EXYNOS7420_PA_PMU_LPI_CCORE 0x105F0000
|
||||
#define EXYNOS7420_PA_PMU_LPI_DISP 0x13BB0000
|
||||
#define EXYNOS7420_PA_PMU_LPI_FSYS0 0x10E70000
|
||||
#define EXYNOS7420_PA_PMU_LPI_FSYS1 0x156C0000
|
||||
#define EXYNOS7420_PA_PMU_LPI_G3D 0x14A40000
|
||||
#define EXYNOS7420_PA_PMU_LPI_IMEM 0x11070000
|
||||
#define EXYNOS7420_PA_PMU_LPI_ISP0 0X146E0000
|
||||
#define EXYNOS7420_PA_PMU_LPI_ISP1 0x147E0000
|
||||
#define EXYNOS7420_PA_PMU_LPI_MFC 0x15290000
|
||||
#define EXYNOS7420_PA_PMU_LPI_MIF0 0x10840000
|
||||
#define EXYNOS7420_PA_PMU_LPI_MIF1 0x10940000
|
||||
#define EXYNOS7420_PA_PMU_LPI_MIF2 0x10A40000
|
||||
#define EXYNOS7420_PA_PMU_LPI_MIF3 0x10B40000
|
||||
#define EXYNOS7420_PA_PMU_LPI_MSCL 0x150F0000
|
||||
#define EXYNOS7420_PA_PMU_LPI_PERIC0 0x13600000
|
||||
#define EXYNOS7420_PA_PMU_LPI_PERIC1 0x14C70000
|
||||
#define EXYNOS7420_PA_PMU_LPI_PERIS 0x10010000
|
||||
#define EXYNOS7420_PA_PMU_LPI_VPP 0x13EE0000
|
||||
|
||||
#define EXYNOS7420_PA_GPIO_GPB0 0x13470000
|
||||
|
||||
#define EXYNOS7420_VA_PMU_LPI_APOLLO (S5P_VA_PMU + SZ_64K + (SZ_4K * 0))
|
||||
#define EXYNOS7420_VA_PMU_LPI_ATLAS (S5P_VA_PMU + SZ_64K + (SZ_4K * 1))
|
||||
#define EXYNOS7420_VA_PMU_LPI_AUD (S5P_VA_PMU + SZ_64K + (SZ_4K * 2))
|
||||
#define EXYNOS7420_VA_PMU_LPI_BUS0 (S5P_VA_PMU + SZ_64K + (SZ_4K * 3))
|
||||
#define EXYNOS7420_VA_PMU_LPI_BUS1 (S5P_VA_PMU + SZ_64K + (SZ_4K * 4))
|
||||
#define EXYNOS7420_VA_PMU_LPI_CAM0 (S5P_VA_PMU + SZ_64K + (SZ_4K * 5))
|
||||
#define EXYNOS7420_VA_PMU_LPI_CAM1 (S5P_VA_PMU + SZ_64K + (SZ_4K * 6))
|
||||
#define EXYNOS7420_VA_PMU_LPI_CCORE (S5P_VA_PMU + SZ_64K + (SZ_4K * 7))
|
||||
#define EXYNOS7420_VA_PMU_LPI_DISP (S5P_VA_PMU + SZ_64K + (SZ_4K * 8))
|
||||
#define EXYNOS7420_VA_PMU_LPI_FSYS0 (S5P_VA_PMU + SZ_64K + (SZ_4K * 9))
|
||||
#define EXYNOS7420_VA_PMU_LPI_FSYS1 (S5P_VA_PMU + SZ_64K + (SZ_4K * 10))
|
||||
#define EXYNOS7420_VA_PMU_LPI_G3D (S5P_VA_PMU + SZ_64K + (SZ_4K * 11))
|
||||
#define EXYNOS7420_VA_PMU_LPI_IMEM (S5P_VA_PMU + SZ_64K + (SZ_4K * 12))
|
||||
#define EXYNOS7420_VA_PMU_LPI_ISP0 (S5P_VA_PMU + SZ_64K + (SZ_4K * 13))
|
||||
#define EXYNOS7420_VA_PMU_LPI_ISP1 (S5P_VA_PMU + SZ_64K + (SZ_4K * 14))
|
||||
#define EXYNOS7420_VA_PMU_LPI_MFC (S5P_VA_PMU + SZ_64K + (SZ_4K * 15))
|
||||
#define EXYNOS7420_VA_PMU_LPI_MIF0 (S5P_VA_PMU + SZ_64K + (SZ_4K * 16))
|
||||
#define EXYNOS7420_VA_PMU_LPI_MIF1 (S5P_VA_PMU + SZ_64K + (SZ_4K * 17))
|
||||
#define EXYNOS7420_VA_PMU_LPI_MIF2 (S5P_VA_PMU + SZ_64K + (SZ_4K * 18))
|
||||
#define EXYNOS7420_VA_PMU_LPI_MIF3 (S5P_VA_PMU + SZ_64K + (SZ_4K * 19))
|
||||
#define EXYNOS7420_VA_PMU_LPI_MSCL (S5P_VA_PMU + SZ_64K + (SZ_4K * 20))
|
||||
#define EXYNOS7420_VA_PMU_LPI_PERIC0 (S5P_VA_PMU + SZ_64K + (SZ_4K * 21))
|
||||
#define EXYNOS7420_VA_PMU_LPI_PERIC1 (S5P_VA_PMU + SZ_64K + (SZ_4K * 22))
|
||||
#define EXYNOS7420_VA_PMU_LPI_PERIS (S5P_VA_PMU + SZ_64K + (SZ_4K * 23))
|
||||
#define EXYNOS7420_VA_PMU_LPI_VPP (S5P_VA_PMU + SZ_64K + (SZ_4K * 24))
|
||||
|
||||
#define EXYNOS7580_PA_PMU 0x10460000
|
||||
#define EXYNOS8890_PA_PMU 0x105C0000
|
||||
#define EXYNOS8890_VA_SYSREG (S5P_VA_CMU + (SZ_4K * 87))
|
||||
#define EXYNOS8890_PA_SYSREG 0x13A60000
|
||||
|
||||
#define EXYNOS8890_PA_FIMC_BNS 0x14020000
|
||||
#define EXYNOS8890_PA_MIPI_CSIS0 0x14000000
|
||||
#define EXYNOS8890_PA_MIPI_CSIS1 0x14010000
|
||||
#define EXYNOS8890_PA_MIPI_CSIS2 0x14100000
|
||||
#define EXYNOS8890_PA_MIPI_CSIS3 0x14110000
|
||||
#define EXYNOS8890_PA_SYSREG_CAM0 0x144F0000
|
||||
#define EXYNOS8890_PA_SYSREG_CAM1 0x145F0000
|
||||
#define EXYNOS8890_PA_SYSREG_ISP0 0x146F0000
|
||||
|
||||
#define EXYNOS4_PA_CMU 0x10030000
|
||||
#define EXYNOS5_PA_CMU 0x10010000
|
||||
|
||||
#define EXYNOS4_PA_SYSTIMER 0x10050000
|
||||
|
||||
#define EXYNOS4_PA_WATCHDOG 0x10060000
|
||||
#define EXYNOS5_PA_WATCHDOG 0x101D0000
|
||||
|
||||
#define EXYNOS4_PA_RTC 0x10070000
|
||||
|
||||
#define EXYNOS4_PA_KEYPAD 0x100A0000
|
||||
|
||||
#define EXYNOS4_PA_DMC0 0x10400000
|
||||
#define EXYNOS4_PA_DMC1 0x10410000
|
||||
|
||||
#define EXYNOS4_PA_COMBINER 0x10440000
|
||||
#define EXYNOS5_PA_COMBINER 0x10440000
|
||||
|
||||
#define EXYNOS4_PA_GIC_CPU 0x10480000
|
||||
#define EXYNOS4_PA_GIC_DIST 0x10490000
|
||||
#define EXYNOS5_PA_GIC_CPU 0x10482000
|
||||
#define EXYNOS5_PA_GIC_DIST 0x10481000
|
||||
|
||||
#define EXYNOS4_PA_COREPERI 0x10500000
|
||||
#define EXYNOS4_PA_TWD 0x10500600
|
||||
#define EXYNOS4_PA_L2CC 0x10502000
|
||||
|
||||
#define EXYNOS4_PA_TMU 0x100C0000
|
||||
|
||||
#define EXYNOS4_PA_MDMA0 0x10810000
|
||||
#define EXYNOS4_PA_MDMA1 0x12850000
|
||||
#define EXYNOS4_PA_S_MDMA1 0x12840000
|
||||
#define EXYNOS4_PA_PDMA0 0x12680000
|
||||
#define EXYNOS4_PA_PDMA1 0x12690000
|
||||
#define EXYNOS5_PA_MDMA0 0x10800000
|
||||
#define EXYNOS5_PA_MDMA1 0x11C10000
|
||||
#define EXYNOS5_PA_PDMA0 0x121A0000
|
||||
#define EXYNOS5_PA_PDMA1 0x121B0000
|
||||
|
||||
#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
|
||||
#define EXYNOS4_PA_SYSMMU_2D_ACP 0x10A40000
|
||||
#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000
|
||||
#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMC_ISP 0x12260000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMC_DRC 0x12270000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMC_FD 0x122A0000
|
||||
#define EXYNOS4_PA_SYSMMU_ISPCPU 0x122B0000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMC_LITE0 0x123B0000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMC_LITE1 0x123C0000
|
||||
#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000
|
||||
#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000
|
||||
#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000
|
||||
#define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000
|
||||
#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
|
||||
#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
|
||||
#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
|
||||
|
||||
#define EXYNOS5_PA_GSC0 0x13E00000
|
||||
#define EXYNOS5_PA_GSC1 0x13E10000
|
||||
#define EXYNOS5_PA_GSC2 0x13E20000
|
||||
#define EXYNOS5_PA_GSC3 0x13E30000
|
||||
|
||||
#define EXYNOS5_PA_SYSMMU_MDMA1 0x10A40000
|
||||
#define EXYNOS5_PA_SYSMMU_SSS 0x10A50000
|
||||
#define EXYNOS5_PA_SYSMMU_2D 0x10A60000
|
||||
#define EXYNOS5_PA_SYSMMU_MFC_L 0x11200000
|
||||
#define EXYNOS5_PA_SYSMMU_MFC_R 0x11210000
|
||||
#define EXYNOS5_PA_SYSMMU_ROTATOR 0x11D40000
|
||||
#define EXYNOS5_PA_SYSMMU_MDMA2 0x11D50000
|
||||
#define EXYNOS5_PA_SYSMMU_JPEG 0x11F20000
|
||||
#define EXYNOS5_PA_SYSMMU_IOP 0x12360000
|
||||
#define EXYNOS5_PA_SYSMMU_RTIC 0x12370000
|
||||
#define EXYNOS5_PA_SYSMMU_ISP 0x13260000
|
||||
#define EXYNOS5_PA_SYSMMU_DRC 0x12370000
|
||||
#define EXYNOS5_PA_SYSMMU_SCALERC 0x13280000
|
||||
#define EXYNOS5_PA_SYSMMU_SCALERP 0x13290000
|
||||
#define EXYNOS5_PA_SYSMMU_FD 0x132A0000
|
||||
#define EXYNOS5_PA_SYSMMU_ISPCPU 0x132B0000
|
||||
#define EXYNOS5_PA_SYSMMU_ODC 0x132C0000
|
||||
#define EXYNOS5_PA_SYSMMU_DIS0 0x132D0000
|
||||
#define EXYNOS5_PA_SYSMMU_DIS1 0x132E0000
|
||||
#define EXYNOS5_PA_SYSMMU_3DNR 0x132F0000
|
||||
#define EXYNOS5_PA_SYSMMU_LITE0 0x13C40000
|
||||
#define EXYNOS5_PA_SYSMMU_LITE1 0x13C50000
|
||||
#define EXYNOS5_PA_SYSMMU_GSC0 0x13E80000
|
||||
#define EXYNOS5_PA_SYSMMU_GSC1 0x13E90000
|
||||
#define EXYNOS5_PA_SYSMMU_GSC2 0x13EA0000
|
||||
#define EXYNOS5_PA_SYSMMU_GSC3 0x13EB0000
|
||||
#define EXYNOS5_PA_SYSMMU_FIMD1 0x14640000
|
||||
#define EXYNOS5_PA_SYSMMU_TV 0x14650000
|
||||
|
||||
#define EXYNOS4_PA_SPI0 0x13920000
|
||||
#define EXYNOS4_PA_SPI1 0x13930000
|
||||
#define EXYNOS4_PA_SPI2 0x13940000
|
||||
#define EXYNOS5_PA_SPI0 0x12D20000
|
||||
#define EXYNOS5_PA_SPI1 0x12D30000
|
||||
#define EXYNOS5_PA_SPI2 0x12D40000
|
||||
|
||||
#define EXYNOS4_PA_GPIO1 0x11400000
|
||||
#define EXYNOS4_PA_GPIO2 0x11000000
|
||||
#define EXYNOS4_PA_GPIO3 0x03860000
|
||||
#define EXYNOS5_PA_GPIO1 0x11400000
|
||||
#define EXYNOS5_PA_GPIO2 0x13400000
|
||||
#define EXYNOS5_PA_GPIO3 0x10D10000
|
||||
#define EXYNOS5_PA_GPIO4 0x03860000
|
||||
#define EXYNOS7580_PA_GPIO_NFC 0x138C0000
|
||||
#define EXYNOS7420_PA_GPIO_ALIVE 0x10580000
|
||||
|
||||
#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
|
||||
#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
|
||||
|
||||
#define EXYNOS4_PA_FIMD0 0x11C00000
|
||||
|
||||
#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
|
||||
#define EXYNOS4_PA_DWMCI 0x12550000
|
||||
#define EXYNOS5_PA_DWMCI0 0x12200000
|
||||
#define EXYNOS5_PA_DWMCI1 0x12210000
|
||||
#define EXYNOS5_PA_DWMCI2 0x12220000
|
||||
#define EXYNOS5_PA_DWMCI3 0x12230000
|
||||
|
||||
#define EXYNOS4_PA_HSOTG 0x12480000
|
||||
#define EXYNOS4_PA_USB_HSPHY 0x125B0000
|
||||
|
||||
#define EXYNOS4_PA_SATA 0x12560000
|
||||
#define EXYNOS4_PA_SATAPHY 0x125D0000
|
||||
#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000
|
||||
|
||||
#define EXYNOS4_PA_SROMC 0x12570000
|
||||
#define EXYNOS5_PA_SROMC 0x12250000
|
||||
|
||||
#define EXYNOS4_PA_EHCI 0x12580000
|
||||
#define EXYNOS4_PA_OHCI 0x12590000
|
||||
#define EXYNOS4_PA_HSPHY 0x125B0000
|
||||
#define EXYNOS4_PA_MFC 0x13400000
|
||||
|
||||
#define EXYNOS4_PA_UART 0x13800000
|
||||
#define EXYNOS5_PA_UART 0x12C00000
|
||||
#define EXYNOS5433_PA_UART 0x14C10000
|
||||
#define EXYNOS7410_PA_UART 0x14C10000
|
||||
#define EXYNOS7420_PA_UART 0x14C10000
|
||||
|
||||
#define EXYNOS4_PA_VP 0x12C00000
|
||||
#define EXYNOS4_PA_MIXER 0x12C10000
|
||||
#define EXYNOS4_PA_SDO 0x12C20000
|
||||
#define EXYNOS4_PA_HDMI 0x12D00000
|
||||
#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000
|
||||
|
||||
#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
|
||||
#define EXYNOS5_PA_IIC(x) (0x12C60000 + ((x) * 0x10000))
|
||||
|
||||
#define EXYNOS4_PA_ADC 0x13910000
|
||||
#define EXYNOS4_PA_ADC1 0x13911000
|
||||
|
||||
#define EXYNOS4_PA_AC97 0x139A0000
|
||||
|
||||
#define EXYNOS4_PA_SPDIF 0x139B0000
|
||||
|
||||
#define EXYNOS4_PA_TIMER 0x139D0000
|
||||
#define EXYNOS5_PA_TIMER 0x12DD0000
|
||||
|
||||
#define EXYNOS5_PA_G3D 0x14AC0000
|
||||
|
||||
#define EXYNOS4_PA_SDRAM 0x40000000
|
||||
#define EXYNOS5_PA_SDRAM 0x40000000
|
||||
|
||||
#define EXYNOS7410_PA_CMU_TOP 0x10030000
|
||||
#define EXYNOS7410_PA_CMU_EGL 0x11800000
|
||||
#define EXYNOS7410_PA_CMU_KFC 0x11900000
|
||||
#define EXYNOS7410_PA_CMU_AUD 0x114C0000
|
||||
#define EXYNOS7410_PA_CMU_BUS1 0x14800000
|
||||
#define EXYNOS7410_PA_CMU_BUS2 0x13400000
|
||||
#define EXYNOS7410_PA_CMU_CAM0 0x120D0000
|
||||
#define EXYNOS7410_PA_CMU_CAM0_LOCAL 0x121C0000
|
||||
#define EXYNOS7410_PA_CMU_CAM1 0x145D0000
|
||||
#define EXYNOS7410_PA_CMU_CAM1_LOCAL 0x142F0000
|
||||
#define EXYNOS7410_PA_CMU_CPIF 0x10FC0000
|
||||
#define EXYNOS7410_PA_CMU_DISP 0x13B90000
|
||||
#define EXYNOS7410_PA_CMU_FSYS 0x156E0000
|
||||
#define EXYNOS7410_PA_CMU_G2D 0x12460000
|
||||
#define EXYNOS7410_PA_CMU_G3D 0x14AA0000
|
||||
#define EXYNOS7410_PA_CMU_GSCL 0x13CF0000
|
||||
#define EXYNOS7410_PA_CMU_HEVC 0x14F80000
|
||||
#define EXYNOS7410_PA_CMU_IMEM 0x11060000
|
||||
#define EXYNOS7410_PA_CMU_ISP 0x146D0000
|
||||
#define EXYNOS7410_PA_CMU_ISP_LOCAL 0x14360000
|
||||
#define EXYNOS7410_PA_CMU_MFC0 0x15280000
|
||||
#define EXYNOS7410_PA_CMU_MFC1 0x15380000
|
||||
#define EXYNOS7410_PA_CMU_MIF 0x105B0000
|
||||
#define EXYNOS7410_PA_CMU_MSCL 0x150D0000
|
||||
#define EXYNOS7410_PA_CMU_PERIC 0x14C80000
|
||||
#define EXYNOS7410_PA_CMU_PERIS 0x10040000
|
||||
|
||||
#define EXYNOS5_PA_FIMC_LITE0 0x12100000
|
||||
#define EXYNOS5_PA_FIMC_LITE1 0x12110000
|
||||
#define EXYNOS5_PA_FIMC_LITE2 0x141C0000
|
||||
#define EXYNOS5_PA_FIMC_LITE3 0x121F0000
|
||||
|
||||
#define EXYNOS5_PA_MIPI_CSIS0 0x12120000
|
||||
#define EXYNOS5_PA_MIPI_CSIS1 0x12130000
|
||||
#define EXYNOS5_PA_MIPI_CSIS2 0x141D0000
|
||||
#define EXYNOS5_PA_FIMC_FD 0x14040000
|
||||
|
||||
#define EXYNOS5_PA_SYSREG_CAM0 0x120F0000
|
||||
#define EXYNOS5_PA_SYSREG_CAM1 0x145F0000
|
||||
|
||||
#define EXYNOS7410_PA_BTS_DECONM0 0x13A80000
|
||||
#define EXYNOS7410_PA_BTS_DECONM1 0x13A90000
|
||||
#define EXYNOS7410_PA_BTS_DECONM2 0x13AA0000
|
||||
#define EXYNOS7410_PA_BTS_DECONM3 0x13AB0000
|
||||
#define EXYNOS7410_PA_BTS_DECONM4 0x13AC0000
|
||||
#define EXYNOS7410_PA_BTS_TV 0x13AD0000
|
||||
#define EXYNOS7410_PA_BTS_FIMC_LITE0 0x12000000
|
||||
#define EXYNOS7410_PA_BTS_FIMC_LITE1 0x12010000
|
||||
#define EXYNOS7410_PA_BTS_FIMC_LITE2 0x14500000
|
||||
#define EXYNOS7410_PA_BTS_FIMC_LITE3 0x12020000
|
||||
#define EXYNOS7410_PA_BTS_3AA0 0x12030000
|
||||
#define EXYNOS7410_PA_BTS_3AA1 0x12040000
|
||||
#define EXYNOS7410_PA_BTS_GSCL0 0x13CC0000
|
||||
#define EXYNOS7410_PA_BTS_GSCL1 0x13CD0000
|
||||
#define EXYNOS7410_PA_BTS_GSCL2 0x13CE0000
|
||||
|
||||
#define EXYNOS5422_NOCP_MEM0_0_BASE 0x10CA1000
|
||||
#define EXYNOS5422_NOCP_MEM0_1_BASE 0x10CA1400
|
||||
#define EXYNOS5422_NOCP_MEM1_0_BASE 0x10CA1800
|
||||
#define EXYNOS5422_NOCP_MEM1_1_BASE 0x10CA1C00
|
||||
|
||||
#define EXYNOS5422_PA_PPMU_DREX0_0 0x10D00000
|
||||
#define EXYNOS5422_PA_PPMU_DREX0_1 0x10D10000
|
||||
#define EXYNOS5422_PA_PPMU_DREX1_0 0x10D60000
|
||||
#define EXYNOS5422_PA_PPMU_DREX1_1 0x10D70000
|
||||
|
||||
#define NOCP_BASE(_name) EXYNOS5422_NOCP_##_name##_BASE
|
||||
|
||||
/* DREX PA Defines */
|
||||
#define EXYNOS5_PA_DREXI_1 0x10C30000
|
||||
#define EXYNOS5_PA_DREXI_0 0x10C20000
|
||||
|
||||
/* Compatibiltiy Defines */
|
||||
|
||||
#define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0)
|
||||
#define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1)
|
||||
#define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2)
|
||||
#define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3)
|
||||
#define S3C_PA_IIC EXYNOS4_PA_IIC(0)
|
||||
#define S3C_PA_IIC1 EXYNOS4_PA_IIC(1)
|
||||
#define S3C_PA_IIC2 EXYNOS4_PA_IIC(2)
|
||||
#define S3C_PA_IIC3 EXYNOS4_PA_IIC(3)
|
||||
#define S3C_PA_IIC4 EXYNOS4_PA_IIC(4)
|
||||
#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
|
||||
#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
|
||||
#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
|
||||
#define S3C_PA_RTC EXYNOS4_PA_RTC
|
||||
#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
|
||||
#define S3C_PA_SPI0 EXYNOS4_PA_SPI0
|
||||
#define S3C_PA_SPI1 EXYNOS4_PA_SPI1
|
||||
#define S3C_PA_SPI2 EXYNOS4_PA_SPI2
|
||||
#define S3C_PA_USB_HSOTG EXYNOS4_PA_HSOTG
|
||||
|
||||
#define S5P_PA_EHCI EXYNOS4_PA_EHCI
|
||||
#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
|
||||
#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1
|
||||
#define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2
|
||||
#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
|
||||
#define S5P_PA_JPEG EXYNOS4_PA_JPEG
|
||||
#define S5P_PA_G2D EXYNOS4_PA_G2D
|
||||
#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0
|
||||
#define S5P_PA_HDMI EXYNOS4_PA_HDMI
|
||||
#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY
|
||||
#define S5P_PA_MFC EXYNOS4_PA_MFC
|
||||
#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
|
||||
#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
|
||||
#define S5P_PA_MIXER EXYNOS4_PA_MIXER
|
||||
#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
|
||||
#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
|
||||
#define S5P_PA_SDO EXYNOS4_PA_SDO
|
||||
#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
|
||||
#define S5P_PA_VP EXYNOS4_PA_VP
|
||||
|
||||
#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
|
||||
#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
|
||||
#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
|
||||
|
||||
/* Compatibility UART */
|
||||
|
||||
#define EXYNOS4_PA_UART0 0x13800000
|
||||
#define EXYNOS4_PA_UART1 0x13810000
|
||||
#define EXYNOS4_PA_UART2 0x13820000
|
||||
#define EXYNOS4_PA_UART3 0x13830000
|
||||
#define EXYNOS4_SZ_UART SZ_256
|
||||
|
||||
#define EXYNOS5_PA_UART0 0x12C00000
|
||||
#define EXYNOS5_PA_UART1 0x12C10000
|
||||
#define EXYNOS5_PA_UART2 0x12C20000
|
||||
#define EXYNOS5_PA_UART3 0x12C30000
|
||||
|
||||
#define EXYNOS5440_PA_UART0 0x000B0000
|
||||
#define EXYNOS5440_PA_UART1 0x000C0000
|
||||
#define EXYNOS5440_SZ_UART SZ_256
|
||||
|
||||
#define EXYNOS7420_PA_UART0 0x13630000
|
||||
#define EXYNOS7420_PA_UART1 0x14C20000
|
||||
#define EXYNOS7420_PA_UART2 0x14C30000
|
||||
#define EXYNOS7420_PA_UART3 0x14C40000
|
||||
#define EXYNOS7420_SZ_UART SZ_256
|
||||
|
||||
#define EXYNOS8890_PA_UART0 0x13630000
|
||||
#define EXYNOS8890_PA_UART1 0x14C20000
|
||||
#define EXYNOS8890_PA_UART2 0x14C30000
|
||||
#define EXYNOS8890_PA_UART3 0x14C40000
|
||||
#define EXYNOS8890_PA_UART4 0x14C50000
|
||||
#define EXYNOS8890_PA_UART5 0x14C10000
|
||||
#define EXYNOS8890_SZ_UART SZ_256
|
||||
|
||||
#define EXYNOS8890_PA_UART EXYNOS8890_PA_UART0
|
||||
|
||||
#define EXYNOS5433_PA_MSCLSYS 0x150E0000
|
||||
|
||||
#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
|
||||
|
||||
#define EXYNOS7410_VA_CMU_TOP (S5P_VA_CMU + (SZ_4K * 0))
|
||||
#define EXYNOS7410_VA_CMU_EGL (S5P_VA_CMU + (SZ_4K * 1))
|
||||
#define EXYNOS7410_VA_CMU_KFC (S5P_VA_CMU + (SZ_4K * 2))
|
||||
#define EXYNOS7410_VA_CMU_AUD (S5P_VA_CMU + (SZ_4K * 3))
|
||||
#define EXYNOS7410_VA_CMU_BUS1 (S5P_VA_CMU + (SZ_4K * 4))
|
||||
#define EXYNOS7410_VA_CMU_BUS2 (S5P_VA_CMU + (SZ_4K * 5))
|
||||
#define EXYNOS7410_VA_CMU_CAM0 (S5P_VA_CMU + (SZ_4K * 6))
|
||||
#define EXYNOS7410_VA_CMU_CAM0_LOCAL (S5P_VA_CMU + (SZ_4K * 7))
|
||||
#define EXYNOS7410_VA_CMU_CAM1 (S5P_VA_CMU + (SZ_4K * 8))
|
||||
#define EXYNOS7410_VA_CMU_CAM1_LOCAL (S5P_VA_CMU + (SZ_4K * 9))
|
||||
#define EXYNOS7410_VA_CMU_CPIF (S5P_VA_CMU + (SZ_4K * 10))
|
||||
#define EXYNOS7410_VA_CMU_DISP (S5P_VA_CMU + (SZ_4K * 11))
|
||||
#define EXYNOS7410_VA_CMU_FSYS (S5P_VA_CMU + (SZ_4K * 12))
|
||||
#define EXYNOS7410_VA_CMU_G2D (S5P_VA_CMU + (SZ_4K * 13))
|
||||
#define EXYNOS7410_VA_CMU_G3D (S5P_VA_CMU + (SZ_4K * 14))
|
||||
#define EXYNOS7410_VA_CMU_GSCL (S5P_VA_CMU + (SZ_4K * 15))
|
||||
#define EXYNOS7410_VA_CMU_HEVC (S5P_VA_CMU + (SZ_4K * 16))
|
||||
#define EXYNOS7410_VA_CMU_IMEM (S5P_VA_CMU + (SZ_4K * 17))
|
||||
#define EXYNOS7410_VA_CMU_ISP (S5P_VA_CMU + (SZ_4K * 18))
|
||||
#define EXYNOS7410_VA_CMU_ISP_LOCAL (S5P_VA_CMU + (SZ_4K * 19))
|
||||
#define EXYNOS7410_VA_CMU_MFC0 (S5P_VA_CMU + (SZ_4K * 20))
|
||||
#define EXYNOS7410_VA_CMU_MFC1 (S5P_VA_CMU + (SZ_4K * 21))
|
||||
#define EXYNOS7410_VA_CMU_MIF (S5P_VA_CMU + (SZ_4K * 22))
|
||||
#define EXYNOS7410_VA_CMU_MSCL (S5P_VA_CMU + (SZ_4K * 23))
|
||||
#define EXYNOS7410_VA_CMU_PERIC (S5P_VA_CMU + (SZ_4K * 24))
|
||||
#define EXYNOS7410_VA_CMU_PERIS (S5P_VA_CMU + (SZ_4K * 25))
|
||||
|
||||
#define EXYNOS5430_VA_CMU_TOP (S5P_VA_CMU + (SZ_4K * 0))
|
||||
#define EXYNOS5430_VA_CMU_EGL (S5P_VA_CMU + (SZ_4K * 1))
|
||||
#define EXYNOS5430_VA_CMU_KFC (S5P_VA_CMU + (SZ_4K * 3))
|
||||
#define EXYNOS5430_VA_CMU_AUD (S5P_VA_CMU + (SZ_4K * 5))
|
||||
#define EXYNOS5430_VA_CMU_BUS1 (S5P_VA_CMU + (SZ_4K * 6))
|
||||
#define EXYNOS5430_VA_CMU_BUS2 (S5P_VA_CMU + (SZ_4K * 7))
|
||||
#define EXYNOS5430_VA_CMU_CAM0 (S5P_VA_CMU + (SZ_4K * 8))
|
||||
#define EXYNOS5430_VA_CMU_CAM0_LOCAL (S5P_VA_CMU + (SZ_4K * 9))
|
||||
#define EXYNOS5430_VA_CMU_CAM1 (S5P_VA_CMU + (SZ_4K * 10))
|
||||
#define EXYNOS5430_VA_CMU_CAM1_LOCAL (S5P_VA_CMU + (SZ_4K * 11))
|
||||
#define EXYNOS5430_VA_CMU_CPIF (S5P_VA_CMU + (SZ_4K * 12))
|
||||
#define EXYNOS5430_VA_CMU_DISP (S5P_VA_CMU + (SZ_4K * 13))
|
||||
#define EXYNOS5430_VA_CMU_FSYS (S5P_VA_CMU + (SZ_4K * 14))
|
||||
#define EXYNOS5430_VA_CMU_G2D (S5P_VA_CMU + (SZ_4K * 15))
|
||||
#define EXYNOS5430_VA_CMU_G3D (S5P_VA_CMU + (SZ_4K * 16))
|
||||
#define EXYNOS5430_VA_CMU_GSCL (S5P_VA_CMU + (SZ_4K * 17))
|
||||
#define EXYNOS5430_VA_CMU_HEVC (S5P_VA_CMU + (SZ_4K * 18))
|
||||
#define EXYNOS5430_VA_CMU_IMEM (S5P_VA_CMU + (SZ_4K * 19))
|
||||
#define EXYNOS5430_VA_CMU_ISP (S5P_VA_CMU + (SZ_4K * 20))
|
||||
#define EXYNOS5430_VA_CMU_ISP_LOCAL (S5P_VA_CMU + (SZ_4K * 21))
|
||||
#define EXYNOS5430_VA_CMU_MFC0 (S5P_VA_CMU + (SZ_4K * 22))
|
||||
#define EXYNOS5430_VA_CMU_MFC1 (S5P_VA_CMU + (SZ_4K * 23))
|
||||
#define EXYNOS5430_VA_CMU_MIF (S5P_VA_CMU + (SZ_4K * 24))
|
||||
#define EXYNOS5430_VA_CMU_MSCL (S5P_VA_CMU + (SZ_4K * 25))
|
||||
#define EXYNOS5430_VA_CMU_PERIC (S5P_VA_CMU + (SZ_4K * 26))
|
||||
#define EXYNOS5430_VA_CMU_PERIS (S5P_VA_CMU + (SZ_4K * 27))
|
||||
|
||||
#define EXYNOS7420_PA_CMU_TOPC 0x10570000
|
||||
#define EXYNOS7420_PA_CMU_TOP0 0x105D0000
|
||||
#define EXYNOS7420_PA_CMU_TOP1 0x105E0000
|
||||
#define EXYNOS7420_PA_CMU_ATLAS 0x11800000
|
||||
#define EXYNOS7420_PA_CMU_APOLLO 0x11900000
|
||||
#define EXYNOS7420_PA_CMU_G3D 0x14AA0000
|
||||
#define EXYNOS7420_PA_CMU_MIF0 0x10850000
|
||||
#define EXYNOS7420_PA_CMU_MIF1 0x10950000
|
||||
#define EXYNOS7420_PA_CMU_MIF2 0x10A50000
|
||||
#define EXYNOS7420_PA_CMU_MIF3 0x10B50000
|
||||
#define EXYNOS7420_PA_CMU_CCORE 0x105B0000
|
||||
#define EXYNOS7420_PA_CMU_IMEM 0x11060000
|
||||
#define EXYNOS7420_PA_CMU_CAM0 0x144D0000
|
||||
#define EXYNOS7420_PA_CMU_CAM0_LOCAL 0x140F0000
|
||||
#define EXYNOS7420_PA_CMU_CAM1 0x145D0000
|
||||
#define EXYNOS7420_PA_CMU_CAM1_LOCAL 0x141F0000
|
||||
#define EXYNOS7420_PA_CMU_ISP0 0x146D0000
|
||||
#define EXYNOS7420_PA_CMU_ISP0_LOCAL 0x14290000
|
||||
#define EXYNOS7420_PA_CMU_ISP1 0x147D0000
|
||||
#define EXYNOS7420_PA_CMU_ISP1_LOCAL 0x142F0000
|
||||
#define EXYNOS7420_PA_CMU_VPP 0x13ED0000
|
||||
#define EXYNOS7420_PA_CMU_PERIC0 0x13610000
|
||||
#define EXYNOS7420_PA_CMU_PERIC1 0x14C80000
|
||||
#define EXYNOS7420_PA_CMU_PERIS 0x10040000
|
||||
#define EXYNOS7420_PA_CMU_BUS0 0x13400000
|
||||
#define EXYNOS7420_PA_CMU_BUS1 0x14800000
|
||||
#define EXYNOS7420_PA_CMU_DISP 0x13AD0000
|
||||
#define EXYNOS7420_PA_CMU_AUD 0x114C0000
|
||||
#define EXYNOS7420_PA_CMU_FSYS0 0x10E90000
|
||||
#define EXYNOS7420_PA_CMU_FSYS1 0x156E0000
|
||||
#define EXYNOS7420_PA_CMU_G2D 0x12460000
|
||||
#define EXYNOS7420_PA_CMU_MSCL 0x150D0000
|
||||
#define EXYNOS7420_PA_CMU_MFC 0x15280000
|
||||
#define EXYNOS7420_PA_CMU_HEVC 0x14F80000
|
||||
|
||||
#define EXYNOS7420_PA_FIMC_BNSA 0x14020000
|
||||
#define EXYNOS7420_PA_FIMC_BNSB 0x14030000
|
||||
#define EXYNOS7420_PA_FIMC_BNSC 0x14110000
|
||||
#define EXYNOS7420_PA_FIMC_BNSD 0x14040000
|
||||
#define EXYNOS7420_PA_MIPI_CSIS0 0x14000000
|
||||
#define EXYNOS7420_PA_MIPI_CSIS1 0x14010000
|
||||
#define EXYNOS7420_PA_MIPI_CSIS2 0x14100000
|
||||
#define EXYNOS7420_PA_MIPI_CSIS3 0x14080000
|
||||
|
||||
#define EXYNOS7420_PA_APM_SRAM 0x11200000
|
||||
#define EXYNOS7420_PA_APM 0x11240000
|
||||
#define EXYNOS7420_PA_APM_NOTI 0x11280000
|
||||
#define EXYNOS8890_PA_APM_SRAM 0x11200000
|
||||
#define EXYNOS8890_PA_APM 0x11240000
|
||||
|
||||
/* CMU Size is 84*4K */
|
||||
#define EXYNOS7420_VA_CMU_TOPC (S5P_VA_CMU + (SZ_64K * 0))
|
||||
#define EXYNOS7420_VA_CMU_TOP0 (S5P_VA_CMU + (SZ_64K * 1))
|
||||
#define EXYNOS7420_VA_CMU_TOP1 (S5P_VA_CMU + (SZ_64K * 2))
|
||||
#define EXYNOS7420_VA_CMU_ATLAS (S5P_VA_CMU + (SZ_64K * 3))
|
||||
#define EXYNOS7420_VA_CMU_APOLLO (S5P_VA_CMU + (SZ_8K * 25))
|
||||
#define EXYNOS7420_VA_CMU_G3D (S5P_VA_CMU + (SZ_8K * 26))
|
||||
#define EXYNOS7420_VA_CMU_MIF0 (S5P_VA_CMU + (SZ_8K * 27))
|
||||
#define EXYNOS7420_VA_CMU_MIF1 (S5P_VA_CMU + (SZ_8K * 28))
|
||||
#define EXYNOS7420_VA_CMU_MIF2 (S5P_VA_CMU + (SZ_8K * 29))
|
||||
#define EXYNOS7420_VA_CMU_MIF3 (S5P_VA_CMU + (SZ_8K * 30))
|
||||
#define EXYNOS7420_VA_CMU_CCORE (S5P_VA_CMU + (SZ_8K * 31))
|
||||
#define EXYNOS7420_VA_CMU_IMEM (S5P_VA_CMU + (SZ_4K * 63))
|
||||
#define EXYNOS7420_VA_CMU_CAM0 (S5P_VA_CMU + (SZ_4K * 64))
|
||||
#define EXYNOS7420_VA_CMU_CAM0_LOCAL (S5P_VA_CMU + (SZ_4K * 65))
|
||||
#define EXYNOS7420_VA_CMU_CAM1 (S5P_VA_CMU + (SZ_4K * 66))
|
||||
#define EXYNOS7420_VA_CMU_CAM1_LOCAL (S5P_VA_CMU + (SZ_4K * 67))
|
||||
#define EXYNOS7420_VA_CMU_ISP0 (S5P_VA_CMU + (SZ_4K * 68))
|
||||
#define EXYNOS7420_VA_CMU_ISP0_LOCAL (S5P_VA_CMU + (SZ_4K * 69))
|
||||
#define EXYNOS7420_VA_CMU_ISP1 (S5P_VA_CMU + (SZ_4K * 70))
|
||||
#define EXYNOS7420_VA_CMU_ISP1_LOCAL (S5P_VA_CMU + (SZ_4K * 71))
|
||||
#define EXYNOS7420_VA_CMU_VPP (S5P_VA_CMU + (SZ_4K * 72))
|
||||
#define EXYNOS7420_VA_CMU_PERIC0 (S5P_VA_CMU + (SZ_4K * 73))
|
||||
#define EXYNOS7420_VA_CMU_PERIC1 (S5P_VA_CMU + (SZ_4K * 74))
|
||||
#define EXYNOS7420_VA_CMU_PERIS (S5P_VA_CMU + (SZ_4K * 75))
|
||||
#define EXYNOS7420_VA_CMU_BUS0 (S5P_VA_CMU + (SZ_4K * 76))
|
||||
#define EXYNOS7420_VA_CMU_BUS1 (S5P_VA_CMU + (SZ_4K * 77))
|
||||
#define EXYNOS7420_VA_CMU_DISP (S5P_VA_CMU + (SZ_4K * 78))
|
||||
#define EXYNOS7420_VA_CMU_AUD (S5P_VA_CMU + (SZ_4K * 79))
|
||||
#define EXYNOS7420_VA_CMU_FSYS0 (S5P_VA_CMU + (SZ_4K * 80))
|
||||
#define EXYNOS7420_VA_CMU_FSYS1 (S5P_VA_CMU + (SZ_4K * 81))
|
||||
#define EXYNOS7420_VA_CMU_G2D (S5P_VA_CMU + (SZ_4K * 82))
|
||||
#define EXYNOS7420_VA_CMU_MSCL (S5P_VA_CMU + (SZ_4K * 83))
|
||||
#define EXYNOS7420_VA_CMU_MFC (S5P_VA_CMU + (SZ_4K * 84))
|
||||
#define EXYNOS7420_VA_CMU_HEVC (S5P_VA_CMU + (SZ_4K * 85))
|
||||
#define EXYNOS7420_VA_SYSREG (S5P_VA_CMU + (SZ_4K * 86))
|
||||
|
||||
#define EXYNOS5433_PA_PMU 0x105C0000
|
||||
#define EXYNOS5433_PA_PMU_LPI_EAGLE 0x11820000
|
||||
#define EXYNOS5433_PA_PMU_LPI_CAM0 0x120E0000
|
||||
#define EXYNOS5433_PA_PMU_LPI_CAM1 0x145E0000
|
||||
#define EXYNOS5433_PA_PMU_LPI_ISP 0x146E0000
|
||||
|
||||
#define EXYNOS5433_PA_UART 0x14C10000
|
||||
|
||||
#define EXYNOS5433_PA_CMU_TOP 0x10030000
|
||||
#define EXYNOS5433_PA_CMU_EGL 0x11800000
|
||||
#define EXYNOS5433_PA_CMU_KFC 0x11900000
|
||||
#define EXYNOS5433_PA_CMU_AUD 0x114C0000
|
||||
#define EXYNOS5433_PA_CMU_BUS1 0x14800000
|
||||
#define EXYNOS5433_PA_CMU_BUS2 0x13400000
|
||||
#define EXYNOS5433_PA_CMU_CAM0 0x120D0000
|
||||
#define EXYNOS5433_PA_CMU_CAM0_LOCAL 0x121C0000
|
||||
#define EXYNOS5433_PA_CMU_CAM1 0x145D0000
|
||||
#define EXYNOS5433_PA_CMU_CAM1_LOCAL 0x142F0000
|
||||
#define EXYNOS5433_PA_CMU_CPIF 0x10FC0000
|
||||
#define EXYNOS5433_PA_CMU_DISP 0x13B90000
|
||||
#define EXYNOS5433_PA_CMU_FSYS 0x156E0000
|
||||
#define EXYNOS5433_PA_CMU_G2D 0x12460000
|
||||
#define EXYNOS5433_PA_CMU_G3D 0x14AA0000
|
||||
#define EXYNOS5433_PA_CMU_GSCL 0x13CF0000
|
||||
#define EXYNOS5433_PA_CMU_HEVC 0x14F80000
|
||||
#define EXYNOS5433_PA_CMU_IMEM 0x11060000
|
||||
#define EXYNOS5433_PA_CMU_ISP 0x146D0000
|
||||
#define EXYNOS5433_PA_CMU_ISP_LOCAL 0x14360000
|
||||
#define EXYNOS5433_PA_CMU_MFC0 0x15280000
|
||||
#define EXYNOS5433_PA_CMU_MFC1 0x15380000
|
||||
#define EXYNOS5433_PA_CMU_MIF 0x105B0000
|
||||
#define EXYNOS5433_PA_CMU_MSCL 0x150D0000
|
||||
#define EXYNOS5433_PA_CMU_PERIC 0x14C80000
|
||||
#define EXYNOS5433_PA_CMU_PERIS 0x10040000
|
||||
|
||||
#define EXYNOS5_PA_SYSREG_DISP 0x13B81000
|
||||
#define EXYNOS5_PA_SYSREG_CAM0 0x120F0000
|
||||
#define EXYNOS5_PA_SYSREG_CAM1 0x145F0000
|
||||
#define EXYNOS5_PA_SYSREG_ISP 0x146F0000
|
||||
#define EXYNOS5_PA_SYSREG_HEVC 0x14FA0000
|
||||
#define EXYNOS5_PA_SYSREG_MFC0 0x152A0000
|
||||
#define EXYNOS5_PA_SYSREG_MFC1 0x153A0000
|
||||
#define EXYNOS5_PA_SYSREG_AUD 0x114F0000
|
||||
#define EXYNOS5_PA_SYSREG_G2D 0x124C0000
|
||||
#define EXYNOS5_PA_SYSREG_GSCL 0x13CB0000
|
||||
#define EXYNOS5_PA_SYSREG_G3D 0x14A90000
|
||||
|
||||
#define EXYNOS5433_PA_DECON 0x13800000
|
||||
#define EXYNOS5433_PA_DECONTV 0x13880000
|
||||
#define EXYNOS5433_PA_SYSREG_DISP 0x13B80000
|
||||
|
||||
#define EXYNOS5433_PA_MSCLSYS 0x150E0000
|
||||
|
||||
#define EXYNOS5433_VA_CMU_TOP (S5P_VA_CMU + (SZ_4K * 0))
|
||||
#define EXYNOS5433_VA_CMU_EGL (S5P_VA_CMU + (SZ_4K * 1))
|
||||
#define EXYNOS5433_VA_CMU_KFC (S5P_VA_CMU + (SZ_4K * 3))
|
||||
#define EXYNOS5433_VA_CMU_AUD (S5P_VA_CMU + (SZ_4K * 5))
|
||||
#define EXYNOS5433_VA_CMU_BUS1 (S5P_VA_CMU + (SZ_4K * 6))
|
||||
#define EXYNOS5433_VA_CMU_BUS2 (S5P_VA_CMU + (SZ_4K * 7))
|
||||
#define EXYNOS5433_VA_CMU_CAM0 (S5P_VA_CMU + (SZ_4K * 8))
|
||||
#define EXYNOS5433_VA_CMU_CAM0_LOCAL (S5P_VA_CMU + (SZ_4K * 9))
|
||||
#define EXYNOS5433_VA_CMU_CAM1 (S5P_VA_CMU + (SZ_4K * 10))
|
||||
#define EXYNOS5433_VA_CMU_CAM1_LOCAL (S5P_VA_CMU + (SZ_4K * 11))
|
||||
#define EXYNOS5433_VA_CMU_CPIF (S5P_VA_CMU + (SZ_4K * 12))
|
||||
#define EXYNOS5433_VA_CMU_DISP (S5P_VA_CMU + (SZ_4K * 13))
|
||||
#define EXYNOS5433_VA_CMU_FSYS (S5P_VA_CMU + (SZ_4K * 14))
|
||||
#define EXYNOS5433_VA_CMU_G2D (S5P_VA_CMU + (SZ_4K * 15))
|
||||
#define EXYNOS5433_VA_CMU_G3D (S5P_VA_CMU + (SZ_4K * 16))
|
||||
#define EXYNOS5433_VA_CMU_GSCL (S5P_VA_CMU + (SZ_4K * 17))
|
||||
#define EXYNOS5433_VA_CMU_HEVC (S5P_VA_CMU + (SZ_4K * 18))
|
||||
#define EXYNOS5433_VA_CMU_IMEM (S5P_VA_CMU + (SZ_4K * 19))
|
||||
#define EXYNOS5433_VA_CMU_ISP (S5P_VA_CMU + (SZ_4K * 20))
|
||||
#define EXYNOS5433_VA_CMU_ISP_LOCAL (S5P_VA_CMU + (SZ_4K * 21))
|
||||
#define EXYNOS5433_VA_CMU_MFC0 (S5P_VA_CMU + (SZ_4K * 22))
|
||||
#define EXYNOS5433_VA_CMU_MFC1 (S5P_VA_CMU + (SZ_4K * 23))
|
||||
#define EXYNOS5433_VA_CMU_MIF (S5P_VA_CMU + (SZ_4K * 24))
|
||||
#define EXYNOS5433_VA_CMU_MSCL (S5P_VA_CMU + (SZ_4K * 25))
|
||||
#define EXYNOS5433_VA_CMU_PERIC (S5P_VA_CMU + (SZ_4K * 26))
|
||||
#define EXYNOS5433_VA_CMU_PERIS (S5P_VA_CMU + (SZ_4K * 27))
|
||||
|
||||
#define EXYNOS5433_VA_PMU_LPI_CAM0 (S5P_VA_PMU + SZ_64K + (SZ_4K * 0))
|
||||
#define EXYNOS5433_VA_PMU_LPI_CAM1 (S5P_VA_PMU + SZ_64K + (SZ_4K * 1))
|
||||
#define EXYNOS5433_VA_PMU_LPI_ISP (S5P_VA_PMU + SZ_64K + (SZ_4K * 2))
|
||||
#define EXYNOS5433_VA_PMU_LPI_EAGLE (S5P_VA_PMU + SZ_64K + (SZ_4K * 3))
|
||||
|
||||
#define EXYNOS7580_PA_CMU_TOP 0x10010000
|
||||
#define EXYNOS7580_PA_CMU_MIF 0x10430000
|
||||
#define EXYNOS7580_PA_CMU_APL 0x10800000
|
||||
#define EXYNOS7580_PA_CMU_CPU 0x10900000
|
||||
#define EXYNOS7580_PA_CMU_IMEM 0x10C60000
|
||||
#define EXYNOS7580_PA_CMU_AUD 0x110C0000
|
||||
#define EXYNOS7580_PA_CMU_G3D 0x11460000
|
||||
#define EXYNOS7580_PA_CMU_BUS0 0x11800000
|
||||
#define EXYNOS7580_PA_CMU_BUS1 0x12400000
|
||||
#define EXYNOS7580_PA_CMU_MFCMSCL 0x12CB0000
|
||||
#define EXYNOS7580_PA_CMU_BUS2 0x13000000
|
||||
#define EXYNOS7580_PA_CMU_FSYS 0x13730000
|
||||
#define EXYNOS7580_PA_CMU_PERI 0x139F0000
|
||||
#define EXYNOS7580_PA_CMU_ISP_LOCAL 0x144F0000
|
||||
#define EXYNOS7580_PA_CMU_ISP 0x14720000
|
||||
#define EXYNOS7580_PA_CMU_DISP 0x14870000
|
||||
#define EXYNOS7580_PA_SYSREG_DISP 0x14890000
|
||||
#define EXYNOS7580_PA_SYSREG_MIF 0x10450000
|
||||
|
||||
#define EXYNOS7580_VA_CMU_TOP (S5P_VA_CMU + (SZ_4K * 0))
|
||||
#define EXYNOS7580_VA_CMU_MIF (S5P_VA_CMU + (SZ_4K * 1)) /* SZ_8K */
|
||||
#define EXYNOS7580_VA_CMU_APL (S5P_VA_CMU + (SZ_4K * 3)) /* SZ_8K */
|
||||
#define EXYNOS7580_VA_CMU_CPU (S5P_VA_CMU + (SZ_4K * 5)) /* SZ_8K */
|
||||
#define EXYNOS7580_VA_CMU_IMEM (S5P_VA_CMU + (SZ_4K * 7))
|
||||
#define EXYNOS7580_VA_CMU_AUD (S5P_VA_CMU + (SZ_4K * 8))
|
||||
#define EXYNOS7580_VA_CMU_G3D (S5P_VA_CMU + (SZ_4K * 9))
|
||||
#define EXYNOS7580_VA_CMU_BUS0 (S5P_VA_CMU + (SZ_4K * 10))
|
||||
#define EXYNOS7580_VA_CMU_BUS1 (S5P_VA_CMU + (SZ_4K * 11))
|
||||
#define EXYNOS7580_VA_CMU_MFCMSCL (S5P_VA_CMU + (SZ_4K * 12))
|
||||
#define EXYNOS7580_VA_CMU_BUS2 (S5P_VA_CMU + (SZ_4K * 13))
|
||||
#define EXYNOS7580_VA_CMU_FSYS (S5P_VA_CMU + (SZ_4K * 14))
|
||||
#define EXYNOS7580_VA_CMU_PERI (S5P_VA_CMU + (SZ_4K * 15))
|
||||
#define EXYNOS7580_VA_CMU_ISP_LOCAL (S5P_VA_CMU + (SZ_4K * 16))
|
||||
#define EXYNOS7580_VA_CMU_ISP (S5P_VA_CMU + (SZ_4K * 17))
|
||||
#define EXYNOS7580_VA_CMU_DISP (S5P_VA_CMU + (SZ_4K * 18))
|
||||
#define EXYNOS7580_VA_SYSREG_DISP (S5P_VA_CMU + (SZ_4K * 19))
|
||||
|
||||
#define EXYNOS7580_VA_SYSREG_MIF (S5P_VA_SYSREG_MIF + (SZ_8K * 0))
|
||||
|
||||
#endif /* __ASM_ARCH_MAP_H */
|
||||
106
include/soc/samsung/pmu-cp.h
Normal file
106
include/soc/samsung/pmu-cp.h
Normal file
|
|
@ -0,0 +1,106 @@
|
|||
/*
|
||||
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* EXYNOS - PMU(Power Management Unit) support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __EXYNOS_PMU_CP_H
|
||||
#define __EXYNOS_PMU_CP_H __FILE__
|
||||
|
||||
/* BLK_ALIVE: CP related SFRs */
|
||||
#define EXYNOS_PMU_CP_CTRL_NS 0x0030
|
||||
#define EXYNOS_PMU_CP_CTRL_S 0x0034
|
||||
#define EXYNOS_PMU_CP_STAT 0x0038
|
||||
#define EXYNOS_PMU_CP_DEBUG 0x003C
|
||||
|
||||
#define EXYNOS_PMU_CP2AP_MEM_CONFIG 0x0050
|
||||
#define EXYNOS_PMU_CP2AP_MIF_ACCESS_WIN0 0x0054
|
||||
#define EXYNOS_PMU_CP2AP_MIF_ACCESS_WIN1 0x0058
|
||||
#define EXYNOS_PMU_CP2AP_MIF_ACCESS_WIN2 0x005C
|
||||
#define EXYNOS_PMU_CP2AP_MIF_ACCESS_WIN3 0x0060
|
||||
#define EXYNOS_PMU_CP2AP_MIF_CONFIG1 0x0064
|
||||
#define EXYNOS_PMU_CP_BOOT_TEST_RST_CONFIG 0x0068
|
||||
#define EXYNOS_PMU_CP2AP_PERI_ACCESS_WIN 0x006C
|
||||
#define EXYNOS_PMU_MODAPIF_CONFIG 0x0070
|
||||
#define EXYNOS_PMU_CP_CLK_CTRL 0x0074
|
||||
#define EXYNOS_PMU_CP_QOS 0x0078
|
||||
#define EXYNOS_PMU_CP2AP_MIF_CONFIG2 0x007C
|
||||
#define EXYNOS_PMU_CP2AP_ADDR_RNG 0x0084
|
||||
|
||||
#define EXYNOS_PMU_CENTRAL_SEQ_CP_CONFIGURATION 0x0280
|
||||
#define EXYNOS_PMU_RESET_AHEAD_CP_SYS_PWR_REG 0x1170
|
||||
#define EXYNOS_PMU_CLEANY_BUS_SYS_PWR_REG 0x11CC
|
||||
#define EXYNOS_PMU_LOGIC_RESET_CP_SYS_PWR_REG 0x11D0
|
||||
#define EXYNOS_PMU_TCXO_GATE_SYS_PWR_REG 0x11D4
|
||||
#define EXYNOS_PMU_RESET_ASB_CP_SYS_PWR_REG 0x11D8
|
||||
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS7870) || defined(CONFIG_SOC_EXYNOS7570)
|
||||
#define PMU_USBDEV_PHY_CONTROL 0x0704
|
||||
#define USBDEV_PHY_ENABLE BIT(1)
|
||||
/* UART IO SHARE CTRL */
|
||||
#define EXYNOS_PMU_UART_IO_SHARE_CTRL 0x6200
|
||||
#define SEL_CP_UART_DBG BIT(8)
|
||||
#define SEL_UART_DBG_GPIO BIT(4)
|
||||
#define FUNC_ISO_EN BIT(0)
|
||||
#endif
|
||||
|
||||
/* CP PMU */
|
||||
/* For EXYNOS_PMU_CP_CTRL Register */
|
||||
#define CP_PWRON BIT(1)
|
||||
#define CP_RESET_SET BIT(2)
|
||||
#define CP_START BIT(3)
|
||||
#define CP_ACTIVE_REQ_EN BIT(5)
|
||||
#define CP_ACTIVE_REQ_CLR BIT(6)
|
||||
#define CP_RESET_REQ_EN BIT(7)
|
||||
#define CP_RESET_REQ_CLR BIT(8)
|
||||
#define MASK_CP_PWRDN_DONE BIT(9)
|
||||
#define RTC_OUT_EN BIT(10)
|
||||
#define MASK_SLEEP_START_REQ BIT(12)
|
||||
#define SET_SW_SLEEP_START_REQ BIT(13)
|
||||
#define CLEANY_BYPASS_END BIT(16)
|
||||
|
||||
#define SMC_ID 0x82000700
|
||||
#define READ_CTRL 0x3
|
||||
#define WRITE_CTRL 0x4
|
||||
|
||||
#ifdef CONFIG_SOC_EXYNOS7870
|
||||
/* UART IO SHARE CTRL */
|
||||
#define EXYNOS_PMU_UART_IO_SHARE_CTRL 0x6200
|
||||
#define SEL_CP_UART_DBG BIT(8)
|
||||
#define SEL_UART_DBG_GPIO BIT(4)
|
||||
#define FUNC_ISO_EN BIT(0)
|
||||
#endif
|
||||
|
||||
enum cp_mode {
|
||||
CP_POWER_ON,
|
||||
CP_RESET,
|
||||
CP_POWER_OFF,
|
||||
NUM_CP_MODE,
|
||||
};
|
||||
|
||||
enum reset_mode {
|
||||
CP_HW_RESET,
|
||||
CP_SW_RESET,
|
||||
};
|
||||
|
||||
enum cp_control {
|
||||
CP_CTRL_S,
|
||||
CP_CTRL_NS,
|
||||
};
|
||||
|
||||
extern int exynos_cp_reset(void);
|
||||
extern int exynos_cp_release(void);
|
||||
extern int exynos_cp_init(void);
|
||||
extern int exynos_cp_active_clear(void);
|
||||
extern int exynos_clear_cp_reset(void);
|
||||
extern int exynos_get_cp_power_status(void);
|
||||
extern int exynos_set_cp_power_onoff(enum cp_mode mode);
|
||||
extern void exynos_sys_powerdown_conf_cp(void);
|
||||
extern int exynos_pmu_cp_init(void);
|
||||
#endif /* __EXYNOS_PMU_CP_H */
|
||||
72
include/soc/samsung/secmem.h
Normal file
72
include/soc/samsung/secmem.h
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
/* include/soc/samsung/secmem.h
|
||||
*
|
||||
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS - Secure memory support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_SECMEM_H
|
||||
#define __ASM_ARCH_SECMEM_H __FILE__
|
||||
|
||||
#if defined(CONFIG_ION)
|
||||
#include <linux/ion.h>
|
||||
#endif
|
||||
|
||||
#define MAX_NAME_LEN 20
|
||||
|
||||
struct secchunk_info {
|
||||
int index;
|
||||
char name[MAX_NAME_LEN];
|
||||
phys_addr_t base;
|
||||
size_t size;
|
||||
};
|
||||
|
||||
#if defined(CONFIG_ION)
|
||||
extern struct ion_device *ion_exynos;
|
||||
struct secfd_info {
|
||||
int fd;
|
||||
ion_phys_addr_t phys;
|
||||
};
|
||||
#endif
|
||||
|
||||
struct secmem_crypto_driver_ftn {
|
||||
int (*lock) (void);
|
||||
int (*release) (void);
|
||||
};
|
||||
|
||||
struct secmem_region {
|
||||
char *virt_addr;
|
||||
unsigned long phys_addr;
|
||||
unsigned long len;
|
||||
};
|
||||
|
||||
#if defined(CONFIG_EXYNOS_CONTENT_PATH_PROTECTION)
|
||||
void secmem_crypto_register(struct secmem_crypto_driver_ftn *ftn);
|
||||
void secmem_crypto_deregister(void);
|
||||
#else
|
||||
#define secmem_crypto_register(ftn)
|
||||
#define secmem_crypto_deregister()
|
||||
#endif
|
||||
|
||||
int drm_gsc_enable_locked(bool enable);
|
||||
|
||||
#define SECMEM_IOC_CHUNKINFO _IOWR('S', 1, struct secchunk_info)
|
||||
#define SECMEM_IOC_SET_DRM_ONOFF _IOWR('S', 2, int)
|
||||
#define SECMEM_IOC_GET_DRM_ONOFF _IOWR('S', 3, int)
|
||||
#define SECMEM_IOC_GET_CRYPTO_LOCK _IOR('S', 4, int)
|
||||
#define SECMEM_IOC_RELEASE_CRYPTO_LOCK _IOR('S', 5, int)
|
||||
#if defined(CONFIG_ION)
|
||||
#define SECMEM_IOC_GET_FD_PHYS_ADDR _IOWR('S', 8, struct secfd_info)
|
||||
#endif
|
||||
#define SECMEM_IOC_GET_CHUNK_NUM _IOWR('S', 9, int)
|
||||
#define SECMEM_IOC_SET_TZPC _IOWR('S', 11, struct protect_info)
|
||||
#define SECMEM_IOC_SET_PROTECT _IOWR('S', 12, int)
|
||||
#define SECMEM_IOC_SET_VIDEO_EXT_PROC _IOWR('S', 13, int)
|
||||
#define SECMEM_IOC_GET_DRM_PROT_VER _IOWR('S', 14, int)
|
||||
|
||||
#endif /* __ASM_ARCH_SECMEM_H */
|
||||
31
include/soc/samsung/secos_booster.h
Normal file
31
include/soc/samsung/secos_booster.h
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
/* linux/arch/arm/mach-exynos/include/mach/secos_booster.h
|
||||
*
|
||||
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* Header file for secure OS booster API
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __LINUX_SECOS_BOOST_H__
|
||||
#define __LINUX_SECOS_BOOST_H__
|
||||
|
||||
/*
|
||||
* Secure OS Boost Policy
|
||||
*/
|
||||
enum secos_boost_policy {
|
||||
MAX_PERFORMANCE,
|
||||
MID_PERFORMANCE,
|
||||
MIN_PERFORMANCE,
|
||||
STB_PERFORMANCE,
|
||||
PERFORMANCE_MAX_CNT,
|
||||
};
|
||||
|
||||
int secos_booster_start(enum secos_boost_policy policy);
|
||||
int secos_booster_stop(void);
|
||||
|
||||
#endif
|
||||
163
include/soc/samsung/tmu.h
Normal file
163
include/soc/samsung/tmu.h
Normal file
|
|
@ -0,0 +1,163 @@
|
|||
/*
|
||||
* Copyright 2014 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* Header file for tmu support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_TMU_H
|
||||
#define __ASM_ARCH_TMU_H
|
||||
|
||||
#include <linux/platform_data/exynos_thermal.h>
|
||||
|
||||
#define MUX_ADDR_VALUE 6
|
||||
#define TMU_SAVE_NUM 10
|
||||
#define TMU_DC_VALUE 25
|
||||
#define UNUSED_THRESHOLD 0xFF
|
||||
|
||||
#define COLD_TEMP 19
|
||||
#define HOT_NORMAL_TEMP 95
|
||||
#define HOT_CRITICAL_TEMP 110
|
||||
#define MIF_TH_TEMP1 55
|
||||
#define MIF_TH_TEMP2 95
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS5433)
|
||||
#define GPU_TH_TEMP1 95
|
||||
#define GPU_TH_TEMP2 100
|
||||
#define GPU_TH_TEMP3 105
|
||||
#define GPU_TH_TEMP4 110
|
||||
#define GPU_TH_TEMP5 115
|
||||
#elif defined(CONFIG_SOC_EXYNOS7420)
|
||||
#define GPU_TH_TEMP1 90
|
||||
#define GPU_TH_TEMP2 95
|
||||
#define GPU_TH_TEMP3 100
|
||||
#define GPU_TH_TEMP4 105
|
||||
#define GPU_TH_TEMP5 110
|
||||
#elif defined(CONFIG_SOC_EXYNOS7890)
|
||||
#define GPU_TH_TEMP1 85
|
||||
#define GPU_TH_TEMP2 90
|
||||
#define GPU_TH_TEMP3 95
|
||||
#define GPU_TH_TEMP4 100
|
||||
#define GPU_TH_TEMP5 105
|
||||
#else
|
||||
#define GPU_TH_TEMP1 85
|
||||
#define GPU_TH_TEMP2 90
|
||||
#define GPU_TH_TEMP3 95
|
||||
#define GPU_TH_TEMP4 100
|
||||
#define GPU_TH_TEMP5 110
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS7420) || defined(CONFIG_SOC_EXYNOS7890)
|
||||
#define ISP_TH_TEMP1 85
|
||||
#define ISP_TH_TEMP2 95
|
||||
#define ISP_TH_TEMP3 100
|
||||
#define ISP_TH_TEMP4 105
|
||||
#define ISP_TH_TEMP5 110
|
||||
#endif
|
||||
|
||||
enum isp_noti_state_t {
|
||||
ISP_NORMAL = 0,
|
||||
ISP_COLD,
|
||||
ISP_THROTTLING1,
|
||||
ISP_THROTTLING2,
|
||||
ISP_THROTTLING3,
|
||||
ISP_THROTTLING4,
|
||||
ISP_TRIPPING,
|
||||
};
|
||||
|
||||
enum tmu_status_t {
|
||||
TMU_STATUS_INIT = 0,
|
||||
TMU_STATUS_NORMAL,
|
||||
TMU_STATUS_THROTTLED,
|
||||
TMU_STATUS_TRIPPED,
|
||||
};
|
||||
|
||||
enum mif_noti_state_t {
|
||||
MIF_TH_LV1 = 4,
|
||||
MIF_TH_LV2,
|
||||
MIF_TH_LV3,
|
||||
};
|
||||
|
||||
enum tmu_noti_state_t {
|
||||
TMU_NORMAL,
|
||||
TMU_COLD,
|
||||
TMU_HOT,
|
||||
TMU_CRITICAL,
|
||||
};
|
||||
|
||||
enum gpu_noti_state_t {
|
||||
GPU_NORMAL,
|
||||
GPU_COLD,
|
||||
GPU_THROTTLING1,
|
||||
GPU_THROTTLING2,
|
||||
GPU_THROTTLING3,
|
||||
GPU_THROTTLING4,
|
||||
GPU_TRIPPING,
|
||||
GPU_THROTTLING,
|
||||
};
|
||||
|
||||
enum mif_thermal_state_t {
|
||||
MIF_NORMAL = 0,
|
||||
MIF_THROTTLING1,
|
||||
MIF_THROTTLING2,
|
||||
MIF_TRIPPING,
|
||||
};
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS5433)
|
||||
enum tmu_core_number {
|
||||
EXYNOS_TMU_CORE_BIG0 = 0,
|
||||
EXYNOS_TMU_CORE_BIG1,
|
||||
EXYNOS_TMU_CORE_GPU,
|
||||
EXYNOS_TMU_CORE_LITTLE,
|
||||
EXYNOS_TMU_CORE_ISP,
|
||||
};
|
||||
#elif defined(CONFIG_SOC_EXYNOS7420) || defined(CONFIG_SOC_EXYNOS7890)
|
||||
enum tmu_core_number {
|
||||
EXYNOS_TMU_CORE_BIG = 0,
|
||||
EXYNOS_TMU_CORE_LITTLE,
|
||||
EXYNOS_TMU_CORE_GPU,
|
||||
EXYNOS_TMU_CORE_ISP,
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_EXYNOS_THERMAL
|
||||
extern int exynos_tmu_add_notifier(struct notifier_block *n);
|
||||
#if !defined(CONFIG_GPU_THERMAL) && defined(CONFIG_SOC_EXYNOS7580)
|
||||
static inline int exynos_gpu_add_notifier(struct notifier_block *n)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
extern int exynos_gpu_add_notifier(struct notifier_block *n);
|
||||
#endif
|
||||
#else
|
||||
static inline int exynos_tmu_add_notifier(struct notifier_block *n)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_EXYNOS_THERMAL) && (defined(CONFIG_SOC_EXYNOS7420) || defined(CONFIG_SOC_EXYNOS7890) || defined(CONFIG_SOC_EXYNOS8890))
|
||||
extern int exynos_tmu_isp_add_notifier(struct notifier_block *n);
|
||||
#else
|
||||
static inline int exynos_tmu_isp_add_notifier(struct notifier_block *n)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_EXYNOS_THERMAL) && (defined(CONFIG_SOC_EXYNOS5433) || defined(CONFIG_SOC_EXYNOS7420) || defined(CONFIG_SOC_EXYNOS7890) \
|
||||
|| defined(CONFIG_SOC_EXYNOS7870) || defined(CONFIG_SOC_EXYNOS8890) || defined(CONFIG_SOC_EXYNOS7580))
|
||||
extern void exynos_tmu_core_control(bool on, int id);
|
||||
#else
|
||||
static inline void exynos_tmu_core_control(bool on, int id)
|
||||
{
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_ARCH_TMU_H */
|
||||
19
include/soc/tegra/ahb.h
Normal file
19
include/soc/tegra/ahb.h
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
/*
|
||||
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef __SOC_TEGRA_AHB_H__
|
||||
#define __SOC_TEGRA_AHB_H__
|
||||
|
||||
extern int tegra_ahb_enable_smmu(struct device_node *ahb);
|
||||
|
||||
#endif /* __SOC_TEGRA_AHB_H__ */
|
||||
14
include/soc/tegra/common.h
Normal file
14
include/soc/tegra/common.h
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
/*
|
||||
* Copyright (C) 2014 NVIDIA Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __SOC_TEGRA_COMMON_H__
|
||||
#define __SOC_TEGRA_COMMON_H__
|
||||
|
||||
bool soc_is_tegra(void);
|
||||
|
||||
#endif /* __SOC_TEGRA_COMMON_H__ */
|
||||
25
include/soc/tegra/cpuidle.h
Normal file
25
include/soc/tegra/cpuidle.h
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*/
|
||||
|
||||
#ifndef __SOC_TEGRA_CPUIDLE_H__
|
||||
#define __SOC_TEGRA_CPUIDLE_H__
|
||||
|
||||
#ifdef CONFIG_CPU_IDLE
|
||||
void tegra_cpuidle_pcie_irqs_in_use(void);
|
||||
#else
|
||||
static inline void tegra_cpuidle_pcie_irqs_in_use(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SOC_TEGRA_CPUIDLE_H__ */
|
||||
65
include/soc/tegra/fuse.h
Normal file
65
include/soc/tegra/fuse.h
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef __SOC_TEGRA_FUSE_H__
|
||||
#define __SOC_TEGRA_FUSE_H__
|
||||
|
||||
#define TEGRA20 0x20
|
||||
#define TEGRA30 0x30
|
||||
#define TEGRA114 0x35
|
||||
#define TEGRA124 0x40
|
||||
|
||||
#define TEGRA_FUSE_SKU_CALIB_0 0xf0
|
||||
#define TEGRA30_FUSE_SATA_CALIB 0x124
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
u32 tegra_read_chipid(void);
|
||||
u8 tegra_get_chip_id(void);
|
||||
|
||||
enum tegra_revision {
|
||||
TEGRA_REVISION_UNKNOWN = 0,
|
||||
TEGRA_REVISION_A01,
|
||||
TEGRA_REVISION_A02,
|
||||
TEGRA_REVISION_A03,
|
||||
TEGRA_REVISION_A03p,
|
||||
TEGRA_REVISION_A04,
|
||||
TEGRA_REVISION_MAX,
|
||||
};
|
||||
|
||||
struct tegra_sku_info {
|
||||
int sku_id;
|
||||
int cpu_process_id;
|
||||
int cpu_speedo_id;
|
||||
int cpu_speedo_value;
|
||||
int cpu_iddq_value;
|
||||
int core_process_id;
|
||||
int soc_speedo_id;
|
||||
int gpu_speedo_id;
|
||||
int gpu_process_id;
|
||||
int gpu_speedo_value;
|
||||
enum tegra_revision revision;
|
||||
};
|
||||
|
||||
u32 tegra_read_straps(void);
|
||||
u32 tegra_read_chipid(void);
|
||||
int tegra_fuse_readl(unsigned long offset, u32 *value);
|
||||
|
||||
extern struct tegra_sku_info tegra_sku_info;
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __SOC_TEGRA_FUSE_H__ */
|
||||
38
include/soc/tegra/pm.h
Normal file
38
include/soc/tegra/pm.h
Normal file
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright (C) 2014 NVIDIA Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __SOC_TEGRA_PM_H__
|
||||
#define __SOC_TEGRA_PM_H__
|
||||
|
||||
enum tegra_suspend_mode {
|
||||
TEGRA_SUSPEND_NONE = 0,
|
||||
TEGRA_SUSPEND_LP2, /* CPU voltage off */
|
||||
TEGRA_SUSPEND_LP1, /* CPU voltage off, DRAM self-refresh */
|
||||
TEGRA_SUSPEND_LP0, /* CPU + core voltage off, DRAM self-refresh */
|
||||
TEGRA_MAX_SUSPEND_MODE,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
enum tegra_suspend_mode
|
||||
tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode);
|
||||
|
||||
/* low-level resume entry point */
|
||||
void tegra_resume(void);
|
||||
#else
|
||||
static inline enum tegra_suspend_mode
|
||||
tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode)
|
||||
{
|
||||
return TEGRA_SUSPEND_NONE;
|
||||
}
|
||||
|
||||
static inline void tegra_resume(void)
|
||||
{
|
||||
}
|
||||
#endif /* CONFIG_PM_SLEEP */
|
||||
|
||||
#endif /* __SOC_TEGRA_PM_H__ */
|
||||
157
include/soc/tegra/pmc.h
Normal file
157
include/soc/tegra/pmc.h
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/*
|
||||
* Copyright (c) 2010 Google, Inc
|
||||
* Copyright (c) 2014 NVIDIA Corporation
|
||||
*
|
||||
* Author:
|
||||
* Colin Cross <ccross@google.com>
|
||||
*
|
||||
* This software is licensed under the terms of the GNU General Public
|
||||
* License version 2, as published by the Free Software Foundation, and
|
||||
* may be copied, distributed, and modified under those terms.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __SOC_TEGRA_PMC_H__
|
||||
#define __SOC_TEGRA_PMC_H__
|
||||
|
||||
#include <linux/reboot.h>
|
||||
|
||||
#include <soc/tegra/pm.h>
|
||||
|
||||
struct clk;
|
||||
struct reset_control;
|
||||
|
||||
void tegra_pmc_restart(enum reboot_mode mode, const char *cmd);
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
|
||||
void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);
|
||||
void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode);
|
||||
#endif /* CONFIG_PM_SLEEP */
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
bool tegra_pmc_cpu_is_powered(int cpuid);
|
||||
int tegra_pmc_cpu_power_on(int cpuid);
|
||||
int tegra_pmc_cpu_remove_clamping(int cpuid);
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
/*
|
||||
* powergate and I/O rail APIs
|
||||
*/
|
||||
|
||||
#define TEGRA_POWERGATE_CPU 0
|
||||
#define TEGRA_POWERGATE_3D 1
|
||||
#define TEGRA_POWERGATE_VENC 2
|
||||
#define TEGRA_POWERGATE_PCIE 3
|
||||
#define TEGRA_POWERGATE_VDEC 4
|
||||
#define TEGRA_POWERGATE_L2 5
|
||||
#define TEGRA_POWERGATE_MPE 6
|
||||
#define TEGRA_POWERGATE_HEG 7
|
||||
#define TEGRA_POWERGATE_SATA 8
|
||||
#define TEGRA_POWERGATE_CPU1 9
|
||||
#define TEGRA_POWERGATE_CPU2 10
|
||||
#define TEGRA_POWERGATE_CPU3 11
|
||||
#define TEGRA_POWERGATE_CELP 12
|
||||
#define TEGRA_POWERGATE_3D1 13
|
||||
#define TEGRA_POWERGATE_CPU0 14
|
||||
#define TEGRA_POWERGATE_C0NC 15
|
||||
#define TEGRA_POWERGATE_C1NC 16
|
||||
#define TEGRA_POWERGATE_SOR 17
|
||||
#define TEGRA_POWERGATE_DIS 18
|
||||
#define TEGRA_POWERGATE_DISB 19
|
||||
#define TEGRA_POWERGATE_XUSBA 20
|
||||
#define TEGRA_POWERGATE_XUSBB 21
|
||||
#define TEGRA_POWERGATE_XUSBC 22
|
||||
#define TEGRA_POWERGATE_VIC 23
|
||||
#define TEGRA_POWERGATE_IRAM 24
|
||||
|
||||
#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
|
||||
|
||||
#define TEGRA_IO_RAIL_CSIA 0
|
||||
#define TEGRA_IO_RAIL_CSIB 1
|
||||
#define TEGRA_IO_RAIL_DSI 2
|
||||
#define TEGRA_IO_RAIL_MIPI_BIAS 3
|
||||
#define TEGRA_IO_RAIL_PEX_BIAS 4
|
||||
#define TEGRA_IO_RAIL_PEX_CLK1 5
|
||||
#define TEGRA_IO_RAIL_PEX_CLK2 6
|
||||
#define TEGRA_IO_RAIL_USB0 9
|
||||
#define TEGRA_IO_RAIL_USB1 10
|
||||
#define TEGRA_IO_RAIL_USB2 11
|
||||
#define TEGRA_IO_RAIL_USB_BIAS 12
|
||||
#define TEGRA_IO_RAIL_NAND 13
|
||||
#define TEGRA_IO_RAIL_UART 14
|
||||
#define TEGRA_IO_RAIL_BB 15
|
||||
#define TEGRA_IO_RAIL_AUDIO 17
|
||||
#define TEGRA_IO_RAIL_HSIC 19
|
||||
#define TEGRA_IO_RAIL_COMP 22
|
||||
#define TEGRA_IO_RAIL_HDMI 28
|
||||
#define TEGRA_IO_RAIL_PEX_CNTRL 32
|
||||
#define TEGRA_IO_RAIL_SDMMC1 33
|
||||
#define TEGRA_IO_RAIL_SDMMC3 34
|
||||
#define TEGRA_IO_RAIL_SDMMC4 35
|
||||
#define TEGRA_IO_RAIL_CAM 36
|
||||
#define TEGRA_IO_RAIL_RES 37
|
||||
#define TEGRA_IO_RAIL_HV 38
|
||||
#define TEGRA_IO_RAIL_DSIB 39
|
||||
#define TEGRA_IO_RAIL_DSIC 40
|
||||
#define TEGRA_IO_RAIL_DSID 41
|
||||
#define TEGRA_IO_RAIL_CSIE 44
|
||||
#define TEGRA_IO_RAIL_LVDS 57
|
||||
#define TEGRA_IO_RAIL_SYS_DDC 58
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA
|
||||
int tegra_powergate_is_powered(int id);
|
||||
int tegra_powergate_power_on(int id);
|
||||
int tegra_powergate_power_off(int id);
|
||||
int tegra_powergate_remove_clamping(int id);
|
||||
|
||||
/* Must be called with clk disabled, and returns with clk enabled */
|
||||
int tegra_powergate_sequence_power_up(int id, struct clk *clk,
|
||||
struct reset_control *rst);
|
||||
|
||||
int tegra_io_rail_power_on(int id);
|
||||
int tegra_io_rail_power_off(int id);
|
||||
#else
|
||||
static inline int tegra_powergate_is_powered(int id)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int tegra_powergate_power_on(int id)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int tegra_powergate_power_off(int id)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int tegra_powergate_remove_clamping(int id)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int tegra_powergate_sequence_power_up(int id, struct clk *clk,
|
||||
struct reset_control *rst)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int tegra_io_rail_power_on(int id)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static inline int tegra_io_rail_power_off(int id)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
#endif /* CONFIG_ARCH_TEGRA */
|
||||
|
||||
#endif /* __SOC_TEGRA_PMC_H__ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue