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Fixed MTP to work with TWRP

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awab228 2018-06-19 23:16:04 +02:00
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/*
* Copyright (C) 2013 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _VIDEO_ADF_H
#define _VIDEO_ADF_H
#include <linux/device.h>
#include <linux/dma-buf.h>
#include <linux/idr.h>
#include <linux/kref.h>
#include <linux/kthread.h>
#include <linux/ktime.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/scatterlist.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/wait.h>
#include <linux/workqueue.h>
#include <uapi/video/adf.h>
#include "sync.h"
struct adf_obj;
struct adf_obj_ops;
struct adf_device;
struct adf_device_ops;
struct adf_interface;
struct adf_interface_ops;
struct adf_overlay_engine;
struct adf_overlay_engine_ops;
/**
* struct adf_buffer - buffer displayed by adf_post
*
* @overlay_engine: target overlay engine
* @w: width of display region in pixels
* @h: height of display region in pixels
* @format: DRM-style fourcc, see drm_fourcc.h for standard formats
* @dma_bufs: dma_buf for each plane
* @offset: location of first pixel to scan out, in bytes
* @pitch: length of a scanline including padding, in bytes
* @n_planes: number of planes in buffer
* @acquire_fence: sync_fence which will clear when the buffer is
* ready for display
*
* &struct adf_buffer is the in-kernel counterpart to the userspace-facing
* &struct adf_buffer_config.
*/
struct adf_buffer {
struct adf_overlay_engine *overlay_engine;
u32 w;
u32 h;
u32 format;
struct dma_buf *dma_bufs[ADF_MAX_PLANES];
u32 offset[ADF_MAX_PLANES];
u32 pitch[ADF_MAX_PLANES];
u8 n_planes;
struct sync_fence *acquire_fence;
};
/**
* struct adf_buffer_mapping - state for mapping a &struct adf_buffer into the
* display device
*
* @attachments: dma-buf attachment for each plane
* @sg_tables: SG tables for each plane
*/
struct adf_buffer_mapping {
struct dma_buf_attachment *attachments[ADF_MAX_PLANES];
struct sg_table *sg_tables[ADF_MAX_PLANES];
};
/**
* struct adf_post - request to flip to a new set of buffers
*
* @n_bufs: number of buffers displayed
* @bufs: buffers displayed
* @mappings: in-device mapping state for each buffer
* @custom_data_size: size of driver-private data
* @custom_data: driver-private data
*
* &struct adf_post is the in-kernel counterpart to the userspace-facing
* &struct adf_post_config.
*/
struct adf_post {
size_t n_bufs;
struct adf_buffer *bufs;
struct adf_buffer_mapping *mappings;
size_t custom_data_size;
void *custom_data;
};
/**
* struct adf_attachment - description of attachment between an overlay engine
* and an interface
*
* @overlay_engine: the overlay engine
* @interface: the interface
*
* &struct adf_attachment is the in-kernel counterpart to the userspace-facing
* &struct adf_attachment_config.
*/
struct adf_attachment {
struct adf_overlay_engine *overlay_engine;
struct adf_interface *interface;
};
struct adf_pending_post {
struct list_head head;
struct adf_post config;
void *state;
};
enum adf_obj_type {
ADF_OBJ_OVERLAY_ENGINE = 0,
ADF_OBJ_INTERFACE = 1,
ADF_OBJ_DEVICE = 2,
};
/**
* struct adf_obj_ops - common ADF object implementation ops
*
* @open: handle opening the object's device node
* @release: handle releasing an open file
* @ioctl: handle custom ioctls
*
* @supports_event: return whether the object supports generating events of type
* @type
* @set_event: enable or disable events of type @type
* @event_type_str: return a string representation of custom event @type
* (@type >= %ADF_EVENT_DEVICE_CUSTOM).
*
* @custom_data: copy up to %ADF_MAX_CUSTOM_DATA_SIZE bytes of driver-private
* data into @data (allocated by ADF) and return the number of copied bytes
* in @size. Return 0 on success or an error code (<0) on failure.
*/
struct adf_obj_ops {
/* optional */
int (*open)(struct adf_obj *obj, struct inode *inode,
struct file *file);
/* optional */
void (*release)(struct adf_obj *obj, struct inode *inode,
struct file *file);
/* optional */
long (*ioctl)(struct adf_obj *obj, unsigned int cmd, unsigned long arg);
/* optional */
bool (*supports_event)(struct adf_obj *obj, enum adf_event_type type);
/* required if supports_event is implemented */
void (*set_event)(struct adf_obj *obj, enum adf_event_type type,
bool enabled);
/* optional */
const char *(*event_type_str)(struct adf_obj *obj,
enum adf_event_type type);
/* optional */
int (*custom_data)(struct adf_obj *obj, void *data, size_t *size);
};
struct adf_obj {
enum adf_obj_type type;
char name[ADF_NAME_LEN];
struct adf_device *parent;
const struct adf_obj_ops *ops;
struct device dev;
struct spinlock file_lock;
struct list_head file_list;
struct mutex event_lock;
struct rb_root event_refcount;
int id;
int minor;
};
/**
* struct adf_device_quirks - common display device quirks
*
* @buffer_padding: whether the last scanline of a buffer extends to the
* buffer's pitch (@ADF_BUFFER_PADDED_TO_PITCH) or just to the visible
* width (@ADF_BUFFER_UNPADDED)
*/
struct adf_device_quirks {
/* optional, defaults to ADF_BUFFER_PADDED_TO_PITCH */
enum {
ADF_BUFFER_PADDED_TO_PITCH = 0,
ADF_BUFFER_UNPADDED = 1,
} buffer_padding;
};
/**
* struct adf_device_ops - display device implementation ops
*
* @owner: device's module
* @base: common operations (see &struct adf_obj_ops)
* @quirks: device's quirks (see &struct adf_device_quirks)
*
* @attach: attach overlay engine @eng to interface @intf. Return 0 on success
* or error code (<0) on failure.
* @detach: detach overlay engine @eng from interface @intf. Return 0 on
* success or error code (<0) on failure.
*
* @validate_custom_format: validate the number and size of planes
* in buffers with a custom format (i.e., not one of the @DRM_FORMAT_*
* types defined in drm/drm_fourcc.h). Return 0 if the buffer is valid or
* an error code (<0) otherwise.
*
* @validate: validate that the proposed configuration @cfg is legal. The
* driver may optionally allocate and return some driver-private state in
* @driver_state, which will be passed to the corresponding post(). The
* driver may NOT commit any changes to hardware. Return 0 if @cfg is
* valid or an error code (<0) otherwise.
* @complete_fence: create a hardware-backed sync fence to be signaled when
* @cfg is removed from the screen. If unimplemented, ADF automatically
* creates an sw_sync fence. Return the sync fence on success or a
* PTR_ERR() on failure.
* @post: flip @cfg onto the screen. Wait for the display to begin scanning out
* @cfg before returning.
* @advance_timeline: signal the sync fence for the last configuration to leave
* the display. If unimplemented, ADF automatically advances an sw_sync
* timeline.
* @state_free: free driver-private state allocated during validate()
*/
struct adf_device_ops {
/* required */
struct module *owner;
const struct adf_obj_ops base;
/* optional */
const struct adf_device_quirks quirks;
/* optional */
int (*attach)(struct adf_device *dev, struct adf_overlay_engine *eng,
struct adf_interface *intf);
/* optional */
int (*detach)(struct adf_device *dev, struct adf_overlay_engine *eng,
struct adf_interface *intf);
/* required if any of the device's overlay engines supports at least one
custom format */
int (*validate_custom_format)(struct adf_device *dev,
struct adf_buffer *buf);
/* required */
int (*validate)(struct adf_device *dev, struct adf_post *cfg,
void **driver_state);
/* optional */
struct sync_fence *(*complete_fence)(struct adf_device *dev,
struct adf_post *cfg, void *driver_state);
/* required */
void (*post)(struct adf_device *dev, struct adf_post *cfg,
void *driver_state);
/* required if complete_fence is implemented */
void (*advance_timeline)(struct adf_device *dev,
struct adf_post *cfg, void *driver_state);
/* required if validate allocates driver state */
void (*state_free)(struct adf_device *dev, void *driver_state);
};
struct adf_attachment_list {
struct adf_attachment attachment;
struct list_head head;
};
struct adf_device {
struct adf_obj base;
struct device *dev;
const struct adf_device_ops *ops;
struct mutex client_lock;
struct idr interfaces;
size_t n_interfaces;
struct idr overlay_engines;
struct list_head post_list;
struct mutex post_lock;
struct kthread_worker post_worker;
struct task_struct *post_thread;
struct kthread_work post_work;
struct list_head attached;
size_t n_attached;
struct list_head attach_allowed;
size_t n_attach_allowed;
struct adf_pending_post *onscreen;
struct sw_sync_timeline *timeline;
int timeline_max;
};
/**
* struct adf_interface_ops - display interface implementation ops
*
* @base: common operations (see &struct adf_obj_ops)
*
* @blank: change the display's DPMS state. Return 0 on success or error
* code (<0) on failure.
*
* @alloc_simple_buffer: allocate a buffer with the specified @w, @h, and
* @format. @format will be a standard RGB format (i.e.,
* adf_format_is_rgb(@format) == true). Return 0 on success or error code
* (<0) on failure. On success, return the buffer, offset, and pitch in
* @dma_buf, @offset, and @pitch respectively.
* @describe_simple_post: provide driver-private data needed to post a single
* buffer @buf. Copy up to ADF_MAX_CUSTOM_DATA_SIZE bytes into @data
* (allocated by ADF) and return the number of bytes in @size. Return 0 on
* success or error code (<0) on failure.
*
* @modeset: change the interface's mode. @mode is not necessarily part of the
* modelist passed to adf_hotplug_notify_connected(); the driver may
* accept or reject custom modes at its discretion. Return 0 on success or
* error code (<0) if the mode could not be set.
*
* @screen_size: copy the screen dimensions in millimeters into @width_mm
* and @height_mm. Return 0 on success or error code (<0) if the display
* dimensions are unknown.
*
* @type_str: return a string representation of custom @intf->type
* (@intf->type >= @ADF_INTF_TYPE_DEVICE_CUSTOM).
*/
struct adf_interface_ops {
const struct adf_obj_ops base;
/* optional */
int (*blank)(struct adf_interface *intf, u8 state);
/* optional */
int (*alloc_simple_buffer)(struct adf_interface *intf,
u16 w, u16 h, u32 format,
struct dma_buf **dma_buf, u32 *offset, u32 *pitch);
/* optional */
int (*describe_simple_post)(struct adf_interface *intf,
struct adf_buffer *fb, void *data, size_t *size);
/* optional */
int (*modeset)(struct adf_interface *intf,
struct drm_mode_modeinfo *mode);
/* optional */
int (*screen_size)(struct adf_interface *intf, u16 *width_mm,
u16 *height_mm);
/* optional */
const char *(*type_str)(struct adf_interface *intf);
};
struct adf_interface {
struct adf_obj base;
const struct adf_interface_ops *ops;
struct drm_mode_modeinfo current_mode;
enum adf_interface_type type;
u32 idx;
u32 flags;
wait_queue_head_t vsync_wait;
ktime_t vsync_timestamp;
rwlock_t vsync_lock;
u8 dpms_state;
bool hotplug_detect;
struct drm_mode_modeinfo *modelist;
size_t n_modes;
rwlock_t hotplug_modelist_lock;
};
/**
* struct adf_interface_ops - overlay engine implementation ops
*
* @base: common operations (see &struct adf_obj_ops)
*
* @supported_formats: list of fourccs the overlay engine can scan out
* @n_supported_formats: length of supported_formats, up to
* ADF_MAX_SUPPORTED_FORMATS
*/
struct adf_overlay_engine_ops {
const struct adf_obj_ops base;
/* required */
const u32 *supported_formats;
/* required */
const size_t n_supported_formats;
};
struct adf_overlay_engine {
struct adf_obj base;
const struct adf_overlay_engine_ops *ops;
};
#define adf_obj_to_device(ptr) \
container_of((ptr), struct adf_device, base)
#define adf_obj_to_interface(ptr) \
container_of((ptr), struct adf_interface, base)
#define adf_obj_to_overlay_engine(ptr) \
container_of((ptr), struct adf_overlay_engine, base)
int __printf(4, 5) adf_device_init(struct adf_device *dev,
struct device *parent, const struct adf_device_ops *ops,
const char *fmt, ...);
void adf_device_destroy(struct adf_device *dev);
int __printf(7, 8) adf_interface_init(struct adf_interface *intf,
struct adf_device *dev, enum adf_interface_type type, u32 idx,
u32 flags, const struct adf_interface_ops *ops, const char *fmt,
...);
void adf_interface_destroy(struct adf_interface *intf);
static inline struct adf_device *adf_interface_parent(
struct adf_interface *intf)
{
return intf->base.parent;
}
int __printf(4, 5) adf_overlay_engine_init(struct adf_overlay_engine *eng,
struct adf_device *dev,
const struct adf_overlay_engine_ops *ops, const char *fmt, ...);
void adf_overlay_engine_destroy(struct adf_overlay_engine *eng);
static inline struct adf_device *adf_overlay_engine_parent(
struct adf_overlay_engine *eng)
{
return eng->base.parent;
}
int adf_attachment_allow(struct adf_device *dev, struct adf_overlay_engine *eng,
struct adf_interface *intf);
const char *adf_obj_type_str(enum adf_obj_type type);
const char *adf_interface_type_str(struct adf_interface *intf);
const char *adf_event_type_str(struct adf_obj *obj, enum adf_event_type type);
#define ADF_FORMAT_STR_SIZE 5
void adf_format_str(u32 format, char buf[ADF_FORMAT_STR_SIZE]);
int adf_format_validate_yuv(struct adf_device *dev, struct adf_buffer *buf,
u8 num_planes, u8 hsub, u8 vsub, u8 cpp[]);
/**
* adf_format_validate_rgb - validate the number and size of planes in buffers
* with a custom RGB format.
*
* @dev: ADF device performing the validation
* @buf: buffer to validate
* @cpp: expected bytes per pixel
*
* adf_format_validate_rgb() is intended to be called as a helper from @dev's
* validate_custom_format() op. @buf must have a single RGB plane.
*
* Returns 0 if @buf has a single plane with sufficient size, or -EINVAL
* otherwise.
*/
static inline int adf_format_validate_rgb(struct adf_device *dev,
struct adf_buffer *buf, u8 cpp)
{
return adf_format_validate_yuv(dev, buf, 1, 1, 1, &cpp);
}
int adf_event_get(struct adf_obj *obj, enum adf_event_type type);
int adf_event_put(struct adf_obj *obj, enum adf_event_type type);
int adf_event_notify(struct adf_obj *obj, struct adf_event *event);
static inline void adf_vsync_get(struct adf_interface *intf)
{
adf_event_get(&intf->base, ADF_EVENT_VSYNC);
}
static inline void adf_vsync_put(struct adf_interface *intf)
{
adf_event_put(&intf->base, ADF_EVENT_VSYNC);
}
int adf_vsync_wait(struct adf_interface *intf, long timeout);
void adf_vsync_notify(struct adf_interface *intf, ktime_t timestamp);
int adf_hotplug_notify_connected(struct adf_interface *intf,
struct drm_mode_modeinfo *modelist, size_t n_modes);
void adf_hotplug_notify_disconnected(struct adf_interface *intf);
void adf_modeinfo_set_name(struct drm_mode_modeinfo *mode);
void adf_modeinfo_set_vrefresh(struct drm_mode_modeinfo *mode);
#endif /* _VIDEO_ADF_H */

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/*
* Copyright (C) 2013 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _VIDEO_ADF_CLIENT_H_
#define _VIDEO_ADF_CLIENT_H_
#include <video/adf.h>
int adf_interface_blank(struct adf_interface *intf, u8 state);
u8 adf_interface_dpms_state(struct adf_interface *intf);
void adf_interface_current_mode(struct adf_interface *intf,
struct drm_mode_modeinfo *mode);
size_t adf_interface_modelist(struct adf_interface *intf,
struct drm_mode_modeinfo *modelist, size_t n_modes);
int adf_interface_set_mode(struct adf_interface *intf,
struct drm_mode_modeinfo *mode);
int adf_interface_get_screen_size(struct adf_interface *intf, u16 *width,
u16 *height);
int adf_interface_simple_buffer_alloc(struct adf_interface *intf, u16 w, u16 h,
u32 format, struct dma_buf **dma_buf, u32 *offset, u32 *pitch);
struct sync_fence *adf_interface_simple_post(struct adf_interface *intf,
struct adf_buffer *buf);
bool adf_overlay_engine_supports_format(struct adf_overlay_engine *eng,
u32 format);
size_t adf_device_attachments(struct adf_device *dev,
struct adf_attachment *attachments, size_t n_attachments);
size_t adf_device_attachments_allowed(struct adf_device *dev,
struct adf_attachment *attachments, size_t n_attachments);
bool adf_device_attached(struct adf_device *dev, struct adf_overlay_engine *eng,
struct adf_interface *intf);
bool adf_device_attach_allowed(struct adf_device *dev,
struct adf_overlay_engine *eng, struct adf_interface *intf);
int adf_device_attach(struct adf_device *dev, struct adf_overlay_engine *eng,
struct adf_interface *intf);
int adf_device_detach(struct adf_device *dev, struct adf_overlay_engine *eng,
struct adf_interface *intf);
struct sync_fence *adf_device_post(struct adf_device *dev,
struct adf_interface **intfs, size_t n_intfs,
struct adf_buffer *bufs, size_t n_bufs, void *custom_data,
size_t custom_data_size);
struct sync_fence *adf_device_post_nocopy(struct adf_device *dev,
struct adf_interface **intfs, size_t n_intfs,
struct adf_buffer *bufs, size_t n_bufs, void *custom_data,
size_t custom_data_size);
#endif /* _VIDEO_ADF_CLIENT_H_ */

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/*
* Copyright (C) 2013 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _VIDEO_ADF_FBDEV_H_
#define _VIDEO_ADF_FBDEV_H_
#include <linux/fb.h>
#include <linux/mutex.h>
#include <video/adf.h>
struct adf_fbdev {
struct adf_interface *intf;
struct adf_overlay_engine *eng;
struct fb_info *info;
u32 pseudo_palette[16];
unsigned int refcount;
struct mutex refcount_lock;
struct dma_buf *dma_buf;
u32 offset;
u32 pitch;
void *vaddr;
u32 format;
u16 default_xres_virtual;
u16 default_yres_virtual;
u32 default_format;
};
#if IS_ENABLED(CONFIG_ADF_FBDEV)
void adf_modeinfo_to_fb_videomode(const struct drm_mode_modeinfo *mode,
struct fb_videomode *vmode);
void adf_modeinfo_from_fb_videomode(const struct fb_videomode *vmode,
struct drm_mode_modeinfo *mode);
int adf_fbdev_init(struct adf_fbdev *fbdev, struct adf_interface *interface,
struct adf_overlay_engine *eng,
u16 xres_virtual, u16 yres_virtual, u32 format,
struct fb_ops *fbops, const char *fmt, ...);
void adf_fbdev_destroy(struct adf_fbdev *fbdev);
int adf_fbdev_open(struct fb_info *info, int user);
int adf_fbdev_release(struct fb_info *info, int user);
int adf_fbdev_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
int adf_fbdev_set_par(struct fb_info *info);
int adf_fbdev_blank(int blank, struct fb_info *info);
int adf_fbdev_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
int adf_fbdev_mmap(struct fb_info *info, struct vm_area_struct *vma);
#else
static inline void adf_modeinfo_to_fb_videomode(const struct drm_mode_modeinfo *mode,
struct fb_videomode *vmode)
{
WARN_ONCE(1, "%s: CONFIG_ADF_FBDEV is disabled\n", __func__);
}
static inline void adf_modeinfo_from_fb_videomode(const struct fb_videomode *vmode,
struct drm_mode_modeinfo *mode)
{
WARN_ONCE(1, "%s: CONFIG_ADF_FBDEV is disabled\n", __func__);
}
static inline int adf_fbdev_init(struct adf_fbdev *fbdev,
struct adf_interface *interface,
struct adf_overlay_engine *eng,
u16 xres_virtual, u16 yres_virtual, u32 format,
struct fb_ops *fbops, const char *fmt, ...)
{
return -ENODEV;
}
static inline void adf_fbdev_destroy(struct adf_fbdev *fbdev) { }
static inline int adf_fbdev_open(struct fb_info *info, int user)
{
return -ENODEV;
}
static inline int adf_fbdev_release(struct fb_info *info, int user)
{
return -ENODEV;
}
static inline int adf_fbdev_check_var(struct fb_var_screeninfo *var,
struct fb_info *info)
{
return -ENODEV;
}
static inline int adf_fbdev_set_par(struct fb_info *info)
{
return -ENODEV;
}
static inline int adf_fbdev_blank(int blank, struct fb_info *info)
{
return -ENODEV;
}
static inline int adf_fbdev_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
return -ENODEV;
}
static inline int adf_fbdev_mmap(struct fb_info *info,
struct vm_area_struct *vma)
{
return -ENODEV;
}
#endif
#endif /* _VIDEO_ADF_FBDEV_H_ */

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/*
* Copyright (C) 2013 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _VIDEO_ADF_FORMAT_H
#define _VIDEO_ADF_FORMAT_H
bool adf_format_is_standard(u32 format);
bool adf_format_is_rgb(u32 format);
u8 adf_format_num_planes(u32 format);
u8 adf_format_bpp(u32 format);
u8 adf_format_plane_cpp(u32 format, int plane);
u8 adf_format_horz_chroma_subsampling(u32 format);
u8 adf_format_vert_chroma_subsampling(u32 format);
#endif /* _VIDEO_ADF_FORMAT_H */

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/*
* Copyright (C) 2013 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef _VIDEO_ADF_MEMBLOCK_H_
#define _VIDEO_ADF_MEMBLOCK_H_
struct dma_buf *adf_memblock_export(phys_addr_t base, size_t size, int flags);
#endif /* _VIDEO_ADF_MEMBLOCK_H_ */

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/*
* Header file for AT91/AT32 LCD Controller
*
* Data structure and register user interface
*
* Copyright (C) 2007 Atmel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ATMEL_LCDC_H__
#define __ATMEL_LCDC_H__
#include <linux/workqueue.h>
/* Way LCD wires are connected to the chip:
* Some Atmel chips use BGR color mode (instead of standard RGB)
* A swapped wiring onboard can bring to RGB mode.
*/
#define ATMEL_LCDC_WIRING_BGR 0
#define ATMEL_LCDC_WIRING_RGB 1
/* LCD Controller info data structure, stored in device platform_data */
struct atmel_lcdfb_pdata {
unsigned int guard_time;
bool lcdcon_is_backlight;
bool lcdcon_pol_negative;
u8 default_bpp;
u8 lcd_wiring_mode;
unsigned int default_lcdcon2;
unsigned int default_dmacon;
void (*atmel_lcdfb_power_control)(struct atmel_lcdfb_pdata *pdata, int on);
struct fb_monspecs *default_monspecs;
struct list_head pwr_gpios;
};
#define ATMEL_LCDC_DMABADDR1 0x00
#define ATMEL_LCDC_DMABADDR2 0x04
#define ATMEL_LCDC_DMAFRMPT1 0x08
#define ATMEL_LCDC_DMAFRMPT2 0x0c
#define ATMEL_LCDC_DMAFRMADD1 0x10
#define ATMEL_LCDC_DMAFRMADD2 0x14
#define ATMEL_LCDC_DMAFRMCFG 0x18
#define ATMEL_LCDC_FRSIZE (0x7fffff << 0)
#define ATMEL_LCDC_BLENGTH_OFFSET 24
#define ATMEL_LCDC_BLENGTH (0x7f << ATMEL_LCDC_BLENGTH_OFFSET)
#define ATMEL_LCDC_DMACON 0x1c
#define ATMEL_LCDC_DMAEN (0x1 << 0)
#define ATMEL_LCDC_DMARST (0x1 << 1)
#define ATMEL_LCDC_DMABUSY (0x1 << 2)
#define ATMEL_LCDC_DMAUPDT (0x1 << 3)
#define ATMEL_LCDC_DMA2DEN (0x1 << 4)
#define ATMEL_LCDC_DMA2DCFG 0x20
#define ATMEL_LCDC_ADDRINC_OFFSET 0
#define ATMEL_LCDC_ADDRINC (0xffff)
#define ATMEL_LCDC_PIXELOFF_OFFSET 24
#define ATMEL_LCDC_PIXELOFF (0x1f << 24)
#define ATMEL_LCDC_LCDCON1 0x0800
#define ATMEL_LCDC_BYPASS (1 << 0)
#define ATMEL_LCDC_CLKVAL_OFFSET 12
#define ATMEL_LCDC_CLKVAL (0x1ff << ATMEL_LCDC_CLKVAL_OFFSET)
#define ATMEL_LCDC_LINCNT (0x7ff << 21)
#define ATMEL_LCDC_LCDCON2 0x0804
#define ATMEL_LCDC_DISTYPE (3 << 0)
#define ATMEL_LCDC_DISTYPE_STNMONO (0 << 0)
#define ATMEL_LCDC_DISTYPE_STNCOLOR (1 << 0)
#define ATMEL_LCDC_DISTYPE_TFT (2 << 0)
#define ATMEL_LCDC_SCANMOD (1 << 2)
#define ATMEL_LCDC_SCANMOD_SINGLE (0 << 2)
#define ATMEL_LCDC_SCANMOD_DUAL (1 << 2)
#define ATMEL_LCDC_IFWIDTH (3 << 3)
#define ATMEL_LCDC_IFWIDTH_4 (0 << 3)
#define ATMEL_LCDC_IFWIDTH_8 (1 << 3)
#define ATMEL_LCDC_IFWIDTH_16 (2 << 3)
#define ATMEL_LCDC_PIXELSIZE (7 << 5)
#define ATMEL_LCDC_PIXELSIZE_1 (0 << 5)
#define ATMEL_LCDC_PIXELSIZE_2 (1 << 5)
#define ATMEL_LCDC_PIXELSIZE_4 (2 << 5)
#define ATMEL_LCDC_PIXELSIZE_8 (3 << 5)
#define ATMEL_LCDC_PIXELSIZE_16 (4 << 5)
#define ATMEL_LCDC_PIXELSIZE_24 (5 << 5)
#define ATMEL_LCDC_PIXELSIZE_32 (6 << 5)
#define ATMEL_LCDC_INVVD (1 << 8)
#define ATMEL_LCDC_INVVD_NORMAL (0 << 8)
#define ATMEL_LCDC_INVVD_INVERTED (1 << 8)
#define ATMEL_LCDC_INVFRAME (1 << 9 )
#define ATMEL_LCDC_INVFRAME_NORMAL (0 << 9)
#define ATMEL_LCDC_INVFRAME_INVERTED (1 << 9)
#define ATMEL_LCDC_INVLINE (1 << 10)
#define ATMEL_LCDC_INVLINE_NORMAL (0 << 10)
#define ATMEL_LCDC_INVLINE_INVERTED (1 << 10)
#define ATMEL_LCDC_INVCLK (1 << 11)
#define ATMEL_LCDC_INVCLK_NORMAL (0 << 11)
#define ATMEL_LCDC_INVCLK_INVERTED (1 << 11)
#define ATMEL_LCDC_INVDVAL (1 << 12)
#define ATMEL_LCDC_INVDVAL_NORMAL (0 << 12)
#define ATMEL_LCDC_INVDVAL_INVERTED (1 << 12)
#define ATMEL_LCDC_CLKMOD (1 << 15)
#define ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15)
#define ATMEL_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15)
#define ATMEL_LCDC_MEMOR (1 << 31)
#define ATMEL_LCDC_MEMOR_BIG (0 << 31)
#define ATMEL_LCDC_MEMOR_LITTLE (1 << 31)
#define ATMEL_LCDC_TIM1 0x0808
#define ATMEL_LCDC_VFP (0xffU << 0)
#define ATMEL_LCDC_VBP_OFFSET 8
#define ATMEL_LCDC_VBP (0xffU << ATMEL_LCDC_VBP_OFFSET)
#define ATMEL_LCDC_VPW_OFFSET 16
#define ATMEL_LCDC_VPW (0x3fU << ATMEL_LCDC_VPW_OFFSET)
#define ATMEL_LCDC_VHDLY_OFFSET 24
#define ATMEL_LCDC_VHDLY (0xfU << ATMEL_LCDC_VHDLY_OFFSET)
#define ATMEL_LCDC_TIM2 0x080c
#define ATMEL_LCDC_HBP (0xffU << 0)
#define ATMEL_LCDC_HPW_OFFSET 8
#define ATMEL_LCDC_HPW (0x3fU << ATMEL_LCDC_HPW_OFFSET)
#define ATMEL_LCDC_HFP_OFFSET 21
#define ATMEL_LCDC_HFP (0x7ffU << ATMEL_LCDC_HFP_OFFSET)
#define ATMEL_LCDC_LCDFRMCFG 0x0810
#define ATMEL_LCDC_LINEVAL (0x7ff << 0)
#define ATMEL_LCDC_HOZVAL_OFFSET 21
#define ATMEL_LCDC_HOZVAL (0x7ff << ATMEL_LCDC_HOZVAL_OFFSET)
#define ATMEL_LCDC_FIFO 0x0814
#define ATMEL_LCDC_FIFOTH (0xffff)
#define ATMEL_LCDC_MVAL 0x0818
#define ATMEL_LCDC_DP1_2 0x081c
#define ATMEL_LCDC_DP4_7 0x0820
#define ATMEL_LCDC_DP3_5 0x0824
#define ATMEL_LCDC_DP2_3 0x0828
#define ATMEL_LCDC_DP5_7 0x082c
#define ATMEL_LCDC_DP3_4 0x0830
#define ATMEL_LCDC_DP4_5 0x0834
#define ATMEL_LCDC_DP6_7 0x0838
#define ATMEL_LCDC_DP1_2_VAL (0xff)
#define ATMEL_LCDC_DP4_7_VAL (0xfffffff)
#define ATMEL_LCDC_DP3_5_VAL (0xfffff)
#define ATMEL_LCDC_DP2_3_VAL (0xfff)
#define ATMEL_LCDC_DP5_7_VAL (0xfffffff)
#define ATMEL_LCDC_DP3_4_VAL (0xffff)
#define ATMEL_LCDC_DP4_5_VAL (0xfffff)
#define ATMEL_LCDC_DP6_7_VAL (0xfffffff)
#define ATMEL_LCDC_PWRCON 0x083c
#define ATMEL_LCDC_PWR (1 << 0)
#define ATMEL_LCDC_GUARDT_OFFSET 1
#define ATMEL_LCDC_GUARDT (0x7f << ATMEL_LCDC_GUARDT_OFFSET)
#define ATMEL_LCDC_BUSY (1 << 31)
#define ATMEL_LCDC_CONTRAST_CTR 0x0840
#define ATMEL_LCDC_PS (3 << 0)
#define ATMEL_LCDC_PS_DIV1 (0 << 0)
#define ATMEL_LCDC_PS_DIV2 (1 << 0)
#define ATMEL_LCDC_PS_DIV4 (2 << 0)
#define ATMEL_LCDC_PS_DIV8 (3 << 0)
#define ATMEL_LCDC_POL (1 << 2)
#define ATMEL_LCDC_POL_NEGATIVE (0 << 2)
#define ATMEL_LCDC_POL_POSITIVE (1 << 2)
#define ATMEL_LCDC_ENA (1 << 3)
#define ATMEL_LCDC_ENA_PWMDISABLE (0 << 3)
#define ATMEL_LCDC_ENA_PWMENABLE (1 << 3)
#define ATMEL_LCDC_CONTRAST_VAL 0x0844
#define ATMEL_LCDC_CVAL (0xff)
#define ATMEL_LCDC_IER 0x0848
#define ATMEL_LCDC_IDR 0x084c
#define ATMEL_LCDC_IMR 0x0850
#define ATMEL_LCDC_ISR 0x0854
#define ATMEL_LCDC_ICR 0x0858
#define ATMEL_LCDC_LNI (1 << 0)
#define ATMEL_LCDC_LSTLNI (1 << 1)
#define ATMEL_LCDC_EOFI (1 << 2)
#define ATMEL_LCDC_UFLWI (1 << 4)
#define ATMEL_LCDC_OWRI (1 << 5)
#define ATMEL_LCDC_MERI (1 << 6)
#define ATMEL_LCDC_LUT(n) (0x0c00 + ((n)*4))
#endif /* __ATMEL_LCDC_H__ */

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/* $Id: aty128.h,v 1.1 1999/10/12 11:00:40 geert Exp $
* linux/drivers/video/aty128.h
* Register definitions for ATI Rage128 boards
*
* Anthony Tong <atong@uiuc.edu>, 1999
* Brad Douglas <brad@neruo.com>, 2000
*/
#ifndef REG_RAGE128_H
#define REG_RAGE128_H
#define CLOCK_CNTL_INDEX 0x0008
#define CLOCK_CNTL_DATA 0x000c
#define BIOS_0_SCRATCH 0x0010
#define BUS_CNTL 0x0030
#define BUS_CNTL1 0x0034
#define GEN_INT_CNTL 0x0040
#define CRTC_GEN_CNTL 0x0050
#define CRTC_EXT_CNTL 0x0054
#define DAC_CNTL 0x0058
#define I2C_CNTL_1 0x0094
#define PALETTE_INDEX 0x00b0
#define PALETTE_DATA 0x00b4
#define CNFG_CNTL 0x00e0
#define GEN_RESET_CNTL 0x00f0
#define CNFG_MEMSIZE 0x00f8
#define MEM_CNTL 0x0140
#define MEM_POWER_MISC 0x015c
#define AGP_BASE 0x0170
#define AGP_CNTL 0x0174
#define AGP_APER_OFFSET 0x0178
#define PCI_GART_PAGE 0x017c
#define PC_NGUI_MODE 0x0180
#define PC_NGUI_CTLSTAT 0x0184
#define MPP_TB_CONFIG 0x01C0
#define MPP_GP_CONFIG 0x01C8
#define VIPH_CONTROL 0x01D0
#define CRTC_H_TOTAL_DISP 0x0200
#define CRTC_H_SYNC_STRT_WID 0x0204
#define CRTC_V_TOTAL_DISP 0x0208
#define CRTC_V_SYNC_STRT_WID 0x020c
#define CRTC_VLINE_CRNT_VLINE 0x0210
#define CRTC_CRNT_FRAME 0x0214
#define CRTC_GUI_TRIG_VLINE 0x0218
#define CRTC_OFFSET 0x0224
#define CRTC_OFFSET_CNTL 0x0228
#define CRTC_PITCH 0x022c
#define OVR_CLR 0x0230
#define OVR_WID_LEFT_RIGHT 0x0234
#define OVR_WID_TOP_BOTTOM 0x0238
#define LVDS_GEN_CNTL 0x02d0
#define DDA_CONFIG 0x02e0
#define DDA_ON_OFF 0x02e4
#define VGA_DDA_CONFIG 0x02e8
#define VGA_DDA_ON_OFF 0x02ec
#define CRTC2_H_TOTAL_DISP 0x0300
#define CRTC2_H_SYNC_STRT_WID 0x0304
#define CRTC2_V_TOTAL_DISP 0x0308
#define CRTC2_V_SYNC_STRT_WID 0x030c
#define CRTC2_VLINE_CRNT_VLINE 0x0310
#define CRTC2_CRNT_FRAME 0x0314
#define CRTC2_GUI_TRIG_VLINE 0x0318
#define CRTC2_OFFSET 0x0324
#define CRTC2_OFFSET_CNTL 0x0328
#define CRTC2_PITCH 0x032c
#define DDA2_CONFIG 0x03e0
#define DDA2_ON_OFF 0x03e4
#define CRTC2_GEN_CNTL 0x03f8
#define CRTC2_STATUS 0x03fc
#define OV0_SCALE_CNTL 0x0420
#define SUBPIC_CNTL 0x0540
#define PM4_BUFFER_OFFSET 0x0700
#define PM4_BUFFER_CNTL 0x0704
#define PM4_BUFFER_WM_CNTL 0x0708
#define PM4_BUFFER_DL_RPTR_ADDR 0x070c
#define PM4_BUFFER_DL_RPTR 0x0710
#define PM4_BUFFER_DL_WPTR 0x0714
#define PM4_VC_FPU_SETUP 0x071c
#define PM4_FPU_CNTL 0x0720
#define PM4_VC_FORMAT 0x0724
#define PM4_VC_CNTL 0x0728
#define PM4_VC_I01 0x072c
#define PM4_VC_VLOFF 0x0730
#define PM4_VC_VLSIZE 0x0734
#define PM4_IW_INDOFF 0x0738
#define PM4_IW_INDSIZE 0x073c
#define PM4_FPU_FPX0 0x0740
#define PM4_FPU_FPY0 0x0744
#define PM4_FPU_FPX1 0x0748
#define PM4_FPU_FPY1 0x074c
#define PM4_FPU_FPX2 0x0750
#define PM4_FPU_FPY2 0x0754
#define PM4_FPU_FPY3 0x0758
#define PM4_FPU_FPY4 0x075c
#define PM4_FPU_FPY5 0x0760
#define PM4_FPU_FPY6 0x0764
#define PM4_FPU_FPR 0x0768
#define PM4_FPU_FPG 0x076c
#define PM4_FPU_FPB 0x0770
#define PM4_FPU_FPA 0x0774
#define PM4_FPU_INTXY0 0x0780
#define PM4_FPU_INTXY1 0x0784
#define PM4_FPU_INTXY2 0x0788
#define PM4_FPU_INTARGB 0x078c
#define PM4_FPU_FPTWICEAREA 0x0790
#define PM4_FPU_DMAJOR01 0x0794
#define PM4_FPU_DMAJOR12 0x0798
#define PM4_FPU_DMAJOR02 0x079c
#define PM4_FPU_STAT 0x07a0
#define PM4_STAT 0x07b8
#define PM4_TEST_CNTL 0x07d0
#define PM4_MICROCODE_ADDR 0x07d4
#define PM4_MICROCODE_RADDR 0x07d8
#define PM4_MICROCODE_DATAH 0x07dc
#define PM4_MICROCODE_DATAL 0x07e0
#define PM4_CMDFIFO_ADDR 0x07e4
#define PM4_CMDFIFO_DATAH 0x07e8
#define PM4_CMDFIFO_DATAL 0x07ec
#define PM4_BUFFER_ADDR 0x07f0
#define PM4_BUFFER_DATAH 0x07f4
#define PM4_BUFFER_DATAL 0x07f8
#define PM4_MICRO_CNTL 0x07fc
#define CAP0_TRIG_CNTL 0x0950
#define CAP1_TRIG_CNTL 0x09c0
/******************************************************************************
* GUI Block Memory Mapped Registers *
* These registers are FIFOed. *
*****************************************************************************/
#define PM4_FIFO_DATA_EVEN 0x1000
#define PM4_FIFO_DATA_ODD 0x1004
#define DST_OFFSET 0x1404
#define DST_PITCH 0x1408
#define DST_WIDTH 0x140c
#define DST_HEIGHT 0x1410
#define SRC_X 0x1414
#define SRC_Y 0x1418
#define DST_X 0x141c
#define DST_Y 0x1420
#define SRC_PITCH_OFFSET 0x1428
#define DST_PITCH_OFFSET 0x142c
#define SRC_Y_X 0x1434
#define DST_Y_X 0x1438
#define DST_HEIGHT_WIDTH 0x143c
#define DP_GUI_MASTER_CNTL 0x146c
#define BRUSH_SCALE 0x1470
#define BRUSH_Y_X 0x1474
#define DP_BRUSH_BKGD_CLR 0x1478
#define DP_BRUSH_FRGD_CLR 0x147c
#define DST_WIDTH_X 0x1588
#define DST_HEIGHT_WIDTH_8 0x158c
#define SRC_X_Y 0x1590
#define DST_X_Y 0x1594
#define DST_WIDTH_HEIGHT 0x1598
#define DST_WIDTH_X_INCY 0x159c
#define DST_HEIGHT_Y 0x15a0
#define DST_X_SUB 0x15a4
#define DST_Y_SUB 0x15a8
#define SRC_OFFSET 0x15ac
#define SRC_PITCH 0x15b0
#define DST_HEIGHT_WIDTH_BW 0x15b4
#define CLR_CMP_CNTL 0x15c0
#define CLR_CMP_CLR_SRC 0x15c4
#define CLR_CMP_CLR_DST 0x15c8
#define CLR_CMP_MASK 0x15cc
#define DP_SRC_FRGD_CLR 0x15d8
#define DP_SRC_BKGD_CLR 0x15dc
#define DST_BRES_ERR 0x1628
#define DST_BRES_INC 0x162c
#define DST_BRES_DEC 0x1630
#define DST_BRES_LNTH 0x1634
#define DST_BRES_LNTH_SUB 0x1638
#define SC_LEFT 0x1640
#define SC_RIGHT 0x1644
#define SC_TOP 0x1648
#define SC_BOTTOM 0x164c
#define SRC_SC_RIGHT 0x1654
#define SRC_SC_BOTTOM 0x165c
#define GUI_DEBUG0 0x16a0
#define GUI_DEBUG1 0x16a4
#define GUI_TIMEOUT 0x16b0
#define GUI_TIMEOUT0 0x16b4
#define GUI_TIMEOUT1 0x16b8
#define GUI_PROBE 0x16bc
#define DP_CNTL 0x16c0
#define DP_DATATYPE 0x16c4
#define DP_MIX 0x16c8
#define DP_WRITE_MASK 0x16cc
#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0
#define DEFAULT_OFFSET 0x16e0
#define DEFAULT_PITCH 0x16e4
#define DEFAULT_SC_BOTTOM_RIGHT 0x16e8
#define SC_TOP_LEFT 0x16ec
#define SC_BOTTOM_RIGHT 0x16f0
#define SRC_SC_BOTTOM_RIGHT 0x16f4
#define WAIT_UNTIL 0x1720
#define CACHE_CNTL 0x1724
#define GUI_STAT 0x1740
#define PC_GUI_MODE 0x1744
#define PC_GUI_CTLSTAT 0x1748
#define PC_DEBUG_MODE 0x1760
#define BRES_DST_ERR_DEC 0x1780
#define TRAIL_BRES_T12_ERR_DEC 0x1784
#define TRAIL_BRES_T12_INC 0x1788
#define DP_T12_CNTL 0x178c
#define DST_BRES_T1_LNTH 0x1790
#define DST_BRES_T2_LNTH 0x1794
#define SCALE_SRC_HEIGHT_WIDTH 0x1994
#define SCALE_OFFSET_0 0x1998
#define SCALE_PITCH 0x199c
#define SCALE_X_INC 0x19a0
#define SCALE_Y_INC 0x19a4
#define SCALE_HACC 0x19a8
#define SCALE_VACC 0x19ac
#define SCALE_DST_X_Y 0x19b0
#define SCALE_DST_HEIGHT_WIDTH 0x19b4
#define SCALE_3D_CNTL 0x1a00
#define SCALE_3D_DATATYPE 0x1a20
#define SETUP_CNTL 0x1bc4
#define SOLID_COLOR 0x1bc8
#define WINDOW_XY_OFFSET 0x1bcc
#define DRAW_LINE_POINT 0x1bd0
#define SETUP_CNTL_PM4 0x1bd4
#define DST_PITCH_OFFSET_C 0x1c80
#define DP_GUI_MASTER_CNTL_C 0x1c84
#define SC_TOP_LEFT_C 0x1c88
#define SC_BOTTOM_RIGHT_C 0x1c8c
#define CLR_CMP_MASK_3D 0x1A28
#define MISC_3D_STATE_CNTL_REG 0x1CA0
#define MC_SRC1_CNTL 0x19D8
#define TEX_CNTL 0x1800
/* CONSTANTS */
#define GUI_ACTIVE 0x80000000
#define ENGINE_IDLE 0x0
#define PLL_WR_EN 0x00000080
#define CLK_PIN_CNTL 0x0001
#define PPLL_CNTL 0x0002
#define PPLL_REF_DIV 0x0003
#define PPLL_DIV_0 0x0004
#define PPLL_DIV_1 0x0005
#define PPLL_DIV_2 0x0006
#define PPLL_DIV_3 0x0007
#define VCLK_ECP_CNTL 0x0008
#define HTOTAL_CNTL 0x0009
#define X_MPLL_REF_FB_DIV 0x000a
#define XPLL_CNTL 0x000b
#define XDLL_CNTL 0x000c
#define XCLK_CNTL 0x000d
#define MPLL_CNTL 0x000e
#define MCLK_CNTL 0x000f
#define AGP_PLL_CNTL 0x0010
#define FCP_CNTL 0x0012
#define PLL_TEST_CNTL 0x0013
#define P2PLL_CNTL 0x002a
#define P2PLL_REF_DIV 0x002b
#define P2PLL_DIV_0 0x002b
#define POWER_MANAGEMENT 0x002f
#define PPLL_RESET 0x01
#define PPLL_ATOMIC_UPDATE_EN 0x10000
#define PPLL_VGA_ATOMIC_UPDATE_EN 0x20000
#define PPLL_REF_DIV_MASK 0x3FF
#define PPLL_FB3_DIV_MASK 0x7FF
#define PPLL_POST3_DIV_MASK 0x70000
#define PPLL_ATOMIC_UPDATE_R 0x8000
#define PPLL_ATOMIC_UPDATE_W 0x8000
#define MEM_CFG_TYPE_MASK 0x3
#define XCLK_SRC_SEL_MASK 0x7
#define XPLL_FB_DIV_MASK 0xFF00
#define X_MPLL_REF_DIV_MASK 0xFF
/* CRTC control values (CRTC_GEN_CNTL) */
#define CRTC_CSYNC_EN 0x00000010
#define CRTC2_DBL_SCAN_EN 0x00000001
#define CRTC2_DISPLAY_DIS 0x00800000
#define CRTC2_FIFO_EXTSENSE 0x00200000
#define CRTC2_ICON_EN 0x00100000
#define CRTC2_CUR_EN 0x00010000
#define CRTC2_EN 0x02000000
#define CRTC2_DISP_REQ_EN_B 0x04000000
#define CRTC_PIX_WIDTH_MASK 0x00000700
#define CRTC_PIX_WIDTH_4BPP 0x00000100
#define CRTC_PIX_WIDTH_8BPP 0x00000200
#define CRTC_PIX_WIDTH_15BPP 0x00000300
#define CRTC_PIX_WIDTH_16BPP 0x00000400
#define CRTC_PIX_WIDTH_24BPP 0x00000500
#define CRTC_PIX_WIDTH_32BPP 0x00000600
/* DAC_CNTL bit constants */
#define DAC_8BIT_EN 0x00000100
#define DAC_MASK 0xFF000000
#define DAC_BLANKING 0x00000004
#define DAC_RANGE_CNTL 0x00000003
#define DAC_CLK_SEL 0x00000010
#define DAC_PALETTE_ACCESS_CNTL 0x00000020
#define DAC_PALETTE2_SNOOP_EN 0x00000040
#define DAC_PDWN 0x00008000
/* CRTC_EXT_CNTL */
#define CRT_CRTC_ON 0x00008000
/* GEN_RESET_CNTL bit constants */
#define SOFT_RESET_GUI 0x00000001
#define SOFT_RESET_VCLK 0x00000100
#define SOFT_RESET_PCLK 0x00000200
#define SOFT_RESET_ECP 0x00000400
#define SOFT_RESET_DISPENG_XCLK 0x00000800
/* PC_GUI_CTLSTAT bit constants */
#define PC_BUSY_INIT 0x10000000
#define PC_BUSY_GUI 0x20000000
#define PC_BUSY_NGUI 0x40000000
#define PC_BUSY 0x80000000
#define BUS_MASTER_DIS 0x00000040
#define PM4_BUFFER_CNTL_NONPM4 0x00000000
/* DP_DATATYPE bit constants */
#define DST_8BPP 0x00000002
#define DST_15BPP 0x00000003
#define DST_16BPP 0x00000004
#define DST_24BPP 0x00000005
#define DST_32BPP 0x00000006
#define BRUSH_SOLIDCOLOR 0x00000d00
/* DP_GUI_MASTER_CNTL bit constants */
#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000
#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000
#define GMC_SRC_CLIP_DEFAULT 0x00000000
#define GMC_DST_CLIP_DEFAULT 0x00000000
#define GMC_BRUSH_SOLIDCOLOR 0x000000d0
#define GMC_SRC_DSTCOLOR 0x00003000
#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000
#define GMC_DP_SRC_RECT 0x02000000
#define GMC_3D_FCN_EN_CLR 0x00000000
#define GMC_AUX_CLIP_CLEAR 0x20000000
#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000
#define GMC_WRITE_MASK_SET 0x40000000
#define GMC_DP_CONVERSION_TEMP_6500 0x00000000
/* DP_GUI_MASTER_CNTL ROP3 named constants */
#define ROP3_PATCOPY 0x00f00000
#define ROP3_SRCCOPY 0x00cc0000
#define SRC_DSTCOLOR 0x00030000
/* DP_CNTL bit constants */
#define DST_X_RIGHT_TO_LEFT 0x00000000
#define DST_X_LEFT_TO_RIGHT 0x00000001
#define DST_Y_BOTTOM_TO_TOP 0x00000000
#define DST_Y_TOP_TO_BOTTOM 0x00000002
#define DST_X_MAJOR 0x00000000
#define DST_Y_MAJOR 0x00000004
#define DST_X_TILE 0x00000008
#define DST_Y_TILE 0x00000010
#define DST_LAST_PEL 0x00000020
#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000
#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040
#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000
#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080
#define DST_BRES_SIGN 0x00000100
#define DST_HOST_BIG_ENDIAN_EN 0x00000200
#define DST_POLYLINE_NONLAST 0x00008000
#define DST_RASTER_STALL 0x00010000
#define DST_POLY_EDGE 0x00040000
/* DP_MIX bit constants */
#define DP_SRC_RECT 0x00000200
#define DP_SRC_HOST 0x00000300
#define DP_SRC_HOST_BYTEALIGN 0x00000400
/* LVDS_GEN_CNTL constants */
#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00
#define LVDS_BL_MOD_LEVEL_SHIFT 8
#define LVDS_BL_MOD_EN 0x00010000
#define LVDS_DIGION 0x00040000
#define LVDS_BLON 0x00080000
#define LVDS_ON 0x00000001
#define LVDS_DISPLAY_DIS 0x00000002
#define LVDS_PANEL_TYPE_2PIX_PER_CLK 0x00000004
#define LVDS_PANEL_24BITS_TFT 0x00000008
#define LVDS_FRAME_MOD_NO 0x00000000
#define LVDS_FRAME_MOD_2_LEVELS 0x00000010
#define LVDS_FRAME_MOD_4_LEVELS 0x00000020
#define LVDS_RST_FM 0x00000040
#define LVDS_EN 0x00000080
/* CRTC2_GEN_CNTL constants */
#define CRTC2_EN 0x02000000
/* POWER_MANAGEMENT constants */
#define PWR_MGT_ON 0x00000001
#define PWR_MGT_MODE_MASK 0x00000006
#define PWR_MGT_MODE_PIN 0x00000000
#define PWR_MGT_MODE_REGISTER 0x00000002
#define PWR_MGT_MODE_TIMER 0x00000004
#define PWR_MGT_MODE_PCI 0x00000006
#define PWR_MGT_AUTO_PWR_UP_EN 0x00000008
#define PWR_MGT_ACTIVITY_PIN_ON 0x00000010
#define PWR_MGT_STANDBY_POL 0x00000020
#define PWR_MGT_SUSPEND_POL 0x00000040
#define PWR_MGT_SELF_REFRESH 0x00000080
#define PWR_MGT_ACTIVITY_PIN_EN 0x00000100
#define PWR_MGT_KEYBD_SNOOP 0x00000200
#define PWR_MGT_TRISTATE_MEM_EN 0x00000800
#define PWR_MGT_SELW4MS 0x00001000
#define PWR_MGT_SLOWDOWN_MCLK 0x00002000
#define PMI_PMSCR_REG 0x60
/* used by ATI bug fix for hardware ROM */
#define RAGE128_MPP_TB_CONFIG 0x01c0
#endif /* REG_RAGE128_H */

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/*
* Definitions for AUO-K190X framebuffer drivers
*
* Copyright (C) 2012 Heiko Stuebner <heiko@sntech.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _LINUX_VIDEO_AUO_K190XFB_H_
#define _LINUX_VIDEO_AUO_K190XFB_H_
/* Controller standby command needs a param */
#define AUOK190X_QUIRK_STANDBYPARAM (1 << 0)
/* Controller standby is completely broken */
#define AUOK190X_QUIRK_STANDBYBROKEN (1 << 1)
/*
* Resolutions for the displays
*/
#define AUOK190X_RESOLUTION_800_600 0
#define AUOK190X_RESOLUTION_1024_768 1
#define AUOK190X_RESOLUTION_600_800 4
#define AUOK190X_RESOLUTION_768_1024 5
/*
* struct used by auok190x. board specific stuff comes from *board
*/
struct auok190xfb_par {
struct fb_info *info;
struct auok190x_board *board;
struct regulator *regulator;
struct mutex io_lock;
struct delayed_work work;
wait_queue_head_t waitq;
int resolution;
int rotation;
int consecutive_threshold;
int update_cnt;
/* panel and controller informations */
int epd_type;
int panel_size_int;
int panel_size_float;
int panel_model;
int tcon_version;
int lut_version;
/* individual controller callbacks */
void (*update_partial)(struct auok190xfb_par *par, u16 y1, u16 y2);
void (*update_all)(struct auok190xfb_par *par);
bool (*need_refresh)(struct auok190xfb_par *par);
void (*init)(struct auok190xfb_par *par);
void (*recover)(struct auok190xfb_par *par);
int update_mode; /* mode to use for updates */
int last_mode; /* update mode last used */
int flash;
/* power management */
int autosuspend_delay;
bool standby;
bool manual_standby;
};
/**
* Board specific platform-data
* @init: initialize the controller interface
* @cleanup: cleanup the controller interface
* @wait_for_rdy: wait until the controller is not busy anymore
* @set_ctl: change an interface control
* @set_hdb: write a value to the data register
* @get_hdb: read a value from the data register
* @setup_irq: method to setup the irq handling on the busy gpio
* @gpio_nsleep: sleep gpio
* @gpio_nrst: reset gpio
* @gpio_nbusy: busy gpio
* @resolution: one of the AUOK190X_RESOLUTION constants
* @rotation: rotation of the framebuffer
* @quirks: controller quirks to honor
* @fps: frames per second for defio
*/
struct auok190x_board {
int (*init)(struct auok190xfb_par *);
void (*cleanup)(struct auok190xfb_par *);
int (*wait_for_rdy)(struct auok190xfb_par *);
void (*set_ctl)(struct auok190xfb_par *, unsigned char, u8);
void (*set_hdb)(struct auok190xfb_par *, u16);
u16 (*get_hdb)(struct auok190xfb_par *);
int (*setup_irq)(struct fb_info *);
int gpio_nsleep;
int gpio_nrst;
int gpio_nbusy;
int resolution;
int quirks;
int fps;
};
#endif

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/*
* broadsheetfb.h - definitions for the broadsheet framebuffer driver
*
* Copyright (C) 2008 by Jaya Kumar
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
*/
#ifndef _LINUX_BROADSHEETFB_H_
#define _LINUX_BROADSHEETFB_H_
/* Broadsheet command defines */
#define BS_CMD_INIT_SYS_RUN 0x06
#define BS_CMD_INIT_DSPE_CFG 0x09
#define BS_CMD_INIT_DSPE_TMG 0x0A
#define BS_CMD_INIT_ROTMODE 0x0B
#define BS_CMD_RD_REG 0x10
#define BS_CMD_WR_REG 0x11
#define BS_CMD_LD_IMG 0x20
#define BS_CMD_LD_IMG_AREA 0x22
#define BS_CMD_LD_IMG_END 0x23
#define BS_CMD_WAIT_DSPE_TRG 0x28
#define BS_CMD_WAIT_DSPE_FREND 0x29
#define BS_CMD_RD_WFM_INFO 0x30
#define BS_CMD_UPD_INIT 0x32
#define BS_CMD_UPD_FULL 0x33
#define BS_CMD_UPD_GDRV_CLR 0x37
/* Broadsheet register interface defines */
#define BS_REG_REV 0x00
#define BS_REG_PRC 0x02
/* Broadsheet pin interface specific defines */
#define BS_CS 0x01
#define BS_DC 0x02
#define BS_WR 0x03
/* Broadsheet IO interface specific defines */
#define BS_MMIO_CMD 0x01
#define BS_MMIO_DATA 0x02
/* struct used by broadsheet. board specific stuff comes from *board */
struct broadsheetfb_par {
struct fb_info *info;
struct broadsheet_board *board;
void (*write_reg)(struct broadsheetfb_par *, u16 reg, u16 val);
u16 (*read_reg)(struct broadsheetfb_par *, u16 reg);
wait_queue_head_t waitq;
int panel_index;
struct mutex io_lock;
};
/* board specific routines */
struct broadsheet_board {
struct module *owner;
int (*init)(struct broadsheetfb_par *);
int (*wait_for_rdy)(struct broadsheetfb_par *);
void (*cleanup)(struct broadsheetfb_par *);
int (*get_panel_type)(void);
int (*setup_irq)(struct fb_info *);
/* Functions for boards that use GPIO */
void (*set_ctl)(struct broadsheetfb_par *, unsigned char, u8);
void (*set_hdb)(struct broadsheetfb_par *, u16);
u16 (*get_hdb)(struct broadsheetfb_par *);
/* Functions for boards that have specialized MMIO */
void (*mmio_write)(struct broadsheetfb_par *, int type, u16);
u16 (*mmio_read)(struct broadsheetfb_par *);
};
#endif

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/*
* drivers/video/clgenfb.h - Cirrus Logic chipset constants
*
* Copyright 1999 Jeff Garzik <jgarzik@pobox.com>
*
* Original clgenfb author: Frank Neumann
*
* Based on retz3fb.c and clgen.c:
* Copyright (C) 1997 Jes Sorensen
* Copyright (C) 1996 Frank Neumann
*
***************************************************************
*
* Format this code with GNU indent '-kr -i8 -pcs' options.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*
*/
#ifndef __CLGENFB_H__
#define __CLGENFB_H__
/* OLD COMMENT: definitions for Piccolo/SD64 VGA controller chip */
/* OLD COMMENT: these definitions might most of the time also work */
/* OLD COMMENT: for other CL-GD542x/543x based boards.. */
/*** External/General Registers ***/
#define CL_POS102 0x102 /* POS102 register */
#define CL_VSSM 0x46e8 /* Adapter Sleep */
#define CL_VSSM2 0x3c3 /* Motherboard Sleep */
/*** VGA Sequencer Registers ***/
/* the following are from the "extension registers" group */
#define CL_SEQR6 0x6 /* Unlock ALL Extensions */
#define CL_SEQR7 0x7 /* Extended Sequencer Mode */
#define CL_SEQR8 0x8 /* EEPROM Control */
#define CL_SEQR9 0x9 /* Scratch Pad 0 (do not access!) */
#define CL_SEQRA 0xa /* Scratch Pad 1 (do not access!) */
#define CL_SEQRB 0xb /* VCLK0 Numerator */
#define CL_SEQRC 0xc /* VCLK1 Numerator */
#define CL_SEQRD 0xd /* VCLK2 Numerator */
#define CL_SEQRE 0xe /* VCLK3 Numerator */
#define CL_SEQRF 0xf /* DRAM Control */
#define CL_SEQR10 0x10 /* Graphics Cursor X Position */
#define CL_SEQR11 0x11 /* Graphics Cursor Y Position */
#define CL_SEQR12 0x12 /* Graphics Cursor Attributes */
#define CL_SEQR13 0x13 /* Graphics Cursor Pattern Address Offset */
#define CL_SEQR14 0x14 /* Scratch Pad 2 (CL-GD5426/'28 Only) (do not access!) */
#define CL_SEQR15 0x15 /* Scratch Pad 3 (CL-GD5426/'28 Only) (do not access!) */
#define CL_SEQR16 0x16 /* Performance Tuning (CL-GD5424/'26/'28 Only) */
#define CL_SEQR17 0x17 /* Configuration ReadBack and Extended Control (CL-GF5428 Only) */
#define CL_SEQR18 0x18 /* Signature Generator Control (Not CL-GD5420) */
#define CL_SEQR19 0x19 /* Signature Generator Result Low Byte (Not CL-GD5420) */
#define CL_SEQR1A 0x1a /* Signature Generator Result High Byte (Not CL-GD5420) */
#define CL_SEQR1B 0x1b /* VCLK0 Denominator and Post-Scalar Value */
#define CL_SEQR1C 0x1c /* VCLK1 Denominator and Post-Scalar Value */
#define CL_SEQR1D 0x1d /* VCLK2 Denominator and Post-Scalar Value */
#define CL_SEQR1E 0x1e /* VCLK3 Denominator and Post-Scalar Value */
#define CL_SEQR1F 0x1f /* BIOS ROM write enable and MCLK Select */
/*** CRT Controller Registers ***/
#define CL_CRT22 0x22 /* Graphics Data Latches ReadBack */
#define CL_CRT24 0x24 /* Attribute Controller Toggle ReadBack */
#define CL_CRT26 0x26 /* Attribute Controller Index ReadBack */
/* the following are from the "extension registers" group */
#define CL_CRT19 0x19 /* Interlace End */
#define CL_CRT1A 0x1a /* Interlace Control */
#define CL_CRT1B 0x1b /* Extended Display Controls */
#define CL_CRT1C 0x1c /* Sync adjust and genlock register */
#define CL_CRT1D 0x1d /* Overlay Extended Control register */
#define CL_CRT1E 0x1e /* Another overflow register */
#define CL_CRT25 0x25 /* Part Status Register */
#define CL_CRT27 0x27 /* ID Register */
#define CL_CRT51 0x51 /* P4 disable "flicker fixer" */
/*** Graphics Controller Registers ***/
/* the following are from the "extension registers" group */
#define CL_GR9 0x9 /* Offset Register 0 */
#define CL_GRA 0xa /* Offset Register 1 */
#define CL_GRB 0xb /* Graphics Controller Mode Extensions */
#define CL_GRC 0xc /* Color Key (CL-GD5424/'26/'28 Only) */
#define CL_GRD 0xd /* Color Key Mask (CL-GD5424/'26/'28 Only) */
#define CL_GRE 0xe /* Miscellaneous Control (Cl-GD5428 Only) */
#define CL_GRF 0xf /* Display Compression Control register */
#define CL_GR10 0x10 /* 16-bit Pixel BG Color High Byte (Not CL-GD5420) */
#define CL_GR11 0x11 /* 16-bit Pixel FG Color High Byte (Not CL-GD5420) */
#define CL_GR12 0x12 /* Background Color Byte 2 Register */
#define CL_GR13 0x13 /* Foreground Color Byte 2 Register */
#define CL_GR14 0x14 /* Background Color Byte 3 Register */
#define CL_GR15 0x15 /* Foreground Color Byte 3 Register */
/* the following are CL-GD5426/'28 specific blitter registers */
#define CL_GR20 0x20 /* BLT Width Low */
#define CL_GR21 0x21 /* BLT Width High */
#define CL_GR22 0x22 /* BLT Height Low */
#define CL_GR23 0x23 /* BLT Height High */
#define CL_GR24 0x24 /* BLT Destination Pitch Low */
#define CL_GR25 0x25 /* BLT Destination Pitch High */
#define CL_GR26 0x26 /* BLT Source Pitch Low */
#define CL_GR27 0x27 /* BLT Source Pitch High */
#define CL_GR28 0x28 /* BLT Destination Start Low */
#define CL_GR29 0x29 /* BLT Destination Start Mid */
#define CL_GR2A 0x2a /* BLT Destination Start High */
#define CL_GR2C 0x2c /* BLT Source Start Low */
#define CL_GR2D 0x2d /* BLT Source Start Mid */
#define CL_GR2E 0x2e /* BLT Source Start High */
#define CL_GR2F 0x2f /* Picasso IV Blitter compat mode..? */
#define CL_GR30 0x30 /* BLT Mode */
#define CL_GR31 0x31 /* BLT Start/Status */
#define CL_GR32 0x32 /* BLT Raster Operation */
#define CL_GR33 0x33 /* another P4 "compat" register.. */
#define CL_GR34 0x34 /* Transparent Color Select Low */
#define CL_GR35 0x35 /* Transparent Color Select High */
#define CL_GR38 0x38 /* Source Transparent Color Mask Low */
#define CL_GR39 0x39 /* Source Transparent Color Mask High */
/*** Attribute Controller Registers ***/
#define CL_AR33 0x33 /* The "real" Pixel Panning register (?) */
#define CL_AR34 0x34 /* TEST */
#endif /* __CLGENFB_H__ */

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/*
* Phase5 CybervisionPPC (TVP4020) definitions for the Permedia2 framebuffer
* driver.
*
* Copyright (c) 1998-1999 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
* --------------------------------------------------------------------------
* $Id: cvisionppc.h,v 1.8 1999/01/28 13:18:07 illo Exp $
* --------------------------------------------------------------------------
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#ifndef CVISIONPPC_H
#define CVISIONPPC_H
#ifndef PM2FB_H
#include "pm2fb.h"
#endif
struct cvppc_par {
unsigned char* pci_config;
unsigned char* pci_bridge;
u32 user_flags;
};
#define CSPPC_PCI_BRIDGE 0xfffe0000
#define CSPPC_BRIDGE_ENDIAN 0x0000
#define CSPPC_BRIDGE_INT 0x0010
#define CVPPC_PCI_CONFIG 0xfffc0000
#define CVPPC_ROM_ADDRESS 0xe2000001
#define CVPPC_REGS_REGION 0xef000000
#define CVPPC_FB_APERTURE_ONE 0xe0000000
#define CVPPC_FB_APERTURE_TWO 0xe1000000
#define CVPPC_FB_SIZE 0x00800000
#define CVPPC_MEM_CONFIG_OLD 0xed61fcaa /* FIXME Fujitsu?? */
#define CVPPC_MEM_CONFIG_NEW 0xed41c532 /* FIXME USA?? */
#define CVPPC_MEMCLOCK 83000 /* in KHz */
/* CVPPC_BRIDGE_ENDIAN */
#define CSPPCF_BRIDGE_BIG_ENDIAN 0x02
/* CVPPC_BRIDGE_INT */
#define CSPPCF_BRIDGE_ACTIVE_INT2 0x01
#endif /* CVISIONPPC_H */
/*****************************************************************************
* That's all folks!
*****************************************************************************/

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/*
* Header file for TI DA8XX LCD controller platform data.
*
* Copyright (C) 2008-2009 MontaVista Software Inc.
* Copyright (C) 2008-2009 Texas Instruments Inc
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#ifndef DA8XX_FB_H
#define DA8XX_FB_H
enum panel_shade {
MONOCHROME = 0,
COLOR_ACTIVE,
COLOR_PASSIVE,
};
enum raster_load_mode {
LOAD_DATA = 1,
LOAD_PALETTE,
};
enum da8xx_frame_complete {
DA8XX_FRAME_WAIT,
DA8XX_FRAME_NOWAIT,
};
struct da8xx_lcdc_platform_data {
const char manu_name[10];
void *controller_data;
const char type[25];
void (*panel_power_ctrl)(int);
};
struct lcd_ctrl_config {
enum panel_shade panel_shade;
/* AC Bias Pin Frequency */
int ac_bias;
/* AC Bias Pin Transitions per Interrupt */
int ac_bias_intrpt;
/* DMA burst size */
int dma_burst_sz;
/* Bits per pixel */
int bpp;
/* FIFO DMA Request Delay */
int fdd;
/* TFT Alternative Signal Mapping (Only for active) */
unsigned char tft_alt_mode;
/* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */
unsigned char stn_565_mode;
/* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
unsigned char mono_8bit_mode;
/* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
unsigned char sync_edge;
/* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
unsigned char raster_order;
/* DMA FIFO threshold */
int fifo_th;
};
struct lcd_sync_arg {
int back_porch;
int front_porch;
int pulse_width;
};
/* ioctls */
#define FBIOGET_CONTRAST _IOR('F', 1, int)
#define FBIOPUT_CONTRAST _IOW('F', 2, int)
#define FBIGET_BRIGHTNESS _IOR('F', 3, int)
#define FBIPUT_BRIGHTNESS _IOW('F', 3, int)
#define FBIGET_COLOR _IOR('F', 5, int)
#define FBIPUT_COLOR _IOW('F', 6, int)
#define FBIPUT_HSYNC _IOW('F', 9, int)
#define FBIPUT_VSYNC _IOW('F', 10, int)
/* Proprietary FB_SYNC_ flags */
#define FB_SYNC_CLK_INVERT 0x40000000
#endif /* ifndef DA8XX_FB_H */

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/*
* Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>
*
* description of display timings
*
* This file is released under the GPLv2
*/
#ifndef __LINUX_DISPLAY_TIMING_H
#define __LINUX_DISPLAY_TIMING_H
#include <linux/bitops.h>
#include <linux/types.h>
enum display_flags {
DISPLAY_FLAGS_HSYNC_LOW = BIT(0),
DISPLAY_FLAGS_HSYNC_HIGH = BIT(1),
DISPLAY_FLAGS_VSYNC_LOW = BIT(2),
DISPLAY_FLAGS_VSYNC_HIGH = BIT(3),
/* data enable flag */
DISPLAY_FLAGS_DE_LOW = BIT(4),
DISPLAY_FLAGS_DE_HIGH = BIT(5),
/* drive data on pos. edge */
DISPLAY_FLAGS_PIXDATA_POSEDGE = BIT(6),
/* drive data on neg. edge */
DISPLAY_FLAGS_PIXDATA_NEGEDGE = BIT(7),
DISPLAY_FLAGS_INTERLACED = BIT(8),
DISPLAY_FLAGS_DOUBLESCAN = BIT(9),
DISPLAY_FLAGS_DOUBLECLK = BIT(10),
};
/*
* A single signal can be specified via a range of minimal and maximal values
* with a typical value, that lies somewhere inbetween.
*/
struct timing_entry {
u32 min;
u32 typ;
u32 max;
};
/*
* Single "mode" entry. This describes one set of signal timings a display can
* have in one setting. This struct can later be converted to struct videomode
* (see include/video/videomode.h). As each timing_entry can be defined as a
* range, one struct display_timing may become multiple struct videomodes.
*
* Example: hsync active high, vsync active low
*
* Active Video
* Video ______________________XXXXXXXXXXXXXXXXXXXXXX_____________________
* |<- sync ->|<- back ->|<----- active ----->|<- front ->|<- sync..
* | | porch | | porch |
*
* HSync _|¯¯¯¯¯¯¯¯¯¯|___________________________________________|¯¯¯¯¯¯¯¯¯
*
* VSync ¯|__________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_________
*/
struct display_timing {
struct timing_entry pixelclock;
struct timing_entry hactive; /* hor. active video */
struct timing_entry hfront_porch; /* hor. front porch */
struct timing_entry hback_porch; /* hor. back porch */
struct timing_entry hsync_len; /* hor. sync len */
struct timing_entry vactive; /* ver. active video */
struct timing_entry vfront_porch; /* ver. front porch */
struct timing_entry vback_porch; /* ver. back porch */
struct timing_entry vsync_len; /* ver. sync len */
enum display_flags flags; /* display flags */
};
/*
* This describes all timing settings a display provides.
* The native_mode is the default setting for this display.
* Drivers that can handle multiple videomodes should work with this struct and
* convert each entry to the desired end result.
*/
struct display_timings {
unsigned int num_timings;
unsigned int native_mode;
struct display_timing **timings;
};
/* get one entry from struct display_timings */
static inline struct display_timing *display_timings_get(const struct
display_timings *disp,
unsigned int index)
{
if (disp->num_timings > index)
return disp->timings[index];
else
return NULL;
}
void display_timings_release(struct display_timings *disp);
#endif

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#ifndef __linux_video_edid_h__
#define __linux_video_edid_h__
#include <uapi/video/edid.h>
#ifdef CONFIG_X86
extern struct edid_info edid_info;
#endif
#endif /* __linux_video_edid_h__ */

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/* include/video/exynos_mipi_dsim.h
*
* Platform data header for Samsung SoC MIPI-DSIM.
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd
*
* InKi Dae <inki.dae@samsung.com>
* Donghwa Lee <dh09.lee@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _EXYNOS_MIPI_DSIM_H
#define _EXYNOS_MIPI_DSIM_H
#include <linux/device.h>
#include <linux/fb.h>
#define PANEL_NAME_SIZE (32)
/*
* Enumerate display interface type.
*
* DSIM_COMMAND means cpu interface and rgb interface for DSIM_VIDEO.
*
* P.S. MIPI DSI Master has two display controller intefaces, RGB Interface
* for main display and CPU Interface(same as I80 Interface) for main
* and sub display.
*/
enum mipi_dsim_interface_type {
DSIM_COMMAND,
DSIM_VIDEO
};
enum mipi_dsim_virtual_ch_no {
DSIM_VIRTUAL_CH_0,
DSIM_VIRTUAL_CH_1,
DSIM_VIRTUAL_CH_2,
DSIM_VIRTUAL_CH_3
};
enum mipi_dsim_burst_mode_type {
DSIM_NON_BURST_SYNC_EVENT,
DSIM_BURST_SYNC_EVENT,
DSIM_NON_BURST_SYNC_PULSE,
DSIM_BURST,
DSIM_NON_VIDEO_MODE
};
enum mipi_dsim_no_of_data_lane {
DSIM_DATA_LANE_1,
DSIM_DATA_LANE_2,
DSIM_DATA_LANE_3,
DSIM_DATA_LANE_4
};
enum mipi_dsim_byte_clk_src {
DSIM_PLL_OUT_DIV8,
DSIM_EXT_CLK_DIV8,
DSIM_EXT_CLK_BYPASS
};
enum mipi_dsim_pixel_format {
DSIM_CMD_3BPP,
DSIM_CMD_8BPP,
DSIM_CMD_12BPP,
DSIM_CMD_16BPP,
DSIM_VID_16BPP_565,
DSIM_VID_18BPP_666PACKED,
DSIM_18BPP_666LOOSELYPACKED,
DSIM_24BPP_888
};
/*
* struct mipi_dsim_config - interface for configuring mipi-dsi controller.
*
* @auto_flush: enable or disable Auto flush of MD FIFO using VSYNC pulse.
* @eot_disable: enable or disable EoT packet in HS mode.
* @auto_vertical_cnt: specifies auto vertical count mode.
* in Video mode, the vertical line transition uses line counter
* configured by VSA, VBP, and Vertical resolution.
* If this bit is set to '1', the line counter does not use VSA and VBP
* registers.(in command mode, this variable is ignored)
* @hse: set horizontal sync event mode.
* In VSYNC pulse and Vporch area, MIPI DSI master transfers only HSYNC
* start packet to MIPI DSI slave at MIPI DSI spec1.1r02.
* this bit transfers HSYNC end packet in VSYNC pulse and Vporch area
* (in mommand mode, this variable is ignored)
* @hfp: specifies HFP disable mode.
* if this variable is set, DSI master ignores HFP area in VIDEO mode.
* (in command mode, this variable is ignored)
* @hbp: specifies HBP disable mode.
* if this variable is set, DSI master ignores HBP area in VIDEO mode.
* (in command mode, this variable is ignored)
* @hsa: specifies HSA disable mode.
* if this variable is set, DSI master ignores HSA area in VIDEO mode.
* (in command mode, this variable is ignored)
* @cma_allow: specifies the number of horizontal lines, where command packet
* transmission is allowed after Stable VFP period.
* @e_interface: specifies interface to be used.(CPU or RGB interface)
* @e_virtual_ch: specifies virtual channel number that main or
* sub diaplsy uses.
* @e_pixel_format: specifies pixel stream format for main or sub display.
* @e_burst_mode: selects Burst mode in Video mode.
* in Non-burst mode, RGB data area is filled with RGB data and NULL
* packets, according to input bandwidth of RGB interface.
* In Burst mode, RGB data area is filled with RGB data only.
* @e_no_data_lane: specifies data lane count to be used by Master.
* @e_byte_clk: select byte clock source. (it must be DSIM_PLL_OUT_DIV8)
* DSIM_EXT_CLK_DIV8 and DSIM_EXT_CLK_BYPASSS are not supported.
* @pll_stable_time: specifies the PLL Timer for stability of the ganerated
* clock(System clock cycle base)
* if the timer value goes to 0x00000000, the clock stable bit of status
* and interrupt register is set.
* @esc_clk: specifies escape clock frequency for getting the escape clock
* prescaler value.
* @stop_holding_cnt: specifies the interval value between transmitting
* read packet(or write "set_tear_on" command) and BTA request.
* after transmitting read packet or write "set_tear_on" command,
* BTA requests to D-PHY automatically. this counter value specifies
* the interval between them.
* @bta_timeout: specifies the timer for BTA.
* this register specifies time out from BTA request to change
* the direction with respect to Tx escape clock.
* @rx_timeout: specifies the timer for LP Rx mode timeout.
* this register specifies time out on how long RxValid deasserts,
* after RxLpdt asserts with respect to Tx escape clock.
* - RxValid specifies Rx data valid indicator.
* - RxLpdt specifies an indicator that D-PHY is under RxLpdt mode.
* - RxValid and RxLpdt specifies signal from D-PHY.
*/
struct mipi_dsim_config {
unsigned char auto_flush;
unsigned char eot_disable;
unsigned char auto_vertical_cnt;
unsigned char hse;
unsigned char hfp;
unsigned char hbp;
unsigned char hsa;
unsigned char cmd_allow;
enum mipi_dsim_interface_type e_interface;
enum mipi_dsim_virtual_ch_no e_virtual_ch;
enum mipi_dsim_pixel_format e_pixel_format;
enum mipi_dsim_burst_mode_type e_burst_mode;
enum mipi_dsim_no_of_data_lane e_no_data_lane;
enum mipi_dsim_byte_clk_src e_byte_clk;
/*
* ===========================================
* | P | M | S | MHz |
* -------------------------------------------
* | 3 | 100 | 3 | 100 |
* | 3 | 100 | 2 | 200 |
* | 3 | 63 | 1 | 252 |
* | 4 | 100 | 1 | 300 |
* | 4 | 110 | 1 | 330 |
* | 12 | 350 | 1 | 350 |
* | 3 | 100 | 1 | 400 |
* | 4 | 150 | 1 | 450 |
* | 6 | 118 | 1 | 472 |
* | 3 | 120 | 1 | 480 |
* | 12 | 250 | 0 | 500 |
* | 4 | 100 | 0 | 600 |
* | 3 | 81 | 0 | 648 |
* | 3 | 88 | 0 | 704 |
* | 3 | 90 | 0 | 720 |
* | 3 | 100 | 0 | 800 |
* | 12 | 425 | 0 | 850 |
* | 4 | 150 | 0 | 900 |
* | 12 | 475 | 0 | 950 |
* | 6 | 250 | 0 | 1000 |
* -------------------------------------------
*/
/*
* pms could be calculated as the following.
* M * 24 / P * 2 ^ S = MHz
*/
unsigned char p;
unsigned short m;
unsigned char s;
unsigned int pll_stable_time;
unsigned long esc_clk;
unsigned short stop_holding_cnt;
unsigned char bta_timeout;
unsigned short rx_timeout;
};
/*
* struct mipi_dsim_device - global interface for mipi-dsi driver.
*
* @dev: driver model representation of the device.
* @id: unique device id.
* @clock: pointer to MIPI-DSI clock of clock framework.
* @irq: interrupt number to MIPI-DSI controller.
* @reg_base: base address to memory mapped SRF of MIPI-DSI controller.
* (virtual address)
* @lock: the mutex protecting this data structure.
* @dsim_info: infomation for configuring mipi-dsi controller.
* @master_ops: callbacks to mipi-dsi operations.
* @dsim_lcd_dev: pointer to activated ddi device.
* (it would be registered by mipi-dsi driver.)
* @dsim_lcd_drv: pointer to activated_ddi driver.
* (it would be registered by mipi-dsi driver.)
* @lcd_info: pointer to mipi_lcd_info structure.
* @state: specifies status of MIPI-DSI controller.
* the status could be RESET, INIT, STOP, HSCLKEN and ULPS.
* @data_lane: specifiec enabled data lane number.
* this variable would be set by driver according to e_no_data_lane
* automatically.
* @e_clk_src: select byte clock source.
* @pd: pointer to MIPI-DSI driver platform data.
* @phy: pointer to the MIPI-DSI PHY
*/
struct mipi_dsim_device {
struct device *dev;
int id;
struct clk *clock;
unsigned int irq;
void __iomem *reg_base;
struct mutex lock;
struct mipi_dsim_config *dsim_config;
struct mipi_dsim_master_ops *master_ops;
struct mipi_dsim_lcd_device *dsim_lcd_dev;
struct mipi_dsim_lcd_driver *dsim_lcd_drv;
unsigned int state;
unsigned int data_lane;
unsigned int e_clk_src;
bool suspended;
struct mipi_dsim_platform_data *pd;
struct phy *phy;
};
/*
* struct mipi_dsim_platform_data - interface to platform data
* for mipi-dsi driver.
*
* @lcd_panel_name: specifies lcd panel name registered to mipi-dsi driver.
* lcd panel driver searched would be actived.
* @dsim_config: pointer of structure for configuring mipi-dsi controller.
* @enabled: indicate whether mipi controller got enabled or not.
* @lcd_panel_info: pointer for lcd panel specific structure.
* this structure specifies width, height, timing and polarity and so on.
*/
struct mipi_dsim_platform_data {
char lcd_panel_name[PANEL_NAME_SIZE];
struct mipi_dsim_config *dsim_config;
unsigned int enabled;
void *lcd_panel_info;
};
/*
* struct mipi_dsim_master_ops - callbacks to mipi-dsi operations.
*
* @cmd_write: transfer command to lcd panel at LP mode.
* @cmd_read: read command from rx register.
* @get_dsim_frame_done: get the status that all screen data have been
* transferred to mipi-dsi.
* @clear_dsim_frame_done: clear frame done status.
* @get_fb_frame_done: get frame done status of display controller.
* @trigger: trigger display controller.
* - this one would be used only in case of CPU mode.
* @set_early_blank_mode: set framebuffer blank mode.
* - this callback should be called prior to fb_blank() by a client driver
* only if needing.
* @set_blank_mode: set framebuffer blank mode.
* - this callback should be called after fb_blank() by a client driver
* only if needing.
*/
struct mipi_dsim_master_ops {
int (*cmd_write)(struct mipi_dsim_device *dsim, unsigned int data_id,
const unsigned char *data0, unsigned int data1);
int (*cmd_read)(struct mipi_dsim_device *dsim, unsigned int data_id,
unsigned int data0, unsigned int req_size, u8 *rx_buf);
int (*get_dsim_frame_done)(struct mipi_dsim_device *dsim);
int (*clear_dsim_frame_done)(struct mipi_dsim_device *dsim);
int (*get_fb_frame_done)(struct fb_info *info);
void (*trigger)(struct fb_info *info);
int (*set_early_blank_mode)(struct mipi_dsim_device *dsim, int power);
int (*set_blank_mode)(struct mipi_dsim_device *dsim, int power);
};
/*
* device structure for mipi-dsi based lcd panel.
*
* @name: name of the device to use with this device, or an
* alias for that name.
* @dev: driver model representation of the device.
* @id: id of device to be registered.
* @bus_id: bus id for identifing connected bus
* and this bus id should be same as id of mipi_dsim_device.
* @irq: irq number for signaling when framebuffer transfer of
* lcd panel module is completed.
* this irq would be used only for MIPI-DSI based CPU mode lcd panel.
* @master: pointer to mipi-dsi master device object.
* @platform_data: lcd panel specific platform data.
*/
struct mipi_dsim_lcd_device {
char *name;
struct device dev;
int id;
int bus_id;
int irq;
int panel_reverse;
struct mipi_dsim_device *master;
void *platform_data;
};
/*
* driver structure for mipi-dsi based lcd panel.
*
* this structure should be registered by lcd panel driver.
* mipi-dsi driver seeks lcd panel registered through name field
* and calls these callback functions in appropriate time.
*
* @name: name of the driver to use with this device, or an
* alias for that name.
* @id: id of driver to be registered.
* this id would be used for finding device object registered.
*/
struct mipi_dsim_lcd_driver {
char *name;
int id;
void (*power_on)(struct mipi_dsim_lcd_device *dsim_dev, int enable);
void (*set_sequence)(struct mipi_dsim_lcd_device *dsim_dev);
int (*probe)(struct mipi_dsim_lcd_device *dsim_dev);
int (*remove)(struct mipi_dsim_lcd_device *dsim_dev);
void (*shutdown)(struct mipi_dsim_lcd_device *dsim_dev);
int (*suspend)(struct mipi_dsim_lcd_device *dsim_dev);
int (*resume)(struct mipi_dsim_lcd_device *dsim_dev);
};
/*
* register mipi_dsim_lcd_device to mipi-dsi master.
*/
int exynos_mipi_dsi_register_lcd_device(struct mipi_dsim_lcd_device
*lcd_dev);
/**
* register mipi_dsim_lcd_driver object defined by lcd panel driver
* to mipi-dsi driver.
*/
int exynos_mipi_dsi_register_lcd_driver(struct mipi_dsim_lcd_driver
*lcd_drv);
#endif /* _EXYNOS_MIPI_DSIM_H */

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/*
* include/video/gbe.h -- SGI GBE (Graphics Back End)
*
* Copyright (C) 1999 Silicon Graphics, Inc. (Jeffrey Newquist)
*
* This file is subject to the terms and conditions of the GNU General Public
* License version 2 as published by the Free Software Foundation.
*/
#ifndef __GBE_H__
#define __GBE_H__
struct sgi_gbe {
volatile uint32_t ctrlstat; /* general control */
volatile uint32_t dotclock; /* dot clock PLL control */
volatile uint32_t i2c; /* crt I2C control */
volatile uint32_t sysclk; /* system clock PLL control */
volatile uint32_t i2cfp; /* flat panel I2C control */
volatile uint32_t id; /* device id/chip revision */
volatile uint32_t config; /* power on configuration [1] */
volatile uint32_t bist; /* internal bist status [1] */
uint32_t _pad0[0x010000/4 - 8];
volatile uint32_t vt_xy; /* current dot coords */
volatile uint32_t vt_xymax; /* maximum dot coords */
volatile uint32_t vt_vsync; /* vsync on/off */
volatile uint32_t vt_hsync; /* hsync on/off */
volatile uint32_t vt_vblank; /* vblank on/off */
volatile uint32_t vt_hblank; /* hblank on/off */
volatile uint32_t vt_flags; /* polarity of vt signals */
volatile uint32_t vt_f2rf_lock; /* f2rf & framelck y coord */
volatile uint32_t vt_intr01; /* intr 0,1 y coords */
volatile uint32_t vt_intr23; /* intr 2,3 y coords */
volatile uint32_t fp_hdrv; /* flat panel hdrv on/off */
volatile uint32_t fp_vdrv; /* flat panel vdrv on/off */
volatile uint32_t fp_de; /* flat panel de on/off */
volatile uint32_t vt_hpixen; /* intrnl horiz pixel on/off */
volatile uint32_t vt_vpixen; /* intrnl vert pixel on/off */
volatile uint32_t vt_hcmap; /* cmap write (horiz) */
volatile uint32_t vt_vcmap; /* cmap write (vert) */
volatile uint32_t did_start_xy; /* eol/f did/xy reset val */
volatile uint32_t crs_start_xy; /* eol/f crs/xy reset val */
volatile uint32_t vc_start_xy; /* eol/f vc/xy reset val */
uint32_t _pad1[0xffb0/4];
volatile uint32_t ovr_width_tile;/*overlay plane ctrl 0 */
volatile uint32_t ovr_inhwctrl; /* overlay plane ctrl 1 */
volatile uint32_t ovr_control; /* overlay plane ctrl 1 */
uint32_t _pad2[0xfff4/4];
volatile uint32_t frm_size_tile;/* normal plane ctrl 0 */
volatile uint32_t frm_size_pixel;/*normal plane ctrl 1 */
volatile uint32_t frm_inhwctrl; /* normal plane ctrl 2 */
volatile uint32_t frm_control; /* normal plane ctrl 3 */
uint32_t _pad3[0xfff0/4];
volatile uint32_t did_inhwctrl; /* DID control */
volatile uint32_t did_control; /* DID shadow */
uint32_t _pad4[0x7ff8/4];
volatile uint32_t mode_regs[32];/* WID table */
uint32_t _pad5[0x7f80/4];
volatile uint32_t cmap[6144]; /* color map */
uint32_t _pad6[0x2000/4];
volatile uint32_t cm_fifo; /* color map fifo status */
uint32_t _pad7[0x7ffc/4];
volatile uint32_t gmap[256]; /* gamma map */
uint32_t _pad8[0x7c00/4];
volatile uint32_t gmap10[1024]; /* gamma map */
uint32_t _pad9[0x7000/4];
volatile uint32_t crs_pos; /* cusror control 0 */
volatile uint32_t crs_ctl; /* cusror control 1 */
volatile uint32_t crs_cmap[3]; /* crs cmap */
uint32_t _pad10[0x7fec/4];
volatile uint32_t crs_glyph[64];/* crs glyph */
uint32_t _pad11[0x7f00/4];
volatile uint32_t vc_0; /* video capture crtl 0 */
volatile uint32_t vc_1; /* video capture crtl 1 */
volatile uint32_t vc_2; /* video capture crtl 2 */
volatile uint32_t vc_3; /* video capture crtl 3 */
volatile uint32_t vc_4; /* video capture crtl 4 */
volatile uint32_t vc_5; /* video capture crtl 5 */
volatile uint32_t vc_6; /* video capture crtl 6 */
volatile uint32_t vc_7; /* video capture crtl 7 */
volatile uint32_t vc_8; /* video capture crtl 8 */
};
#define MASK(msb, lsb) \
( (((u32)1<<((msb)-(lsb)+1))-1) << (lsb) )
#define GET(v, msb, lsb) \
( ((u32)(v) & MASK(msb,lsb)) >> (lsb) )
#define SET(v, f, msb, lsb) \
( (v) = ((v)&~MASK(msb,lsb)) | (( (u32)(f)<<(lsb) ) & MASK(msb,lsb)) )
#define GET_GBE_FIELD(reg, field, v) \
GET((v), GBE_##reg##_##field##_MSB, GBE_##reg##_##field##_LSB)
#define SET_GBE_FIELD(reg, field, v, f) \
SET((v), (f), GBE_##reg##_##field##_MSB, GBE_##reg##_##field##_LSB)
/*
* Bit mask information
*/
#define GBE_CTRLSTAT_CHIPID_MSB 3
#define GBE_CTRLSTAT_CHIPID_LSB 0
#define GBE_CTRLSTAT_SENSE_N_MSB 4
#define GBE_CTRLSTAT_SENSE_N_LSB 4
#define GBE_CTRLSTAT_PCLKSEL_MSB 29
#define GBE_CTRLSTAT_PCLKSEL_LSB 28
#define GBE_DOTCLK_M_MSB 7
#define GBE_DOTCLK_M_LSB 0
#define GBE_DOTCLK_N_MSB 13
#define GBE_DOTCLK_N_LSB 8
#define GBE_DOTCLK_P_MSB 15
#define GBE_DOTCLK_P_LSB 14
#define GBE_DOTCLK_RUN_MSB 20
#define GBE_DOTCLK_RUN_LSB 20
#define GBE_VT_XY_Y_MSB 23
#define GBE_VT_XY_Y_LSB 12
#define GBE_VT_XY_X_MSB 11
#define GBE_VT_XY_X_LSB 0
#define GBE_VT_XY_FREEZE_MSB 31
#define GBE_VT_XY_FREEZE_LSB 31
#define GBE_FP_VDRV_ON_MSB 23
#define GBE_FP_VDRV_ON_LSB 12
#define GBE_FP_VDRV_OFF_MSB 11
#define GBE_FP_VDRV_OFF_LSB 0
#define GBE_FP_HDRV_ON_MSB 23
#define GBE_FP_HDRV_ON_LSB 12
#define GBE_FP_HDRV_OFF_MSB 11
#define GBE_FP_HDRV_OFF_LSB 0
#define GBE_FP_DE_ON_MSB 23
#define GBE_FP_DE_ON_LSB 12
#define GBE_FP_DE_OFF_MSB 11
#define GBE_FP_DE_OFF_LSB 0
#define GBE_VT_VSYNC_VSYNC_ON_MSB 23
#define GBE_VT_VSYNC_VSYNC_ON_LSB 12
#define GBE_VT_VSYNC_VSYNC_OFF_MSB 11
#define GBE_VT_VSYNC_VSYNC_OFF_LSB 0
#define GBE_VT_HSYNC_HSYNC_ON_MSB 23
#define GBE_VT_HSYNC_HSYNC_ON_LSB 12
#define GBE_VT_HSYNC_HSYNC_OFF_MSB 11
#define GBE_VT_HSYNC_HSYNC_OFF_LSB 0
#define GBE_VT_VBLANK_VBLANK_ON_MSB 23
#define GBE_VT_VBLANK_VBLANK_ON_LSB 12
#define GBE_VT_VBLANK_VBLANK_OFF_MSB 11
#define GBE_VT_VBLANK_VBLANK_OFF_LSB 0
#define GBE_VT_HBLANK_HBLANK_ON_MSB 23
#define GBE_VT_HBLANK_HBLANK_ON_LSB 12
#define GBE_VT_HBLANK_HBLANK_OFF_MSB 11
#define GBE_VT_HBLANK_HBLANK_OFF_LSB 0
#define GBE_VT_FLAGS_F2RF_HIGH_MSB 6
#define GBE_VT_FLAGS_F2RF_HIGH_LSB 6
#define GBE_VT_FLAGS_SYNC_LOW_MSB 5
#define GBE_VT_FLAGS_SYNC_LOW_LSB 5
#define GBE_VT_FLAGS_SYNC_HIGH_MSB 4
#define GBE_VT_FLAGS_SYNC_HIGH_LSB 4
#define GBE_VT_FLAGS_HDRV_LOW_MSB 3
#define GBE_VT_FLAGS_HDRV_LOW_LSB 3
#define GBE_VT_FLAGS_HDRV_INVERT_MSB 2
#define GBE_VT_FLAGS_HDRV_INVERT_LSB 2
#define GBE_VT_FLAGS_VDRV_LOW_MSB 1
#define GBE_VT_FLAGS_VDRV_LOW_LSB 1
#define GBE_VT_FLAGS_VDRV_INVERT_MSB 0
#define GBE_VT_FLAGS_VDRV_INVERT_LSB 0
#define GBE_VT_VCMAP_VCMAP_ON_MSB 23
#define GBE_VT_VCMAP_VCMAP_ON_LSB 12
#define GBE_VT_VCMAP_VCMAP_OFF_MSB 11
#define GBE_VT_VCMAP_VCMAP_OFF_LSB 0
#define GBE_VT_HCMAP_HCMAP_ON_MSB 23
#define GBE_VT_HCMAP_HCMAP_ON_LSB 12
#define GBE_VT_HCMAP_HCMAP_OFF_MSB 11
#define GBE_VT_HCMAP_HCMAP_OFF_LSB 0
#define GBE_VT_XYMAX_MAXX_MSB 11
#define GBE_VT_XYMAX_MAXX_LSB 0
#define GBE_VT_XYMAX_MAXY_MSB 23
#define GBE_VT_XYMAX_MAXY_LSB 12
#define GBE_VT_HPIXEN_HPIXEN_ON_MSB 23
#define GBE_VT_HPIXEN_HPIXEN_ON_LSB 12
#define GBE_VT_HPIXEN_HPIXEN_OFF_MSB 11
#define GBE_VT_HPIXEN_HPIXEN_OFF_LSB 0
#define GBE_VT_VPIXEN_VPIXEN_ON_MSB 23
#define GBE_VT_VPIXEN_VPIXEN_ON_LSB 12
#define GBE_VT_VPIXEN_VPIXEN_OFF_MSB 11
#define GBE_VT_VPIXEN_VPIXEN_OFF_LSB 0
#define GBE_OVR_CONTROL_OVR_DMA_ENABLE_MSB 0
#define GBE_OVR_CONTROL_OVR_DMA_ENABLE_LSB 0
#define GBE_OVR_INHWCTRL_OVR_DMA_ENABLE_MSB 0
#define GBE_OVR_INHWCTRL_OVR_DMA_ENABLE_LSB 0
#define GBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_MSB 13
#define GBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_LSB 13
#define GBE_FRM_CONTROL_FRM_DMA_ENABLE_MSB 0
#define GBE_FRM_CONTROL_FRM_DMA_ENABLE_LSB 0
#define GBE_FRM_CONTROL_FRM_TILE_PTR_MSB 31
#define GBE_FRM_CONTROL_FRM_TILE_PTR_LSB 9
#define GBE_FRM_CONTROL_FRM_LINEAR_MSB 1
#define GBE_FRM_CONTROL_FRM_LINEAR_LSB 1
#define GBE_FRM_INHWCTRL_FRM_DMA_ENABLE_MSB 0
#define GBE_FRM_INHWCTRL_FRM_DMA_ENABLE_LSB 0
#define GBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_MSB 12
#define GBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_LSB 5
#define GBE_FRM_SIZE_TILE_FRM_RHS_MSB 4
#define GBE_FRM_SIZE_TILE_FRM_RHS_LSB 0
#define GBE_FRM_SIZE_TILE_FRM_DEPTH_MSB 14
#define GBE_FRM_SIZE_TILE_FRM_DEPTH_LSB 13
#define GBE_FRM_SIZE_TILE_FRM_FIFO_RESET_MSB 15
#define GBE_FRM_SIZE_TILE_FRM_FIFO_RESET_LSB 15
#define GBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_MSB 31
#define GBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_LSB 16
#define GBE_DID_CONTROL_DID_DMA_ENABLE_MSB 0
#define GBE_DID_CONTROL_DID_DMA_ENABLE_LSB 0
#define GBE_DID_INHWCTRL_DID_DMA_ENABLE_MSB 0
#define GBE_DID_INHWCTRL_DID_DMA_ENABLE_LSB 0
#define GBE_DID_START_XY_DID_STARTY_MSB 23
#define GBE_DID_START_XY_DID_STARTY_LSB 12
#define GBE_DID_START_XY_DID_STARTX_MSB 11
#define GBE_DID_START_XY_DID_STARTX_LSB 0
#define GBE_CRS_START_XY_CRS_STARTY_MSB 23
#define GBE_CRS_START_XY_CRS_STARTY_LSB 12
#define GBE_CRS_START_XY_CRS_STARTX_MSB 11
#define GBE_CRS_START_XY_CRS_STARTX_LSB 0
#define GBE_WID_AUX_MSB 12
#define GBE_WID_AUX_LSB 11
#define GBE_WID_GAMMA_MSB 10
#define GBE_WID_GAMMA_LSB 10
#define GBE_WID_CM_MSB 9
#define GBE_WID_CM_LSB 5
#define GBE_WID_TYP_MSB 4
#define GBE_WID_TYP_LSB 2
#define GBE_WID_BUF_MSB 1
#define GBE_WID_BUF_LSB 0
#define GBE_VC_START_XY_VC_STARTY_MSB 23
#define GBE_VC_START_XY_VC_STARTY_LSB 12
#define GBE_VC_START_XY_VC_STARTX_MSB 11
#define GBE_VC_START_XY_VC_STARTX_LSB 0
/* Constants */
#define GBE_FRM_DEPTH_8 0
#define GBE_FRM_DEPTH_16 1
#define GBE_FRM_DEPTH_32 2
#define GBE_CMODE_I8 0
#define GBE_CMODE_I12 1
#define GBE_CMODE_RG3B2 2
#define GBE_CMODE_RGB4 3
#define GBE_CMODE_ARGB5 4
#define GBE_CMODE_RGB8 5
#define GBE_CMODE_RGBA5 6
#define GBE_CMODE_RGB10 7
#define GBE_BMODE_BOTH 3
#define GBE_CRS_MAGIC 54
#define GBE_PIXEN_MAGIC_ON 19
#define GBE_PIXEN_MAGIC_OFF 2
#define GBE_TLB_SIZE 128
/* [1] - only GBE revision 2 and later */
/*
* Video Timing Data Structure
*/
struct gbe_timing_info {
int flags;
short width; /* Monitor resolution */
short height;
int fields_sec; /* fields/sec (Hz -3 dec. places */
int cfreq; /* pixel clock frequency (MHz -3 dec. places) */
short htotal; /* Horizontal total pixels */
short hblank_start; /* Horizontal blank start */
short hblank_end; /* Horizontal blank end */
short hsync_start; /* Horizontal sync start */
short hsync_end; /* Horizontal sync end */
short vtotal; /* Vertical total lines */
short vblank_start; /* Vertical blank start */
short vblank_end; /* Vertical blank end */
short vsync_start; /* Vertical sync start */
short vsync_end; /* Vertical sync end */
short pll_m; /* PLL M parameter */
short pll_n; /* PLL P parameter */
short pll_p; /* PLL N parameter */
};
/* Defines for gbe_vof_info_t flags */
#define GBE_VOF_UNKNOWNMON 1
#define GBE_VOF_STEREO 2
#define GBE_VOF_DO_GENSYNC 4 /* enable incoming sync */
#define GBE_VOF_SYNC_ON_GREEN 8 /* sync on green */
#define GBE_VOF_FLATPANEL 0x1000 /* FLATPANEL Timing */
#define GBE_VOF_MAGICKEY 0x2000 /* Backdoor key */
#endif /* ! __GBE_H__ */

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/*
* hecubafb.h - definitions for the hecuba framebuffer driver
*
* Copyright (C) 2008 by Jaya Kumar
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
*/
#ifndef _LINUX_HECUBAFB_H_
#define _LINUX_HECUBAFB_H_
/* Apollo controller specific defines */
#define APOLLO_START_NEW_IMG 0xA0
#define APOLLO_STOP_IMG_DATA 0xA1
#define APOLLO_DISPLAY_IMG 0xA2
#define APOLLO_ERASE_DISPLAY 0xA3
#define APOLLO_INIT_DISPLAY 0xA4
/* Hecuba interface specific defines */
#define HCB_WUP_BIT 0x01
#define HCB_DS_BIT 0x02
#define HCB_RW_BIT 0x04
#define HCB_CD_BIT 0x08
#define HCB_ACK_BIT 0x80
/* struct used by hecuba. board specific stuff comes from *board */
struct hecubafb_par {
struct fb_info *info;
struct hecuba_board *board;
void (*send_command)(struct hecubafb_par *, unsigned char);
void (*send_data)(struct hecubafb_par *, unsigned char);
};
/* board specific routines
board drivers can implement wait_for_ack with interrupts if desired. if
wait_for_ack is called with clear=0, then go to sleep and return when ack
goes hi or if wait_for_ack with clear=1, then return when ack goes lo */
struct hecuba_board {
struct module *owner;
void (*remove)(struct hecubafb_par *);
void (*set_ctl)(struct hecubafb_par *, unsigned char, unsigned char);
void (*set_data)(struct hecubafb_par *, unsigned char);
void (*wait_for_ack)(struct hecubafb_par *, int);
int (*init)(struct hecubafb_par *);
};
#endif

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/* $Id: iga.h,v 1.2 1999/09/11 22:56:31 zaitcev Exp $
* iga1682.h: Sparc/PCI iga1682 driver constants etc.
*
* Copyleft 1998 V. Roganov and G. Raiko
*/
#ifndef _IGA1682_H
#define _IGA1682_H 1
#define IGA_ATTR_CTL 0x3C0
#define IGA_IDX_VGA_OVERSCAN 0x11
#define DAC_W_INDEX 0x03C8
#define DAC_DATA 0x03C9
#define IGA_EXT_CNTRL 0x3CE
#define IGA_IDX_EXT_BUS_CNTL 0x30
#define MEM_SIZE_ALIAS 0x3
#define MEM_SIZE_1M 0x0
#define MEM_SIZE_2M 0x1
#define MEM_SIZE_4M 0x2
#define MEM_SIZE_RESERVED 0x3
#define IGA_IDX_OVERSCAN_COLOR 0x58
#define IGA_IDX_EXT_MEM_2 0x72
#endif /* !(_IGA1682_H) */

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/* include/video/ili9320.c
*
* ILI9320 LCD controller configuration control.
*
* Copyright 2007 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* http://armlinux.simtec.co.uk/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define ILI9320_REG(x) (x)
#define ILI9320_INDEX ILI9320_REG(0x00)
#define ILI9320_OSCILATION ILI9320_REG(0x00)
#define ILI9320_DRIVER ILI9320_REG(0x01)
#define ILI9320_DRIVEWAVE ILI9320_REG(0x02)
#define ILI9320_ENTRYMODE ILI9320_REG(0x03)
#define ILI9320_RESIZING ILI9320_REG(0x04)
#define ILI9320_DISPLAY1 ILI9320_REG(0x07)
#define ILI9320_DISPLAY2 ILI9320_REG(0x08)
#define ILI9320_DISPLAY3 ILI9320_REG(0x09)
#define ILI9320_DISPLAY4 ILI9320_REG(0x0A)
#define ILI9320_RGB_IF1 ILI9320_REG(0x0C)
#define ILI9320_FRAMEMAKER ILI9320_REG(0x0D)
#define ILI9320_RGB_IF2 ILI9320_REG(0x0F)
#define ILI9320_POWER1 ILI9320_REG(0x10)
#define ILI9320_POWER2 ILI9320_REG(0x11)
#define ILI9320_POWER3 ILI9320_REG(0x12)
#define ILI9320_POWER4 ILI9320_REG(0x13)
#define ILI9320_GRAM_HORIZ_ADDR ILI9320_REG(0x20)
#define ILI9320_GRAM_VERT_ADD ILI9320_REG(0x21)
#define ILI9320_POWER7 ILI9320_REG(0x29)
#define ILI9320_FRAME_RATE_COLOUR ILI9320_REG(0x2B)
#define ILI9320_GAMMA1 ILI9320_REG(0x30)
#define ILI9320_GAMMA2 ILI9320_REG(0x31)
#define ILI9320_GAMMA3 ILI9320_REG(0x32)
#define ILI9320_GAMMA4 ILI9320_REG(0x35)
#define ILI9320_GAMMA5 ILI9320_REG(0x36)
#define ILI9320_GAMMA6 ILI9320_REG(0x37)
#define ILI9320_GAMMA7 ILI9320_REG(0x38)
#define ILI9320_GAMMA8 ILI9320_REG(0x39)
#define ILI9320_GAMMA9 ILI9320_REG(0x3C)
#define ILI9320_GAMMA10 ILI9320_REG(0x3D)
#define ILI9320_HORIZ_START ILI9320_REG(0x50)
#define ILI9320_HORIZ_END ILI9320_REG(0x51)
#define ILI9320_VERT_START ILI9320_REG(0x52)
#define ILI9320_VERT_END ILI9320_REG(0x53)
#define ILI9320_DRIVER2 ILI9320_REG(0x60)
#define ILI9320_BASE_IMAGE ILI9320_REG(0x61)
#define ILI9320_VERT_SCROLL ILI9320_REG(0x6a)
#define ILI9320_PARTIAL1_POSITION ILI9320_REG(0x80)
#define ILI9320_PARTIAL1_START ILI9320_REG(0x81)
#define ILI9320_PARTIAL1_END ILI9320_REG(0x82)
#define ILI9320_PARTIAL2_POSITION ILI9320_REG(0x83)
#define ILI9320_PARTIAL2_START ILI9320_REG(0x84)
#define ILI9320_PARTIAL2_END ILI9320_REG(0x85)
#define ILI9320_INTERFACE1 ILI9320_REG(0x90)
#define ILI9320_INTERFACE2 ILI9320_REG(0x92)
#define ILI9320_INTERFACE3 ILI9320_REG(0x93)
#define ILI9320_INTERFACE4 ILI9320_REG(0x95)
#define ILI9320_INTERFACE5 ILI9320_REG(0x97)
#define ILI9320_INTERFACE6 ILI9320_REG(0x98)
/* Register contents definitions. */
#define ILI9320_OSCILATION_OSC (1 << 0)
#define ILI9320_DRIVER_SS (1 << 8)
#define ILI9320_DRIVER_SM (1 << 10)
#define ILI9320_DRIVEWAVE_EOR (1 << 8)
#define ILI9320_DRIVEWAVE_BC (1 << 9)
#define ILI9320_DRIVEWAVE_MUSTSET (1 << 10)
#define ILI9320_ENTRYMODE_AM (1 << 3)
#define ILI9320_ENTRYMODE_ID(x) ((x) << 4)
#define ILI9320_ENTRYMODE_ORG (1 << 7)
#define ILI9320_ENTRYMODE_HWM (1 << 8)
#define ILI9320_ENTRYMODE_BGR (1 << 12)
#define ILI9320_ENTRYMODE_DFM (1 << 14)
#define ILI9320_ENTRYMODE_TRI (1 << 15)
#define ILI9320_RESIZING_RSZ(x) ((x) << 0)
#define ILI9320_RESIZING_RCH(x) ((x) << 4)
#define ILI9320_RESIZING_RCV(x) ((x) << 8)
#define ILI9320_DISPLAY1_D(x) ((x) << 0)
#define ILI9320_DISPLAY1_CL (1 << 3)
#define ILI9320_DISPLAY1_DTE (1 << 4)
#define ILI9320_DISPLAY1_GON (1 << 5)
#define ILI9320_DISPLAY1_BASEE (1 << 8)
#define ILI9320_DISPLAY1_PTDE(x) ((x) << 12)
#define ILI9320_DISPLAY2_BP(x) ((x) << 0)
#define ILI9320_DISPLAY2_FP(x) ((x) << 8)
#define ILI9320_RGBIF1_RIM_RGB18 (0 << 0)
#define ILI9320_RGBIF1_RIM_RGB16 (1 << 0)
#define ILI9320_RGBIF1_RIM_RGB6 (2 << 0)
#define ILI9320_RGBIF1_CLK_INT (0 << 4)
#define ILI9320_RGBIF1_CLK_RGBIF (1 << 4)
#define ILI9320_RGBIF1_CLK_VSYNC (2 << 4)
#define ILI9320_RGBIF1_RM (1 << 8)
#define ILI9320_RGBIF1_ENC_FRAMES(x) (((x) - 1)<< 13)
#define ILI9320_RGBIF2_DPL (1 << 0)
#define ILI9320_RGBIF2_EPL (1 << 1)
#define ILI9320_RGBIF2_HSPL (1 << 3)
#define ILI9320_RGBIF2_VSPL (1 << 4)
#define ILI9320_POWER1_SLP (1 << 1)
#define ILI9320_POWER1_DSTB (1 << 2)
#define ILI9320_POWER1_AP(x) ((x) << 4)
#define ILI9320_POWER1_APE (1 << 7)
#define ILI9320_POWER1_BT(x) ((x) << 8)
#define ILI9320_POWER1_SAP (1 << 12)
#define ILI9320_POWER2_VC(x) ((x) << 0)
#define ILI9320_POWER2_DC0(x) ((x) << 4)
#define ILI9320_POWER2_DC1(x) ((x) << 8)
#define ILI9320_POWER3_VRH(x) ((x) << 0)
#define ILI9320_POWER3_PON (1 << 4)
#define ILI9320_POWER3_VCMR (1 << 8)
#define ILI9320_POWER4_VREOUT(x) ((x) << 8)
#define ILI9320_DRIVER2_SCNL(x) ((x) << 0)
#define ILI9320_DRIVER2_NL(x) ((x) << 8)
#define ILI9320_DRIVER2_GS (1 << 15)
#define ILI9320_BASEIMAGE_REV (1 << 0)
#define ILI9320_BASEIMAGE_VLE (1 << 1)
#define ILI9320_BASEIMAGE_NDL (1 << 2)
#define ILI9320_INTERFACE4_RTNE(x) (x)
#define ILI9320_INTERFACE4_DIVE(x) ((x) << 8)
/* SPI interface definitions */
#define ILI9320_SPI_IDCODE (0x70)
#define ILI9320_SPI_ID(x) ((x) << 2)
#define ILI9320_SPI_READ (0x01)
#define ILI9320_SPI_WRITE (0x00)
#define ILI9320_SPI_DATA (0x02)
#define ILI9320_SPI_INDEX (0x00)
/* platform data to pass configuration from lcd */
enum ili9320_suspend {
ILI9320_SUSPEND_OFF,
ILI9320_SUSPEND_DEEP,
};
struct ili9320_platdata {
unsigned short hsize;
unsigned short vsize;
enum ili9320_suspend suspend;
/* set the reset line, 0 = reset asserted, 1 = normal */
void (*reset)(unsigned int val);
unsigned short entry_mode;
unsigned short display2;
unsigned short display3;
unsigned short display4;
unsigned short rgb_if1;
unsigned short rgb_if2;
unsigned short interface2;
unsigned short interface3;
unsigned short interface4;
unsigned short interface5;
unsigned short interface6;
};

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/*
* Copyright 2005-2009 Freescale Semiconductor, Inc.
*
* The code contained herein is licensed under the GNU Lesser General
* Public License. You may obtain a copy of the GNU Lesser General
* Public License Version 2.1 or later at the following locations:
*
* http://www.opensource.org/licenses/lgpl-license.html
* http://www.gnu.org/copyleft/lgpl.html
*/
#ifndef __DRM_IPU_H__
#define __DRM_IPU_H__
#include <linux/types.h>
#include <linux/videodev2.h>
#include <linux/bitmap.h>
#include <linux/fb.h>
#include <media/v4l2-mediabus.h>
struct ipu_soc;
enum ipuv3_type {
IPUV3EX,
IPUV3M,
IPUV3H,
};
#define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
/*
* Bitfield of Display Interface signal polarities.
*/
struct ipu_di_signal_cfg {
unsigned datamask_en:1;
unsigned interlaced:1;
unsigned odd_field_first:1;
unsigned clksel_en:1;
unsigned clkidle_en:1;
unsigned data_pol:1; /* true = inverted */
unsigned clk_pol:1; /* true = rising edge */
unsigned enable_pol:1;
unsigned Hsync_pol:1; /* true = active high */
unsigned Vsync_pol:1;
u16 width;
u16 height;
u32 pixel_fmt;
u16 h_start_width;
u16 h_sync_width;
u16 h_end_width;
u16 v_start_width;
u16 v_sync_width;
u16 v_end_width;
u32 v_to_h_sync;
unsigned long pixelclock;
#define IPU_DI_CLKMODE_SYNC (1 << 0)
#define IPU_DI_CLKMODE_EXT (1 << 1)
unsigned long clkflags;
u8 hsync_pin;
u8 vsync_pin;
};
/*
* Enumeration of CSI destinations
*/
enum ipu_csi_dest {
IPU_CSI_DEST_IDMAC, /* to memory via SMFC */
IPU_CSI_DEST_IC, /* to Image Converter */
IPU_CSI_DEST_VDIC, /* to VDIC */
};
/*
* Enumeration of IPU rotation modes
*/
enum ipu_rotate_mode {
IPU_ROTATE_NONE = 0,
IPU_ROTATE_VERT_FLIP,
IPU_ROTATE_HORIZ_FLIP,
IPU_ROTATE_180,
IPU_ROTATE_90_RIGHT,
IPU_ROTATE_90_RIGHT_VFLIP,
IPU_ROTATE_90_RIGHT_HFLIP,
IPU_ROTATE_90_LEFT,
};
enum ipu_color_space {
IPUV3_COLORSPACE_RGB,
IPUV3_COLORSPACE_YUV,
IPUV3_COLORSPACE_UNKNOWN,
};
struct ipuv3_channel;
enum ipu_channel_irq {
IPU_IRQ_EOF = 0,
IPU_IRQ_NFACK = 64,
IPU_IRQ_NFB4EOF = 128,
IPU_IRQ_EOS = 192,
};
/*
* Enumeration of IDMAC channels
*/
#define IPUV3_CHANNEL_CSI0 0
#define IPUV3_CHANNEL_CSI1 1
#define IPUV3_CHANNEL_CSI2 2
#define IPUV3_CHANNEL_CSI3 3
#define IPUV3_CHANNEL_VDI_MEM_IC_VF 5
#define IPUV3_CHANNEL_MEM_IC_PP 11
#define IPUV3_CHANNEL_MEM_IC_PRP_VF 12
#define IPUV3_CHANNEL_G_MEM_IC_PRP_VF 14
#define IPUV3_CHANNEL_G_MEM_IC_PP 15
#define IPUV3_CHANNEL_IC_PRP_ENC_MEM 20
#define IPUV3_CHANNEL_IC_PRP_VF_MEM 21
#define IPUV3_CHANNEL_IC_PP_MEM 22
#define IPUV3_CHANNEL_MEM_BG_SYNC 23
#define IPUV3_CHANNEL_MEM_BG_ASYNC 24
#define IPUV3_CHANNEL_MEM_FG_SYNC 27
#define IPUV3_CHANNEL_MEM_DC_SYNC 28
#define IPUV3_CHANNEL_MEM_FG_ASYNC 29
#define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA 31
#define IPUV3_CHANNEL_MEM_DC_ASYNC 41
#define IPUV3_CHANNEL_MEM_ROT_ENC 45
#define IPUV3_CHANNEL_MEM_ROT_VF 46
#define IPUV3_CHANNEL_MEM_ROT_PP 47
#define IPUV3_CHANNEL_ROT_ENC_MEM 48
#define IPUV3_CHANNEL_ROT_VF_MEM 49
#define IPUV3_CHANNEL_ROT_PP_MEM 50
#define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA 51
int ipu_map_irq(struct ipu_soc *ipu, int irq);
int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
enum ipu_channel_irq irq);
#define IPU_IRQ_DP_SF_START (448 + 2)
#define IPU_IRQ_DP_SF_END (448 + 3)
#define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END,
#define IPU_IRQ_DC_FC_0 (448 + 8)
#define IPU_IRQ_DC_FC_1 (448 + 9)
#define IPU_IRQ_DC_FC_2 (448 + 10)
#define IPU_IRQ_DC_FC_3 (448 + 11)
#define IPU_IRQ_DC_FC_4 (448 + 12)
#define IPU_IRQ_DC_FC_6 (448 + 13)
#define IPU_IRQ_VSYNC_PRE_0 (448 + 14)
#define IPU_IRQ_VSYNC_PRE_1 (448 + 15)
/*
* IPU Common functions
*/
void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2);
void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi);
void ipu_dump(struct ipu_soc *ipu);
/*
* IPU Image DMA Controller (idmac) functions
*/
struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
void ipu_idmac_put(struct ipuv3_channel *);
int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable);
int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts);
int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
bool doublebuffer);
int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num);
void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num);
/*
* IPU Channel Parameter Memory (cpmem) functions
*/
struct ipu_rgb {
struct fb_bitfield red;
struct fb_bitfield green;
struct fb_bitfield blue;
struct fb_bitfield transp;
int bits_per_pixel;
};
struct ipu_image {
struct v4l2_pix_format pix;
struct v4l2_rect rect;
dma_addr_t phys0;
dma_addr_t phys1;
};
void ipu_cpmem_zero(struct ipuv3_channel *ch);
void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch);
void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
enum ipu_rotate_mode rot);
int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
const struct ipu_rgb *rgb);
int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
u32 pixel_format, int stride,
int u_offset, int v_offset);
void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
u32 pixel_format, int stride, int height);
int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image);
void ipu_cpmem_dump(struct ipuv3_channel *ch);
/*
* IPU Display Controller (dc) functions
*/
struct ipu_dc;
struct ipu_di;
struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
void ipu_dc_put(struct ipu_dc *dc);
int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
u32 pixel_fmt, u32 width);
void ipu_dc_enable(struct ipu_soc *ipu);
void ipu_dc_enable_channel(struct ipu_dc *dc);
void ipu_dc_disable_channel(struct ipu_dc *dc);
void ipu_dc_disable(struct ipu_soc *ipu);
/*
* IPU Display Interface (di) functions
*/
struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
void ipu_di_put(struct ipu_di *);
int ipu_di_disable(struct ipu_di *);
int ipu_di_enable(struct ipu_di *);
int ipu_di_get_num(struct ipu_di *);
int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
/*
* IPU Display Multi FIFO Controller (dmfc) functions
*/
struct dmfc_channel;
int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
unsigned long bandwidth_mbs, int burstsize);
void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc);
int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width);
struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
void ipu_dmfc_put(struct dmfc_channel *dmfc);
/*
* IPU Display Processor (dp) functions
*/
#define IPU_DP_FLOW_SYNC_BG 0
#define IPU_DP_FLOW_SYNC_FG 1
#define IPU_DP_FLOW_ASYNC0_BG 2
#define IPU_DP_FLOW_ASYNC0_FG 3
#define IPU_DP_FLOW_ASYNC1_BG 4
#define IPU_DP_FLOW_ASYNC1_FG 5
struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
void ipu_dp_put(struct ipu_dp *);
int ipu_dp_enable(struct ipu_soc *ipu);
int ipu_dp_enable_channel(struct ipu_dp *dp);
void ipu_dp_disable_channel(struct ipu_dp *dp);
void ipu_dp_disable(struct ipu_soc *ipu);
int ipu_dp_setup_channel(struct ipu_dp *dp,
enum ipu_color_space in, enum ipu_color_space out);
int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
bool bg_chan);
/*
* IPU CMOS Sensor Interface (csi) functions
*/
struct ipu_csi;
int ipu_csi_init_interface(struct ipu_csi *csi,
struct v4l2_mbus_config *mbus_cfg,
struct v4l2_mbus_framefmt *mbus_fmt);
bool ipu_csi_is_interlaced(struct ipu_csi *csi);
void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w);
void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w);
void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
u32 r_value, u32 g_value, u32 b_value,
u32 pix_clk);
int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
struct v4l2_mbus_framefmt *mbus_fmt);
int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
u32 max_ratio, u32 id);
int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest);
int ipu_csi_enable(struct ipu_csi *csi);
int ipu_csi_disable(struct ipu_csi *csi);
struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id);
void ipu_csi_put(struct ipu_csi *csi);
void ipu_csi_dump(struct ipu_csi *csi);
/*
* IPU Image Converter (ic) functions
*/
enum ipu_ic_task {
IC_TASK_ENCODER,
IC_TASK_VIEWFINDER,
IC_TASK_POST_PROCESSOR,
IC_NUM_TASKS,
};
struct ipu_ic;
int ipu_ic_task_init(struct ipu_ic *ic,
int in_width, int in_height,
int out_width, int out_height,
enum ipu_color_space in_cs,
enum ipu_color_space out_cs);
int ipu_ic_task_graphics_init(struct ipu_ic *ic,
enum ipu_color_space in_g_cs,
bool galpha_en, u32 galpha,
bool colorkey_en, u32 colorkey);
void ipu_ic_task_enable(struct ipu_ic *ic);
void ipu_ic_task_disable(struct ipu_ic *ic);
int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel,
u32 width, u32 height, int burst_size,
enum ipu_rotate_mode rot);
int ipu_ic_enable(struct ipu_ic *ic);
int ipu_ic_disable(struct ipu_ic *ic);
struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task);
void ipu_ic_put(struct ipu_ic *ic);
void ipu_ic_dump(struct ipu_ic *ic);
/*
* IPU Sensor Multiple FIFO Controller (SMFC) functions
*/
struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno);
void ipu_smfc_put(struct ipu_smfc *smfc);
int ipu_smfc_enable(struct ipu_smfc *smfc);
int ipu_smfc_disable(struct ipu_smfc *smfc);
int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id);
int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize);
int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level);
enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code);
int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat);
bool ipu_pixelformat_is_planar(u32 pixelformat);
int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
bool hflip, bool vflip);
int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
bool hflip, bool vflip);
struct ipu_client_platformdata {
int csi;
int di;
int dc;
int dp;
int dmfc;
int dma[2];
};
#endif /* __DRM_IPU_H__ */

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/*
* linux/drivers/video/kyro/kryo.h
*
* Copyright (C) 2002 STMicroelectronics
* Copyright (C) 2004 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#ifndef _KYRO_H
#define _KYRO_H
struct kyrofb_info {
void __iomem *regbase;
u32 palette[16];
u32 HTot; /* Hor Total Time */
u32 HFP; /* Hor Front Porch */
u32 HST; /* Hor Sync Time */
u32 HBP; /* Hor Back Porch */
s32 HSP; /* Hor Sync Polarity */
u32 VTot; /* Ver Total Time */
u32 VFP; /* Ver Front Porch */
u32 VST; /* Ver Sync Time */
u32 VBP; /* Ver Back Porch */
s32 VSP; /* Ver Sync Polarity */
u32 XRES; /* X Resolution */
u32 YRES; /* Y Resolution */
u32 VFREQ; /* Ver Frequency */
u32 PIXCLK; /* Pixel Clock */
u32 HCLK; /* Hor Clock */
/* Useful to hold depth here for Linux */
u8 PIXDEPTH;
#ifdef CONFIG_MTRR
int mtrr_handle;
#endif
};
extern int kyro_dev_init(void);
extern void kyro_dev_reset(void);
extern unsigned char *kyro_dev_physical_fb_ptr(void);
extern unsigned char *kyro_dev_virtual_fb_ptr(void);
extern void *kyro_dev_physical_regs_ptr(void);
extern void *kyro_dev_virtual_regs_ptr(void);
extern unsigned int kyro_dev_fb_size(void);
extern unsigned int kyro_dev_regs_size(void);
extern u32 kyro_dev_overlay_offset(void);
/*
* benedict.gaster@superh.com
* Added the follow IOCTLS for the creation of overlay services...
*/
#define KYRO_IOC_MAGIC 'k'
#define KYRO_IOCTL_OVERLAY_CREATE _IO(KYRO_IOC_MAGIC, 0)
#define KYRO_IOCTL_OVERLAY_VIEWPORT_SET _IO(KYRO_IOC_MAGIC, 1)
#define KYRO_IOCTL_SET_VIDEO_MODE _IO(KYRO_IOC_MAGIC, 2)
#define KYRO_IOCTL_UVSTRIDE _IO(KYRO_IOC_MAGIC, 3)
#define KYRO_IOCTL_OVERLAY_OFFSET _IO(KYRO_IOC_MAGIC, 4)
#define KYRO_IOCTL_STRIDE _IO(KYRO_IOC_MAGIC, 5)
/*
* The follow 3 structures are used to pass data from user space into the kernel
* for the creation of overlay surfaces and setting the video mode.
*/
typedef struct _OVERLAY_CREATE {
u32 ulWidth;
u32 ulHeight;
int bLinear;
} overlay_create;
typedef struct _OVERLAY_VIEWPORT_SET {
u32 xOrgin;
u32 yOrgin;
u32 xSize;
u32 ySize;
} overlay_viewport_set;
typedef struct _SET_VIDEO_MODE {
u32 ulWidth;
u32 ulHeight;
u32 ulScan;
u8 displayDepth;
int bLinear;
} set_video_mode;
#endif /* _KYRO_H */

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/*
* linux/drivers/video/maxinefb.h
*
* DECstation 5000/xx onboard framebuffer support, Copyright (C) 1999 by
* Michael Engel <engel@unix-ag.org> and Karsten Merker <merker@guug.de>
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*/
#include <asm/addrspace.h>
/*
* IMS332 video controller register base address
*/
#define MAXINEFB_IMS332_ADDRESS KSEG1ADDR(0x1c140000)
/*
* Begin of DECstation 5000/xx onboard framebuffer memory, default resolution
* is 1024x768x8
*/
#define DS5000_xx_ONBOARD_FBMEM_START KSEG1ADDR(0x0a000000)
/*
* The IMS 332 video controller used in the DECstation 5000/xx series
* uses 32 bits wide registers; the following defines declare the
* register numbers, to get the real offset, these have to be multiplied
* by four.
*/
#define IMS332_REG_CURSOR_RAM 0x200 /* hardware cursor bitmap */
/*
* The color palette entries have the form 0x00BBGGRR
*/
#define IMS332_REG_COLOR_PALETTE 0x100 /* color palette, 256 entries */
#define IMS332_REG_CURSOR_COLOR_PALETTE 0x0a1 /* cursor color palette, */
/* 3 entries */

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#ifndef __MBX_FB_H
#define __MBX_FB_H
#include <asm/ioctl.h>
#include <asm/types.h>
struct mbxfb_val {
unsigned int defval;
unsigned int min;
unsigned int max;
};
struct fb_info;
struct mbxfb_platform_data {
/* Screen info */
struct mbxfb_val xres;
struct mbxfb_val yres;
struct mbxfb_val bpp;
/* Memory info */
unsigned long memsize; /* if 0 use ODFB? */
unsigned long timings1;
unsigned long timings2;
unsigned long timings3;
int (*probe)(struct fb_info *fb);
int (*remove)(struct fb_info *fb);
};
/* planar */
#define MBXFB_FMT_YUV16 0
#define MBXFB_FMT_YUV12 1
/* packed */
#define MBXFB_FMT_UY0VY1 2
#define MBXFB_FMT_VY0UY1 3
#define MBXFB_FMT_Y0UY1V 4
#define MBXFB_FMT_Y0VY1U 5
struct mbxfb_overlaySetup {
__u32 enable;
__u32 x, y;
__u32 width, height;
__u32 fmt;
__u32 mem_offset;
__u32 scaled_width;
__u32 scaled_height;
/* Filled by the driver */
__u32 U_offset;
__u32 V_offset;
__u16 Y_stride;
__u16 UV_stride;
};
#define MBXFB_ALPHABLEND_NONE 0
#define MBXFB_ALPHABLEND_GLOBAL 1
#define MBXFB_ALPHABLEND_PIXEL 2
#define MBXFB_COLORKEY_DISABLED 0
#define MBXFB_COLORKEY_PREVIOUS 1
#define MBXFB_COLORKEY_CURRENT 2
struct mbxfb_alphaCtl {
__u8 overlay_blend_mode;
__u8 overlay_colorkey_mode;
__u8 overlay_global_alpha;
__u32 overlay_colorkey;
__u32 overlay_colorkey_mask;
__u8 graphics_blend_mode;
__u8 graphics_colorkey_mode;
__u8 graphics_global_alpha;
__u32 graphics_colorkey;
__u32 graphics_colorkey_mask;
};
#define MBXFB_PLANE_GRAPHICS 0
#define MBXFB_PLANE_VIDEO 1
struct mbxfb_planeorder {
__u8 bottom;
__u8 top;
};
struct mbxfb_reg {
__u32 addr; /* offset from 0x03fe 0000 */
__u32 val; /* value */
__u32 mask; /* which bits to touch (for write) */
};
#define MBXFB_IOCX_OVERLAY _IOWR(0xF4, 0x00,struct mbxfb_overlaySetup)
#define MBXFB_IOCG_ALPHA _IOR(0xF4, 0x01,struct mbxfb_alphaCtl)
#define MBXFB_IOCS_ALPHA _IOW(0xF4, 0x02,struct mbxfb_alphaCtl)
#define MBXFB_IOCS_PLANEORDER _IOR(0xF4, 0x03,struct mbxfb_planeorder)
#define MBXFB_IOCS_REG _IOW(0xF4, 0x04,struct mbxfb_reg)
#define MBXFB_IOCX_REG _IOWR(0xF4, 0x05,struct mbxfb_reg)
#endif /* __MBX_FB_H */

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/*
* metronomefb.h - definitions for the metronome framebuffer driver
*
* Copyright (C) 2008 by Jaya Kumar
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
*/
#ifndef _LINUX_METRONOMEFB_H_
#define _LINUX_METRONOMEFB_H_
/* command structure used by metronome controller */
struct metromem_cmd {
u16 opcode;
u16 args[((64-2)/2)];
u16 csum;
};
/* struct used by metronome. board specific stuff comes from *board */
struct metronomefb_par {
struct metromem_cmd *metromem_cmd;
unsigned char *metromem_wfm;
unsigned char *metromem_img;
u16 *metromem_img_csum;
u16 *csum_table;
dma_addr_t metromem_dma;
struct fb_info *info;
struct metronome_board *board;
wait_queue_head_t waitq;
u8 frame_count;
int extra_size;
int dt;
};
/* board specific routines and data */
struct metronome_board {
struct module *owner; /* the platform device */
void (*set_rst)(struct metronomefb_par *, int);
void (*set_stdby)(struct metronomefb_par *, int);
void (*cleanup)(struct metronomefb_par *);
int (*met_wait_event)(struct metronomefb_par *);
int (*met_wait_event_intr)(struct metronomefb_par *);
int (*setup_irq)(struct fb_info *);
int (*setup_fb)(struct metronomefb_par *);
int (*setup_io)(struct metronomefb_par *);
int (*get_panel_type)(void);
unsigned char *metromem;
int fw;
int fh;
int wfm_size;
struct fb_info *host_fbinfo; /* the host LCD controller's fbi */
};
#endif

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/*
* Defines for Mobile Industry Processor Interface (MIPI(R))
* Display Working Group standards: DSI, DCS, DBI, DPI
*
* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
* Copyright (C) 2006 Nokia Corporation
* Author: Imre Deak <imre.deak@nokia.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef MIPI_DISPLAY_H
#define MIPI_DISPLAY_H
/* MIPI DSI Processor-to-Peripheral transaction types */
enum {
MIPI_DSI_V_SYNC_START = 0x01,
MIPI_DSI_V_SYNC_END = 0x11,
MIPI_DSI_H_SYNC_START = 0x21,
MIPI_DSI_H_SYNC_END = 0x31,
MIPI_DSI_COLOR_MODE_OFF = 0x02,
MIPI_DSI_COLOR_MODE_ON = 0x12,
MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22,
MIPI_DSI_TURN_ON_PERIPHERAL = 0x32,
MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03,
MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13,
MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23,
MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04,
MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14,
MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24,
MIPI_DSI_DCS_SHORT_WRITE = 0x05,
MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15,
MIPI_DSI_DCS_READ = 0x06,
MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37,
MIPI_DSI_END_OF_TRANSMISSION = 0x08,
MIPI_DSI_NULL_PACKET = 0x09,
MIPI_DSI_BLANKING_PACKET = 0x19,
MIPI_DSI_GENERIC_LONG_WRITE = 0x29,
MIPI_DSI_DCS_LONG_WRITE = 0x39,
MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c,
MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c,
MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c,
MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d,
MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d,
MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d,
MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e,
MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e,
MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e,
MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e,
};
/* MIPI DSI Peripheral-to-Processor transaction types */
enum {
MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02,
MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08,
MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11,
MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12,
MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a,
MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c,
MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21,
MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22,
};
/* MIPI DCS commands */
enum {
MIPI_DCS_NOP = 0x00,
MIPI_DCS_SOFT_RESET = 0x01,
MIPI_DCS_GET_DISPLAY_ID = 0x04,
MIPI_DCS_GET_RED_CHANNEL = 0x06,
MIPI_DCS_GET_GREEN_CHANNEL = 0x07,
MIPI_DCS_GET_BLUE_CHANNEL = 0x08,
MIPI_DCS_GET_DISPLAY_STATUS = 0x09,
MIPI_DCS_GET_POWER_MODE = 0x0A,
MIPI_DCS_GET_ADDRESS_MODE = 0x0B,
MIPI_DCS_GET_PIXEL_FORMAT = 0x0C,
MIPI_DCS_GET_DISPLAY_MODE = 0x0D,
MIPI_DCS_GET_SIGNAL_MODE = 0x0E,
MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F,
MIPI_DCS_ENTER_SLEEP_MODE = 0x10,
MIPI_DCS_EXIT_SLEEP_MODE = 0x11,
MIPI_DCS_ENTER_PARTIAL_MODE = 0x12,
MIPI_DCS_ENTER_NORMAL_MODE = 0x13,
MIPI_DCS_EXIT_INVERT_MODE = 0x20,
MIPI_DCS_ENTER_INVERT_MODE = 0x21,
MIPI_DCS_SET_GAMMA_CURVE = 0x26,
MIPI_DCS_SET_DISPLAY_OFF = 0x28,
MIPI_DCS_SET_DISPLAY_ON = 0x29,
MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A,
MIPI_DCS_SET_PAGE_ADDRESS = 0x2B,
MIPI_DCS_WRITE_MEMORY_START = 0x2C,
MIPI_DCS_WRITE_LUT = 0x2D,
MIPI_DCS_READ_MEMORY_START = 0x2E,
MIPI_DCS_SET_PARTIAL_AREA = 0x30,
MIPI_DCS_SET_SCROLL_AREA = 0x33,
MIPI_DCS_SET_TEAR_OFF = 0x34,
MIPI_DCS_SET_TEAR_ON = 0x35,
MIPI_DCS_SET_ADDRESS_MODE = 0x36,
MIPI_DCS_SET_SCROLL_START = 0x37,
MIPI_DCS_EXIT_IDLE_MODE = 0x38,
MIPI_DCS_ENTER_IDLE_MODE = 0x39,
MIPI_DCS_SET_PIXEL_FORMAT = 0x3A,
MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C,
MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E,
MIPI_DCS_SET_TEAR_SCANLINE = 0x44,
MIPI_DCS_GET_SCANLINE = 0x45,
MIPI_DCS_READ_DDB_START = 0xA1,
MIPI_DCS_READ_DDB_CONTINUE = 0xA8,
};
/* MIPI DCS pixel formats */
#define MIPI_DCS_PIXEL_FMT_24BIT 7
#define MIPI_DCS_PIXEL_FMT_18BIT 6
#define MIPI_DCS_PIXEL_FMT_16BIT 5
#define MIPI_DCS_PIXEL_FMT_12BIT 3
#define MIPI_DCS_PIXEL_FMT_8BIT 2
#define MIPI_DCS_PIXEL_FMT_3BIT 1
#endif

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/*
* linux/include/video/mmp_disp.h
* Header file for Marvell MMP Display Controller
*
* Copyright (C) 2012 Marvell Technology Group Ltd.
* Authors: Zhou Zhu <zzhu3@marvell.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
#ifndef _MMP_DISP_H_
#define _MMP_DISP_H_
#include <linux/kthread.h>
enum {
PIXFMT_UYVY = 0,
PIXFMT_VYUY,
PIXFMT_YUYV,
PIXFMT_YUV422P,
PIXFMT_YVU422P,
PIXFMT_YUV420P,
PIXFMT_YVU420P,
PIXFMT_RGB565 = 0x100,
PIXFMT_BGR565,
PIXFMT_RGB1555,
PIXFMT_BGR1555,
PIXFMT_RGB888PACK,
PIXFMT_BGR888PACK,
PIXFMT_RGB888UNPACK,
PIXFMT_BGR888UNPACK,
PIXFMT_RGBA888,
PIXFMT_BGRA888,
PIXFMT_RGB666, /* for output usage */
PIXFMT_PSEUDOCOLOR = 0x200,
};
static inline int pixfmt_to_stride(int pix_fmt)
{
switch (pix_fmt) {
case PIXFMT_RGB565:
case PIXFMT_BGR565:
case PIXFMT_RGB1555:
case PIXFMT_BGR1555:
case PIXFMT_UYVY:
case PIXFMT_VYUY:
case PIXFMT_YUYV:
return 2;
case PIXFMT_RGB888UNPACK:
case PIXFMT_BGR888UNPACK:
case PIXFMT_RGBA888:
case PIXFMT_BGRA888:
return 4;
case PIXFMT_RGB888PACK:
case PIXFMT_BGR888PACK:
return 3;
case PIXFMT_YUV422P:
case PIXFMT_YVU422P:
case PIXFMT_YUV420P:
case PIXFMT_YVU420P:
case PIXFMT_PSEUDOCOLOR:
return 1;
default:
return 0;
}
}
/* parameters used by path/overlay */
/* overlay related para: win/addr */
struct mmp_win {
/* position/size of window */
u16 xsrc;
u16 ysrc;
u16 xdst;
u16 ydst;
u16 xpos;
u16 ypos;
u16 left_crop;
u16 right_crop;
u16 up_crop;
u16 bottom_crop;
int pix_fmt;
/*
* pitch[0]: graphics/video layer line length or y pitch
* pitch[1]/pitch[2]: video u/v pitch if non-zero
*/
u32 pitch[3];
};
struct mmp_addr {
/* phys address */
u32 phys[6];
};
/* path related para: mode */
struct mmp_mode {
const char *name;
u32 refresh;
u32 xres;
u32 yres;
u32 left_margin;
u32 right_margin;
u32 upper_margin;
u32 lower_margin;
u32 hsync_len;
u32 vsync_len;
u32 hsync_invert;
u32 vsync_invert;
u32 invert_pixclock;
u32 pixclock_freq;
int pix_fmt_out;
};
/* main structures */
struct mmp_path;
struct mmp_overlay;
struct mmp_panel;
/* status types */
enum {
MMP_OFF = 0,
MMP_ON,
};
static inline const char *stat_name(int stat)
{
switch (stat) {
case MMP_OFF:
return "OFF";
case MMP_ON:
return "ON";
default:
return "UNKNOWNSTAT";
}
}
struct mmp_overlay_ops {
/* should be provided by driver */
void (*set_fetch)(struct mmp_overlay *overlay, int fetch_id);
void (*set_onoff)(struct mmp_overlay *overlay, int status);
void (*set_win)(struct mmp_overlay *overlay, struct mmp_win *win);
int (*set_addr)(struct mmp_overlay *overlay, struct mmp_addr *addr);
};
/* overlay describes a z-order indexed slot in each path. */
struct mmp_overlay {
int id;
const char *name;
struct mmp_path *path;
/* overlay info: private data */
int dmafetch_id;
struct mmp_addr addr;
struct mmp_win win;
/* state */
int open_count;
int status;
struct mutex access_ok;
struct mmp_overlay_ops *ops;
};
/* panel type */
enum {
PANELTYPE_ACTIVE = 0,
PANELTYPE_SMART,
PANELTYPE_TV,
PANELTYPE_DSI_CMD,
PANELTYPE_DSI_VIDEO,
};
struct mmp_panel {
/* use node to register to list */
struct list_head node;
const char *name;
/* path name used to connect to proper path configed */
const char *plat_path_name;
struct device *dev;
int panel_type;
void *plat_data;
int (*get_modelist)(struct mmp_panel *panel,
struct mmp_mode **modelist);
void (*set_mode)(struct mmp_panel *panel,
struct mmp_mode *mode);
void (*set_onoff)(struct mmp_panel *panel,
int status);
};
struct mmp_path_ops {
int (*check_status)(struct mmp_path *path);
struct mmp_overlay *(*get_overlay)(struct mmp_path *path,
int overlay_id);
int (*get_modelist)(struct mmp_path *path,
struct mmp_mode **modelist);
/* follow ops should be provided by driver */
void (*set_mode)(struct mmp_path *path, struct mmp_mode *mode);
void (*set_onoff)(struct mmp_path *path, int status);
/* todo: add query */
};
/* path output types */
enum {
PATH_OUT_PARALLEL,
PATH_OUT_DSI,
PATH_OUT_HDMI,
};
/* path is main part of mmp-disp */
struct mmp_path {
/* use node to register to list */
struct list_head node;
/* init data */
struct device *dev;
int id;
const char *name;
int output_type;
struct mmp_panel *panel;
void *plat_data;
/* dynamic use */
struct mmp_mode mode;
/* state */
int open_count;
int status;
struct mutex access_ok;
struct mmp_path_ops ops;
/* layers */
int overlay_num;
struct mmp_overlay overlays[0];
};
extern struct mmp_path *mmp_get_path(const char *name);
static inline void mmp_path_set_mode(struct mmp_path *path,
struct mmp_mode *mode)
{
if (path)
path->ops.set_mode(path, mode);
}
static inline void mmp_path_set_onoff(struct mmp_path *path, int status)
{
if (path)
path->ops.set_onoff(path, status);
}
static inline int mmp_path_get_modelist(struct mmp_path *path,
struct mmp_mode **modelist)
{
if (path)
return path->ops.get_modelist(path, modelist);
return 0;
}
static inline struct mmp_overlay *mmp_path_get_overlay(
struct mmp_path *path, int overlay_id)
{
if (path)
return path->ops.get_overlay(path, overlay_id);
return NULL;
}
static inline void mmp_overlay_set_fetch(struct mmp_overlay *overlay,
int fetch_id)
{
if (overlay)
overlay->ops->set_fetch(overlay, fetch_id);
}
static inline void mmp_overlay_set_onoff(struct mmp_overlay *overlay,
int status)
{
if (overlay)
overlay->ops->set_onoff(overlay, status);
}
static inline void mmp_overlay_set_win(struct mmp_overlay *overlay,
struct mmp_win *win)
{
if (overlay)
overlay->ops->set_win(overlay, win);
}
static inline int mmp_overlay_set_addr(struct mmp_overlay *overlay,
struct mmp_addr *addr)
{
if (overlay)
return overlay->ops->set_addr(overlay, addr);
return 0;
}
/*
* driver data is set from each detailed ctrl driver for path usage
* it defined a common interface that plat driver need to implement
*/
struct mmp_path_info {
/* driver data, set when registed*/
const char *name;
struct device *dev;
int id;
int output_type;
int overlay_num;
void (*set_mode)(struct mmp_path *path, struct mmp_mode *mode);
void (*set_onoff)(struct mmp_path *path, int status);
struct mmp_overlay_ops *overlay_ops;
void *plat_data;
};
extern struct mmp_path *mmp_register_path(
struct mmp_path_info *info);
extern void mmp_unregister_path(struct mmp_path *path);
extern void mmp_register_panel(struct mmp_panel *panel);
extern void mmp_unregister_panel(struct mmp_panel *panel);
/* defintions for platform data */
/* interface for buffer driver */
struct mmp_buffer_driver_mach_info {
const char *name;
const char *path_name;
int overlay_id;
int dmafetch_id;
int default_pixfmt;
};
/* interface for controllers driver */
struct mmp_mach_path_config {
const char *name;
int overlay_num;
int output_type;
u32 path_config;
u32 link_config;
u32 dsi_rbswap;
};
struct mmp_mach_plat_info {
const char *name;
const char *clk_name;
int path_num;
struct mmp_mach_path_config *paths;
};
/* interface for panel drivers */
struct mmp_mach_panel_info {
const char *name;
void (*plat_set_onoff)(int status);
const char *plat_path_name;
};
#endif /* _MMP_DISP_H_ */

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/*
* linux/include/video/neo_reg.h -- NeoMagic Framebuffer Driver
*
* Copyright (c) 2001 Denis Oliver Kropp <dok@convergence.de>
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*/
#define NEO_BS0_BLT_BUSY 0x00000001
#define NEO_BS0_FIFO_AVAIL 0x00000002
#define NEO_BS0_FIFO_PEND 0x00000004
#define NEO_BC0_DST_Y_DEC 0x00000001
#define NEO_BC0_X_DEC 0x00000002
#define NEO_BC0_SRC_TRANS 0x00000004
#define NEO_BC0_SRC_IS_FG 0x00000008
#define NEO_BC0_SRC_Y_DEC 0x00000010
#define NEO_BC0_FILL_PAT 0x00000020
#define NEO_BC0_SRC_MONO 0x00000040
#define NEO_BC0_SYS_TO_VID 0x00000080
#define NEO_BC1_DEPTH8 0x00000100
#define NEO_BC1_DEPTH16 0x00000200
#define NEO_BC1_X_320 0x00000400
#define NEO_BC1_X_640 0x00000800
#define NEO_BC1_X_800 0x00000c00
#define NEO_BC1_X_1024 0x00001000
#define NEO_BC1_X_1152 0x00001400
#define NEO_BC1_X_1280 0x00001800
#define NEO_BC1_X_1600 0x00001c00
#define NEO_BC1_DST_TRANS 0x00002000
#define NEO_BC1_MSTR_BLT 0x00004000
#define NEO_BC1_FILTER_Z 0x00008000
#define NEO_BC2_WR_TR_DST 0x00800000
#define NEO_BC3_SRC_XY_ADDR 0x01000000
#define NEO_BC3_DST_XY_ADDR 0x02000000
#define NEO_BC3_CLIP_ON 0x04000000
#define NEO_BC3_FIFO_EN 0x08000000
#define NEO_BC3_BLT_ON_ADDR 0x10000000
#define NEO_BC3_SKIP_MAPPING 0x80000000
#define NEO_MODE1_DEPTH8 0x0100
#define NEO_MODE1_DEPTH16 0x0200
#define NEO_MODE1_DEPTH24 0x0300
#define NEO_MODE1_X_320 0x0400
#define NEO_MODE1_X_640 0x0800
#define NEO_MODE1_X_800 0x0c00
#define NEO_MODE1_X_1024 0x1000
#define NEO_MODE1_X_1152 0x1400
#define NEO_MODE1_X_1280 0x1800
#define NEO_MODE1_X_1600 0x1c00
#define NEO_MODE1_BLT_ON_ADDR 0x2000
/* These are offseted in MMIO space by par->CursorOff */
#define NEOREG_CURSCNTL 0x00
#define NEOREG_CURSX 0x04
#define NEOREG_CURSY 0x08
#define NEOREG_CURSBGCOLOR 0x0C
#define NEOREG_CURSFGCOLOR 0x10
#define NEOREG_CURSMEMPOS 0x14
#define NEO_CURS_DISABLE 0x00000000
#define NEO_CURS_ENABLE 0x00000001
#define NEO_ICON64_ENABLE 0x00000008
#define NEO_ICON128_ENABLE 0x0000000C
#define NEO_ICON_BLANK 0x00000010
#define NEO_GR01_SUPPRESS_VSYNC 0x10
#define NEO_GR01_SUPPRESS_HSYNC 0x20
#ifdef __KERNEL__
#ifdef NEOFB_DEBUG
# define DBG(x) printk (KERN_DEBUG "neofb: %s\n", (x));
#else
# define DBG(x)
#endif
#define PCI_CHIP_NM2070 0x0001
#define PCI_CHIP_NM2090 0x0002
#define PCI_CHIP_NM2093 0x0003
#define PCI_CHIP_NM2097 0x0083
#define PCI_CHIP_NM2160 0x0004
#define PCI_CHIP_NM2200 0x0005
#define PCI_CHIP_NM2230 0x0025
#define PCI_CHIP_NM2360 0x0006
#define PCI_CHIP_NM2380 0x0016
/* --------------------------------------------------------------------- */
typedef volatile struct {
__u32 bltStat;
__u32 bltCntl;
__u32 xpColor;
__u32 fgColor;
__u32 bgColor;
__u32 pitch;
__u32 clipLT;
__u32 clipRB;
__u32 srcBitOffset;
__u32 srcStart;
__u32 reserved0;
__u32 dstStart;
__u32 xyExt;
__u32 reserved1[19];
__u32 pageCntl;
__u32 pageBase;
__u32 postBase;
__u32 postPtr;
__u32 dataPtr;
} Neo2200;
#define MMIO_SIZE 0x200000
#define NEO_EXT_CR_MAX 0x85
#define NEO_EXT_GR_MAX 0xC7
struct neofb_par {
struct vgastate state;
unsigned int ref_count;
unsigned char MiscOutReg; /* Misc */
unsigned char CRTC[25]; /* Crtc Controller */
unsigned char Sequencer[5]; /* Video Sequencer */
unsigned char Graphics[9]; /* Video Graphics */
unsigned char Attribute[21]; /* Video Attribute */
unsigned char GeneralLockReg;
unsigned char ExtCRTDispAddr;
unsigned char ExtCRTOffset;
unsigned char SysIfaceCntl1;
unsigned char SysIfaceCntl2;
unsigned char ExtColorModeSelect;
unsigned char biosMode;
unsigned char PanelDispCntlReg1;
unsigned char PanelDispCntlReg2;
unsigned char PanelDispCntlReg3;
unsigned char PanelDispCntlRegRead;
unsigned char PanelVertCenterReg1;
unsigned char PanelVertCenterReg2;
unsigned char PanelVertCenterReg3;
unsigned char PanelVertCenterReg4;
unsigned char PanelVertCenterReg5;
unsigned char PanelHorizCenterReg1;
unsigned char PanelHorizCenterReg2;
unsigned char PanelHorizCenterReg3;
unsigned char PanelHorizCenterReg4;
unsigned char PanelHorizCenterReg5;
int ProgramVCLK;
unsigned char VCLK3NumeratorLow;
unsigned char VCLK3NumeratorHigh;
unsigned char VCLK3Denominator;
unsigned char VerticalExt;
#ifdef CONFIG_MTRR
int mtrr;
#endif
u8 __iomem *mmio_vbase;
u8 cursorOff;
u8 *cursorPad; /* Must die !! */
Neo2200 __iomem *neo2200;
/* Panels size */
int NeoPanelWidth;
int NeoPanelHeight;
int maxClock;
int pci_burst;
int lcd_stretch;
int internal_display;
int external_display;
int libretto;
u32 palette[16];
};
typedef struct {
int x_res;
int y_res;
int mode;
} biosMode;
#endif

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/* $Id: newport.h,v 1.5 1999/08/04 06:01:51 ulfc Exp $
*
* newport.h: Defines and register layout for NEWPORT graphics
* hardware.
*
* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
*
* Ulf Carlsson - Compatibility with the IRIX structures added
*/
#ifndef _SGI_NEWPORT_H
#define _SGI_NEWPORT_H
typedef volatile unsigned int npireg_t;
union npfloat {
volatile float flt;
npireg_t word;
};
typedef union npfloat npfreg_t;
union np_dcb {
npireg_t byword;
struct { volatile unsigned short s0, s1; } byshort;
struct { volatile unsigned char b0, b1, b2, b3; } bybytes;
};
struct newport_rexregs {
npireg_t drawmode1; /* GL extra mode bits */
#define DM1_PLANES 0x00000007
#define DM1_NOPLANES 0x00000000
#define DM1_RGBPLANES 0x00000001
#define DM1_RGBAPLANES 0x00000002
#define DM1_OLAYPLANES 0x00000004
#define DM1_PUPPLANES 0x00000005
#define DM1_CIDPLANES 0x00000006
#define NPORT_DMODE1_DDMASK 0x00000018
#define NPORT_DMODE1_DD4 0x00000000
#define NPORT_DMODE1_DD8 0x00000008
#define NPORT_DMODE1_DD12 0x00000010
#define NPORT_DMODE1_DD24 0x00000018
#define NPORT_DMODE1_DSRC 0x00000020
#define NPORT_DMODE1_YFLIP 0x00000040
#define NPORT_DMODE1_RWPCKD 0x00000080
#define NPORT_DMODE1_HDMASK 0x00000300
#define NPORT_DMODE1_HD4 0x00000000
#define NPORT_DMODE1_HD8 0x00000100
#define NPORT_DMODE1_HD12 0x00000200
#define NPORT_DMODE1_HD32 0x00000300
#define NPORT_DMODE1_RWDBL 0x00000400
#define NPORT_DMODE1_ESWAP 0x00000800 /* Endian swap */
#define NPORT_DMODE1_CCMASK 0x00007000
#define NPORT_DMODE1_CCLT 0x00001000
#define NPORT_DMODE1_CCEQ 0x00002000
#define NPORT_DMODE1_CCGT 0x00004000
#define NPORT_DMODE1_RGBMD 0x00008000
#define NPORT_DMODE1_DENAB 0x00010000 /* Dither enable */
#define NPORT_DMODE1_FCLR 0x00020000 /* Fast clear */
#define NPORT_DMODE1_BENAB 0x00040000 /* Blend enable */
#define NPORT_DMODE1_SFMASK 0x00380000
#define NPORT_DMODE1_SF0 0x00000000
#define NPORT_DMODE1_SF1 0x00080000
#define NPORT_DMODE1_SFDC 0x00100000
#define NPORT_DMODE1_SFMDC 0x00180000
#define NPORT_DMODE1_SFSA 0x00200000
#define NPORT_DMODE1_SFMSA 0x00280000
#define NPORT_DMODE1_DFMASK 0x01c00000
#define NPORT_DMODE1_DF0 0x00000000
#define NPORT_DMODE1_DF1 0x00400000
#define NPORT_DMODE1_DFSC 0x00800000
#define NPORT_DMODE1_DFMSC 0x00c00000
#define NPORT_DMODE1_DFSA 0x01000000
#define NPORT_DMODE1_DFMSA 0x01400000
#define NPORT_DMODE1_BBENAB 0x02000000 /* Back blend enable */
#define NPORT_DMODE1_PFENAB 0x04000000 /* Pre-fetch enable */
#define NPORT_DMODE1_ABLEND 0x08000000 /* Alpha blend */
#define NPORT_DMODE1_LOMASK 0xf0000000
#define NPORT_DMODE1_LOZERO 0x00000000
#define NPORT_DMODE1_LOAND 0x10000000
#define NPORT_DMODE1_LOANDR 0x20000000
#define NPORT_DMODE1_LOSRC 0x30000000
#define NPORT_DMODE1_LOANDI 0x40000000
#define NPORT_DMODE1_LODST 0x50000000
#define NPORT_DMODE1_LOXOR 0x60000000
#define NPORT_DMODE1_LOOR 0x70000000
#define NPORT_DMODE1_LONOR 0x80000000
#define NPORT_DMODE1_LOXNOR 0x90000000
#define NPORT_DMODE1_LONDST 0xa0000000
#define NPORT_DMODE1_LOORR 0xb0000000
#define NPORT_DMODE1_LONSRC 0xc0000000
#define NPORT_DMODE1_LOORI 0xd0000000
#define NPORT_DMODE1_LONAND 0xe0000000
#define NPORT_DMODE1_LOONE 0xf0000000
npireg_t drawmode0; /* REX command register */
/* These bits define the graphics opcode being performed. */
#define NPORT_DMODE0_OPMASK 0x00000003 /* Opcode mask */
#define NPORT_DMODE0_NOP 0x00000000 /* No operation */
#define NPORT_DMODE0_RD 0x00000001 /* Read operation */
#define NPORT_DMODE0_DRAW 0x00000002 /* Draw operation */
#define NPORT_DMODE0_S2S 0x00000003 /* Screen to screen operation */
/* The following decide what addressing mode(s) are to be used */
#define NPORT_DMODE0_AMMASK 0x0000001c /* Address mode mask */
#define NPORT_DMODE0_SPAN 0x00000000 /* Spanning address mode */
#define NPORT_DMODE0_BLOCK 0x00000004 /* Block address mode */
#define NPORT_DMODE0_ILINE 0x00000008 /* Iline address mode */
#define NPORT_DMODE0_FLINE 0x0000000c /* Fline address mode */
#define NPORT_DMODE0_ALINE 0x00000010 /* Aline address mode */
#define NPORT_DMODE0_TLINE 0x00000014 /* Tline address mode */
#define NPORT_DMODE0_BLINE 0x00000018 /* Bline address mode */
/* And now some misc. operation control bits. */
#define NPORT_DMODE0_DOSETUP 0x00000020
#define NPORT_DMODE0_CHOST 0x00000040
#define NPORT_DMODE0_AHOST 0x00000080
#define NPORT_DMODE0_STOPX 0x00000100
#define NPORT_DMODE0_STOPY 0x00000200
#define NPORT_DMODE0_SK1ST 0x00000400
#define NPORT_DMODE0_SKLST 0x00000800
#define NPORT_DMODE0_ZPENAB 0x00001000
#define NPORT_DMODE0_LISPENAB 0x00002000
#define NPORT_DMODE0_LISLST 0x00004000
#define NPORT_DMODE0_L32 0x00008000
#define NPORT_DMODE0_ZOPQ 0x00010000
#define NPORT_DMODE0_LISOPQ 0x00020000
#define NPORT_DMODE0_SHADE 0x00040000
#define NPORT_DMODE0_LRONLY 0x00080000
#define NPORT_DMODE0_XYOFF 0x00100000
#define NPORT_DMODE0_CLAMP 0x00200000
#define NPORT_DMODE0_ENDPF 0x00400000
#define NPORT_DMODE0_YSTR 0x00800000
npireg_t lsmode; /* Mode for line stipple ops */
npireg_t lspattern; /* Pattern for line stipple ops */
npireg_t lspatsave; /* Backup save pattern */
npireg_t zpattern; /* Pixel zpattern */
npireg_t colorback; /* Background color */
npireg_t colorvram; /* Clear color for fast vram */
npireg_t alpharef; /* Reference value for afunctions */
unsigned int pad0;
npireg_t smask0x; /* Window GL relative screen mask 0 */
npireg_t smask0y; /* Window GL relative screen mask 0 */
npireg_t _setup;
npireg_t _stepz;
npireg_t _lsrestore;
npireg_t _lssave;
unsigned int _pad1[0x30];
/* Iterators, full state for context switch */
npfreg_t _xstart; /* X-start point (current) */
npfreg_t _ystart; /* Y-start point (current) */
npfreg_t _xend; /* x-end point */
npfreg_t _yend; /* y-end point */
npireg_t xsave; /* copy of xstart integer value for BLOCk addressing MODE */
npireg_t xymove; /* x.y offset from xstart, ystart for relative operations */
npfreg_t bresd;
npfreg_t bress1;
npireg_t bresoctinc1;
volatile int bresrndinc2;
npireg_t brese1;
npireg_t bress2;
npireg_t aweight0;
npireg_t aweight1;
npfreg_t xstartf;
npfreg_t ystartf;
npfreg_t xendf;
npfreg_t yendf;
npireg_t xstarti;
npfreg_t xendf1;
npireg_t xystarti;
npireg_t xyendi;
npireg_t xstartendi;
unsigned int _unused2[0x29];
npfreg_t colorred;
npfreg_t coloralpha;
npfreg_t colorgrn;
npfreg_t colorblue;
npfreg_t slopered;
npfreg_t slopealpha;
npfreg_t slopegrn;
npfreg_t slopeblue;
npireg_t wrmask;
npireg_t colori;
npfreg_t colorx;
npfreg_t slopered1;
npireg_t hostrw0;
npireg_t hostrw1;
npireg_t dcbmode;
#define NPORT_DMODE_WMASK 0x00000003
#define NPORT_DMODE_W4 0x00000000
#define NPORT_DMODE_W1 0x00000001
#define NPORT_DMODE_W2 0x00000002
#define NPORT_DMODE_W3 0x00000003
#define NPORT_DMODE_EDPACK 0x00000004
#define NPORT_DMODE_ECINC 0x00000008
#define NPORT_DMODE_CMASK 0x00000070
#define NPORT_DMODE_AMASK 0x00000780
#define NPORT_DMODE_AVC2 0x00000000
#define NPORT_DMODE_ACMALL 0x00000080
#define NPORT_DMODE_ACM0 0x00000100
#define NPORT_DMODE_ACM1 0x00000180
#define NPORT_DMODE_AXMALL 0x00000200
#define NPORT_DMODE_AXM0 0x00000280
#define NPORT_DMODE_AXM1 0x00000300
#define NPORT_DMODE_ABT 0x00000380
#define NPORT_DMODE_AVCC1 0x00000400
#define NPORT_DMODE_AVAB1 0x00000480
#define NPORT_DMODE_ALG3V0 0x00000500
#define NPORT_DMODE_A1562 0x00000580
#define NPORT_DMODE_ESACK 0x00000800
#define NPORT_DMODE_EASACK 0x00001000
#define NPORT_DMODE_CWMASK 0x0003e000
#define NPORT_DMODE_CHMASK 0x007c0000
#define NPORT_DMODE_CSMASK 0x0f800000
#define NPORT_DMODE_SENDIAN 0x10000000
unsigned int _unused3;
union np_dcb dcbdata0;
npireg_t dcbdata1;
};
struct newport_cregs {
npireg_t smask1x;
npireg_t smask1y;
npireg_t smask2x;
npireg_t smask2y;
npireg_t smask3x;
npireg_t smask3y;
npireg_t smask4x;
npireg_t smask4y;
npireg_t topscan;
npireg_t xywin;
npireg_t clipmode;
#define NPORT_CMODE_SM0 0x00000001
#define NPORT_CMODE_SM1 0x00000002
#define NPORT_CMODE_SM2 0x00000004
#define NPORT_CMODE_SM3 0x00000008
#define NPORT_CMODE_SM4 0x00000010
#define NPORT_CMODE_CMSK 0x00001e00
unsigned int _unused0;
unsigned int config;
#define NPORT_CFG_G32MD 0x00000001
#define NPORT_CFG_BWIDTH 0x00000002
#define NPORT_CFG_ERCVR 0x00000004
#define NPORT_CFG_BDMSK 0x00000078
#define NPORT_CFG_BFAINT 0x00000080
#define NPORT_CFG_GDMSK 0x00001f80
#define NPORT_CFG_GD0 0x00000100
#define NPORT_CFG_GD1 0x00000200
#define NPORT_CFG_GD2 0x00000400
#define NPORT_CFG_GD3 0x00000800
#define NPORT_CFG_GD4 0x00001000
#define NPORT_CFG_GFAINT 0x00002000
#define NPORT_CFG_TOMSK 0x0001c000
#define NPORT_CFG_VRMSK 0x000e0000
#define NPORT_CFG_FBTYP 0x00100000
npireg_t _unused1;
npireg_t status;
#define NPORT_STAT_VERS 0x00000007
#define NPORT_STAT_GBUSY 0x00000008
#define NPORT_STAT_BBUSY 0x00000010
#define NPORT_STAT_VRINT 0x00000020
#define NPORT_STAT_VIDINT 0x00000040
#define NPORT_STAT_GLMSK 0x00001f80
#define NPORT_STAT_BLMSK 0x0007e000
#define NPORT_STAT_BFIRQ 0x00080000
#define NPORT_STAT_GFIRQ 0x00100000
npireg_t ustatus;
npireg_t dcbreset;
};
struct newport_regs {
struct newport_rexregs set;
unsigned int _unused0[0x16e];
struct newport_rexregs go;
unsigned int _unused1[0x22e];
struct newport_cregs cset;
unsigned int _unused2[0x1ef];
struct newport_cregs cgo;
};
typedef struct {
unsigned int drawmode1;
unsigned int drawmode0;
unsigned int lsmode;
unsigned int lspattern;
unsigned int lspatsave;
unsigned int zpattern;
unsigned int colorback;
unsigned int colorvram;
unsigned int alpharef;
unsigned int smask0x;
unsigned int smask0y;
unsigned int _xstart;
unsigned int _ystart;
unsigned int _xend;
unsigned int _yend;
unsigned int xsave;
unsigned int xymove;
unsigned int bresd;
unsigned int bress1;
unsigned int bresoctinc1;
unsigned int bresrndinc2;
unsigned int brese1;
unsigned int bress2;
unsigned int aweight0;
unsigned int aweight1;
unsigned int colorred;
unsigned int coloralpha;
unsigned int colorgrn;
unsigned int colorblue;
unsigned int slopered;
unsigned int slopealpha;
unsigned int slopegrn;
unsigned int slopeblue;
unsigned int wrmask;
unsigned int hostrw0;
unsigned int hostrw1;
/* configregs */
unsigned int smask1x;
unsigned int smask1y;
unsigned int smask2x;
unsigned int smask2y;
unsigned int smask3x;
unsigned int smask3y;
unsigned int smask4x;
unsigned int smask4y;
unsigned int topscan;
unsigned int xywin;
unsigned int clipmode;
unsigned int config;
/* dcb registers */
unsigned int dcbmode;
unsigned int dcbdata0;
unsigned int dcbdata1;
} newport_ctx;
/* Reading/writing VC2 registers. */
#define VC2_REGADDR_INDEX 0x00000000
#define VC2_REGADDR_IREG 0x00000010
#define VC2_REGADDR_RAM 0x00000030
#define VC2_PROTOCOL (NPORT_DMODE_EASACK | 0x00800000 | 0x00040000)
#define VC2_VLINET_ADDR 0x000
#define VC2_VFRAMET_ADDR 0x400
#define VC2_CGLYPH_ADDR 0x500
/* Now the Indexed registers of the VC2. */
#define VC2_IREG_VENTRY 0x00
#define VC2_IREG_CENTRY 0x01
#define VC2_IREG_CURSX 0x02
#define VC2_IREG_CURSY 0x03
#define VC2_IREG_CCURSX 0x04
#define VC2_IREG_DENTRY 0x05
#define VC2_IREG_SLEN 0x06
#define VC2_IREG_RADDR 0x07
#define VC2_IREG_VFPTR 0x08
#define VC2_IREG_VLSPTR 0x09
#define VC2_IREG_VLIR 0x0a
#define VC2_IREG_VLCTR 0x0b
#define VC2_IREG_CTPTR 0x0c
#define VC2_IREG_WCURSY 0x0d
#define VC2_IREG_DFPTR 0x0e
#define VC2_IREG_DLTPTR 0x0f
#define VC2_IREG_CONTROL 0x10
#define VC2_IREG_CONFIG 0x20
static inline void newport_vc2_set(struct newport_regs *regs,
unsigned char vc2ireg,
unsigned short val)
{
regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_INDEX | NPORT_DMODE_W3 |
NPORT_DMODE_ECINC | VC2_PROTOCOL);
regs->set.dcbdata0.byword = (vc2ireg << 24) | (val << 8);
}
static inline unsigned short newport_vc2_get(struct newport_regs *regs,
unsigned char vc2ireg)
{
regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_INDEX | NPORT_DMODE_W1 |
NPORT_DMODE_ECINC | VC2_PROTOCOL);
regs->set.dcbdata0.bybytes.b3 = vc2ireg;
regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_IREG | NPORT_DMODE_W2 |
NPORT_DMODE_ECINC | VC2_PROTOCOL);
return regs->set.dcbdata0.byshort.s1;
}
/* VC2 Control register bits */
#define VC2_CTRL_EVIRQ 0x0001
#define VC2_CTRL_EDISP 0x0002
#define VC2_CTRL_EVIDEO 0x0004
#define VC2_CTRL_EDIDS 0x0008
#define VC2_CTRL_ECURS 0x0010
#define VC2_CTRL_EGSYNC 0x0020
#define VC2_CTRL_EILACE 0x0040
#define VC2_CTRL_ECDISP 0x0080
#define VC2_CTRL_ECCURS 0x0100
#define VC2_CTRL_ECG64 0x0200
#define VC2_CTRL_GLSEL 0x0400
/* Controlling the color map on NEWPORT. */
#define NCMAP_REGADDR_AREG 0x00000000
#define NCMAP_REGADDR_ALO 0x00000000
#define NCMAP_REGADDR_AHI 0x00000010
#define NCMAP_REGADDR_PBUF 0x00000020
#define NCMAP_REGADDR_CREG 0x00000030
#define NCMAP_REGADDR_SREG 0x00000040
#define NCMAP_REGADDR_RREG 0x00000060
#define NCMAP_PROTOCOL (0x00008000 | 0x00040000 | 0x00800000)
static __inline__ void newport_cmap_setaddr(struct newport_regs *regs,
unsigned short addr)
{
regs->set.dcbmode = (NPORT_DMODE_ACMALL | NCMAP_PROTOCOL |
NPORT_DMODE_SENDIAN | NPORT_DMODE_ECINC |
NCMAP_REGADDR_AREG | NPORT_DMODE_W2);
regs->set.dcbdata0.byshort.s1 = addr;
regs->set.dcbmode = (NPORT_DMODE_ACMALL | NCMAP_PROTOCOL |
NCMAP_REGADDR_PBUF | NPORT_DMODE_W3);
}
static __inline__ void newport_cmap_setrgb(struct newport_regs *regs,
unsigned char red,
unsigned char green,
unsigned char blue)
{
regs->set.dcbdata0.byword =
(red << 24) |
(green << 16) |
(blue << 8);
}
/* Miscellaneous NEWPORT routines. */
#define BUSY_TIMEOUT 100000
static __inline__ int newport_wait(struct newport_regs *regs)
{
int t = BUSY_TIMEOUT;
while (--t)
if (!(regs->cset.status & NPORT_STAT_GBUSY))
break;
return !t;
}
static __inline__ int newport_bfwait(struct newport_regs *regs)
{
int t = BUSY_TIMEOUT;
while (--t)
if(!(regs->cset.status & NPORT_STAT_BBUSY))
break;
return !t;
}
/*
* DCBMODE register defines:
*/
/* Width of the data being transferred for each DCBDATA[01] word */
#define DCB_DATAWIDTH_4 0x0
#define DCB_DATAWIDTH_1 0x1
#define DCB_DATAWIDTH_2 0x2
#define DCB_DATAWIDTH_3 0x3
/* If set, all of DCBDATA will be moved, otherwise only DATAWIDTH bytes */
#define DCB_ENDATAPACK (1 << 2)
/* Enables DCBCRS auto increment after each DCB transfer */
#define DCB_ENCRSINC (1 << 3)
/* shift for accessing the control register select address (DBCCRS, 3 bits) */
#define DCB_CRS_SHIFT 4
/* DCBADDR (4 bits): display bus slave address */
#define DCB_ADDR_SHIFT 7
#define DCB_VC2 (0 << DCB_ADDR_SHIFT)
#define DCB_CMAP_ALL (1 << DCB_ADDR_SHIFT)
#define DCB_CMAP0 (2 << DCB_ADDR_SHIFT)
#define DCB_CMAP1 (3 << DCB_ADDR_SHIFT)
#define DCB_XMAP_ALL (4 << DCB_ADDR_SHIFT)
#define DCB_XMAP0 (5 << DCB_ADDR_SHIFT)
#define DCB_XMAP1 (6 << DCB_ADDR_SHIFT)
#define DCB_BT445 (7 << DCB_ADDR_SHIFT)
#define DCB_VCC1 (8 << DCB_ADDR_SHIFT)
#define DCB_VAB1 (9 << DCB_ADDR_SHIFT)
#define DCB_LG3_BDVERS0 (10 << DCB_ADDR_SHIFT)
#define DCB_LG3_ICS1562 (11 << DCB_ADDR_SHIFT)
#define DCB_RESERVED (15 << DCB_ADDR_SHIFT)
/* DCB protocol ack types */
#define DCB_ENSYNCACK (1 << 11)
#define DCB_ENASYNCACK (1 << 12)
#define DCB_CSWIDTH_SHIFT 13
#define DCB_CSHOLD_SHIFT 18
#define DCB_CSSETUP_SHIFT 23
/* XMAP9 specific defines */
/* XMAP9 -- registers as seen on the DCBMODE register*/
# define XM9_CRS_CONFIG (0 << DCB_CRS_SHIFT)
# define XM9_PUPMODE (1 << 0)
# define XM9_ODD_PIXEL (1 << 1)
# define XM9_8_BITPLANES (1 << 2)
# define XM9_SLOW_DCB (1 << 3)
# define XM9_VIDEO_RGBMAP_MASK (3 << 4)
# define XM9_EXPRESS_VIDEO (1 << 6)
# define XM9_VIDEO_OPTION (1 << 7)
# define XM9_CRS_REVISION (1 << DCB_CRS_SHIFT)
# define XM9_CRS_FIFO_AVAIL (2 << DCB_CRS_SHIFT)
# define XM9_FIFO_0_AVAIL 0
# define XM9_FIFO_1_AVAIL 1
# define XM9_FIFO_2_AVAIL 3
# define XM9_FIFO_3_AVAIL 2
# define XM9_FIFO_FULL XM9_FIFO_0_AVAIL
# define XM9_FIFO_EMPTY XM9_FIFO_3_AVAIL
# define XM9_CRS_CURS_CMAP_MSB (3 << DCB_CRS_SHIFT)
# define XM9_CRS_PUP_CMAP_MSB (4 << DCB_CRS_SHIFT)
# define XM9_CRS_MODE_REG_DATA (5 << DCB_CRS_SHIFT)
# define XM9_CRS_MODE_REG_INDEX (7 << DCB_CRS_SHIFT)
#define DCB_CYCLES(setup,hold,width) \
((hold << DCB_CSHOLD_SHIFT) | \
(setup << DCB_CSSETUP_SHIFT)| \
(width << DCB_CSWIDTH_SHIFT))
#define W_DCB_XMAP9_PROTOCOL DCB_CYCLES (2, 1, 0)
#define WSLOW_DCB_XMAP9_PROTOCOL DCB_CYCLES (5, 5, 0)
#define WAYSLOW_DCB_XMAP9_PROTOCOL DCB_CYCLES (12, 12, 0)
#define R_DCB_XMAP9_PROTOCOL DCB_CYCLES (2, 1, 3)
static __inline__ void
xmap9FIFOWait (struct newport_regs *rex)
{
rex->set.dcbmode = DCB_XMAP0 | XM9_CRS_FIFO_AVAIL |
DCB_DATAWIDTH_1 | R_DCB_XMAP9_PROTOCOL;
newport_bfwait (rex);
while ((rex->set.dcbdata0.bybytes.b3 & 3) != XM9_FIFO_EMPTY)
;
}
static __inline__ void
xmap9SetModeReg (struct newport_regs *rex, unsigned int modereg, unsigned int data24, int cfreq)
{
if (cfreq > 119)
rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA |
DCB_DATAWIDTH_4 | W_DCB_XMAP9_PROTOCOL;
else if (cfreq > 59)
rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA |
DCB_DATAWIDTH_4 | WSLOW_DCB_XMAP9_PROTOCOL;
else
rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA |
DCB_DATAWIDTH_4 | WAYSLOW_DCB_XMAP9_PROTOCOL;
rex->set.dcbdata0.byword = ((modereg) << 24) | (data24 & 0xffffff);
}
#define BT445_PROTOCOL DCB_CYCLES(1,1,3)
#define BT445_CSR_ADDR_REG (0 << DCB_CRS_SHIFT)
#define BT445_CSR_REVISION (2 << DCB_CRS_SHIFT)
#define BT445_REVISION_REG 0x01
#endif /* !(_SGI_NEWPORT_H) */

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/*
* Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>
*
* display timings of helpers
*
* This file is released under the GPLv2
*/
#ifndef __LINUX_OF_DISPLAY_TIMING_H
#define __LINUX_OF_DISPLAY_TIMING_H
struct device_node;
struct display_timing;
struct display_timings;
#define OF_USE_NATIVE_MODE -1
#ifdef CONFIG_OF
int of_get_display_timing(struct device_node *np, const char *name,
struct display_timing *dt);
struct display_timings *of_get_display_timings(struct device_node *np);
int of_display_timings_exist(struct device_node *np);
#else
static inline int of_get_display_timing(struct device_node *np, const char *name,
struct display_timing *dt)
{
return -ENOSYS;
}
static inline struct display_timings *of_get_display_timings(struct device_node *np)
{
return NULL;
}
static inline int of_display_timings_exist(struct device_node *np)
{
return -ENOSYS;
}
#endif
#endif

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/*
* Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>
*
* videomode of-helpers
*
* This file is released under the GPLv2
*/
#ifndef __LINUX_OF_VIDEOMODE_H
#define __LINUX_OF_VIDEOMODE_H
struct device_node;
struct videomode;
int of_get_videomode(struct device_node *np, struct videomode *vm,
int index);
#endif /* __LINUX_OF_VIDEOMODE_H */

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/*
* Header containing platform_data structs for omap panels
*
* Copyright (C) 2013 Texas Instruments
* Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
* Archit Taneja <archit@ti.com>
*
* Copyright (C) 2011 Texas Instruments
* Author: Mayuresh Janorkar <mayur@ti.com>
*
* Copyright (C) 2010 Canonical Ltd.
* Author: Bryan Wu <bryan.wu@canonical.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __OMAP_PANEL_DATA_H
#define __OMAP_PANEL_DATA_H
#include <video/omapdss.h>
#include <video/display_timing.h>
struct omap_dss_device;
/**
* encoder_tfp410 platform data
* @name: name for this display entity
* @power_down_gpio: gpio number for PD pin (or -1 if not available)
* @data_lines: number of DPI datalines
*/
struct encoder_tfp410_platform_data {
const char *name;
const char *source;
int power_down_gpio;
int data_lines;
};
/**
* encoder_tpd12s015 platform data
* @name: name for this display entity
* @ct_cp_hpd_gpio: CT_CP_HPD gpio number
* @ls_oe_gpio: LS_OE gpio number
* @hpd_gpio: HPD gpio number
*/
struct encoder_tpd12s015_platform_data {
const char *name;
const char *source;
int ct_cp_hpd_gpio;
int ls_oe_gpio;
int hpd_gpio;
};
/**
* connector_dvi platform data
* @name: name for this display entity
* @source: name of the display entity used as a video source
* @i2c_bus_num: i2c bus number to be used for reading EDID
*/
struct connector_dvi_platform_data {
const char *name;
const char *source;
int i2c_bus_num;
};
/**
* connector_hdmi platform data
* @name: name for this display entity
* @source: name of the display entity used as a video source
*/
struct connector_hdmi_platform_data {
const char *name;
const char *source;
};
/**
* connector_atv platform data
* @name: name for this display entity
* @source: name of the display entity used as a video source
* @connector_type: composite/svideo
* @invert_polarity: invert signal polarity
*/
struct connector_atv_platform_data {
const char *name;
const char *source;
enum omap_dss_venc_type connector_type;
bool invert_polarity;
};
/**
* panel_dpi platform data
* @name: name for this display entity
* @source: name of the display entity used as a video source
* @data_lines: number of DPI datalines
* @display_timing: timings for this panel
* @backlight_gpio: gpio to enable/disable the backlight (or -1)
* @enable_gpio: gpio to enable/disable the panel (or -1)
*/
struct panel_dpi_platform_data {
const char *name;
const char *source;
int data_lines;
const struct display_timing *display_timing;
int backlight_gpio;
int enable_gpio;
};
/**
* panel_dsicm platform data
* @name: name for this display entity
* @source: name of the display entity used as a video source
* @reset_gpio: gpio to reset the panel (or -1)
* @use_ext_te: use external TE GPIO
* @ext_te_gpio: external TE GPIO
* @ulps_timeout: time to wait before entering ULPS, 0 = disabled (ms)
* @use_dsi_backlight: true if panel uses DSI command to control backlight
* @pin_config: DSI pin configuration
*/
struct panel_dsicm_platform_data {
const char *name;
const char *source;
int reset_gpio;
bool use_ext_te;
int ext_te_gpio;
unsigned ulps_timeout;
bool use_dsi_backlight;
struct omap_dsi_pin_config pin_config;
};
/**
* panel_acx565akm platform data
* @name: name for this display entity
* @source: name of the display entity used as a video source
* @reset_gpio: gpio to reset the panel (or -1)
* @datapairs: number of SDI datapairs
*/
struct panel_acx565akm_platform_data {
const char *name;
const char *source;
int reset_gpio;
int datapairs;
};
/**
* panel_lb035q02 platform data
* @name: name for this display entity
* @source: name of the display entity used as a video source
* @data_lines: number of DPI datalines
* @backlight_gpio: gpio to enable/disable the backlight (or -1)
* @enable_gpio: gpio to enable/disable the panel (or -1)
*/
struct panel_lb035q02_platform_data {
const char *name;
const char *source;
int data_lines;
int backlight_gpio;
int enable_gpio;
};
/**
* panel_sharp_ls037v7dw01 platform data
* @name: name for this display entity
* @source: name of the display entity used as a video source
* @data_lines: number of DPI datalines
* @resb_gpio: reset signal GPIO
* @ini_gpio: power on control GPIO
* @mo_gpio: selection for resolution(VGA/QVGA) GPIO
* @lr_gpio: selection for horizontal scanning direction GPIO
* @ud_gpio: selection for vertical scanning direction GPIO
*/
struct panel_sharp_ls037v7dw01_platform_data {
const char *name;
const char *source;
int data_lines;
int resb_gpio;
int ini_gpio;
int mo_gpio;
int lr_gpio;
int ud_gpio;
};
/**
* panel-tpo-td043mtea1 platform data
* @name: name for this display entity
* @source: name of the display entity used as a video source
* @data_lines: number of DPI datalines
* @nreset_gpio: reset signal
*/
struct panel_tpo_td043mtea1_platform_data {
const char *name;
const char *source;
int data_lines;
int nreset_gpio;
};
/**
* panel-nec-nl8048hl11 platform data
* @name: name for this display entity
* @source: name of the display entity used as a video source
* @data_lines: number of DPI datalines
* @res_gpio: reset signal
* @qvga_gpio: selection for resolution(QVGA/WVGA)
*/
struct panel_nec_nl8048hl11_platform_data {
const char *name;
const char *source;
int data_lines;
int res_gpio;
int qvga_gpio;
};
/**
* panel-tpo-td028ttec1 platform data
* @name: name for display entity
* @source: name of the display entity used as a video source
* @data_lines: number of DPI datalines
*/
struct panel_tpo_td028ttec1_platform_data {
const char *name;
const char *source;
int data_lines;
};
#endif /* __OMAP_PANEL_DATA_H */

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/*
* VRFB Rotation Engine
*
* Copyright (C) 2009 Nokia Corporation
* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef __OMAP_VRFB_H__
#define __OMAP_VRFB_H__
#define OMAP_VRFB_LINE_LEN 2048
struct vrfb {
u8 context;
void __iomem *vaddr[4];
unsigned long paddr[4];
u16 xres;
u16 yres;
u16 xoffset;
u16 yoffset;
u8 bytespp;
bool yuv_mode;
};
#ifdef CONFIG_OMAP2_VRFB
extern bool omap_vrfb_supported(void);
extern int omap_vrfb_request_ctx(struct vrfb *vrfb);
extern void omap_vrfb_release_ctx(struct vrfb *vrfb);
extern void omap_vrfb_adjust_size(u16 *width, u16 *height,
u8 bytespp);
extern u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp);
extern u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp);
extern void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
u16 width, u16 height,
unsigned bytespp, bool yuv_mode);
extern int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot);
extern void omap_vrfb_restore_context(void);
#else
static inline bool omap_vrfb_supported(void) { return false; }
static inline int omap_vrfb_request_ctx(struct vrfb *vrfb) { return 0; }
static inline void omap_vrfb_release_ctx(struct vrfb *vrfb) {}
static inline void omap_vrfb_adjust_size(u16 *width, u16 *height,
u8 bytespp) {}
static inline u32 omap_vrfb_min_phys_size(u16 width, u16 height, u8 bytespp)
{ return 0; }
static inline u16 omap_vrfb_max_height(u32 phys_size, u16 width, u8 bytespp)
{ return 0; }
static inline void omap_vrfb_setup(struct vrfb *vrfb, unsigned long paddr,
u16 width, u16 height, unsigned bytespp, bool yuv_mode) {}
static inline int omap_vrfb_map_angle(struct vrfb *vrfb, u16 height, u8 rot)
{ return 0; }
static inline void omap_vrfb_restore_context(void) {}
#endif
#endif /* __VRFB_H */

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/*
* Permedia2 framebuffer driver definitions.
* Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
* --------------------------------------------------------------------------
* $Id: pm2fb.h,v 1.26 2000/09/19 00:11:53 illo Exp $
* --------------------------------------------------------------------------
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#ifndef PM2FB_H
#define PM2FB_H
#define PM2_REFERENCE_CLOCK 14318 /* in KHz */
#define PM2_MAX_PIXCLOCK 230000 /* in KHz */
#define PM2_REGS_SIZE 0x10000
#define PM2TAG(r) (u32 )(((r)-0x8000)>>3)
/*****************************************************************************
* Permedia2 registers used in the framebuffer
*****************************************************************************/
#define PM2R_RESET_STATUS 0x0000
#define PM2R_IN_FIFO_SPACE 0x0018
#define PM2R_OUT_FIFO_WORDS 0x0020
#define PM2R_APERTURE_ONE 0x0050
#define PM2R_APERTURE_TWO 0x0058
#define PM2R_FIFO_DISCON 0x0068
#define PM2R_CHIP_CONFIG 0x0070
#define PM2R_REBOOT 0x1000
#define PM2R_MEM_CONTROL 0x1040
#define PM2R_BOOT_ADDRESS 0x1080
#define PM2R_MEM_CONFIG 0x10c0
#define PM2R_BYPASS_WRITE_MASK 0x1100
#define PM2R_FRAMEBUFFER_WRITE_MASK 0x1140
#define PM2R_OUT_FIFO 0x2000
#define PM2R_SCREEN_BASE 0x3000
#define PM2R_SCREEN_STRIDE 0x3008
#define PM2R_H_TOTAL 0x3010
#define PM2R_HG_END 0x3018
#define PM2R_HB_END 0x3020
#define PM2R_HS_START 0x3028
#define PM2R_HS_END 0x3030
#define PM2R_V_TOTAL 0x3038
#define PM2R_VB_END 0x3040
#define PM2R_VS_START 0x3048
#define PM2R_VS_END 0x3050
#define PM2R_VIDEO_CONTROL 0x3058
#define PM2R_LINE_COUNT 0x3070
#define PM2R_FIFO_CONTROL 0x3078
#define PM2R_RD_PALETTE_WRITE_ADDRESS 0x4000
#define PM2R_RD_PALETTE_DATA 0x4008
#define PM2R_RD_PIXEL_MASK 0x4010
#define PM2R_RD_PALETTE_READ_ADDRESS 0x4018
#define PM2R_RD_CURSOR_COLOR_ADDRESS 0x4020
#define PM2R_RD_CURSOR_COLOR_DATA 0x4028
#define PM2R_RD_INDEXED_DATA 0x4050
#define PM2R_RD_CURSOR_DATA 0x4058
#define PM2R_RD_CURSOR_X_LSB 0x4060
#define PM2R_RD_CURSOR_X_MSB 0x4068
#define PM2R_RD_CURSOR_Y_LSB 0x4070
#define PM2R_RD_CURSOR_Y_MSB 0x4078
#define PM2R_START_X_DOM 0x8000
#define PM2R_D_X_DOM 0x8008
#define PM2R_START_X_SUB 0x8010
#define PM2R_D_X_SUB 0x8018
#define PM2R_START_Y 0x8020
#define PM2R_D_Y 0x8028
#define PM2R_COUNT 0x8030
#define PM2R_RENDER 0x8038
#define PM2R_BIT_MASK_PATTERN 0x8068
#define PM2R_RASTERIZER_MODE 0x80a0
#define PM2R_RECTANGLE_ORIGIN 0x80d0
#define PM2R_RECTANGLE_SIZE 0x80d8
#define PM2R_PACKED_DATA_LIMITS 0x8150
#define PM2R_SCISSOR_MODE 0x8180
#define PM2R_SCISSOR_MIN_XY 0x8188
#define PM2R_SCISSOR_MAX_XY 0x8190
#define PM2R_SCREEN_SIZE 0x8198
#define PM2R_AREA_STIPPLE_MODE 0x81a0
#define PM2R_WINDOW_ORIGIN 0x81c8
#define PM2R_TEXTURE_ADDRESS_MODE 0x8380
#define PM2R_TEXTURE_MAP_FORMAT 0x8588
#define PM2R_TEXTURE_DATA_FORMAT 0x8590
#define PM2R_TEXTURE_READ_MODE 0x8670
#define PM2R_TEXEL_LUT_MODE 0x8678
#define PM2R_TEXTURE_COLOR_MODE 0x8680
#define PM2R_FOG_MODE 0x8690
#define PM2R_TEXEL0 0x8760
#define PM2R_COLOR_DDA_MODE 0x87e0
#define PM2R_CONSTANT_COLOR 0x87e8
#define PM2R_ALPHA_BLEND_MODE 0x8810
#define PM2R_DITHER_MODE 0x8818
#define PM2R_FB_SOFT_WRITE_MASK 0x8820
#define PM2R_LOGICAL_OP_MODE 0x8828
#define PM2R_LB_READ_MODE 0x8880
#define PM2R_LB_READ_FORMAT 0x8888
#define PM2R_LB_SOURCE_OFFSET 0x8890
#define PM2R_LB_WINDOW_BASE 0x88b8
#define PM2R_LB_WRITE_FORMAT 0x88c8
#define PM2R_STENCIL_MODE 0x8988
#define PM2R_DEPTH_MODE 0x89a0
#define PM2R_FB_READ_MODE 0x8a80
#define PM2R_FB_SOURCE_OFFSET 0x8a88
#define PM2R_FB_PIXEL_OFFSET 0x8a90
#define PM2R_FB_WINDOW_BASE 0x8ab0
#define PM2R_FB_WRITE_MODE 0x8ab8
#define PM2R_FB_HARD_WRITE_MASK 0x8ac0
#define PM2R_FB_BLOCK_COLOR 0x8ac8
#define PM2R_FB_READ_PIXEL 0x8ad0
#define PM2R_FILTER_MODE 0x8c00
#define PM2R_SYNC 0x8c40
#define PM2R_YUV_MODE 0x8f00
#define PM2R_STATISTICS_MODE 0x8c08
#define PM2R_FB_SOURCE_DELTA 0x8d88
#define PM2R_CONFIG 0x8d90
#define PM2R_DELTA_MODE 0x9300
/* Permedia2v */
#define PM2VR_RD_INDEX_LOW 0x4020
#define PM2VR_RD_INDEX_HIGH 0x4028
#define PM2VR_RD_INDEXED_DATA 0x4030
/* Permedia2 RAMDAC indexed registers */
#define PM2I_RD_CURSOR_CONTROL 0x06
#define PM2I_RD_COLOR_MODE 0x18
#define PM2I_RD_MODE_CONTROL 0x19
#define PM2I_RD_MISC_CONTROL 0x1e
#define PM2I_RD_PIXEL_CLOCK_A1 0x20
#define PM2I_RD_PIXEL_CLOCK_A2 0x21
#define PM2I_RD_PIXEL_CLOCK_A3 0x22
#define PM2I_RD_PIXEL_CLOCK_STATUS 0x29
#define PM2I_RD_MEMORY_CLOCK_1 0x30
#define PM2I_RD_MEMORY_CLOCK_2 0x31
#define PM2I_RD_MEMORY_CLOCK_3 0x32
#define PM2I_RD_MEMORY_CLOCK_STATUS 0x33
#define PM2I_RD_COLOR_KEY_CONTROL 0x40
#define PM2I_RD_OVERLAY_KEY 0x41
#define PM2I_RD_RED_KEY 0x42
#define PM2I_RD_GREEN_KEY 0x43
#define PM2I_RD_BLUE_KEY 0x44
/* Permedia2v extensions */
#define PM2VI_RD_MISC_CONTROL 0x000
#define PM2VI_RD_SYNC_CONTROL 0x001
#define PM2VI_RD_DAC_CONTROL 0x002
#define PM2VI_RD_PIXEL_SIZE 0x003
#define PM2VI_RD_COLOR_FORMAT 0x004
#define PM2VI_RD_CURSOR_MODE 0x005
#define PM2VI_RD_CURSOR_X_LOW 0x007
#define PM2VI_RD_CURSOR_X_HIGH 0x008
#define PM2VI_RD_CURSOR_Y_LOW 0x009
#define PM2VI_RD_CURSOR_Y_HIGH 0x00A
#define PM2VI_RD_CURSOR_X_HOT 0x00B
#define PM2VI_RD_CURSOR_Y_HOT 0x00C
#define PM2VI_RD_OVERLAY_KEY 0x00D
#define PM2VI_RD_CLK0_PRESCALE 0x201
#define PM2VI_RD_CLK0_FEEDBACK 0x202
#define PM2VI_RD_CLK0_POSTSCALE 0x203
#define PM2VI_RD_CLK1_PRESCALE 0x204
#define PM2VI_RD_CLK1_FEEDBACK 0x205
#define PM2VI_RD_CLK1_POSTSCALE 0x206
#define PM2VI_RD_MCLK_CONTROL 0x20D
#define PM2VI_RD_MCLK_PRESCALE 0x20E
#define PM2VI_RD_MCLK_FEEDBACK 0x20F
#define PM2VI_RD_MCLK_POSTSCALE 0x210
#define PM2VI_RD_CURSOR_PALETTE 0x303
#define PM2VI_RD_CURSOR_PATTERN 0x400
/* Fields and flags */
#define PM2F_RENDER_AREASTIPPLE (1L<<0)
#define PM2F_RENDER_FASTFILL (1L<<3)
#define PM2F_RENDER_PRIMITIVE_MASK (3L<<6)
#define PM2F_RENDER_LINE 0
#define PM2F_RENDER_TRAPEZOID (1L<<6)
#define PM2F_RENDER_POINT (2L<<6)
#define PM2F_RENDER_RECTANGLE (3L<<6)
#define PM2F_RENDER_SYNC_ON_BIT_MASK (1L<<11)
#define PM2F_RENDER_TEXTURE_ENABLE (1L<<13)
#define PM2F_SYNCHRONIZATION (1L<<10)
#define PM2F_PLL_LOCKED 0x10
#define PM2F_BEING_RESET (1L<<31)
#define PM2F_DATATYPE_COLOR 0x8000
#define PM2F_VGA_ENABLE 0x02
#define PM2F_VGA_FIXED 0x04
#define PM2F_FB_WRITE_ENABLE 0x01
#define PM2F_FB_READ_SOURCE_ENABLE 0x0200
#define PM2F_RD_PALETTE_WIDTH_8 0x02
#define PM2F_PART_PROD_MASK 0x01ff
#define PM2F_SCREEN_SCISSOR_ENABLE 0x02
#define PM2F_DATA_64_ENABLE 0x00010000
#define PM2F_BLANK_LOW 0x02
#define PM2F_HSYNC_MASK 0x18
#define PM2F_VSYNC_MASK 0x60
#define PM2F_HSYNC_ACT_HIGH 0x08
#define PM2F_HSYNC_FORCED_LOW 0x10
#define PM2F_HSYNC_ACT_LOW 0x18
#define PM2F_VSYNC_ACT_HIGH 0x20
#define PM2F_VSYNC_FORCED_LOW 0x40
#define PM2F_VSYNC_ACT_LOW 0x60
#define PM2F_LINE_DOUBLE 0x04
#define PM2F_VIDEO_ENABLE 0x01
#define PM2F_RD_PIXELFORMAT_SVGA 0x01
#define PM2F_RD_PIXELFORMAT_RGB232OFFSET 0x02
#define PM2F_RD_PIXELFORMAT_RGBA2321 0x03
#define PM2F_RD_PIXELFORMAT_RGBA5551 0x04
#define PM2F_RD_PIXELFORMAT_RGBA4444 0x05
#define PM2F_RD_PIXELFORMAT_RGB565 0x06
#define PM2F_RD_PIXELFORMAT_RGBA8888 0x08
#define PM2F_RD_PIXELFORMAT_RGB888 0x09
#define PM2F_RD_GUI_ACTIVE 0x10
#define PM2F_RD_COLOR_MODE_RGB 0x20
#define PM2F_DELTA_ORDER_RGB (1L<<18)
#define PM2F_RD_TRUECOLOR 0x80
#define PM2F_NO_ALPHA_BUFFER 0x10
#define PM2F_TEXTEL_SIZE_16 0x00080000
#define PM2F_TEXTEL_SIZE_32 0x00100000
#define PM2F_TEXTEL_SIZE_4 0x00180000
#define PM2F_TEXTEL_SIZE_24 0x00200000
#define PM2F_INCREASE_X (1L<<21)
#define PM2F_INCREASE_Y (1L<<22)
#define PM2F_CONFIG_FB_WRITE_ENABLE (1L<<3)
#define PM2F_CONFIG_FB_PACKED_DATA (1L<<2)
#define PM2F_CONFIG_FB_READ_DEST_ENABLE (1L<<1)
#define PM2F_CONFIG_FB_READ_SOURCE_ENABLE (1L<<0)
#define PM2F_COLOR_KEY_TEST_OFF (1L<<4)
#define PM2F_MEM_CONFIG_RAM_MASK (3L<<29)
#define PM2F_MEM_BANKS_1 0L
#define PM2F_MEM_BANKS_2 (1L<<29)
#define PM2F_MEM_BANKS_3 (2L<<29)
#define PM2F_MEM_BANKS_4 (3L<<29)
#define PM2F_APERTURE_STANDARD 0
#define PM2F_APERTURE_BYTESWAP 1
#define PM2F_APERTURE_HALFWORDSWAP 2
#define PM2F_CURSORMODE_CURSOR_ENABLE (1 << 0)
#define PM2F_CURSORMODE_TYPE_X (1 << 4)
typedef enum {
PM2_TYPE_PERMEDIA2,
PM2_TYPE_PERMEDIA2V
} pm2type_t;
#endif /* PM2FB_H */
/*****************************************************************************
* That's all folks!
*****************************************************************************/

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/* include/video/platform_lcd.h
*
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* Generic platform-device LCD power control interface.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
struct plat_lcd_data;
struct fb_info;
struct plat_lcd_data {
int (*probe)(struct plat_lcd_data *);
void (*set_power)(struct plat_lcd_data *, unsigned int power);
int (*match_fb)(struct plat_lcd_data *, struct fb_info *);
};

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/*
* linux/include/video/pmag-ba-fb.h
*
* TURBOchannel PMAG-BA Color Frame Buffer (CFB) card support,
* Copyright (C) 1999, 2000, 2001 by
* Michael Engel <engel@unix-ag.org>,
* Karsten Merker <merker@linuxtag.org>
* Copyright (c) 2005 Maciej W. Rozycki
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*/
/* IOmem resource offsets. */
#define PMAG_BA_FBMEM 0x000000 /* frame buffer */
#define PMAG_BA_BT459 0x200000 /* Bt459 RAMDAC */
#define PMAG_BA_IRQ 0x300000 /* IRQ acknowledge */
#define PMAG_BA_ROM 0x380000 /* REX option ROM */
#define PMAG_BA_BT438 0x380000 /* Bt438 clock chip reset */
#define PMAG_BA_SIZE 0x400000 /* address space size */
/* Bt459 register offsets, byte-wide registers. */
#define BT459_ADDR_LO 0x0 /* address low */
#define BT459_ADDR_HI 0x4 /* address high */
#define BT459_DATA 0x8 /* data window register */
#define BT459_CMAP 0xc /* color map window register */

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/*
* linux/include/video/pmagb-b-fb.h
*
* TURBOchannel PMAGB-B Smart Frame Buffer (SFB) card support,
* Copyright (C) 1999, 2000, 2001 by
* Michael Engel <engel@unix-ag.org> and
* Karsten Merker <merker@linuxtag.org>
* Copyright (c) 2005 Maciej W. Rozycki
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*/
/* IOmem resource offsets. */
#define PMAGB_B_ROM 0x000000 /* REX option ROM */
#define PMAGB_B_SFB 0x100000 /* SFB ASIC */
#define PMAGB_B_GP0 0x140000 /* general purpose output 0 */
#define PMAGB_B_GP1 0x180000 /* general purpose output 1 */
#define PMAGB_B_BT459 0x1c0000 /* Bt459 RAMDAC */
#define PMAGB_B_FBMEM 0x200000 /* frame buffer */
#define PMAGB_B_SIZE 0x400000 /* address space size */
/* IOmem register offsets. */
#define SFB_REG_VID_HOR 0x64 /* video horizontal setup */
#define SFB_REG_VID_VER 0x68 /* video vertical setup */
#define SFB_REG_VID_BASE 0x6c /* video base address */
#define SFB_REG_TCCLK_COUNT 0x78 /* TURBOchannel clock count */
#define SFB_REG_VIDCLK_COUNT 0x7c /* video clock count */
/* Video horizontal setup register constants. All bits are r/w. */
#define SFB_VID_HOR_BP_SHIFT 0x15 /* back porch */
#define SFB_VID_HOR_BP_MASK 0x7f
#define SFB_VID_HOR_SYN_SHIFT 0x0e /* sync pulse */
#define SFB_VID_HOR_SYN_MASK 0x7f
#define SFB_VID_HOR_FP_SHIFT 0x09 /* front porch */
#define SFB_VID_HOR_FP_MASK 0x1f
#define SFB_VID_HOR_PIX_SHIFT 0x00 /* active video */
#define SFB_VID_HOR_PIX_MASK 0x1ff
/* Video vertical setup register constants. All bits are r/w. */
#define SFB_VID_VER_BP_SHIFT 0x16 /* back porch */
#define SFB_VID_VER_BP_MASK 0x3f
#define SFB_VID_VER_SYN_SHIFT 0x10 /* sync pulse */
#define SFB_VID_VER_SYN_MASK 0x3f
#define SFB_VID_VER_FP_SHIFT 0x0b /* front porch */
#define SFB_VID_VER_FP_MASK 0x1f
#define SFB_VID_VER_SL_SHIFT 0x00 /* active scan lines */
#define SFB_VID_VER_SL_MASK 0x7ff
/* Video base address register constants. All bits are r/w. */
#define SFB_VID_BASE_MASK 0x1ff /* video base row address */
/* Bt459 register offsets, byte-wide registers. */
#define BT459_ADDR_LO 0x0 /* address low */
#define BT459_ADDR_HI 0x4 /* address high */
#define BT459_DATA 0x8 /* data window register */
#define BT459_CMAP 0xc /* color map window register */

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/*
* Copyright (C) 2009 Marvell International Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_MACH_PXA168FB_H
#define __ASM_MACH_PXA168FB_H
#include <linux/fb.h>
#include <linux/interrupt.h>
/* Dumb interface */
#define PIN_MODE_DUMB_24 0
#define PIN_MODE_DUMB_18_SPI 1
#define PIN_MODE_DUMB_18_GPIO 2
#define PIN_MODE_DUMB_16_SPI 3
#define PIN_MODE_DUMB_16_GPIO 4
#define PIN_MODE_DUMB_12_SPI_GPIO 5
#define PIN_MODE_SMART_18_SPI 6
#define PIN_MODE_SMART_16_SPI 7
#define PIN_MODE_SMART_8_SPI_GPIO 8
/* Dumb interface pin allocation */
#define DUMB_MODE_RGB565 0
#define DUMB_MODE_RGB565_UPPER 1
#define DUMB_MODE_RGB666 2
#define DUMB_MODE_RGB666_UPPER 3
#define DUMB_MODE_RGB444 4
#define DUMB_MODE_RGB444_UPPER 5
#define DUMB_MODE_RGB888 6
/* default fb buffer size WVGA-32bits */
#define DEFAULT_FB_SIZE (800 * 480 * 4)
/*
* Buffer pixel format
* bit0 is for rb swap.
* bit12 is for Y UorV swap
*/
#define PIX_FMT_RGB565 0
#define PIX_FMT_BGR565 1
#define PIX_FMT_RGB1555 2
#define PIX_FMT_BGR1555 3
#define PIX_FMT_RGB888PACK 4
#define PIX_FMT_BGR888PACK 5
#define PIX_FMT_RGB888UNPACK 6
#define PIX_FMT_BGR888UNPACK 7
#define PIX_FMT_RGBA888 8
#define PIX_FMT_BGRA888 9
#define PIX_FMT_YUV422PACK 10
#define PIX_FMT_YVU422PACK 11
#define PIX_FMT_YUV422PLANAR 12
#define PIX_FMT_YVU422PLANAR 13
#define PIX_FMT_YUV420PLANAR 14
#define PIX_FMT_YVU420PLANAR 15
#define PIX_FMT_PSEUDOCOLOR 20
#define PIX_FMT_UYVY422PACK (0x1000|PIX_FMT_YUV422PACK)
/*
* PXA LCD controller private state.
*/
struct pxa168fb_info {
struct device *dev;
struct clk *clk;
struct fb_info *info;
void __iomem *reg_base;
dma_addr_t fb_start_dma;
u32 pseudo_palette[16];
int pix_fmt;
unsigned is_blanked:1;
unsigned panel_rbswap:1;
unsigned active:1;
};
/*
* PXA fb machine information
*/
struct pxa168fb_mach_info {
char id[16];
int num_modes;
struct fb_videomode *modes;
/*
* Pix_fmt
*/
unsigned pix_fmt;
/*
* I/O pin allocation.
*/
unsigned io_pin_allocation_mode:4;
/*
* Dumb panel -- assignment of R/G/B component info to the 24
* available external data lanes.
*/
unsigned dumb_mode:4;
unsigned panel_rgb_reverse_lanes:1;
/*
* Dumb panel -- GPIO output data.
*/
unsigned gpio_output_mask:8;
unsigned gpio_output_data:8;
/*
* Dumb panel -- configurable output signal polarity.
*/
unsigned invert_composite_blank:1;
unsigned invert_pix_val_ena:1;
unsigned invert_pixclock:1;
unsigned panel_rbswap:1;
unsigned active:1;
unsigned enable_lcd:1;
};
#endif /* __ASM_MACH_PXA168FB_H */

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/* include/video/s1d13xxxfb.h
*
* (c) 2004 Simtec Electronics
* (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
*
* Header file for Epson S1D13XXX driver code
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#ifndef S1D13XXXFB_H
#define S1D13XXXFB_H
#define S1D_PALETTE_SIZE 256
#define S1D_FBID "S1D13xxx"
#define S1D_DEVICENAME "s1d13xxxfb"
/* S1DREG_REV_CODE register = prod_id (6 bits) + revision (2 bits) */
#define S1D13505_PROD_ID 0x3 /* 000011 */
#define S1D13506_PROD_ID 0x4 /* 000100 */
#define S1D13806_PROD_ID 0x7 /* 000111 */
/* register definitions (tested on s1d13896) */
#define S1DREG_REV_CODE 0x0000 /* Prod + Rev Code Register */
#define S1DREG_MISC 0x0001 /* Miscellaneous Register */
#define S1DREG_GPIO_CNF0 0x0004 /* General IO Pins Configuration Register 0 */
#define S1DREG_GPIO_CNF1 0x0005 /* General IO Pins Configuration Register 1 */
#define S1DREG_GPIO_CTL0 0x0008 /* General IO Pins Control Register 0 */
#define S1DREG_GPIO_CTL1 0x0009 /* General IO Pins Control Register 1 */
#define S1DREG_CNF_STATUS 0x000C /* Configuration Status Readback Register */
#define S1DREG_CLK_CNF 0x0010 /* Memory Clock Configuration Register */
#define S1DREG_LCD_CLK_CNF 0x0014 /* LCD Pixel Clock Configuration Register */
#define S1DREG_CRT_CLK_CNF 0x0018 /* CRT/TV Pixel Clock Configuration Register */
#define S1DREG_MPLUG_CLK_CNF 0x001C /* MediaPlug Clock Configuration Register */
#define S1DREG_CPU2MEM_WST_SEL 0x001E /* CPU To Memory Wait State Select Register */
#define S1DREG_MEM_CNF 0x0020 /* Memory Configuration Register */
#define S1DREG_SDRAM_REF_RATE 0x0021 /* SDRAM Refresh Rate Register */
#define S1DREG_SDRAM_TC0 0x002A /* SDRAM Timing Control Register 0 */
#define S1DREG_SDRAM_TC1 0x002B /* SDRAM Timing Control Register 1 */
#define S1DREG_PANEL_TYPE 0x0030 /* Panel Type Register */
#define S1DREG_MOD_RATE 0x0031 /* MOD Rate Register */
#define S1DREG_LCD_DISP_HWIDTH 0x0032 /* LCD Horizontal Display Width Register: ((val)+1)*8)=pix/line */
#define S1DREG_LCD_NDISP_HPER 0x0034 /* LCD Horizontal Non-Display Period Register: ((val)+1)*8)=NDpix/line */
#define S1DREG_TFT_FPLINE_START 0x0035 /* TFT FPLINE Start Position Register */
#define S1DREG_TFT_FPLINE_PWIDTH 0x0036 /* TFT FPLINE Pulse Width Register. */
#define S1DREG_LCD_DISP_VHEIGHT0 0x0038 /* LCD Vertical Display Height Register 0 */
#define S1DREG_LCD_DISP_VHEIGHT1 0x0039 /* LCD Vertical Display Height Register 1 */
#define S1DREG_LCD_NDISP_VPER 0x003A /* LCD Vertical Non-Display Period Register: (val)+1=NDlines */
#define S1DREG_TFT_FPFRAME_START 0x003B /* TFT FPFRAME Start Position Register */
#define S1DREG_TFT_FPFRAME_PWIDTH 0x003C /* TFT FPFRAME Pulse Width Register */
#define S1DREG_LCD_DISP_MODE 0x0040 /* LCD Display Mode Register */
#define S1DREG_LCD_MISC 0x0041 /* LCD Miscellaneous Register */
#define S1DREG_LCD_DISP_START0 0x0042 /* LCD Display Start Address Register 0 */
#define S1DREG_LCD_DISP_START1 0x0043 /* LCD Display Start Address Register 1 */
#define S1DREG_LCD_DISP_START2 0x0044 /* LCD Display Start Address Register 2 */
#define S1DREG_LCD_MEM_OFF0 0x0046 /* LCD Memory Address Offset Register 0 */
#define S1DREG_LCD_MEM_OFF1 0x0047 /* LCD Memory Address Offset Register 1 */
#define S1DREG_LCD_PIX_PAN 0x0048 /* LCD Pixel Panning Register */
#define S1DREG_LCD_DISP_FIFO_HTC 0x004A /* LCD Display FIFO High Threshold Control Register */
#define S1DREG_LCD_DISP_FIFO_LTC 0x004B /* LCD Display FIFO Low Threshold Control Register */
#define S1DREG_CRT_DISP_HWIDTH 0x0050 /* CRT/TV Horizontal Display Width Register: ((val)+1)*8)=pix/line */
#define S1DREG_CRT_NDISP_HPER 0x0052 /* CRT/TV Horizontal Non-Display Period Register */
#define S1DREG_CRT_HRTC_START 0x0053 /* CRT/TV HRTC Start Position Register */
#define S1DREG_CRT_HRTC_PWIDTH 0x0054 /* CRT/TV HRTC Pulse Width Register */
#define S1DREG_CRT_DISP_VHEIGHT0 0x0056 /* CRT/TV Vertical Display Height Register 0 */
#define S1DREG_CRT_DISP_VHEIGHT1 0x0057 /* CRT/TV Vertical Display Height Register 1 */
#define S1DREG_CRT_NDISP_VPER 0x0058 /* CRT/TV Vertical Non-Display Period Register */
#define S1DREG_CRT_VRTC_START 0x0059 /* CRT/TV VRTC Start Position Register */
#define S1DREG_CRT_VRTC_PWIDTH 0x005A /* CRT/TV VRTC Pulse Width Register */
#define S1DREG_TV_OUT_CTL 0x005B /* TV Output Control Register */
#define S1DREG_CRT_DISP_MODE 0x0060 /* CRT/TV Display Mode Register */
#define S1DREG_CRT_DISP_START0 0x0062 /* CRT/TV Display Start Address Register 0 */
#define S1DREG_CRT_DISP_START1 0x0063 /* CRT/TV Display Start Address Register 1 */
#define S1DREG_CRT_DISP_START2 0x0064 /* CRT/TV Display Start Address Register 2 */
#define S1DREG_CRT_MEM_OFF0 0x0066 /* CRT/TV Memory Address Offset Register 0 */
#define S1DREG_CRT_MEM_OFF1 0x0067 /* CRT/TV Memory Address Offset Register 1 */
#define S1DREG_CRT_PIX_PAN 0x0068 /* CRT/TV Pixel Panning Register */
#define S1DREG_CRT_DISP_FIFO_HTC 0x006A /* CRT/TV Display FIFO High Threshold Control Register */
#define S1DREG_CRT_DISP_FIFO_LTC 0x006B /* CRT/TV Display FIFO Low Threshold Control Register */
#define S1DREG_LCD_CUR_CTL 0x0070 /* LCD Ink/Cursor Control Register */
#define S1DREG_LCD_CUR_START 0x0071 /* LCD Ink/Cursor Start Address Register */
#define S1DREG_LCD_CUR_XPOS0 0x0072 /* LCD Cursor X Position Register 0 */
#define S1DREG_LCD_CUR_XPOS1 0x0073 /* LCD Cursor X Position Register 1 */
#define S1DREG_LCD_CUR_YPOS0 0x0074 /* LCD Cursor Y Position Register 0 */
#define S1DREG_LCD_CUR_YPOS1 0x0075 /* LCD Cursor Y Position Register 1 */
#define S1DREG_LCD_CUR_BCTL0 0x0076 /* LCD Ink/Cursor Blue Color 0 Register */
#define S1DREG_LCD_CUR_GCTL0 0x0077 /* LCD Ink/Cursor Green Color 0 Register */
#define S1DREG_LCD_CUR_RCTL0 0x0078 /* LCD Ink/Cursor Red Color 0 Register */
#define S1DREG_LCD_CUR_BCTL1 0x007A /* LCD Ink/Cursor Blue Color 1 Register */
#define S1DREG_LCD_CUR_GCTL1 0x007B /* LCD Ink/Cursor Green Color 1 Register */
#define S1DREG_LCD_CUR_RCTL1 0x007C /* LCD Ink/Cursor Red Color 1 Register */
#define S1DREG_LCD_CUR_FIFO_HTC 0x007E /* LCD Ink/Cursor FIFO High Threshold Register */
#define S1DREG_CRT_CUR_CTL 0x0080 /* CRT/TV Ink/Cursor Control Register */
#define S1DREG_CRT_CUR_START 0x0081 /* CRT/TV Ink/Cursor Start Address Register */
#define S1DREG_CRT_CUR_XPOS0 0x0082 /* CRT/TV Cursor X Position Register 0 */
#define S1DREG_CRT_CUR_XPOS1 0x0083 /* CRT/TV Cursor X Position Register 1 */
#define S1DREG_CRT_CUR_YPOS0 0x0084 /* CRT/TV Cursor Y Position Register 0 */
#define S1DREG_CRT_CUR_YPOS1 0x0085 /* CRT/TV Cursor Y Position Register 1 */
#define S1DREG_CRT_CUR_BCTL0 0x0086 /* CRT/TV Ink/Cursor Blue Color 0 Register */
#define S1DREG_CRT_CUR_GCTL0 0x0087 /* CRT/TV Ink/Cursor Green Color 0 Register */
#define S1DREG_CRT_CUR_RCTL0 0x0088 /* CRT/TV Ink/Cursor Red Color 0 Register */
#define S1DREG_CRT_CUR_BCTL1 0x008A /* CRT/TV Ink/Cursor Blue Color 1 Register */
#define S1DREG_CRT_CUR_GCTL1 0x008B /* CRT/TV Ink/Cursor Green Color 1 Register */
#define S1DREG_CRT_CUR_RCTL1 0x008C /* CRT/TV Ink/Cursor Red Color 1 Register */
#define S1DREG_CRT_CUR_FIFO_HTC 0x008E /* CRT/TV Ink/Cursor FIFO High Threshold Register */
#define S1DREG_BBLT_CTL0 0x0100 /* BitBLT Control Register 0 */
#define S1DREG_BBLT_CTL1 0x0101 /* BitBLT Control Register 1 */
#define S1DREG_BBLT_CC_EXP 0x0102 /* BitBLT Code/Color Expansion Register */
#define S1DREG_BBLT_OP 0x0103 /* BitBLT Operation Register */
#define S1DREG_BBLT_SRC_START0 0x0104 /* BitBLT Source Start Address Register 0 */
#define S1DREG_BBLT_SRC_START1 0x0105 /* BitBLT Source Start Address Register 1 */
#define S1DREG_BBLT_SRC_START2 0x0106 /* BitBLT Source Start Address Register 2 */
#define S1DREG_BBLT_DST_START0 0x0108 /* BitBLT Destination Start Address Register 0 */
#define S1DREG_BBLT_DST_START1 0x0109 /* BitBLT Destination Start Address Register 1 */
#define S1DREG_BBLT_DST_START2 0x010A /* BitBLT Destination Start Address Register 2 */
#define S1DREG_BBLT_MEM_OFF0 0x010C /* BitBLT Memory Address Offset Register 0 */
#define S1DREG_BBLT_MEM_OFF1 0x010D /* BitBLT Memory Address Offset Register 1 */
#define S1DREG_BBLT_WIDTH0 0x0110 /* BitBLT Width Register 0 */
#define S1DREG_BBLT_WIDTH1 0x0111 /* BitBLT Width Register 1 */
#define S1DREG_BBLT_HEIGHT0 0x0112 /* BitBLT Height Register 0 */
#define S1DREG_BBLT_HEIGHT1 0x0113 /* BitBLT Height Register 1 */
#define S1DREG_BBLT_BGC0 0x0114 /* BitBLT Background Color Register 0 */
#define S1DREG_BBLT_BGC1 0x0115 /* BitBLT Background Color Register 1 */
#define S1DREG_BBLT_FGC0 0x0118 /* BitBLT Foreground Color Register 0 */
#define S1DREG_BBLT_FGC1 0x0119 /* BitBLT Foreground Color Register 1 */
#define S1DREG_LKUP_MODE 0x01E0 /* Look-Up Table Mode Register */
#define S1DREG_LKUP_ADDR 0x01E2 /* Look-Up Table Address Register */
#define S1DREG_LKUP_DATA 0x01E4 /* Look-Up Table Data Register */
#define S1DREG_PS_CNF 0x01F0 /* Power Save Configuration Register */
#define S1DREG_PS_STATUS 0x01F1 /* Power Save Status Register */
#define S1DREG_CPU2MEM_WDOGT 0x01F4 /* CPU-to-Memory Access Watchdog Timer Register */
#define S1DREG_COM_DISP_MODE 0x01FC /* Common Display Mode Register */
#define S1DREG_DELAYOFF 0xFFFE
#define S1DREG_DELAYON 0xFFFF
#define BBLT_SOLID_FILL 0x0c
/* Note: all above defines should go in separate header files
when implementing other S1D13xxx chip support. */
struct s1d13xxxfb_regval {
u16 addr;
u8 value;
};
struct s1d13xxxfb_par {
void __iomem *regs;
unsigned char display;
unsigned char prod_id;
unsigned char revision;
unsigned int pseudo_palette[16];
#ifdef CONFIG_PM
void *regs_save; /* pm saves all registers here */
void *disp_save; /* pm saves entire screen here */
#endif
};
struct s1d13xxxfb_pdata {
const struct s1d13xxxfb_regval *initregs;
const unsigned int initregssize;
void (*platform_init_video)(void);
#ifdef CONFIG_PM
int (*platform_suspend_video)(void);
int (*platform_resume_video)(void);
#endif
};
#endif

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/*
* StrongARM 1100 LCD Controller Frame Buffer Device
*
* Copyright (C) 1999 Eric A. Thomas
* Based on acornfb.c Copyright (C) Russell King.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#ifndef _VIDEO_SA1100FB_H
#define _VIDEO_SA1100FB_H
#include <linux/fb.h>
#include <linux/types.h>
#define RGB_4 0
#define RGB_8 1
#define RGB_16 2
#define NR_RGB 3
/* These are the bitfields for each display depth that we support. */
struct sa1100fb_rgb {
struct fb_bitfield red;
struct fb_bitfield green;
struct fb_bitfield blue;
struct fb_bitfield transp;
};
/* This structure describes the machine which we are running on. */
struct sa1100fb_mach_info {
u_long pixclock;
u_short xres;
u_short yres;
u_char bpp;
u_char hsync_len;
u_char left_margin;
u_char right_margin;
u_char vsync_len;
u_char upper_margin;
u_char lower_margin;
u_char sync;
u_int cmap_greyscale:1,
cmap_inverse:1,
cmap_static:1,
unused:29;
u_int lccr0;
u_int lccr3;
/* Overrides for the default RGB maps */
const struct sa1100fb_rgb *rgb[NR_RGB];
void (*backlight_power)(int);
void (*lcd_power)(int);
void (*set_visual)(u32);
};
#endif

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/* include/video/samsung_fimd.h
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
*
* S3C Platform - new-style fimd and framebuffer register definitions
*
* This is the register set for the fimd and new style framebuffer interface
* found from the S3C2443 onwards into the S3C2416, S3C2450, the
* S3C64XX series such as the S3C6400 and S3C6410, and EXYNOS series.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/* VIDCON0 */
#define VIDCON0 0x00
#define VIDCON0_DSI_EN (1 << 30)
#define VIDCON0_INTERLACE (1 << 29)
#define VIDCON0_VIDOUT_MASK (0x7 << 26)
#define VIDCON0_VIDOUT_SHIFT 26
#define VIDCON0_VIDOUT_RGB (0x0 << 26)
#define VIDCON0_VIDOUT_TV (0x1 << 26)
#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
#define VIDCON0_VIDOUT_WB_RGB (0x4 << 26)
#define VIDCON0_VIDOUT_WB_I80_LDI0 (0x6 << 26)
#define VIDCON0_VIDOUT_WB_I80_LDI1 (0x7 << 26)
#define VIDCON0_L1_DATA_MASK (0x7 << 23)
#define VIDCON0_L1_DATA_SHIFT 23
#define VIDCON0_L1_DATA_16BPP (0x0 << 23)
#define VIDCON0_L1_DATA_18BPP16 (0x1 << 23)
#define VIDCON0_L1_DATA_18BPP9 (0x2 << 23)
#define VIDCON0_L1_DATA_24BPP (0x3 << 23)
#define VIDCON0_L1_DATA_18BPP (0x4 << 23)
#define VIDCON0_L1_DATA_16BPP8 (0x5 << 23)
#define VIDCON0_L0_DATA_MASK (0x7 << 20)
#define VIDCON0_L0_DATA_SHIFT 20
#define VIDCON0_L0_DATA_16BPP (0x0 << 20)
#define VIDCON0_L0_DATA_18BPP16 (0x1 << 20)
#define VIDCON0_L0_DATA_18BPP9 (0x2 << 20)
#define VIDCON0_L0_DATA_24BPP (0x3 << 20)
#define VIDCON0_L0_DATA_18BPP (0x4 << 20)
#define VIDCON0_L0_DATA_16BPP8 (0x5 << 20)
#define VIDCON0_PNRMODE_MASK (0x3 << 17)
#define VIDCON0_PNRMODE_SHIFT 17
#define VIDCON0_PNRMODE_RGB (0x0 << 17)
#define VIDCON0_PNRMODE_BGR (0x1 << 17)
#define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17)
#define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17)
#define VIDCON0_CLKVALUP (1 << 16)
#define VIDCON0_CLKVAL_F_MASK (0xff << 6)
#define VIDCON0_CLKVAL_F_SHIFT 6
#define VIDCON0_CLKVAL_F_LIMIT 0xff
#define VIDCON0_CLKVAL_F(_x) ((_x) << 6)
#define VIDCON0_VLCKFREE (1 << 5)
#define VIDCON0_CLKDIR (1 << 4)
#define VIDCON0_CLKSEL_MASK (0x3 << 2)
#define VIDCON0_CLKSEL_SHIFT 2
#define VIDCON0_CLKSEL_HCLK (0x0 << 2)
#define VIDCON0_CLKSEL_LCD (0x1 << 2)
#define VIDCON0_CLKSEL_27M (0x3 << 2)
#define VIDCON0_ENVID (1 << 1)
#define VIDCON0_ENVID_F (1 << 0)
#define VIDCON1 0x04
#define VIDCON1_LINECNT_MASK (0x7ff << 16)
#define VIDCON1_LINECNT_SHIFT 16
#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
#define VIDCON1_FSTATUS_EVEN (1 << 15)
#define VIDCON1_VSTATUS_MASK (0x3 << 13)
#define VIDCON1_VSTATUS_SHIFT 13
#define VIDCON1_VSTATUS_VSYNC (0x0 << 13)
#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
#define VIDCON1_VSTATUS_FRONTPORCH (0x3 << 13)
#define VIDCON1_VCLK_MASK (0x3 << 9)
#define VIDCON1_VCLK_HOLD (0x0 << 9)
#define VIDCON1_VCLK_RUN (0x1 << 9)
#define VIDCON1_INV_VCLK (1 << 7)
#define VIDCON1_INV_HSYNC (1 << 6)
#define VIDCON1_INV_VSYNC (1 << 5)
#define VIDCON1_INV_VDEN (1 << 4)
/* VIDCON2 */
#define VIDCON2 0x08
#define VIDCON2_EN601 (1 << 23)
#define VIDCON2_TVFMTSEL_SW (1 << 14)
#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12)
#define VIDCON2_TVFMTSEL1_SHIFT 12
#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12)
#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12)
#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12)
#define VIDCON2_ORGYCbCr (1 << 8)
#define VIDCON2_YUVORDCrCb (1 << 7)
/* PRTCON (S3C6410)
* Might not be present in the S3C6410 documentation,
* but tests prove it's there almost for sure; shouldn't hurt in any case.
*/
#define PRTCON 0x0c
#define PRTCON_PROTECT (1 << 11)
/* VIDTCON0 */
#define VIDTCON0 0x10
#define VIDTCON0_VBPDE_MASK (0xff << 24)
#define VIDTCON0_VBPDE_SHIFT 24
#define VIDTCON0_VBPDE_LIMIT 0xff
#define VIDTCON0_VBPDE(_x) ((_x) << 24)
#define VIDTCON0_VBPD_MASK (0xff << 16)
#define VIDTCON0_VBPD_SHIFT 16
#define VIDTCON0_VBPD_LIMIT 0xff
#define VIDTCON0_VBPD(_x) ((_x) << 16)
#define VIDTCON0_VFPD_MASK (0xff << 8)
#define VIDTCON0_VFPD_SHIFT 8
#define VIDTCON0_VFPD_LIMIT 0xff
#define VIDTCON0_VFPD(_x) ((_x) << 8)
#define VIDTCON0_VSPW_MASK (0xff << 0)
#define VIDTCON0_VSPW_SHIFT 0
#define VIDTCON0_VSPW_LIMIT 0xff
#define VIDTCON0_VSPW(_x) ((_x) << 0)
/* VIDTCON1 */
#define VIDTCON1 0x14
#define VIDTCON1_VFPDE_MASK (0xff << 24)
#define VIDTCON1_VFPDE_SHIFT 24
#define VIDTCON1_VFPDE_LIMIT 0xff
#define VIDTCON1_VFPDE(_x) ((_x) << 24)
#define VIDTCON1_HBPD_MASK (0xff << 16)
#define VIDTCON1_HBPD_SHIFT 16
#define VIDTCON1_HBPD_LIMIT 0xff
#define VIDTCON1_HBPD(_x) ((_x) << 16)
#define VIDTCON1_HFPD_MASK (0xff << 8)
#define VIDTCON1_HFPD_SHIFT 8
#define VIDTCON1_HFPD_LIMIT 0xff
#define VIDTCON1_HFPD(_x) ((_x) << 8)
#define VIDTCON1_HSPW_MASK (0xff << 0)
#define VIDTCON1_HSPW_SHIFT 0
#define VIDTCON1_HSPW_LIMIT 0xff
#define VIDTCON1_HSPW(_x) ((_x) << 0)
#define VIDTCON2 0x18
#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
#define VIDTCON2_LINEVAL_SHIFT 11
#define VIDTCON2_LINEVAL_LIMIT 0x7ff
#define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11)
#define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22)
#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
#define VIDTCON2_HOZVAL_SHIFT 0
#define VIDTCON2_HOZVAL_LIMIT 0x7ff
#define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0)
/* WINCONx */
#define WINCON(_win) (0x20 + ((_win) * 4))
#define WINCONx_CSCCON_EQ601 (0x0 << 28)
#define WINCONx_CSCCON_EQ709 (0x1 << 28)
#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
#define WINCONx_CSCWIDTH_SHIFT 26
#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
#define WINCONx_CSCWIDTH_NARROW (0x3 << 26)
#define WINCONx_ENLOCAL (1 << 22)
#define WINCONx_BUFSTATUS (1 << 21)
#define WINCONx_BUFSEL (1 << 20)
#define WINCONx_BUFAUTOEN (1 << 19)
#define WINCONx_BITSWP (1 << 18)
#define WINCONx_BYTSWP (1 << 17)
#define WINCONx_HAWSWP (1 << 16)
#define WINCONx_WSWP (1 << 15)
#define WINCONx_YCbCr (1 << 13)
#define WINCONx_BURSTLEN_MASK (0x3 << 9)
#define WINCONx_BURSTLEN_SHIFT 9
#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
#define WINCONx_BURSTLEN_8WORD (0x1 << 9)
#define WINCONx_BURSTLEN_4WORD (0x2 << 9)
#define WINCONx_ENWIN (1 << 0)
#define WINCON0_BPPMODE_MASK (0xf << 2)
#define WINCON0_BPPMODE_SHIFT 2
#define WINCON0_BPPMODE_1BPP (0x0 << 2)
#define WINCON0_BPPMODE_2BPP (0x1 << 2)
#define WINCON0_BPPMODE_4BPP (0x2 << 2)
#define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2)
#define WINCON0_BPPMODE_16BPP_565 (0x5 << 2)
#define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2)
#define WINCON0_BPPMODE_18BPP_666 (0x8 << 2)
#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
#define WINCON1_LOCALSEL_CAMIF (1 << 23)
#define WINCON1_BLD_PIX (1 << 6)
#define WINCON1_BPPMODE_MASK (0xf << 2)
#define WINCON1_BPPMODE_SHIFT 2
#define WINCON1_BPPMODE_1BPP (0x0 << 2)
#define WINCON1_BPPMODE_2BPP (0x1 << 2)
#define WINCON1_BPPMODE_4BPP (0x2 << 2)
#define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2)
#define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2)
#define WINCON1_BPPMODE_16BPP_565 (0x5 << 2)
#define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2)
#define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2)
#define WINCON1_BPPMODE_18BPP_666 (0x8 << 2)
#define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2)
#define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2)
#define WINCON1_BPPMODE_24BPP_888 (0xb << 2)
#define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2)
#define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2)
#define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2)
#define WINCON1_ALPHA_SEL (1 << 1)
/* S5PV210 */
#define SHADOWCON 0x34
#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win)))
/* DMA channels (all windows) */
#define SHADOWCON_CHx_ENABLE(_win) (1 << (_win))
/* Local input channels (windows 0-2) */
#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win)))
/* VIDOSDx */
#define VIDOSD_BASE 0x40
#define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
#define VIDOSDxA_TOPLEFT_X_SHIFT 11
#define VIDOSDxA_TOPLEFT_X_LIMIT 0x7ff
#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11)
#define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
#define VIDOSDxA_TOPLEFT_Y_SHIFT 0
#define VIDOSDxA_TOPLEFT_Y_LIMIT 0x7ff
#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0)
#define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
#define VIDOSDxB_BOTRIGHT_X_SHIFT 11
#define VIDOSDxB_BOTRIGHT_X_LIMIT 0x7ff
#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11)
#define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
#define VIDOSDxB_BOTRIGHT_Y_SHIFT 0
#define VIDOSDxB_BOTRIGHT_Y_LIMIT 0x7ff
#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0)
/* For VIDOSD[1..4]C */
#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
#define VIDISD14C_ALPHA0_G_MASK (0xf << 16)
#define VIDISD14C_ALPHA0_G_SHIFT 16
#define VIDISD14C_ALPHA0_G_LIMIT 0xf
#define VIDISD14C_ALPHA0_G(_x) ((_x) << 16)
#define VIDISD14C_ALPHA0_B_MASK (0xf << 12)
#define VIDISD14C_ALPHA0_B_SHIFT 12
#define VIDISD14C_ALPHA0_B_LIMIT 0xf
#define VIDISD14C_ALPHA0_B(_x) ((_x) << 12)
#define VIDISD14C_ALPHA1_R_MASK (0xf << 8)
#define VIDISD14C_ALPHA1_R_SHIFT 8
#define VIDISD14C_ALPHA1_R_LIMIT 0xf
#define VIDISD14C_ALPHA1_R(_x) ((_x) << 8)
#define VIDISD14C_ALPHA1_G_MASK (0xf << 4)
#define VIDISD14C_ALPHA1_G_SHIFT 4
#define VIDISD14C_ALPHA1_G_LIMIT 0xf
#define VIDISD14C_ALPHA1_G(_x) ((_x) << 4)
#define VIDISD14C_ALPHA1_B_MASK (0xf << 0)
#define VIDISD14C_ALPHA1_B_SHIFT 0
#define VIDISD14C_ALPHA1_B_LIMIT 0xf
#define VIDISD14C_ALPHA1_B(_x) ((_x) << 0)
/* Video buffer addresses */
#define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8))
#define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8))
#define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8))
#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
#define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27)
#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
#define VIDW_BUF_SIZE_OFFSET_SHIFT 13
#define VIDW_BUF_SIZE_OFFSET_LIMIT 0x1fff
#define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13)
#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26)
#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT 0
#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT 0x1fff
#define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0)
/* Interrupt controls and status */
#define VIDINTCON0 0x130
#define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20)
#define VIDINTCON0_FIFOINTERVAL_SHIFT 20
#define VIDINTCON0_FIFOINTERVAL_LIMIT 0x3f
#define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20)
#define VIDINTCON0_INT_SYSMAINCON (1 << 19)
#define VIDINTCON0_INT_SYSSUBCON (1 << 18)
#define VIDINTCON0_INT_I80IFDONE (1 << 17)
#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
#define VIDINTCON0_FRAMESEL0_SHIFT 15
#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
#define VIDINTCON0_FRAMESEL1 (1 << 13)
#define VIDINTCON0_FRAMESEL1_MASK (0x3 << 13)
#define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13)
#define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13)
#define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13)
#define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13)
#define VIDINTCON0_INT_FRAME (1 << 12)
#define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5)
#define VIDINTCON0_FIFIOSEL_SHIFT 5
#define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5)
#define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5)
#define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5)
#define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5)
#define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5)
#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2)
#define VIDINTCON0_FIFOLEVEL_SHIFT 2
#define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2)
#define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2)
#define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2)
#define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2)
#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2)
#define VIDINTCON0_INT_FIFO_MASK (0x3 << 0)
#define VIDINTCON0_INT_FIFO_SHIFT 0
#define VIDINTCON0_INT_ENABLE (1 << 0)
#define VIDINTCON1 0x134
#define VIDINTCON1_INT_I80 (1 << 2)
#define VIDINTCON1_INT_FRAME (1 << 1)
#define VIDINTCON1_INT_FIFO (1 << 0)
/* Window colour-key control registers */
#define WKEYCON 0x140
#define WKEYCON0 0x00
#define WKEYCON1 0x04
#define WxKEYCON0_KEYBL_EN (1 << 26)
#define WxKEYCON0_KEYEN_F (1 << 25)
#define WxKEYCON0_DIRCON (1 << 24)
#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
#define WxKEYCON0_COMPKEY_SHIFT 0
#define WxKEYCON0_COMPKEY_LIMIT 0xffffff
#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
#define WxKEYCON1_COLVAL_SHIFT 0
#define WxKEYCON1_COLVAL_LIMIT 0xffffff
#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
/* Dithering control */
#define DITHMODE 0x170
#define DITHMODE_R_POS_MASK (0x3 << 5)
#define DITHMODE_R_POS_SHIFT 5
#define DITHMODE_R_POS_8BIT (0x0 << 5)
#define DITHMODE_R_POS_6BIT (0x1 << 5)
#define DITHMODE_R_POS_5BIT (0x2 << 5)
#define DITHMODE_G_POS_MASK (0x3 << 3)
#define DITHMODE_G_POS_SHIFT 3
#define DITHMODE_G_POS_8BIT (0x0 << 3)
#define DITHMODE_G_POS_6BIT (0x1 << 3)
#define DITHMODE_G_POS_5BIT (0x2 << 3)
#define DITHMODE_B_POS_MASK (0x3 << 1)
#define DITHMODE_B_POS_SHIFT 1
#define DITHMODE_B_POS_8BIT (0x0 << 1)
#define DITHMODE_B_POS_6BIT (0x1 << 1)
#define DITHMODE_B_POS_5BIT (0x2 << 1)
#define DITHMODE_DITH_EN (1 << 0)
/* Window blanking (MAP) */
#define WINxMAP(_win) (0x180 + ((_win) * 4))
#define WINxMAP_MAP (1 << 24)
#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
#define WINxMAP_MAP_COLOUR_SHIFT 0
#define WINxMAP_MAP_COLOUR_LIMIT 0xffffff
#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
/* Winodw palette control */
#define WPALCON 0x1A0
#define WPALCON_PAL_UPDATE (1 << 9)
#define WPALCON_W4PAL_16BPP_A555 (1 << 8)
#define WPALCON_W3PAL_16BPP_A555 (1 << 7)
#define WPALCON_W2PAL_16BPP_A555 (1 << 6)
#define WPALCON_W1PAL_MASK (0x7 << 3)
#define WPALCON_W1PAL_SHIFT 3
#define WPALCON_W1PAL_25BPP_A888 (0x0 << 3)
#define WPALCON_W1PAL_24BPP (0x1 << 3)
#define WPALCON_W1PAL_19BPP_A666 (0x2 << 3)
#define WPALCON_W1PAL_18BPP_A665 (0x3 << 3)
#define WPALCON_W1PAL_18BPP (0x4 << 3)
#define WPALCON_W1PAL_16BPP_A555 (0x5 << 3)
#define WPALCON_W1PAL_16BPP_565 (0x6 << 3)
#define WPALCON_W0PAL_MASK (0x7 << 0)
#define WPALCON_W0PAL_SHIFT 0
#define WPALCON_W0PAL_25BPP_A888 (0x0 << 0)
#define WPALCON_W0PAL_24BPP (0x1 << 0)
#define WPALCON_W0PAL_19BPP_A666 (0x2 << 0)
#define WPALCON_W0PAL_18BPP_A665 (0x3 << 0)
#define WPALCON_W0PAL_18BPP (0x4 << 0)
#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
/* Blending equation control */
#define BLENDCON 0x260
#define BLENDCON_NEW_MASK (1 << 0)
#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
/* Notes on per-window bpp settings
*
* Value Win0 Win1 Win2 Win3 Win 4
* 0000 1(P) 1(P) 1(P) 1(P) 1(P)
* 0001 2(P) 2(P) 2(P) 2(P) 2(P)
* 0010 4(P) 4(P) 4(P) 4(P) -none-
* 0011 8(P) 8(P) -none- -none- -none-
* 0100 -none- 8(A232) 8(A232) -none- -none-
* 0101 16(565) 16(565) 16(565) 16(565) 16(565)
* 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555)
* 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555)
* 1000 18(666) 18(666) 18(666) 18(666) 18(666)
* 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665)
* 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666)
* 1011 24(888) 24(888) 24(888) 24(888) 24(888)
* 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887)
* 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888)
* 1110 -none- -none- -none- -none- -none-
* 1111 -none- -none- -none- -none- -none-
*/
/* FIMD Version 8 register offset definitions */
#define FIMD_V8_VIDTCON0 0x20010
#define FIMD_V8_VIDTCON1 0x20014
#define FIMD_V8_VIDTCON2 0x20018
#define FIMD_V8_VIDTCON3 0x2001C
#define FIMD_V8_VIDCON1 0x20004

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/*
* Public SH-mobile MIPI DSI header
*
* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef VIDEO_SH_MIPI_DSI_H
#define VIDEO_SH_MIPI_DSI_H
enum sh_mipi_dsi_data_fmt {
MIPI_RGB888,
MIPI_RGB565,
MIPI_RGB666_LP,
MIPI_RGB666,
MIPI_BGR888,
MIPI_BGR565,
MIPI_BGR666_LP,
MIPI_BGR666,
MIPI_YUYV,
MIPI_UYVY,
MIPI_YUV420_L,
MIPI_YUV420,
};
#define SH_MIPI_DSI_HSABM (1 << 0)
#define SH_MIPI_DSI_HBPBM (1 << 1)
#define SH_MIPI_DSI_HFPBM (1 << 2)
#define SH_MIPI_DSI_BL2E (1 << 3)
#define SH_MIPI_DSI_VSEE (1 << 4)
#define SH_MIPI_DSI_HSEE (1 << 5)
#define SH_MIPI_DSI_HSAE (1 << 6)
#define SH_MIPI_DSI_HSbyteCLK (1 << 24)
#define SH_MIPI_DSI_HS6divCLK (1 << 25)
#define SH_MIPI_DSI_HS4divCLK (1 << 26)
#define SH_MIPI_DSI_SYNC_PULSES_MODE (SH_MIPI_DSI_VSEE | \
SH_MIPI_DSI_HSEE | \
SH_MIPI_DSI_HSAE)
#define SH_MIPI_DSI_SYNC_EVENTS_MODE (0)
#define SH_MIPI_DSI_SYNC_BURST_MODE (SH_MIPI_DSI_BL2E)
struct sh_mipi_dsi_info {
enum sh_mipi_dsi_data_fmt data_format;
int channel;
int lane;
unsigned long flags;
u32 clksrc;
u32 phyctrl; /* for extra setting */
unsigned int vsynw_offset;
int (*set_dot_clock)(struct platform_device *pdev,
void __iomem *base,
int enable);
};
#endif

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/*
* SH-Mobile High-Definition Multimedia Interface (HDMI)
*
* Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef SH_MOBILE_HDMI_H
#define SH_MOBILE_HDMI_H
struct sh_mobile_lcdc_chan_cfg;
struct device;
struct clk;
/*
* flags format
*
* 0x00000CBA
*
* A: Audio source select
* B: Int output option
* C: Chip specific option
*/
/* Audio source select */
#define HDMI_SND_SRC_MASK (0xF << 0)
#define HDMI_SND_SRC_I2S (0 << 0) /* default */
#define HDMI_SND_SRC_SPDIF (1 << 0)
#define HDMI_SND_SRC_DSD (2 << 0)
#define HDMI_SND_SRC_HBR (3 << 0)
/* Int output option */
#define HDMI_OUTPUT_PUSH_PULL (1 << 4) /* System control : output mode */
#define HDMI_OUTPUT_POLARITY_HI (1 << 5) /* System control : output polarity */
/* Chip specific option */
#define HDMI_32BIT_REG (1 << 8)
#define HDMI_HAS_HTOP1 (1 << 9)
struct sh_mobile_hdmi_info {
unsigned int flags;
long (*clk_optimize_parent)(unsigned long target, unsigned long *best_freq,
unsigned long *parent_freq);
};
#endif

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#ifndef __ASM_SH_MOBILE_LCDC_H__
#define __ASM_SH_MOBILE_LCDC_H__
#include <linux/fb.h>
#include <video/sh_mobile_meram.h>
/* Register definitions */
#define _LDDCKR 0x410
#define LDDCKR_ICKSEL_BUS (0 << 16)
#define LDDCKR_ICKSEL_MIPI (1 << 16)
#define LDDCKR_ICKSEL_HDMI (2 << 16)
#define LDDCKR_ICKSEL_EXT (3 << 16)
#define LDDCKR_ICKSEL_MASK (7 << 16)
#define LDDCKR_MOSEL (1 << 6)
#define _LDDCKSTPR 0x414
#define _LDINTR 0x468
#define LDINTR_FE (1 << 10)
#define LDINTR_VSE (1 << 9)
#define LDINTR_VEE (1 << 8)
#define LDINTR_FS (1 << 2)
#define LDINTR_VSS (1 << 1)
#define LDINTR_VES (1 << 0)
#define LDINTR_STATUS_MASK (0xff << 0)
#define _LDSR 0x46c
#define LDSR_MSS (1 << 10)
#define LDSR_MRS (1 << 8)
#define LDSR_AS (1 << 1)
#define _LDCNT1R 0x470
#define LDCNT1R_DE (1 << 0)
#define _LDCNT2R 0x474
#define LDCNT2R_BR (1 << 8)
#define LDCNT2R_MD (1 << 3)
#define LDCNT2R_SE (1 << 2)
#define LDCNT2R_ME (1 << 1)
#define LDCNT2R_DO (1 << 0)
#define _LDRCNTR 0x478
#define LDRCNTR_SRS (1 << 17)
#define LDRCNTR_SRC (1 << 16)
#define LDRCNTR_MRS (1 << 1)
#define LDRCNTR_MRC (1 << 0)
#define _LDDDSR 0x47c
#define LDDDSR_LS (1 << 2)
#define LDDDSR_WS (1 << 1)
#define LDDDSR_BS (1 << 0)
#define LDMT1R_VPOL (1 << 28)
#define LDMT1R_HPOL (1 << 27)
#define LDMT1R_DWPOL (1 << 26)
#define LDMT1R_DIPOL (1 << 25)
#define LDMT1R_DAPOL (1 << 24)
#define LDMT1R_HSCNT (1 << 17)
#define LDMT1R_DWCNT (1 << 16)
#define LDMT1R_IFM (1 << 12)
#define LDMT1R_MIFTYP_RGB8 (0x0 << 0)
#define LDMT1R_MIFTYP_RGB9 (0x4 << 0)
#define LDMT1R_MIFTYP_RGB12A (0x5 << 0)
#define LDMT1R_MIFTYP_RGB12B (0x6 << 0)
#define LDMT1R_MIFTYP_RGB16 (0x7 << 0)
#define LDMT1R_MIFTYP_RGB18 (0xa << 0)
#define LDMT1R_MIFTYP_RGB24 (0xb << 0)
#define LDMT1R_MIFTYP_YCBCR (0xf << 0)
#define LDMT1R_MIFTYP_SYS8A (0x0 << 0)
#define LDMT1R_MIFTYP_SYS8B (0x1 << 0)
#define LDMT1R_MIFTYP_SYS8C (0x2 << 0)
#define LDMT1R_MIFTYP_SYS8D (0x3 << 0)
#define LDMT1R_MIFTYP_SYS9 (0x4 << 0)
#define LDMT1R_MIFTYP_SYS12 (0x5 << 0)
#define LDMT1R_MIFTYP_SYS16A (0x7 << 0)
#define LDMT1R_MIFTYP_SYS16B (0x8 << 0)
#define LDMT1R_MIFTYP_SYS16C (0x9 << 0)
#define LDMT1R_MIFTYP_SYS18 (0xa << 0)
#define LDMT1R_MIFTYP_SYS24 (0xb << 0)
#define LDMT1R_MIFTYP_MASK (0xf << 0)
#define LDDFR_CF1 (1 << 18)
#define LDDFR_CF0 (1 << 17)
#define LDDFR_CC (1 << 16)
#define LDDFR_YF_420 (0 << 8)
#define LDDFR_YF_422 (1 << 8)
#define LDDFR_YF_444 (2 << 8)
#define LDDFR_YF_MASK (3 << 8)
#define LDDFR_PKF_ARGB32 (0x00 << 0)
#define LDDFR_PKF_RGB16 (0x03 << 0)
#define LDDFR_PKF_RGB24 (0x0b << 0)
#define LDDFR_PKF_MASK (0x1f << 0)
#define LDSM1R_OS (1 << 0)
#define LDSM2R_OSTRG (1 << 0)
#define LDPMR_LPS (3 << 0)
#define _LDDWD0R 0x800
#define LDDWDxR_WDACT (1 << 28)
#define LDDWDxR_RSW (1 << 24)
#define _LDDRDR 0x840
#define LDDRDR_RSR (1 << 24)
#define LDDRDR_DRD_MASK (0x3ffff << 0)
#define _LDDWAR 0x900
#define LDDWAR_WA (1 << 0)
#define _LDDRAR 0x904
#define LDDRAR_RA (1 << 0)
enum {
RGB8 = LDMT1R_MIFTYP_RGB8, /* 24bpp, 8:8:8 */
RGB9 = LDMT1R_MIFTYP_RGB9, /* 18bpp, 9:9 */
RGB12A = LDMT1R_MIFTYP_RGB12A, /* 24bpp, 12:12 */
RGB12B = LDMT1R_MIFTYP_RGB12B, /* 12bpp */
RGB16 = LDMT1R_MIFTYP_RGB16, /* 16bpp */
RGB18 = LDMT1R_MIFTYP_RGB18, /* 18bpp */
RGB24 = LDMT1R_MIFTYP_RGB24, /* 24bpp */
YUV422 = LDMT1R_MIFTYP_YCBCR, /* 16bpp */
SYS8A = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8A, /* 24bpp, 8:8:8 */
SYS8B = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8B, /* 18bpp, 8:8:2 */
SYS8C = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8C, /* 18bpp, 2:8:8 */
SYS8D = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8D, /* 16bpp, 8:8 */
SYS9 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS9, /* 18bpp, 9:9 */
SYS12 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS12, /* 24bpp, 12:12 */
SYS16A = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16A, /* 16bpp */
SYS16B = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16B, /* 18bpp, 16:2 */
SYS16C = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16C, /* 18bpp, 2:16 */
SYS18 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS18, /* 18bpp */
SYS24 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS24, /* 24bpp */
};
enum { LCDC_CHAN_DISABLED = 0,
LCDC_CHAN_MAINLCD,
LCDC_CHAN_SUBLCD };
enum { LCDC_CLK_BUS, LCDC_CLK_PERIPHERAL, LCDC_CLK_EXTERNAL };
#define LCDC_FLAGS_DWPOL (1 << 0) /* Rising edge dot clock data latch */
#define LCDC_FLAGS_DIPOL (1 << 1) /* Active low display enable polarity */
#define LCDC_FLAGS_DAPOL (1 << 2) /* Active low display data polarity */
#define LCDC_FLAGS_HSCNT (1 << 3) /* Disable HSYNC during VBLANK */
#define LCDC_FLAGS_DWCNT (1 << 4) /* Disable dotclock during blanking */
struct sh_mobile_lcdc_sys_bus_cfg {
unsigned long ldmt2r;
unsigned long ldmt3r;
unsigned long deferred_io_msec;
};
struct sh_mobile_lcdc_sys_bus_ops {
void (*write_index)(void *handle, unsigned long data);
void (*write_data)(void *handle, unsigned long data);
unsigned long (*read_data)(void *handle);
};
struct sh_mobile_lcdc_panel_cfg {
unsigned long width; /* Panel width in mm */
unsigned long height; /* Panel height in mm */
int (*setup_sys)(void *sys_ops_handle,
struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
void (*start_transfer)(void *sys_ops_handle,
struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
void (*display_on)(void);
void (*display_off)(void);
};
/* backlight info */
struct sh_mobile_lcdc_bl_info {
const char *name;
int max_brightness;
int (*set_brightness)(int brightness);
};
struct sh_mobile_lcdc_overlay_cfg {
int fourcc;
unsigned int max_xres;
unsigned int max_yres;
};
struct sh_mobile_lcdc_chan_cfg {
int chan;
int fourcc;
int colorspace;
int interface_type; /* selects RGBn or SYSn I/F, see above */
int clock_divider;
unsigned long flags; /* LCDC_FLAGS_... */
const struct fb_videomode *lcd_modes;
int num_modes;
struct sh_mobile_lcdc_panel_cfg panel_cfg;
struct sh_mobile_lcdc_bl_info bl_info;
struct sh_mobile_lcdc_sys_bus_cfg sys_bus_cfg; /* only for SYSn I/F */
const struct sh_mobile_meram_cfg *meram_cfg;
struct platform_device *tx_dev; /* HDMI/DSI transmitter device */
};
struct sh_mobile_lcdc_info {
int clock_source;
struct sh_mobile_lcdc_chan_cfg ch[2];
struct sh_mobile_lcdc_overlay_cfg overlays[4];
struct sh_mobile_meram_info *meram_dev;
};
#endif /* __ASM_SH_MOBILE_LCDC_H__ */

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#ifndef __VIDEO_SH_MOBILE_MERAM_H__
#define __VIDEO_SH_MOBILE_MERAM_H__
/* For sh_mobile_meram_info.addr_mode */
enum {
SH_MOBILE_MERAM_MODE0 = 0,
SH_MOBILE_MERAM_MODE1
};
enum {
SH_MOBILE_MERAM_PF_NV = 0,
SH_MOBILE_MERAM_PF_RGB,
SH_MOBILE_MERAM_PF_NV24
};
struct sh_mobile_meram_priv;
/*
* struct sh_mobile_meram_info - MERAM platform data
* @reserved_icbs: Bitmask of reserved ICBs (for instance used through UIO)
*/
struct sh_mobile_meram_info {
int addr_mode;
u32 reserved_icbs;
struct sh_mobile_meram_priv *priv;
struct platform_device *pdev;
};
/* icb config */
struct sh_mobile_meram_icb_cfg {
unsigned int meram_size; /* MERAM Buffer Size to use */
};
struct sh_mobile_meram_cfg {
struct sh_mobile_meram_icb_cfg icb[2];
};
#if defined(CONFIG_FB_SH_MOBILE_MERAM) || \
defined(CONFIG_FB_SH_MOBILE_MERAM_MODULE)
unsigned long sh_mobile_meram_alloc(struct sh_mobile_meram_info *meram_dev,
size_t size);
void sh_mobile_meram_free(struct sh_mobile_meram_info *meram_dev,
unsigned long mem, size_t size);
void *sh_mobile_meram_cache_alloc(struct sh_mobile_meram_info *dev,
const struct sh_mobile_meram_cfg *cfg,
unsigned int xres, unsigned int yres,
unsigned int pixelformat,
unsigned int *pitch);
void sh_mobile_meram_cache_free(struct sh_mobile_meram_info *dev, void *data);
void sh_mobile_meram_cache_update(struct sh_mobile_meram_info *dev, void *data,
unsigned long base_addr_y,
unsigned long base_addr_c,
unsigned long *icb_addr_y,
unsigned long *icb_addr_c);
#else
static inline unsigned long
sh_mobile_meram_alloc(struct sh_mobile_meram_info *meram_dev, size_t size)
{
return 0;
}
static inline void
sh_mobile_meram_free(struct sh_mobile_meram_info *meram_dev,
unsigned long mem, size_t size)
{
}
static inline void *
sh_mobile_meram_cache_alloc(struct sh_mobile_meram_info *dev,
const struct sh_mobile_meram_cfg *cfg,
unsigned int xres, unsigned int yres,
unsigned int pixelformat,
unsigned int *pitch)
{
return ERR_PTR(-ENODEV);
}
static inline void
sh_mobile_meram_cache_free(struct sh_mobile_meram_info *dev, void *data)
{
}
static inline void
sh_mobile_meram_cache_update(struct sh_mobile_meram_info *dev, void *data,
unsigned long base_addr_y,
unsigned long base_addr_c,
unsigned long *icb_addr_y,
unsigned long *icb_addr_c)
{
}
#endif
#endif /* __VIDEO_SH_MOBILE_MERAM_H__ */

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/*
* sisfb.h - definitions for the SiS framebuffer driver
*
* Copyright (C) 2001-2005 by Thomas Winischhofer, Vienna, Austria.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the named License,
* or any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
*/
#ifndef _LINUX_SISFB_H_
#define _LINUX_SISFB_H_
#include <linux/pci.h>
#include <uapi/video/sisfb.h>
#define UNKNOWN_VGA 0
#define SIS_300_VGA 1
#define SIS_315_VGA 2
#define SISFB_HAVE_MALLOC_NEW
extern void sis_malloc(struct sis_memreq *req);
extern void sis_malloc_new(struct pci_dev *pdev, struct sis_memreq *req);
extern void sis_free(u32 base);
extern void sis_free_new(struct pci_dev *pdev, u32 base);
#endif

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/*
* linux/drivers/video/sstfb.h -- voodoo graphics frame buffer
*
* Copyright (c) 2000,2001 Ghozlane Toumi <gtoumi@messel.emse.fr>
*
* Created 28 Aug 2001 by Ghozlane Toumi
*/
#ifndef _SSTFB_H_
#define _SSTFB_H_
/*
*
* Debug Stuff
*
*/
#ifdef SST_DEBUG
# define dprintk(X...) printk("sstfb: " X)
# define SST_DEBUG_REG 1
# define SST_DEBUG_FUNC 1
# define SST_DEBUG_VAR 1
#else
# define dprintk(X...)
# define SST_DEBUG_REG 0
# define SST_DEBUG_FUNC 0
# define SST_DEBUG_VAR 0
#endif
#if (SST_DEBUG_REG > 0)
# define r_dprintk(X...) dprintk(X)
#else
# define r_dprintk(X...)
#endif
#if (SST_DEBUG_REG > 1)
# define r_ddprintk(X...) dprintk(" " X)
#else
# define r_ddprintk(X...)
#endif
#if (SST_DEBUG_FUNC > 0)
# define f_dprintk(X...) dprintk(X)
#else
# define f_dprintk(X...)
#endif
#if (SST_DEBUG_FUNC > 1)
# define f_ddprintk(X...) dprintk(" " X)
#else
# define f_ddprintk(X...)
#endif
#if (SST_DEBUG_FUNC > 2)
# define f_dddprintk(X...) dprintk(" " X)
#else
# define f_dddprintk(X...)
#endif
#if (SST_DEBUG_VAR > 0)
# define v_dprintk(X...) dprintk(X)
# define print_var(V, X...) \
{ \
dprintk(X); \
printk(" :\n"); \
sst_dbg_print_var(V); \
}
#else
# define v_dprintk(X...)
# define print_var(X,Y...)
#endif
#define POW2(x) (1ul<<(x))
/*
*
* Const
*
*/
/* pci stuff */
#define PCI_INIT_ENABLE 0x40
# define PCI_EN_INIT_WR BIT(0)
# define PCI_EN_FIFO_WR BIT(1)
# define PCI_REMAP_DAC BIT(2)
#define PCI_VCLK_ENABLE 0xc0 /* enable video */
#define PCI_VCLK_DISABLE 0xe0
/* register offsets from memBaseAddr */
#define STATUS 0x0000
# define STATUS_FBI_BUSY BIT(7)
#define FBZMODE 0x0110
# define EN_CLIPPING BIT(0) /* enable clipping */
# define EN_RGB_WRITE BIT(9) /* enable writes to rgb area */
# define EN_ALPHA_WRITE BIT(10)
# define ENGINE_INVERT_Y BIT(17) /* invert Y origin (pipe) */
#define LFBMODE 0x0114
# define LFB_565 0 /* bits 3:0 .16 bits RGB */
# define LFB_888 4 /* 24 bits RGB */
# define LFB_8888 5 /* 32 bits ARGB */
# define WR_BUFF_FRONT 0 /* write buf select (front) */
# define WR_BUFF_BACK (1 << 4) /* back */
# define RD_BUFF_FRONT 0 /* read buff select (front) */
# define RD_BUFF_BACK (1 << 6) /* back */
# define EN_PXL_PIPELINE BIT(8) /* pixel pipeline (clip..)*/
# define LFB_WORD_SWIZZLE_WR BIT(11) /* enable write-wordswap (big-endian) */
# define LFB_BYTE_SWIZZLE_WR BIT(12) /* enable write-byteswap (big-endian) */
# define LFB_INVERT_Y BIT(13) /* invert Y origin (LFB) */
# define LFB_WORD_SWIZZLE_RD BIT(15) /* enable read-wordswap (big-endian) */
# define LFB_BYTE_SWIZZLE_RD BIT(16) /* enable read-byteswap (big-endian) */
#define CLIP_LEFT_RIGHT 0x0118
#define CLIP_LOWY_HIGHY 0x011c
#define NOPCMD 0x0120
#define FASTFILLCMD 0x0124
#define SWAPBUFFCMD 0x0128
#define FBIINIT4 0x0200 /* misc controls */
# define FAST_PCI_READS 0 /* 1 waitstate */
# define SLOW_PCI_READS BIT(0) /* 2 ws */
# define LFB_READ_AHEAD BIT(1)
#define BACKPORCH 0x0208
#define VIDEODIMENSIONS 0x020c
#define FBIINIT0 0x0210 /* misc+fifo controls */
# define DIS_VGA_PASSTHROUGH BIT(0)
# define FBI_RESET BIT(1)
# define FIFO_RESET BIT(2)
#define FBIINIT1 0x0214 /* PCI + video controls */
# define VIDEO_MASK 0x8080010f /* masks video related bits V1+V2*/
# define FAST_PCI_WRITES 0 /* 0 ws */
# define SLOW_PCI_WRITES BIT(1) /* 1 ws */
# define EN_LFB_READ BIT(3)
# define TILES_IN_X_SHIFT 4
# define VIDEO_RESET BIT(8)
# define EN_BLANKING BIT(12)
# define EN_DATA_OE BIT(13)
# define EN_BLANK_OE BIT(14)
# define EN_HVSYNC_OE BIT(15)
# define EN_DCLK_OE BIT(16)
# define SEL_INPUT_VCLK_2X 0 /* bit 17 */
# define SEL_INPUT_VCLK_SLAVE BIT(17)
# define SEL_SOURCE_VCLK_SLAVE 0 /* bits 21:20 */
# define SEL_SOURCE_VCLK_2X_DIV2 (0x01 << 20)
# define SEL_SOURCE_VCLK_2X_SEL (0x02 << 20)
# define EN_24BPP BIT(22)
# define TILES_IN_X_MSB_SHIFT 24 /* v2 */
# define VCLK_2X_SEL_DEL_SHIFT 27 /* vclk out delay 0,4,6,8ns */
# define VCLK_DEL_SHIFT 29 /* vclk in delay */
#define FBIINIT2 0x0218 /* Dram controls */
# define EN_FAST_RAS_READ BIT(5)
# define EN_DRAM_OE BIT(6)
# define EN_FAST_RD_AHEAD_WR BIT(7)
# define VIDEO_OFFSET_SHIFT 11 /* unit: #rows tile 64x16/2 */
# define SWAP_DACVSYNC 0
# define SWAP_DACDATA0 (1 << 9)
# define SWAP_FIFO_STALL (2 << 9)
# define EN_RD_AHEAD_FIFO BIT(21)
# define EN_DRAM_REFRESH BIT(22)
# define DRAM_REFRESH_16 (0x30 << 23) /* dram 16 ms */
#define DAC_READ FBIINIT2 /* in remap mode */
#define FBIINIT3 0x021c /* fbi controls */
# define DISABLE_TEXTURE BIT(6)
# define Y_SWAP_ORIGIN_SHIFT 22 /* Y swap subtraction value */
#define HSYNC 0x0220
#define VSYNC 0x0224
#define DAC_DATA 0x022c
# define DAC_READ_CMD BIT(11) /* set read dacreg mode */
#define FBIINIT5 0x0244 /* v2 specific */
# define FBIINIT5_MASK 0xfa40ffff /* mask video bits*/
# define HDOUBLESCAN BIT(20)
# define VDOUBLESCAN BIT(21)
# define HSYNC_HIGH BIT(23)
# define VSYNC_HIGH BIT(24)
# define INTERLACE BIT(26)
#define FBIINIT6 0x0248 /* v2 specific */
# define TILES_IN_X_LSB_SHIFT 30 /* v2 */
#define FBIINIT7 0x024c /* v2 specific */
#define BLTSRCBASEADDR 0x02c0 /* BitBLT Source base address */
#define BLTDSTBASEADDR 0x02c4 /* BitBLT Destination base address */
#define BLTXYSTRIDES 0x02c8 /* BitBLT Source and Destination strides */
#define BLTSRCCHROMARANGE 0x02cc /* BitBLT Source Chroma key range */
#define BLTDSTCHROMARANGE 0x02d0 /* BitBLT Destination Chroma key range */
#define BLTCLIPX 0x02d4 /* BitBLT Min/Max X clip values */
#define BLTCLIPY 0x02d8 /* BitBLT Min/Max Y clip values */
#define BLTSRCXY 0x02e0 /* BitBLT Source starting XY coordinates */
#define BLTDSTXY 0x02e4 /* BitBLT Destination starting XY coordinates */
#define BLTSIZE 0x02e8 /* BitBLT width and height */
#define BLTROP 0x02ec /* BitBLT Raster operations */
# define BLTROP_COPY 0x0cccc
# define BLTROP_INVERT 0x05555
# define BLTROP_XOR 0x06666
#define BLTCOLOR 0x02f0 /* BitBLT and foreground background colors */
#define BLTCOMMAND 0x02f8 /* BitBLT command mode (v2 specific) */
# define BLT_SCR2SCR_BITBLT 0 /* Screen-to-Screen BitBLT */
# define BLT_CPU2SCR_BITBLT 1 /* CPU-to-screen BitBLT */
# define BLT_RECFILL_BITBLT 2 /* BitBLT Rectangle Fill */
# define BLT_16BPP_FMT 2 /* 16 BPP (5-6-5 RGB) */
#define BLTDATA 0x02fc /* BitBLT data for CPU-to-Screen BitBLTs */
# define LAUNCH_BITBLT BIT(31) /* Launch BitBLT in BltCommand, bltDstXY or bltSize */
/* Dac Registers */
#define DACREG_WMA 0x0 /* pixel write mode address */
#define DACREG_LUT 0x01 /* color value */
#define DACREG_RMR 0x02 /* pixel mask */
#define DACREG_RMA 0x03 /* pixel read mode address */
/*Dac registers in indexed mode (TI, ATT dacs) */
#define DACREG_ADDR_I DACREG_WMA
#define DACREG_DATA_I DACREG_RMR
#define DACREG_RMR_I 0x00
#define DACREG_CR0_I 0x01
# define DACREG_CR0_EN_INDEXED BIT(0) /* enable indexec mode */
# define DACREG_CR0_8BIT BIT(1) /* set dac to 8 bits/read */
# define DACREG_CR0_PWDOWN BIT(3) /* powerdown dac */
# define DACREG_CR0_16BPP 0x30 /* mode 3 */
# define DACREG_CR0_24BPP 0x50 /* mode 5 */
#define DACREG_CR1_I 0x05
#define DACREG_CC_I 0x06
# define DACREG_CC_CLKA BIT(7) /* clk A controlled by regs */
# define DACREG_CC_CLKA_C (2<<4) /* clk A uses reg C */
# define DACREG_CC_CLKB BIT(3) /* clk B controlled by regs */
# define DACREG_CC_CLKB_D 3 /* clkB uses reg D */
#define DACREG_AC0_I 0x48 /* clock A reg C */
#define DACREG_AC1_I 0x49
#define DACREG_BD0_I 0x6c /* clock B reg D */
#define DACREG_BD1_I 0x6d
/* identification constants */
#define DACREG_MIR_TI 0x97
#define DACREG_DIR_TI 0x09
#define DACREG_MIR_ATT 0x84
#define DACREG_DIR_ATT 0x09
/* ics dac specific registers */
#define DACREG_ICS_PLLWMA 0x04 /* PLL write mode address */
#define DACREG_ICS_PLLDATA 0x05 /* PLL data /parameter */
#define DACREG_ICS_CMD 0x06 /* command */
# define DACREG_ICS_CMD_16BPP 0x50 /* ics color mode 6 (16bpp bypass)*/
# define DACREG_ICS_CMD_24BPP 0x70 /* ics color mode 7 (24bpp bypass)*/
# define DACREG_ICS_CMD_PWDOWN BIT(0) /* powerdown dac */
#define DACREG_ICS_PLLRMA 0x07 /* PLL read mode address */
/*
* pll parameter register:
* indexed : write addr to PLLWMA, write data in PLLDATA.
* for reads use PLLRMA .
* 8 freq registers (0-7) for video clock (CLK0)
* 2 freq registers (a-b) for graphic clock (CLK1)
*/
#define DACREG_ICS_PLL_CLK0_1_INI 0x55 /* initial pll M value for freq f1 */
#define DACREG_ICS_PLL_CLK0_7_INI 0x71 /* f7 */
#define DACREG_ICS_PLL_CLK1_B_INI 0x79 /* fb */
#define DACREG_ICS_PLL_CTRL 0x0e
# define DACREG_ICS_CLK0 BIT(5)
# define DACREG_ICS_CLK0_0 0
# define DACREG_ICS_CLK1_A 0 /* bit4 */
/* sst default init registers */
#define FBIINIT0_DEFAULT DIS_VGA_PASSTHROUGH
#define FBIINIT1_DEFAULT \
( \
FAST_PCI_WRITES \
/* SLOW_PCI_WRITES*/ \
| VIDEO_RESET \
| 10 << TILES_IN_X_SHIFT\
| SEL_SOURCE_VCLK_2X_SEL\
| EN_LFB_READ \
)
#define FBIINIT2_DEFAULT \
( \
SWAP_DACVSYNC \
| EN_DRAM_OE \
| DRAM_REFRESH_16 \
| EN_DRAM_REFRESH \
| EN_FAST_RAS_READ \
| EN_RD_AHEAD_FIFO \
| EN_FAST_RD_AHEAD_WR \
)
#define FBIINIT3_DEFAULT \
( DISABLE_TEXTURE )
#define FBIINIT4_DEFAULT \
( \
FAST_PCI_READS \
/* SLOW_PCI_READS*/ \
| LFB_READ_AHEAD \
)
/* Careful with this one : writing back the data just read will trash the DAC
reading some fields give logic value on pins, but setting this field will
set the source signal driving the pin. conclusion : just use the default
as a base before writing back .
*/
#define FBIINIT6_DEFAULT (0x0)
/*
*
* Misc Const
*
*/
/* ioctl to enable/disable VGA passthrough */
#define SSTFB_SET_VGAPASS _IOW('F', 0xdd, __u32)
#define SSTFB_GET_VGAPASS _IOR('F', 0xdd, __u32)
/* used to know witch clock to set */
enum {
VID_CLOCK=0,
GFX_CLOCK=1,
};
/* freq max */
#define DAC_FREF 14318 /* DAC reference freq (Khz) */
#define VCO_MAX 260000
/*
* driver structs
*/
struct pll_timing {
unsigned int m;
unsigned int n;
unsigned int p;
};
struct dac_switch {
const char *name;
int (*detect) (struct fb_info *info);
int (*set_pll) (struct fb_info *info, const struct pll_timing *t, const int clock);
void (*set_vidmod) (struct fb_info *info, const int bpp);
};
struct sst_spec {
char * name;
int default_gfx_clock; /* 50000 for voodoo1, 75000 for voodoo2 */
int max_gfxclk; /* ! in Mhz ie 60 for voodoo 1 */
};
struct sstfb_par {
u32 palette[16];
unsigned int yDim;
unsigned int hSyncOn; /* hsync_len */
unsigned int hSyncOff; /* left_margin + xres + right_margin */
unsigned int hBackPorch;/* left_margin */
unsigned int vSyncOn;
unsigned int vSyncOff;
unsigned int vBackPorch;
struct pll_timing pll;
unsigned int tiles_in_X;/* num of tiles in X res */
u8 __iomem *mmio_vbase;
struct dac_switch dac_sw; /* dac specific functions */
struct pci_dev *dev;
int type;
u8 revision;
u8 vgapass; /* VGA pass through: 1=enabled, 0=disabled */
};
#endif /* _SSTFB_H_ */

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#ifndef _TDFX_H
#define _TDFX_H
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
/* membase0 register offsets */
#define STATUS 0x00
#define PCIINIT0 0x04
#define SIPMONITOR 0x08
#define LFBMEMORYCONFIG 0x0c
#define MISCINIT0 0x10
#define MISCINIT1 0x14
#define DRAMINIT0 0x18
#define DRAMINIT1 0x1c
#define AGPINIT 0x20
#define TMUGBEINIT 0x24
#define VGAINIT0 0x28
#define VGAINIT1 0x2c
#define DRAMCOMMAND 0x30
#define DRAMDATA 0x34
/* reserved 0x38 */
/* reserved 0x3c */
#define PLLCTRL0 0x40
#define PLLCTRL1 0x44
#define PLLCTRL2 0x48
#define DACMODE 0x4c
#define DACADDR 0x50
#define DACDATA 0x54
#define RGBMAXDELTA 0x58
#define VIDPROCCFG 0x5c
#define HWCURPATADDR 0x60
#define HWCURLOC 0x64
#define HWCURC0 0x68
#define HWCURC1 0x6c
#define VIDINFORMAT 0x70
#define VIDINSTATUS 0x74
#define VIDSERPARPORT 0x78
#define VIDINXDELTA 0x7c
#define VIDININITERR 0x80
#define VIDINYDELTA 0x84
#define VIDPIXBUFTHOLD 0x88
#define VIDCHRMIN 0x8c
#define VIDCHRMAX 0x90
#define VIDCURLIN 0x94
#define VIDSCREENSIZE 0x98
#define VIDOVRSTARTCRD 0x9c
#define VIDOVRENDCRD 0xa0
#define VIDOVRDUDX 0xa4
#define VIDOVRDUDXOFF 0xa8
#define VIDOVRDVDY 0xac
/* ... */
#define VIDOVRDVDYOFF 0xe0
#define VIDDESKSTART 0xe4
#define VIDDESKSTRIDE 0xe8
#define VIDINADDR0 0xec
#define VIDINADDR1 0xf0
#define VIDINADDR2 0xf4
#define VIDINSTRIDE 0xf8
#define VIDCUROVRSTART 0xfc
#define INTCTRL (0x00100000 + 0x04)
#define CLIP0MIN (0x00100000 + 0x08)
#define CLIP0MAX (0x00100000 + 0x0c)
#define DSTBASE (0x00100000 + 0x10)
#define DSTFORMAT (0x00100000 + 0x14)
#define SRCBASE (0x00100000 + 0x34)
#define COMMANDEXTRA_2D (0x00100000 + 0x38)
#define CLIP1MIN (0x00100000 + 0x4c)
#define CLIP1MAX (0x00100000 + 0x50)
#define SRCFORMAT (0x00100000 + 0x54)
#define SRCSIZE (0x00100000 + 0x58)
#define SRCXY (0x00100000 + 0x5c)
#define COLORBACK (0x00100000 + 0x60)
#define COLORFORE (0x00100000 + 0x64)
#define DSTSIZE (0x00100000 + 0x68)
#define DSTXY (0x00100000 + 0x6c)
#define COMMAND_2D (0x00100000 + 0x70)
#define LAUNCH_2D (0x00100000 + 0x80)
#define COMMAND_3D (0x00200000 + 0x120)
/* register bitfields (not all, only as needed) */
/* COMMAND_2D reg. values */
#define TDFX_ROP_COPY 0xcc /* src */
#define TDFX_ROP_INVERT 0x55 /* NOT dst */
#define TDFX_ROP_XOR 0x66 /* src XOR dst */
#define AUTOINC_DSTX BIT(10)
#define AUTOINC_DSTY BIT(11)
#define COMMAND_2D_FILLRECT 0x05
#define COMMAND_2D_S2S_BITBLT 0x01 /* screen to screen */
#define COMMAND_2D_H2S_BITBLT 0x03 /* host to screen */
#define COMMAND_3D_NOP 0x00
#define STATUS_RETRACE BIT(6)
#define STATUS_BUSY BIT(9)
#define MISCINIT1_CLUT_INV BIT(0)
#define MISCINIT1_2DBLOCK_DIS BIT(15)
#define DRAMINIT0_SGRAM_NUM BIT(26)
#define DRAMINIT0_SGRAM_TYPE BIT(27)
#define DRAMINIT0_SGRAM_TYPE_MASK (BIT(27) | BIT(28) | BIT(29))
#define DRAMINIT0_SGRAM_TYPE_SHIFT 27
#define DRAMINIT1_MEM_SDRAM BIT(30)
#define VGAINIT0_VGA_DISABLE BIT(0)
#define VGAINIT0_EXT_TIMING BIT(1)
#define VGAINIT0_8BIT_DAC BIT(2)
#define VGAINIT0_EXT_ENABLE BIT(6)
#define VGAINIT0_WAKEUP_3C3 BIT(8)
#define VGAINIT0_LEGACY_DISABLE BIT(9)
#define VGAINIT0_ALT_READBACK BIT(10)
#define VGAINIT0_FAST_BLINK BIT(11)
#define VGAINIT0_EXTSHIFTOUT BIT(12)
#define VGAINIT0_DECODE_3C6 BIT(13)
#define VGAINIT0_SGRAM_HBLANK_DISABLE BIT(22)
#define VGAINIT1_MASK 0x1fffff
#define VIDCFG_VIDPROC_ENABLE BIT(0)
#define VIDCFG_CURS_X11 BIT(1)
#define VIDCFG_INTERLACE BIT(3)
#define VIDCFG_HALF_MODE BIT(4)
#define VIDCFG_DESK_ENABLE BIT(7)
#define VIDCFG_CLUT_BYPASS BIT(10)
#define VIDCFG_2X BIT(26)
#define VIDCFG_HWCURSOR_ENABLE BIT(27)
#define VIDCFG_PIXFMT_SHIFT 18
#define DACMODE_2X BIT(0)
/* I2C bit locations in the VIDSERPARPORT register */
#define DDC_ENAB 0x00040000
#define DDC_SCL_OUT 0x00080000
#define DDC_SDA_OUT 0x00100000
#define DDC_SCL_IN 0x00200000
#define DDC_SDA_IN 0x00400000
#define I2C_ENAB 0x00800000
#define I2C_SCL_OUT 0x01000000
#define I2C_SDA_OUT 0x02000000
#define I2C_SCL_IN 0x04000000
#define I2C_SDA_IN 0x08000000
/* VGA rubbish, need to change this for multihead support */
#define MISC_W 0x3c2
#define MISC_R 0x3cc
#define SEQ_I 0x3c4
#define SEQ_D 0x3c5
#define CRT_I 0x3d4
#define CRT_D 0x3d5
#define ATT_IW 0x3c0
#define IS1_R 0x3da
#define GRA_I 0x3ce
#define GRA_D 0x3cf
#ifdef __KERNEL__
struct banshee_reg {
/* VGA rubbish */
unsigned char att[21];
unsigned char crt[25];
unsigned char gra[9];
unsigned char misc[1];
unsigned char seq[5];
/* Banshee extensions */
unsigned char ext[2];
unsigned long vidcfg;
unsigned long vidpll;
unsigned long mempll;
unsigned long gfxpll;
unsigned long dacmode;
unsigned long vgainit0;
unsigned long vgainit1;
unsigned long screensize;
unsigned long stride;
unsigned long cursloc;
unsigned long curspataddr;
unsigned long cursc0;
unsigned long cursc1;
unsigned long startaddr;
unsigned long clip0min;
unsigned long clip0max;
unsigned long clip1min;
unsigned long clip1max;
unsigned long miscinit0;
};
struct tdfx_par;
struct tdfxfb_i2c_chan {
struct tdfx_par *par;
struct i2c_adapter adapter;
struct i2c_algo_bit_data algo;
};
struct tdfx_par {
u32 max_pixclock;
u32 palette[16];
void __iomem *regbase_virt;
unsigned long iobase;
int mtrr_handle;
#ifdef CONFIG_FB_3DFX_I2C
struct tdfxfb_i2c_chan chan[2];
#endif
};
#endif /* __KERNEL__ */
#endif /* _TDFX_H */

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/*
* linux/drivers/video/tgafb.h -- DEC 21030 TGA frame buffer device
*
* Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
*
* $Id: tgafb.h,v 1.4.2.3 2000/04/04 06:44:56 mato Exp $
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*/
#ifndef TGAFB_H
#define TGAFB_H
/*
* TGA hardware description (minimal)
*/
#define TGA_TYPE_8PLANE 0
#define TGA_TYPE_24PLANE 1
#define TGA_TYPE_24PLUSZ 3
/*
* Offsets within Memory Space
*/
#define TGA_ROM_OFFSET 0x0000000
#define TGA_REGS_OFFSET 0x0100000
#define TGA_8PLANE_FB_OFFSET 0x0200000
#define TGA_24PLANE_FB_OFFSET 0x0804000
#define TGA_24PLUSZ_FB_OFFSET 0x1004000
#define TGA_FOREGROUND_REG 0x0020
#define TGA_BACKGROUND_REG 0x0024
#define TGA_PLANEMASK_REG 0x0028
#define TGA_PIXELMASK_ONESHOT_REG 0x002c
#define TGA_MODE_REG 0x0030
#define TGA_RASTEROP_REG 0x0034
#define TGA_PIXELSHIFT_REG 0x0038
#define TGA_DEEP_REG 0x0050
#define TGA_START_REG 0x0054
#define TGA_PIXELMASK_REG 0x005c
#define TGA_CURSOR_BASE_REG 0x0060
#define TGA_HORIZ_REG 0x0064
#define TGA_VERT_REG 0x0068
#define TGA_BASE_ADDR_REG 0x006c
#define TGA_VALID_REG 0x0070
#define TGA_CURSOR_XY_REG 0x0074
#define TGA_INTR_STAT_REG 0x007c
#define TGA_DATA_REG 0x0080
#define TGA_RAMDAC_SETUP_REG 0x00c0
#define TGA_BLOCK_COLOR0_REG 0x0140
#define TGA_BLOCK_COLOR1_REG 0x0144
#define TGA_BLOCK_COLOR2_REG 0x0148
#define TGA_BLOCK_COLOR3_REG 0x014c
#define TGA_BLOCK_COLOR4_REG 0x0150
#define TGA_BLOCK_COLOR5_REG 0x0154
#define TGA_BLOCK_COLOR6_REG 0x0158
#define TGA_BLOCK_COLOR7_REG 0x015c
#define TGA_COPY64_SRC 0x0160
#define TGA_COPY64_DST 0x0164
#define TGA_CLOCK_REG 0x01e8
#define TGA_RAMDAC_REG 0x01f0
#define TGA_CMD_STAT_REG 0x01f8
/*
* Useful defines for managing the registers
*/
#define TGA_HORIZ_ODD 0x80000000
#define TGA_HORIZ_POLARITY 0x40000000
#define TGA_HORIZ_ACT_MSB 0x30000000
#define TGA_HORIZ_BP 0x0fe00000
#define TGA_HORIZ_SYNC 0x001fc000
#define TGA_HORIZ_FP 0x00007c00
#define TGA_HORIZ_ACT_LSB 0x000001ff
#define TGA_VERT_SE 0x80000000
#define TGA_VERT_POLARITY 0x40000000
#define TGA_VERT_RESERVED 0x30000000
#define TGA_VERT_BP 0x0fc00000
#define TGA_VERT_SYNC 0x003f0000
#define TGA_VERT_FP 0x0000f800
#define TGA_VERT_ACTIVE 0x000007ff
#define TGA_VALID_VIDEO 0x01
#define TGA_VALID_BLANK 0x02
#define TGA_VALID_CURSOR 0x04
#define TGA_MODE_SBM_8BPP 0x000
#define TGA_MODE_SBM_24BPP 0x300
#define TGA_MODE_SIMPLE 0x00
#define TGA_MODE_SIMPLEZ 0x10
#define TGA_MODE_OPAQUE_STIPPLE 0x01
#define TGA_MODE_OPAQUE_FILL 0x21
#define TGA_MODE_TRANSPARENT_STIPPLE 0x03
#define TGA_MODE_TRANSPARENT_FILL 0x23
#define TGA_MODE_BLOCK_STIPPLE 0x0d
#define TGA_MODE_BLOCK_FILL 0x2d
#define TGA_MODE_COPY 0x07
#define TGA_MODE_DMA_READ_COPY_ND 0x17
#define TGA_MODE_DMA_READ_COPY_D 0x37
#define TGA_MODE_DMA_WRITE_COPY 0x1f
/*
* Useful defines for managing the ICS1562 PLL clock
*/
#define TGA_PLL_BASE_FREQ 14318 /* .18 */
#define TGA_PLL_MAX_FREQ 230000
/*
* Useful defines for managing the BT485 on the 8-plane TGA
*/
#define BT485_READ_BIT 0x01
#define BT485_WRITE_BIT 0x00
#define BT485_ADDR_PAL_WRITE 0x00
#define BT485_DATA_PAL 0x02
#define BT485_PIXEL_MASK 0x04
#define BT485_ADDR_PAL_READ 0x06
#define BT485_ADDR_CUR_WRITE 0x08
#define BT485_DATA_CUR 0x0a
#define BT485_CMD_0 0x0c
#define BT485_ADDR_CUR_READ 0x0e
#define BT485_CMD_1 0x10
#define BT485_CMD_2 0x12
#define BT485_STATUS 0x14
#define BT485_CMD_3 0x14
#define BT485_CUR_RAM 0x16
#define BT485_CUR_LOW_X 0x18
#define BT485_CUR_HIGH_X 0x1a
#define BT485_CUR_LOW_Y 0x1c
#define BT485_CUR_HIGH_Y 0x1e
/*
* Useful defines for managing the BT463 on the 24-plane TGAs/SFB+s
*/
#define BT463_ADDR_LO 0x0
#define BT463_ADDR_HI 0x1
#define BT463_REG_ACC 0x2
#define BT463_PALETTE 0x3
#define BT463_CUR_CLR_0 0x0100
#define BT463_CUR_CLR_1 0x0101
#define BT463_CMD_REG_0 0x0201
#define BT463_CMD_REG_1 0x0202
#define BT463_CMD_REG_2 0x0203
#define BT463_READ_MASK_0 0x0205
#define BT463_READ_MASK_1 0x0206
#define BT463_READ_MASK_2 0x0207
#define BT463_READ_MASK_3 0x0208
#define BT463_BLINK_MASK_0 0x0209
#define BT463_BLINK_MASK_1 0x020a
#define BT463_BLINK_MASK_2 0x020b
#define BT463_BLINK_MASK_3 0x020c
#define BT463_WINDOW_TYPE_BASE 0x0300
/*
* Useful defines for managing the BT459 on the 8-plane SFB+s
*/
#define BT459_ADDR_LO 0x0
#define BT459_ADDR_HI 0x1
#define BT459_REG_ACC 0x2
#define BT459_PALETTE 0x3
#define BT459_CUR_CLR_1 0x0181
#define BT459_CUR_CLR_2 0x0182
#define BT459_CUR_CLR_3 0x0183
#define BT459_CMD_REG_0 0x0201
#define BT459_CMD_REG_1 0x0202
#define BT459_CMD_REG_2 0x0203
#define BT459_READ_MASK 0x0204
#define BT459_BLINK_MASK 0x0206
#define BT459_CUR_CMD_REG 0x0300
/*
* The framebuffer driver private data.
*/
struct tga_par {
/* PCI/TC device. */
struct device *dev;
/* Device dependent information. */
void __iomem *tga_mem_base;
void __iomem *tga_fb_base;
void __iomem *tga_regs_base;
u8 tga_type; /* TGA_TYPE_XXX */
u8 tga_chip_rev; /* dc21030 revision */
/* Remember blank mode. */
u8 vesa_blanked;
/* Define the video mode. */
u32 xres, yres; /* resolution in pixels */
u32 htimings; /* horizontal timing register */
u32 vtimings; /* vertical timing register */
u32 pll_freq; /* pixclock in mhz */
u32 bits_per_pixel; /* bits per pixel */
u32 sync_on_green; /* set if sync is on green */
u32 palette[16];
};
/*
* Macros for reading/writing TGA and RAMDAC registers
*/
static inline void
TGA_WRITE_REG(struct tga_par *par, u32 v, u32 r)
{
writel(v, par->tga_regs_base +r);
}
static inline u32
TGA_READ_REG(struct tga_par *par, u32 r)
{
return readl(par->tga_regs_base +r);
}
static inline void
BT485_WRITE(struct tga_par *par, u8 v, u8 r)
{
TGA_WRITE_REG(par, r, TGA_RAMDAC_SETUP_REG);
TGA_WRITE_REG(par, v | (r << 8), TGA_RAMDAC_REG);
}
static inline void
BT463_LOAD_ADDR(struct tga_par *par, u16 a)
{
TGA_WRITE_REG(par, BT463_ADDR_LO<<2, TGA_RAMDAC_SETUP_REG);
TGA_WRITE_REG(par, (BT463_ADDR_LO<<10) | (a & 0xff), TGA_RAMDAC_REG);
TGA_WRITE_REG(par, BT463_ADDR_HI<<2, TGA_RAMDAC_SETUP_REG);
TGA_WRITE_REG(par, (BT463_ADDR_HI<<10) | (a >> 8), TGA_RAMDAC_REG);
}
static inline void
BT463_WRITE(struct tga_par *par, u32 m, u16 a, u8 v)
{
BT463_LOAD_ADDR(par, a);
TGA_WRITE_REG(par, m << 2, TGA_RAMDAC_SETUP_REG);
TGA_WRITE_REG(par, m << 10 | v, TGA_RAMDAC_REG);
}
static inline void
BT459_LOAD_ADDR(struct tga_par *par, u16 a)
{
TGA_WRITE_REG(par, BT459_ADDR_LO << 2, TGA_RAMDAC_SETUP_REG);
TGA_WRITE_REG(par, a & 0xff, TGA_RAMDAC_REG);
TGA_WRITE_REG(par, BT459_ADDR_HI << 2, TGA_RAMDAC_SETUP_REG);
TGA_WRITE_REG(par, a >> 8, TGA_RAMDAC_REG);
}
static inline void
BT459_WRITE(struct tga_par *par, u32 m, u16 a, u8 v)
{
BT459_LOAD_ADDR(par, a);
TGA_WRITE_REG(par, m << 2, TGA_RAMDAC_SETUP_REG);
TGA_WRITE_REG(par, v, TGA_RAMDAC_REG);
}
#endif /* TGAFB_H */

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#ifndef TRIDENTFB_DEBUG
#define TRIDENTFB_DEBUG 0
#endif
#if TRIDENTFB_DEBUG
#define debug(f, a...) printk("%s:" f, __func__ , ## a);
#else
#define debug(f, a...)
#endif
#define output(f, a...) pr_info("tridentfb: " f, ## a)
#define Kb (1024)
#define Mb (Kb*Kb)
/* PCI IDS of supported cards temporarily here */
#define CYBER9320 0x9320
#define CYBER9388 0x9388
#define CYBER9382 0x9382 /* the real PCI id for this is 9660 */
#define CYBER9385 0x9385 /* ditto */
#define CYBER9397 0x9397
#define CYBER9397DVD 0x939A
#define CYBER9520 0x9520
#define CYBER9525DVD 0x9525
#define TGUI9440 0x9440
#define TGUI9660 0x9660
#define PROVIDIA9685 0x9685
#define IMAGE975 0x9750
#define IMAGE985 0x9850
#define BLADE3D 0x9880
#define CYBERBLADEE4 0x9540
#define CYBERBLADEi7 0x8400
#define CYBERBLADEi7D 0x8420
#define CYBERBLADEi1 0x8500
#define CYBERBLADEi1D 0x8520
#define CYBERBLADEAi1 0x8600
#define CYBERBLADEAi1D 0x8620
#define CYBERBLADEXPAi1 0x8820
#define CYBERBLADEXPm8 0x9910
#define CYBERBLADEXPm16 0x9930
/* these defines are for 'lcd' variable */
#define LCD_STRETCH 0
#define LCD_CENTER 1
#define LCD_BIOS 2
/* General Registers */
#define SPR 0x1F /* Software Programming Register (videoram) */
/* 3C4 */
#define RevisionID 0x09
#define OldOrNew 0x0B
#define ConfPort1 0x0C
#define ConfPort2 0x0C
#define NewMode2 0x0D
#define NewMode1 0x0E
#define Protection 0x11
#define MCLKLow 0x16
#define MCLKHigh 0x17
#define ClockLow 0x18
#define ClockHigh 0x19
#define SSetup 0x20
#define SKey 0x37
#define SPKey 0x57
/* 3x4 */
#define CRTCModuleTest 0x1E
#define FIFOControl 0x20
#define LinearAddReg 0x21
#define DRAMTiming 0x23
#define New32 0x23
#define RAMDACTiming 0x25
#define CRTHiOrd 0x27
#define AddColReg 0x29
#define InterfaceSel 0x2A
#define HorizOverflow 0x2B
#define GETest 0x2D
#define Performance 0x2F
#define GraphEngReg 0x36
#define I2C 0x37
#define PixelBusReg 0x38
#define PCIReg 0x39
#define DRAMControl 0x3A
#define MiscContReg 0x3C
#define CursorXLow 0x40
#define CursorXHigh 0x41
#define CursorYLow 0x42
#define CursorYHigh 0x43
#define CursorLocLow 0x44
#define CursorLocHigh 0x45
#define CursorXOffset 0x46
#define CursorYOffset 0x47
#define CursorFG1 0x48
#define CursorFG2 0x49
#define CursorFG3 0x4A
#define CursorFG4 0x4B
#define CursorBG1 0x4C
#define CursorBG2 0x4D
#define CursorBG3 0x4E
#define CursorBG4 0x4F
#define CursorControl 0x50
#define PCIRetry 0x55
#define PreEndControl 0x56
#define PreEndFetch 0x57
#define PCIMaster 0x60
#define Enhancement0 0x62
#define NewEDO 0x64
#define TVinterface 0xC0
#define TVMode 0xC1
#define ClockControl 0xCF
/* 3CE */
#define MiscExtFunc 0x0F
#define PowerStatus 0x23
#define MiscIntContReg 0x2F
#define CyberControl 0x30
#define CyberEnhance 0x31
#define FPConfig 0x33
#define VertStretch 0x52
#define HorStretch 0x53
#define BiosMode 0x5c
#define BiosReg 0x5d
/* Graphics Engine */
#define STATUS 0x2120
#define OLDCMD 0x2124
#define DRAWFL 0x2128
#define OLDCLR 0x212C
#define OLDDST 0x2138
#define OLDSRC 0x213C
#define OLDDIM 0x2140
#define CMD 0x2144
#define ROP 0x2148
#define COLOR 0x2160
#define BGCOLOR 0x2164
#define SRC1 0x2100
#define SRC2 0x2104
#define DST1 0x2108
#define DST2 0x210C
#define ROP_S 0xCC
#define ROP_P 0xF0
#define ROP_X 0x66

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#ifndef UDLFB_H
#define UDLFB_H
/*
* TODO: Propose standard fb.h ioctl for reporting damage,
* using _IOWR() and one of the existing area structs from fb.h
* Consider these ioctls deprecated, but they're still used by the
* DisplayLink X server as yet - need both to be modified in tandem
* when new ioctl(s) are ready.
*/
#define DLFB_IOCTL_RETURN_EDID 0xAD
#define DLFB_IOCTL_REPORT_DAMAGE 0xAA
struct dloarea {
int x, y;
int w, h;
int x2, y2;
};
struct urb_node {
struct list_head entry;
struct dlfb_data *dev;
struct delayed_work release_urb_work;
struct urb *urb;
};
struct urb_list {
struct list_head list;
spinlock_t lock;
struct semaphore limit_sem;
int available;
int count;
size_t size;
};
struct dlfb_data {
struct usb_device *udev;
struct device *gdev; /* &udev->dev */
struct fb_info *info;
struct urb_list urbs;
struct kref kref;
char *backing_buffer;
int fb_count;
bool virtualized; /* true when physical usb device not present */
struct delayed_work init_framebuffer_work;
struct delayed_work free_framebuffer_work;
atomic_t usb_active; /* 0 = update virtual buffer, but no usb traffic */
atomic_t lost_pixels; /* 1 = a render op failed. Need screen refresh */
char *edid; /* null until we read edid from hw or get from sysfs */
size_t edid_size;
int sku_pixel_limit;
int base16;
int base8;
u32 pseudo_palette[256];
int blank_mode; /*one of FB_BLANK_ */
/* blit-only rendering path metrics, exposed through sysfs */
atomic_t bytes_rendered; /* raw pixel-bytes driver asked to render */
atomic_t bytes_identical; /* saved effort with backbuffer comparison */
atomic_t bytes_sent; /* to usb, after compression including overhead */
atomic_t cpu_kcycles_used; /* transpired during pixel processing */
};
#define NR_USB_REQUEST_I2C_SUB_IO 0x02
#define NR_USB_REQUEST_CHANNEL 0x12
/* -BULK_SIZE as per usb-skeleton. Can we get full page and avoid overhead? */
#define BULK_SIZE 512
#define MAX_TRANSFER (PAGE_SIZE*16 - BULK_SIZE)
#define WRITES_IN_FLIGHT (4)
#define MAX_VENDOR_DESCRIPTOR_SIZE 256
#define GET_URB_TIMEOUT HZ
#define FREE_URB_TIMEOUT (HZ*2)
#define BPP 2
#define MAX_CMD_PIXELS 255
#define RLX_HEADER_BYTES 7
#define MIN_RLX_PIX_BYTES 4
#define MIN_RLX_CMD_BYTES (RLX_HEADER_BYTES + MIN_RLX_PIX_BYTES)
#define RLE_HEADER_BYTES 6
#define MIN_RLE_PIX_BYTES 3
#define MIN_RLE_CMD_BYTES (RLE_HEADER_BYTES + MIN_RLE_PIX_BYTES)
#define RAW_HEADER_BYTES 6
#define MIN_RAW_PIX_BYTES 2
#define MIN_RAW_CMD_BYTES (RAW_HEADER_BYTES + MIN_RAW_PIX_BYTES)
#define DL_DEFIO_WRITE_DELAY 5 /* fb_deferred_io.delay in jiffies */
#define DL_DEFIO_WRITE_DISABLE (HZ*60) /* "disable" with long delay */
/* remove these once align.h patch is taken into kernel */
#define DL_ALIGN_UP(x, a) ALIGN(x, a)
#define DL_ALIGN_DOWN(x, a) ALIGN(x-(a-1), a)
#endif

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#ifndef _UVESAFB_H
#define _UVESAFB_H
#include <uapi/video/uvesafb.h>
/* VBE CRTC Info Block */
struct vbe_crtc_ib {
u16 horiz_total;
u16 horiz_start;
u16 horiz_end;
u16 vert_total;
u16 vert_start;
u16 vert_end;
u8 flags;
u32 pixel_clock;
u16 refresh_rate;
u8 reserved[40];
} __attribute__ ((packed));
#define VBE_MODE_VGACOMPAT 0x20
#define VBE_MODE_COLOR 0x08
#define VBE_MODE_SUPPORTEDHW 0x01
#define VBE_MODE_GRAPHICS 0x10
#define VBE_MODE_LFB 0x80
#define VBE_MODE_MASK (VBE_MODE_COLOR | VBE_MODE_SUPPORTEDHW | \
VBE_MODE_GRAPHICS | VBE_MODE_LFB)
/* VBE Mode Info Block */
struct vbe_mode_ib {
/* for all VBE revisions */
u16 mode_attr;
u8 winA_attr;
u8 winB_attr;
u16 win_granularity;
u16 win_size;
u16 winA_seg;
u16 winB_seg;
u32 win_func_ptr;
u16 bytes_per_scan_line;
/* for VBE 1.2+ */
u16 x_res;
u16 y_res;
u8 x_char_size;
u8 y_char_size;
u8 planes;
u8 bits_per_pixel;
u8 banks;
u8 memory_model;
u8 bank_size;
u8 image_pages;
u8 reserved1;
/* Direct color fields for direct/6 and YUV/7 memory models. */
/* Offsets are bit positions of lsb in the mask. */
u8 red_len;
u8 red_off;
u8 green_len;
u8 green_off;
u8 blue_len;
u8 blue_off;
u8 rsvd_len;
u8 rsvd_off;
u8 direct_color_info; /* direct color mode attributes */
/* for VBE 2.0+ */
u32 phys_base_ptr;
u8 reserved2[6];
/* for VBE 3.0+ */
u16 lin_bytes_per_scan_line;
u8 bnk_image_pages;
u8 lin_image_pages;
u8 lin_red_len;
u8 lin_red_off;
u8 lin_green_len;
u8 lin_green_off;
u8 lin_blue_len;
u8 lin_blue_off;
u8 lin_rsvd_len;
u8 lin_rsvd_off;
u32 max_pixel_clock;
u16 mode_id;
u8 depth;
} __attribute__ ((packed));
#define UVESAFB_DEFAULT_MODE "640x480-16"
/* How long to wait for a reply from userspace [ms] */
#define UVESAFB_TIMEOUT 5000
/* Max number of concurrent tasks */
#define UVESAFB_TASKS_MAX 16
#define dac_reg (0x3c8)
#define dac_val (0x3c9)
struct uvesafb_pal_entry {
u_char blue, green, red, pad;
} __attribute__ ((packed));
struct uvesafb_ktask {
struct uvesafb_task t;
void *buf;
struct completion *done;
u32 ack;
};
static int uvesafb_exec(struct uvesafb_ktask *tsk);
#define UVESAFB_EXACT_RES 1
#define UVESAFB_EXACT_DEPTH 2
struct uvesafb_par {
struct vbe_ib vbe_ib; /* VBE Info Block */
struct vbe_mode_ib *vbe_modes; /* list of supported VBE modes */
int vbe_modes_cnt;
u8 nocrtc;
u8 ypan; /* 0 - nothing, 1 - ypan, 2 - ywrap */
u8 pmi_setpal; /* PMI for palette changes */
u16 *pmi_base; /* protected mode interface location */
void *pmi_start;
void *pmi_pal;
u8 *vbe_state_orig; /*
* original hardware state, before the
* driver was loaded
*/
u8 *vbe_state_saved; /* state saved by fb_save_state */
int vbe_state_size;
atomic_t ref_count;
int mode_idx;
struct vbe_crtc_ib crtc;
int mtrr_handle;
};
#endif /* _UVESAFB_H */

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/*
* linux/include/video/vga.h -- standard VGA chipset interaction
*
* Copyright 1999 Jeff Garzik <jgarzik@pobox.com>
*
* Copyright history from vga16fb.c:
* Copyright 1999 Ben Pfaff and Petr Vandrovec
* Based on VGA info at http://www.osdever.net/FreeVGA/home.htm
* Based on VESA framebuffer (c) 1998 Gerd Knorr
*
* This file is subject to the terms and conditions of the GNU General
* Public License. See the file COPYING in the main directory of this
* archive for more details.
*
*/
#ifndef __linux_video_vga_h__
#define __linux_video_vga_h__
#include <linux/types.h>
#include <asm/io.h>
#include <asm/vga.h>
#include <asm/byteorder.h>
/* Some of the code below is taken from SVGAlib. The original,
unmodified copyright notice for that code is below. */
/* VGAlib version 1.2 - (c) 1993 Tommy Frandsen */
/* */
/* This library is free software; you can redistribute it and/or */
/* modify it without any restrictions. This library is distributed */
/* in the hope that it will be useful, but without any warranty. */
/* Multi-chipset support Copyright 1993 Harm Hanemaayer */
/* partially copyrighted (C) 1993 by Hartmut Schirmer */
/* VGA data register ports */
#define VGA_CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */
#define VGA_CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */
#define VGA_ATT_R 0x3C1 /* Attribute Controller Data Read Register */
#define VGA_ATT_W 0x3C0 /* Attribute Controller Data Write Register */
#define VGA_GFX_D 0x3CF /* Graphics Controller Data Register */
#define VGA_SEQ_D 0x3C5 /* Sequencer Data Register */
#define VGA_MIS_R 0x3CC /* Misc Output Read Register */
#define VGA_MIS_W 0x3C2 /* Misc Output Write Register */
#define VGA_FTC_R 0x3CA /* Feature Control Read Register */
#define VGA_IS1_RC 0x3DA /* Input Status Register 1 - color emulation */
#define VGA_IS1_RM 0x3BA /* Input Status Register 1 - mono emulation */
#define VGA_PEL_D 0x3C9 /* PEL Data Register */
#define VGA_PEL_MSK 0x3C6 /* PEL mask register */
/* EGA-specific registers */
#define EGA_GFX_E0 0x3CC /* Graphics enable processor 0 */
#define EGA_GFX_E1 0x3CA /* Graphics enable processor 1 */
/* VGA index register ports */
#define VGA_CRT_IC 0x3D4 /* CRT Controller Index - color emulation */
#define VGA_CRT_IM 0x3B4 /* CRT Controller Index - mono emulation */
#define VGA_ATT_IW 0x3C0 /* Attribute Controller Index & Data Write Register */
#define VGA_GFX_I 0x3CE /* Graphics Controller Index */
#define VGA_SEQ_I 0x3C4 /* Sequencer Index */
#define VGA_PEL_IW 0x3C8 /* PEL Write Index */
#define VGA_PEL_IR 0x3C7 /* PEL Read Index */
/* standard VGA indexes max counts */
#define VGA_CRT_C 0x19 /* Number of CRT Controller Registers */
#define VGA_ATT_C 0x15 /* Number of Attribute Controller Registers */
#define VGA_GFX_C 0x09 /* Number of Graphics Controller Registers */
#define VGA_SEQ_C 0x05 /* Number of Sequencer Registers */
#define VGA_MIS_C 0x01 /* Number of Misc Output Register */
/* VGA misc register bit masks */
#define VGA_MIS_COLOR 0x01
#define VGA_MIS_ENB_MEM_ACCESS 0x02
#define VGA_MIS_DCLK_28322_720 0x04
#define VGA_MIS_ENB_PLL_LOAD (0x04 | 0x08)
#define VGA_MIS_SEL_HIGH_PAGE 0x20
/* VGA CRT controller register indices */
#define VGA_CRTC_H_TOTAL 0
#define VGA_CRTC_H_DISP 1
#define VGA_CRTC_H_BLANK_START 2
#define VGA_CRTC_H_BLANK_END 3
#define VGA_CRTC_H_SYNC_START 4
#define VGA_CRTC_H_SYNC_END 5
#define VGA_CRTC_V_TOTAL 6
#define VGA_CRTC_OVERFLOW 7
#define VGA_CRTC_PRESET_ROW 8
#define VGA_CRTC_MAX_SCAN 9
#define VGA_CRTC_CURSOR_START 0x0A
#define VGA_CRTC_CURSOR_END 0x0B
#define VGA_CRTC_START_HI 0x0C
#define VGA_CRTC_START_LO 0x0D
#define VGA_CRTC_CURSOR_HI 0x0E
#define VGA_CRTC_CURSOR_LO 0x0F
#define VGA_CRTC_V_SYNC_START 0x10
#define VGA_CRTC_V_SYNC_END 0x11
#define VGA_CRTC_V_DISP_END 0x12
#define VGA_CRTC_OFFSET 0x13
#define VGA_CRTC_UNDERLINE 0x14
#define VGA_CRTC_V_BLANK_START 0x15
#define VGA_CRTC_V_BLANK_END 0x16
#define VGA_CRTC_MODE 0x17
#define VGA_CRTC_LINE_COMPARE 0x18
#define VGA_CRTC_REGS VGA_CRT_C
/* VGA CRT controller bit masks */
#define VGA_CR11_LOCK_CR0_CR7 0x80 /* lock writes to CR0 - CR7 */
#define VGA_CR17_H_V_SIGNALS_ENABLED 0x80
/* VGA attribute controller register indices */
#define VGA_ATC_PALETTE0 0x00
#define VGA_ATC_PALETTE1 0x01
#define VGA_ATC_PALETTE2 0x02
#define VGA_ATC_PALETTE3 0x03
#define VGA_ATC_PALETTE4 0x04
#define VGA_ATC_PALETTE5 0x05
#define VGA_ATC_PALETTE6 0x06
#define VGA_ATC_PALETTE7 0x07
#define VGA_ATC_PALETTE8 0x08
#define VGA_ATC_PALETTE9 0x09
#define VGA_ATC_PALETTEA 0x0A
#define VGA_ATC_PALETTEB 0x0B
#define VGA_ATC_PALETTEC 0x0C
#define VGA_ATC_PALETTED 0x0D
#define VGA_ATC_PALETTEE 0x0E
#define VGA_ATC_PALETTEF 0x0F
#define VGA_ATC_MODE 0x10
#define VGA_ATC_OVERSCAN 0x11
#define VGA_ATC_PLANE_ENABLE 0x12
#define VGA_ATC_PEL 0x13
#define VGA_ATC_COLOR_PAGE 0x14
#define VGA_AR_ENABLE_DISPLAY 0x20
/* VGA sequencer register indices */
#define VGA_SEQ_RESET 0x00
#define VGA_SEQ_CLOCK_MODE 0x01
#define VGA_SEQ_PLANE_WRITE 0x02
#define VGA_SEQ_CHARACTER_MAP 0x03
#define VGA_SEQ_MEMORY_MODE 0x04
/* VGA sequencer register bit masks */
#define VGA_SR01_CHAR_CLK_8DOTS 0x01 /* bit 0: character clocks 8 dots wide are generated */
#define VGA_SR01_SCREEN_OFF 0x20 /* bit 5: Screen is off */
#define VGA_SR02_ALL_PLANES 0x0F /* bits 3-0: enable access to all planes */
#define VGA_SR04_EXT_MEM 0x02 /* bit 1: allows complete mem access to 256K */
#define VGA_SR04_SEQ_MODE 0x04 /* bit 2: directs system to use a sequential addressing mode */
#define VGA_SR04_CHN_4M 0x08 /* bit 3: selects modulo 4 addressing for CPU access to display memory */
/* VGA graphics controller register indices */
#define VGA_GFX_SR_VALUE 0x00
#define VGA_GFX_SR_ENABLE 0x01
#define VGA_GFX_COMPARE_VALUE 0x02
#define VGA_GFX_DATA_ROTATE 0x03
#define VGA_GFX_PLANE_READ 0x04
#define VGA_GFX_MODE 0x05
#define VGA_GFX_MISC 0x06
#define VGA_GFX_COMPARE_MASK 0x07
#define VGA_GFX_BIT_MASK 0x08
/* VGA graphics controller bit masks */
#define VGA_GR06_GRAPHICS_MODE 0x01
/* macro for composing an 8-bit VGA register index and value
* into a single 16-bit quantity */
#define VGA_OUT16VAL(v, r) (((v) << 8) | (r))
/* decide whether we should enable the faster 16-bit VGA register writes */
#ifdef __LITTLE_ENDIAN
#define VGA_OUTW_WRITE
#endif
/* VGA State Save and Restore */
#define VGA_SAVE_FONT0 1 /* save/restore plane 2 fonts */
#define VGA_SAVE_FONT1 2 /* save/restore plane 3 fonts */
#define VGA_SAVE_TEXT 4 /* save/restore plane 0/1 fonts */
#define VGA_SAVE_FONTS 7 /* save/restore all fonts */
#define VGA_SAVE_MODE 8 /* save/restore video mode */
#define VGA_SAVE_CMAP 16 /* save/restore color map/DAC */
struct vgastate {
void __iomem *vgabase; /* mmio base, if supported */
unsigned long membase; /* VGA window base, 0 for default - 0xA000 */
__u32 memsize; /* VGA window size, 0 for default 64K */
__u32 flags; /* what state[s] to save (see VGA_SAVE_*) */
__u32 depth; /* current fb depth, not important */
__u32 num_attr; /* number of att registers, 0 for default */
__u32 num_crtc; /* number of crt registers, 0 for default */
__u32 num_gfx; /* number of gfx registers, 0 for default */
__u32 num_seq; /* number of seq registers, 0 for default */
void *vidstate;
};
extern int save_vga(struct vgastate *state);
extern int restore_vga(struct vgastate *state);
/*
* generic VGA port read/write
*/
static inline unsigned char vga_io_r (unsigned short port)
{
return inb_p(port);
}
static inline void vga_io_w (unsigned short port, unsigned char val)
{
outb_p(val, port);
}
static inline void vga_io_w_fast (unsigned short port, unsigned char reg,
unsigned char val)
{
outw(VGA_OUT16VAL (val, reg), port);
}
static inline unsigned char vga_mm_r (void __iomem *regbase, unsigned short port)
{
return readb (regbase + port);
}
static inline void vga_mm_w (void __iomem *regbase, unsigned short port, unsigned char val)
{
writeb (val, regbase + port);
}
static inline void vga_mm_w_fast (void __iomem *regbase, unsigned short port,
unsigned char reg, unsigned char val)
{
writew (VGA_OUT16VAL (val, reg), regbase + port);
}
static inline unsigned char vga_r (void __iomem *regbase, unsigned short port)
{
if (regbase)
return vga_mm_r (regbase, port);
else
return vga_io_r (port);
}
static inline void vga_w (void __iomem *regbase, unsigned short port, unsigned char val)
{
if (regbase)
vga_mm_w (regbase, port, val);
else
vga_io_w (port, val);
}
static inline void vga_w_fast (void __iomem *regbase, unsigned short port,
unsigned char reg, unsigned char val)
{
if (regbase)
vga_mm_w_fast (regbase, port, reg, val);
else
vga_io_w_fast (port, reg, val);
}
/*
* VGA CRTC register read/write
*/
static inline unsigned char vga_rcrt (void __iomem *regbase, unsigned char reg)
{
vga_w (regbase, VGA_CRT_IC, reg);
return vga_r (regbase, VGA_CRT_DC);
}
static inline void vga_wcrt (void __iomem *regbase, unsigned char reg, unsigned char val)
{
#ifdef VGA_OUTW_WRITE
vga_w_fast (regbase, VGA_CRT_IC, reg, val);
#else
vga_w (regbase, VGA_CRT_IC, reg);
vga_w (regbase, VGA_CRT_DC, val);
#endif /* VGA_OUTW_WRITE */
}
static inline unsigned char vga_io_rcrt (unsigned char reg)
{
vga_io_w (VGA_CRT_IC, reg);
return vga_io_r (VGA_CRT_DC);
}
static inline void vga_io_wcrt (unsigned char reg, unsigned char val)
{
#ifdef VGA_OUTW_WRITE
vga_io_w_fast (VGA_CRT_IC, reg, val);
#else
vga_io_w (VGA_CRT_IC, reg);
vga_io_w (VGA_CRT_DC, val);
#endif /* VGA_OUTW_WRITE */
}
static inline unsigned char vga_mm_rcrt (void __iomem *regbase, unsigned char reg)
{
vga_mm_w (regbase, VGA_CRT_IC, reg);
return vga_mm_r (regbase, VGA_CRT_DC);
}
static inline void vga_mm_wcrt (void __iomem *regbase, unsigned char reg, unsigned char val)
{
#ifdef VGA_OUTW_WRITE
vga_mm_w_fast (regbase, VGA_CRT_IC, reg, val);
#else
vga_mm_w (regbase, VGA_CRT_IC, reg);
vga_mm_w (regbase, VGA_CRT_DC, val);
#endif /* VGA_OUTW_WRITE */
}
/*
* VGA sequencer register read/write
*/
static inline unsigned char vga_rseq (void __iomem *regbase, unsigned char reg)
{
vga_w (regbase, VGA_SEQ_I, reg);
return vga_r (regbase, VGA_SEQ_D);
}
static inline void vga_wseq (void __iomem *regbase, unsigned char reg, unsigned char val)
{
#ifdef VGA_OUTW_WRITE
vga_w_fast (regbase, VGA_SEQ_I, reg, val);
#else
vga_w (regbase, VGA_SEQ_I, reg);
vga_w (regbase, VGA_SEQ_D, val);
#endif /* VGA_OUTW_WRITE */
}
static inline unsigned char vga_io_rseq (unsigned char reg)
{
vga_io_w (VGA_SEQ_I, reg);
return vga_io_r (VGA_SEQ_D);
}
static inline void vga_io_wseq (unsigned char reg, unsigned char val)
{
#ifdef VGA_OUTW_WRITE
vga_io_w_fast (VGA_SEQ_I, reg, val);
#else
vga_io_w (VGA_SEQ_I, reg);
vga_io_w (VGA_SEQ_D, val);
#endif /* VGA_OUTW_WRITE */
}
static inline unsigned char vga_mm_rseq (void __iomem *regbase, unsigned char reg)
{
vga_mm_w (regbase, VGA_SEQ_I, reg);
return vga_mm_r (regbase, VGA_SEQ_D);
}
static inline void vga_mm_wseq (void __iomem *regbase, unsigned char reg, unsigned char val)
{
#ifdef VGA_OUTW_WRITE
vga_mm_w_fast (regbase, VGA_SEQ_I, reg, val);
#else
vga_mm_w (regbase, VGA_SEQ_I, reg);
vga_mm_w (regbase, VGA_SEQ_D, val);
#endif /* VGA_OUTW_WRITE */
}
/*
* VGA graphics controller register read/write
*/
static inline unsigned char vga_rgfx (void __iomem *regbase, unsigned char reg)
{
vga_w (regbase, VGA_GFX_I, reg);
return vga_r (regbase, VGA_GFX_D);
}
static inline void vga_wgfx (void __iomem *regbase, unsigned char reg, unsigned char val)
{
#ifdef VGA_OUTW_WRITE
vga_w_fast (regbase, VGA_GFX_I, reg, val);
#else
vga_w (regbase, VGA_GFX_I, reg);
vga_w (regbase, VGA_GFX_D, val);
#endif /* VGA_OUTW_WRITE */
}
static inline unsigned char vga_io_rgfx (unsigned char reg)
{
vga_io_w (VGA_GFX_I, reg);
return vga_io_r (VGA_GFX_D);
}
static inline void vga_io_wgfx (unsigned char reg, unsigned char val)
{
#ifdef VGA_OUTW_WRITE
vga_io_w_fast (VGA_GFX_I, reg, val);
#else
vga_io_w (VGA_GFX_I, reg);
vga_io_w (VGA_GFX_D, val);
#endif /* VGA_OUTW_WRITE */
}
static inline unsigned char vga_mm_rgfx (void __iomem *regbase, unsigned char reg)
{
vga_mm_w (regbase, VGA_GFX_I, reg);
return vga_mm_r (regbase, VGA_GFX_D);
}
static inline void vga_mm_wgfx (void __iomem *regbase, unsigned char reg, unsigned char val)
{
#ifdef VGA_OUTW_WRITE
vga_mm_w_fast (regbase, VGA_GFX_I, reg, val);
#else
vga_mm_w (regbase, VGA_GFX_I, reg);
vga_mm_w (regbase, VGA_GFX_D, val);
#endif /* VGA_OUTW_WRITE */
}
/*
* VGA attribute controller register read/write
*/
static inline unsigned char vga_rattr (void __iomem *regbase, unsigned char reg)
{
vga_w (regbase, VGA_ATT_IW, reg);
return vga_r (regbase, VGA_ATT_R);
}
static inline void vga_wattr (void __iomem *regbase, unsigned char reg, unsigned char val)
{
vga_w (regbase, VGA_ATT_IW, reg);
vga_w (regbase, VGA_ATT_W, val);
}
static inline unsigned char vga_io_rattr (unsigned char reg)
{
vga_io_w (VGA_ATT_IW, reg);
return vga_io_r (VGA_ATT_R);
}
static inline void vga_io_wattr (unsigned char reg, unsigned char val)
{
vga_io_w (VGA_ATT_IW, reg);
vga_io_w (VGA_ATT_W, val);
}
static inline unsigned char vga_mm_rattr (void __iomem *regbase, unsigned char reg)
{
vga_mm_w (regbase, VGA_ATT_IW, reg);
return vga_mm_r (regbase, VGA_ATT_R);
}
static inline void vga_mm_wattr (void __iomem *regbase, unsigned char reg, unsigned char val)
{
vga_mm_w (regbase, VGA_ATT_IW, reg);
vga_mm_w (regbase, VGA_ATT_W, val);
}
#endif /* __linux_video_vga_h__ */

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/*
* Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>
*
* generic videomode description
*
* This file is released under the GPLv2
*/
#ifndef __LINUX_VIDEOMODE_H
#define __LINUX_VIDEOMODE_H
#include <linux/types.h>
#include <video/display_timing.h>
/*
* Subsystem independent description of a videomode.
* Can be generated from struct display_timing.
*/
struct videomode {
unsigned long pixelclock; /* pixelclock in Hz */
u32 hactive;
u32 hfront_porch;
u32 hback_porch;
u32 hsync_len;
u32 vactive;
u32 vfront_porch;
u32 vback_porch;
u32 vsync_len;
enum display_flags flags; /* display flags */
};
/**
* videomode_from_timing - convert display timing to videomode
* @dt: display_timing structure
* @vm: return value
*
* DESCRIPTION:
* This function converts a struct display_timing to a struct videomode.
*/
void videomode_from_timing(const struct display_timing *dt,
struct videomode *vm);
/**
* videomode_from_timings - convert one display timings entry to videomode
* @disp: structure with all possible timing entries
* @vm: return value
* @index: index into the list of display timings in devicetree
*
* DESCRIPTION:
* This function converts one struct display_timing entry to a struct videomode.
*/
int videomode_from_timings(const struct display_timings *disp,
struct videomode *vm, unsigned int index);
#endif

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/* include/video/videonode.h
*
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Video node definitions for EXYNOS
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __VIDEO_VIDEONODE_H
#define __VIDEO_VIDEONODE_H __FILE__
#define EXYNOS_VIDEONODE_MFC_DEC 6
#define EXYNOS_VIDEONODE_MFC_ENC 7
#define EXYNOS_VIDEONODE_MFC_DEC_DRM 8
#define EXYNOS_VIDEONODE_MFC_ENC_DRM 9
#define EXYNOS_VIDEONODE_JPEG_HX_DEC(x) (13 - (x) * 2)
#define EXYNOS_VIDEONODE_JPEG_HX_ENC(x) (14 - (x) * 2)
#define EXYNOS_VIDEONODE_SCALER(x) (50 + x)
#define EXYNOS_VIDEONODE_FIMG2D 55
/* 100 ~ 149 is used by FIMC-IS */
#define EXYNOS_VIDEONODE_FIMC_IS (100)
#endif /* __VIDEO_VIDEONODE_H */

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/*
* Support for the w100 frame buffer.
*
* Copyright (c) 2004-2005 Richard Purdie
* Copyright (c) 2005 Ian Molton
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define W100_GPIO_PORT_A 0
#define W100_GPIO_PORT_B 1
#define CLK_SRC_XTAL 0
#define CLK_SRC_PLL 1
struct w100fb_par;
unsigned long w100fb_gpio_read(int port);
void w100fb_gpio_write(int port, unsigned long value);
unsigned long w100fb_get_hsynclen(struct device *dev);
/* LCD Specific Routines and Config */
struct w100_tg_info {
void (*change)(struct w100fb_par*);
void (*suspend)(struct w100fb_par*);
void (*resume)(struct w100fb_par*);
};
/* General Platform Specific w100 Register Values */
struct w100_gen_regs {
unsigned long lcd_format;
unsigned long lcdd_cntl1;
unsigned long lcdd_cntl2;
unsigned long genlcd_cntl1;
unsigned long genlcd_cntl2;
unsigned long genlcd_cntl3;
};
struct w100_gpio_regs {
unsigned long init_data1;
unsigned long init_data2;
unsigned long gpio_dir1;
unsigned long gpio_oe1;
unsigned long gpio_dir2;
unsigned long gpio_oe2;
};
/* Optional External Memory Configuration */
struct w100_mem_info {
unsigned long ext_cntl;
unsigned long sdram_mode_reg;
unsigned long ext_timing_cntl;
unsigned long io_cntl;
unsigned int size;
};
struct w100_bm_mem_info {
unsigned long ext_mem_bw;
unsigned long offset;
unsigned long ext_timing_ctl;
unsigned long ext_cntl;
unsigned long mode_reg;
unsigned long io_cntl;
unsigned long config;
};
/* LCD Mode definition */
struct w100_mode {
unsigned int xres;
unsigned int yres;
unsigned short left_margin;
unsigned short right_margin;
unsigned short upper_margin;
unsigned short lower_margin;
unsigned long crtc_ss;
unsigned long crtc_ls;
unsigned long crtc_gs;
unsigned long crtc_vpos_gs;
unsigned long crtc_rev;
unsigned long crtc_dclk;
unsigned long crtc_gclk;
unsigned long crtc_goe;
unsigned long crtc_ps1_active;
char pll_freq;
char fast_pll_freq;
int sysclk_src;
int sysclk_divider;
int pixclk_src;
int pixclk_divider;
int pixclk_divider_rotated;
};
struct w100_pll_info {
uint16_t freq; /* desired Fout for PLL (Mhz) */
uint8_t M; /* input divider */
uint8_t N_int; /* VCO multiplier */
uint8_t N_fac; /* VCO multiplier fractional part */
uint8_t tfgoal;
uint8_t lock_time;
};
/* Initial Video mode orientation flags */
#define INIT_MODE_ROTATED 0x1
#define INIT_MODE_FLIPPED 0x2
/*
* This structure describes the machine which we are running on.
* It is set by machine specific code and used in the probe routine
* of drivers/video/w100fb.c
*/
struct w100fb_mach_info {
/* General Platform Specific Registers */
struct w100_gen_regs *regs;
/* Table of modes the LCD is capable of */
struct w100_mode *modelist;
unsigned int num_modes;
/* Hooks for any platform specific tg/lcd code (optional) */
struct w100_tg_info *tg;
/* External memory definition (if present) */
struct w100_mem_info *mem;
/* Additional External memory definition (if present) */
struct w100_bm_mem_info *bm_mem;
/* GPIO definitions (optional) */
struct w100_gpio_regs *gpio;
/* Initial Mode flags */
unsigned int init_mode;
/* Xtal Frequency */
unsigned int xtal_freq;
/* Enable Xtal input doubler (1 == enable) */
unsigned int xtal_dbl;
};
/* General frame buffer data structure */
struct w100fb_par {
unsigned int chip_id;
unsigned int xres;
unsigned int yres;
unsigned int extmem_active;
unsigned int flip;
unsigned int blanked;
unsigned int fastpll_mode;
unsigned long hsync_len;
struct w100_mode *mode;
struct w100_pll_info *pll_table;
struct w100fb_mach_info *mach;
uint32_t *saved_intmem;
uint32_t *saved_extmem;
};