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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-10 09:22:44 -04:00
Fixed MTP to work with TWRP
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commit
f6dfaef42e
50820 changed files with 20846062 additions and 0 deletions
162
sound/pci/echoaudio/darla24_dsp.c
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162
sound/pci/echoaudio/darla24_dsp.c
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/***************************************************************************
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Copyright Echo Digital Audio Corporation (c) 1998 - 2004
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All rights reserved
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www.echoaudio.com
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This file is part of Echo Digital Audio's generic driver library.
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Echo Digital Audio's generic driver library is free software;
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you can redistribute it and/or modify it under the terms of
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the GNU General Public License as published by the Free Software
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Foundation.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston,
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MA 02111-1307, USA.
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*************************************************************************
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Translation from C++ and adaptation for use in ALSA-Driver
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were made by Giuliano Pochini <pochini@shiny.it>
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****************************************************************************/
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static int init_hw(struct echoaudio *chip, u16 device_id, u16 subdevice_id)
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{
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int err;
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DE_INIT(("init_hw() - Darla24\n"));
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if (snd_BUG_ON((subdevice_id & 0xfff0) != DARLA24))
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return -ENODEV;
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if ((err = init_dsp_comm_page(chip))) {
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DE_INIT(("init_hw - could not initialize DSP comm page\n"));
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return err;
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}
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chip->device_id = device_id;
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chip->subdevice_id = subdevice_id;
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chip->bad_board = TRUE;
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chip->dsp_code_to_load = FW_DARLA24_DSP;
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/* Since this card has no ASIC, mark it as loaded so everything
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works OK */
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chip->asic_loaded = TRUE;
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chip->input_clock_types = ECHO_CLOCK_BIT_INTERNAL |
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ECHO_CLOCK_BIT_ESYNC;
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if ((err = load_firmware(chip)) < 0)
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return err;
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chip->bad_board = FALSE;
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DE_INIT(("init_hw done\n"));
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return err;
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}
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static int set_mixer_defaults(struct echoaudio *chip)
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{
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return init_line_levels(chip);
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}
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static u32 detect_input_clocks(const struct echoaudio *chip)
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{
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u32 clocks_from_dsp, clock_bits;
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/* Map the DSP clock detect bits to the generic driver clock
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detect bits */
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clocks_from_dsp = le32_to_cpu(chip->comm_page->status_clocks);
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clock_bits = ECHO_CLOCK_BIT_INTERNAL;
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if (clocks_from_dsp & GLDM_CLOCK_DETECT_BIT_ESYNC)
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clock_bits |= ECHO_CLOCK_BIT_ESYNC;
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return clock_bits;
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}
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/* The Darla24 has no ASIC. Just do nothing */
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static int load_asic(struct echoaudio *chip)
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{
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return 0;
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}
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static int set_sample_rate(struct echoaudio *chip, u32 rate)
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{
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u8 clock;
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switch (rate) {
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case 96000:
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clock = GD24_96000;
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break;
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case 88200:
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clock = GD24_88200;
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break;
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case 48000:
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clock = GD24_48000;
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break;
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case 44100:
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clock = GD24_44100;
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break;
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case 32000:
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clock = GD24_32000;
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break;
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case 22050:
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clock = GD24_22050;
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break;
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case 16000:
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clock = GD24_16000;
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break;
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case 11025:
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clock = GD24_11025;
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break;
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case 8000:
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clock = GD24_8000;
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break;
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default:
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DE_ACT(("set_sample_rate: Error, invalid sample rate %d\n",
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rate));
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return -EINVAL;
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}
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if (wait_handshake(chip))
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return -EIO;
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DE_ACT(("set_sample_rate: %d clock %d\n", rate, clock));
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chip->sample_rate = rate;
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/* Override the sample rate if this card is set to Echo sync. */
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if (chip->input_clock == ECHO_CLOCK_ESYNC)
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clock = GD24_EXT_SYNC;
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chip->comm_page->sample_rate = cpu_to_le32(rate); /* ignored by the DSP ? */
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chip->comm_page->gd_clock_state = clock;
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clear_handshake(chip);
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return send_vector(chip, DSP_VC_SET_GD_AUDIO_STATE);
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}
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static int set_input_clock(struct echoaudio *chip, u16 clock)
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{
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if (snd_BUG_ON(clock != ECHO_CLOCK_INTERNAL &&
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clock != ECHO_CLOCK_ESYNC))
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return -EINVAL;
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chip->input_clock = clock;
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return set_sample_rate(chip, chip->sample_rate);
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}
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