/*
 * Copyright (c) 2015 Samsung Electronics Co., Ltd. All rights reserved.
 *		http://www.samsung.com
 *
 * Chip Abstraction Layer for local/system power down support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef __EXYNOS7570_PMUSFR_H__
#define __EXYNOS7570_PMUSFR_H__

#include "S5E7570-sfrbase.h"
#define GPIO_GPB0_BASE	0x13470000

#define OM_STAT							((void *)(PMU_ALIVE_BASE + 0x0000))
#define ALIVE_SFR_APB						((void *)(PMU_ALIVE_BASE + 0x0004))
#define RTC_CLKO_SEL						((void *)(PMU_ALIVE_BASE + 0x001C))
#define PMU_SYNC_CTRL						((void *)(PMU_ALIVE_BASE + 0x0020))
#define SFR_ACCESS_CONTROL_REG					((void *)(PMU_ALIVE_BASE + 0x0024))
#define CLKREQ_PAD_CONTROL					((void *)(PMU_ALIVE_BASE + 0x0028))
#define PWREN_G3D_PAD_CONTROL					((void *)(PMU_ALIVE_BASE + 0x002C))
#define CP_CTRL_NS						((void *)(PMU_ALIVE_BASE + 0x0030))
#define CP_CTRL_S						((void *)(PMU_ALIVE_BASE + 0x0034))
#define CP_STAT							((void *)(PMU_ALIVE_BASE + 0x0038))
#define CP_DEBUG						((void *)(PMU_ALIVE_BASE + 0x003C))
#define GNSS_CTRL_NS						((void *)(PMU_ALIVE_BASE + 0x0040))
#define GNSS_CTRL_S						((void *)(PMU_ALIVE_BASE + 0x0044))
#define GNSS_STAT						((void *)(PMU_ALIVE_BASE + 0x0048))
#define GNSS_DEBUG						((void *)(PMU_ALIVE_BASE + 0x004C))
#define CP2AP_MEM_CONFIG0					((void *)(PMU_ALIVE_BASE + 0x0050))
#define CP2AP_MIF_ACCESS_WIN0					((void *)(PMU_ALIVE_BASE + 0x0054))
#define CP2AP_MIF_ACCESS_WIN1					((void *)(PMU_ALIVE_BASE + 0x0058))
#define CP2AP_MIF_ACCESS_WIN2					((void *)(PMU_ALIVE_BASE + 0x005C))
#define CP2AP_MIF_ACCESS_WIN3					((void *)(PMU_ALIVE_BASE + 0x0060))
#define CP2AP_MEM_CONFIG1					((void *)(PMU_ALIVE_BASE + 0x0064))
#define CP_BOOT_TEST_RST_CONFIG					((void *)(PMU_ALIVE_BASE + 0x0068))
#define CP2AP_PERI_ACCESS_WIN					((void *)(PMU_ALIVE_BASE + 0x006C))
#define CP_MODAPIF_CONFIG					((void *)(PMU_ALIVE_BASE + 0x0070))
#define CP_CLK_CTRL						((void *)(PMU_ALIVE_BASE + 0x0074))
#define CP_QOS							((void *)(PMU_ALIVE_BASE + 0x0078))
#define CP2AP_MEM_CONFIG2					((void *)(PMU_ALIVE_BASE + 0x007C))
#define AUD_PATH_CFG						((void *)(PMU_ALIVE_BASE + 0x0080))
#define CP2AP_MEM_CONFIG3					((void *)(PMU_ALIVE_BASE + 0x0084))
#define CP_ADDR_MAP_ACCESS_WIN_START				((void *)(PMU_ALIVE_BASE + 0x0088))
#define CP_ADDR_MAP_ACCESS_WIN_END				((void *)(PMU_ALIVE_BASE + 0x008C))
#define GNSS2AP_MEM_CONFIG0					((void *)(PMU_ALIVE_BASE + 0x0090))
#define GNSS2AP_MIF_ACCESS_WIN0					((void *)(PMU_ALIVE_BASE + 0x0094))
#define GNSS2AP_MIF_ACCESS_WIN1					((void *)(PMU_ALIVE_BASE + 0x0098))
#define GNSS2AP_MIF_ACCESS_WIN2					((void *)(PMU_ALIVE_BASE + 0x009C))
#define GNSS2AP_MIF_ACCESS_WIN3					((void *)(PMU_ALIVE_BASE + 0x00A0))
#define GNSS2AP_MEM_CONFIG1					((void *)(PMU_ALIVE_BASE + 0x00A4))
#define GNSS_BOOT_TEST_RST_CONFIG				((void *)(PMU_ALIVE_BASE + 0x00A8))
#define GNSS2AP_PERI_ACCESS_WIN					((void *)(PMU_ALIVE_BASE + 0x00AC))
#define GNSS_MODAPIF_CONFIG					((void *)(PMU_ALIVE_BASE + 0x00B0))
#define GNSS_QOS						((void *)(PMU_ALIVE_BASE + 0x00B8))
#define GNSS2AP_MEM_CONFIG2					((void *)(PMU_ALIVE_BASE + 0x00BC))
#define GNSS2AP_MEM_CONFIG3					((void *)(PMU_ALIVE_BASE + 0x00C4))
#define CPUCL0_INTR_SPREAD_ENABLE				((void *)(PMU_ALIVE_BASE + 0x0100))
#define CPUCL0_INTR_SPREAD_USE_STANDBYWFI			((void *)(PMU_ALIVE_BASE + 0x0104))
#define CPUCL0_INTR_SPREAD_BLOCKING_DURATION			((void *)(PMU_ALIVE_BASE + 0x0108))
#define CPUCL1_INTR_SPREAD_ENABLE				((void *)(PMU_ALIVE_BASE + 0x0110))
#define CPUCL1_INTR_SPREAD_USE_STANDBYWFI			((void *)(PMU_ALIVE_BASE + 0x0114))
#define CPUCL1_INTR_SPREAD_BLOCKING_DURATION			((void *)(PMU_ALIVE_BASE + 0x0118))
#define UP_SCHEDULER						((void *)(PMU_ALIVE_BASE + 0x0120))
#define WIFI_CTRL_NS						((void *)(PMU_ALIVE_BASE + 0x0140))
#define WIFI_CTRL_S						((void *)(PMU_ALIVE_BASE + 0x0144))
#define WIFI_STAT						((void *)(PMU_ALIVE_BASE + 0x0148))
#define WIFI_DEBUG						((void *)(PMU_ALIVE_BASE + 0x014C))
#define WIFI2AP_MEM_CONFIG0					((void *)(PMU_ALIVE_BASE + 0x0150))
#define WIFI2AP_MIF_ACCESS_WIN0					((void *)(PMU_ALIVE_BASE + 0x0154))
#define WIFI2AP_MIF_ACCESS_WIN1					((void *)(PMU_ALIVE_BASE + 0x0158))
#define WIFI2AP_MIF_ACCESS_WIN2					((void *)(PMU_ALIVE_BASE + 0x015C))
#define WIFI2AP_MIF_ACCESS_WIN3					((void *)(PMU_ALIVE_BASE + 0x0160))
#define WIFI2AP_MEM_CONFIG1					((void *)(PMU_ALIVE_BASE + 0x0164))
#define WIFI_BOOT_TEST_RST_CONFIG				((void *)(PMU_ALIVE_BASE + 0x0168))
#define WIFI2AP_PERI_ACCESS_WIN					((void *)(PMU_ALIVE_BASE + 0x016C))
#define WIFI_MODAPIF_CONFIG					((void *)(PMU_ALIVE_BASE + 0x0170))
#define WIFI_QOS						((void *)(PMU_ALIVE_BASE + 0x0178))
#define WIFI2AP_MEM_CONFIG2					((void *)(PMU_ALIVE_BASE + 0x017C))
#define WIFI2AP_MEM_CONFIG3					((void *)(PMU_ALIVE_BASE + 0x0184))
#define CENTRAL_SEQ_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x0200))
#define CENTRAL_SEQ_STATUS					((void *)(PMU_ALIVE_BASE + 0x0204))
#define CENTRAL_SEQ_OPTION					((void *)(PMU_ALIVE_BASE + 0x0208))
#define CENTRAL_SEQ_OPTION1					((void *)(PMU_ALIVE_BASE + 0x020C))
#define CENTRAL_SEQ_DURATION0					((void *)(PMU_ALIVE_BASE + 0x0210))
#define CENTRAL_SEQ_DURATION1					((void *)(PMU_ALIVE_BASE + 0x0214))
#define CENTRAL_SEQ_DURATION2					((void *)(PMU_ALIVE_BASE + 0x0218))
#define CENTRAL_SEQ_DURATION3					((void *)(PMU_ALIVE_BASE + 0x021C))
#define SEQ_TRANSITION0						((void *)(PMU_ALIVE_BASE + 0x0220))
#define SEQ_TRANSITION1						((void *)(PMU_ALIVE_BASE + 0x0224))
#define SEQ_TRANSITION2						((void *)(PMU_ALIVE_BASE + 0x0228))
#define SEQ_TRANSITION3						((void *)(PMU_ALIVE_BASE + 0x022C))
#define SEQ_TRANSITION4						((void *)(PMU_ALIVE_BASE + 0x0230))
#define SEQ_TRANSITION5						((void *)(PMU_ALIVE_BASE + 0x0234))
#define SEQ_TRANSITION6						((void *)(PMU_ALIVE_BASE + 0x0238))
#define SEQ_TRANSITION7						((void *)(PMU_ALIVE_BASE + 0x023C))
#define CENTRAL_SEQ_MIF_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x0240))
#define CENTRAL_SEQ_MIF_STATUS					((void *)(PMU_ALIVE_BASE + 0x0244))
#define CENTRAL_SEQ_MIF_OPTION					((void *)(PMU_ALIVE_BASE + 0x0248))
#define CENTRAL_SEQ_MIF_DURATION0				((void *)(PMU_ALIVE_BASE + 0x0250))
#define CENTRAL_SEQ_MIF_DURATION1				((void *)(PMU_ALIVE_BASE + 0x0254))
#define CENTRAL_SEQ_MIF_DURATION2				((void *)(PMU_ALIVE_BASE + 0x0258))
#define CENTRAL_SEQ_MIF_DURATION3				((void *)(PMU_ALIVE_BASE + 0x025C))
#define SEQ_MIF_TRANSITION0					((void *)(PMU_ALIVE_BASE + 0x0260))
#define SEQ_MIF_TRANSITION1					((void *)(PMU_ALIVE_BASE + 0x0264))
#define SEQ_MIF_TRANSITION2					((void *)(PMU_ALIVE_BASE + 0x0268))
#define SEQ_MIF_TRANSITION3					((void *)(PMU_ALIVE_BASE + 0x026C))
#define SEQ_MIF_TRANSITION4					((void *)(PMU_ALIVE_BASE + 0x0270))
#define SEQ_MIF_TRANSITION5					((void *)(PMU_ALIVE_BASE + 0x0274))
#define SEQ_MIF_TRANSITION6					((void *)(PMU_ALIVE_BASE + 0x0278))
#define SEQ_MIF_TRANSITION7					((void *)(PMU_ALIVE_BASE + 0x027C))
#define CENTRAL_SEQ_CP_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x0280))
#define CENTRAL_SEQ_CP_STATUS					((void *)(PMU_ALIVE_BASE + 0x0284))
#define CENTRAL_SEQ_CP_OPTION					((void *)(PMU_ALIVE_BASE + 0x0288))
#define CENTRAL_SEQ_CP_DURATION0				((void *)(PMU_ALIVE_BASE + 0x0290))
#define CENTRAL_SEQ_CP_DURATION1				((void *)(PMU_ALIVE_BASE + 0x0294))
#define CENTRAL_SEQ_CP_DURATION2				((void *)(PMU_ALIVE_BASE + 0x0298))
#define CENTRAL_SEQ_CP_DURATION3				((void *)(PMU_ALIVE_BASE + 0x029C))
#define SEQ_CP_TRANSITION0					((void *)(PMU_ALIVE_BASE + 0x02A0))
#define SEQ_CP_TRANSITION1					((void *)(PMU_ALIVE_BASE + 0x02A4))
#define SEQ_CP_TRANSITION2					((void *)(PMU_ALIVE_BASE + 0x02A8))
#define SEQ_CP_TRANSITION3					((void *)(PMU_ALIVE_BASE + 0x02AC))
#define SEQ_CP_TRANSITION4					((void *)(PMU_ALIVE_BASE + 0x02B0))
#define SEQ_CP_TRANSITION5					((void *)(PMU_ALIVE_BASE + 0x02B4))
#define SEQ_CP_TRANSITION6					((void *)(PMU_ALIVE_BASE + 0x02B8))
#define SEQ_CP_TRANSITION7					((void *)(PMU_ALIVE_BASE + 0x02BC))
#define CENTRAL_SEQ_GNSS_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x02C0))
#define CENTRAL_SEQ_GNSS_STATUS					((void *)(PMU_ALIVE_BASE + 0x02C4))
#define CENTRAL_SEQ_GNSS_OPTION					((void *)(PMU_ALIVE_BASE + 0x02C8))
#define CENTRAL_SEQ_GNSS_DURATION0				((void *)(PMU_ALIVE_BASE + 0x02D0))
#define CENTRAL_SEQ_GNSS_DURATION1				((void *)(PMU_ALIVE_BASE + 0x02D4))
#define CENTRAL_SEQ_GNSS_DURATION2				((void *)(PMU_ALIVE_BASE + 0x02D8))
#define CENTRAL_SEQ_GNSS_DURATION3				((void *)(PMU_ALIVE_BASE + 0x02DC))
#define SEQ_GNSS_TRANSITION0					((void *)(PMU_ALIVE_BASE + 0x02E0))
#define SEQ_GNSS_TRANSITION1					((void *)(PMU_ALIVE_BASE + 0x02E4))
#define SEQ_GNSS_TRANSITION2					((void *)(PMU_ALIVE_BASE + 0x02E8))
#define SEQ_GNSS_TRANSITION3					((void *)(PMU_ALIVE_BASE + 0x02EC))
#define SEQ_GNSS_TRANSITION4					((void *)(PMU_ALIVE_BASE + 0x02F0))
#define SEQ_GNSS_TRANSITION5					((void *)(PMU_ALIVE_BASE + 0x02F4))
#define SEQ_GNSS_TRANSITION6					((void *)(PMU_ALIVE_BASE + 0x02F8))
#define SEQ_GNSS_TRANSITION7					((void *)(PMU_ALIVE_BASE + 0x02FC))
#define SEQ_TRANSITION8						((void *)(PMU_ALIVE_BASE + 0x0300))
#define SEQ_TRANSITION9						((void *)(PMU_ALIVE_BASE + 0x0304))
#define SEQ_TRANSITION10					((void *)(PMU_ALIVE_BASE + 0x0308))
#define SEQ_TRANSITION11					((void *)(PMU_ALIVE_BASE + 0x030C))
#define SEQ_TRANSITION12					((void *)(PMU_ALIVE_BASE + 0x0310))
#define SEQ_TRANSITION13					((void *)(PMU_ALIVE_BASE + 0x0314))
#define SEQ_TRANSITION14					((void *)(PMU_ALIVE_BASE + 0x0318))
#define SEQ_TRANSITION15					((void *)(PMU_ALIVE_BASE + 0x031C))
#define SEQ_MIF_TRANSITION8					((void *)(PMU_ALIVE_BASE + 0x0320))
#define SEQ_MIF_TRANSITION9					((void *)(PMU_ALIVE_BASE + 0x0324))
#define SEQ_MIF_TRANSITION10					((void *)(PMU_ALIVE_BASE + 0x0328))
#define SEQ_MIF_TRANSITION11					((void *)(PMU_ALIVE_BASE + 0x032C))
#define SEQ_MIF_TRANSITION12					((void *)(PMU_ALIVE_BASE + 0x0330))
#define SEQ_MIF_TRANSITION13					((void *)(PMU_ALIVE_BASE + 0x0334))
#define SEQ_MIF_TRANSITION14					((void *)(PMU_ALIVE_BASE + 0x0338))
#define SEQ_MIF_TRANSITION15					((void *)(PMU_ALIVE_BASE + 0x033C))
#define SEQ_CP_TRANSITION8					((void *)(PMU_ALIVE_BASE + 0x0340))
#define SEQ_CP_TRANSITION9					((void *)(PMU_ALIVE_BASE + 0x0344))
#define SEQ_CP_TRANSITION10					((void *)(PMU_ALIVE_BASE + 0x0348))
#define SEQ_CP_TRANSITION11					((void *)(PMU_ALIVE_BASE + 0x034C))
#define SEQ_CP_TRANSITION12					((void *)(PMU_ALIVE_BASE + 0x0350))
#define SEQ_CP_TRANSITION13					((void *)(PMU_ALIVE_BASE + 0x0354))
#define SEQ_CP_TRANSITION14					((void *)(PMU_ALIVE_BASE + 0x0358))
#define SEQ_CP_TRANSITION15					((void *)(PMU_ALIVE_BASE + 0x035C))
#define SEQ_GNSS_TRANSITION8					((void *)(PMU_ALIVE_BASE + 0x0360))
#define SEQ_GNSS_TRANSITION9					((void *)(PMU_ALIVE_BASE + 0x0364))
#define SEQ_GNSS_TRANSITION10					((void *)(PMU_ALIVE_BASE + 0x0368))
#define SEQ_GNSS_TRANSITION11					((void *)(PMU_ALIVE_BASE + 0x036C))
#define SEQ_GNSS_TRANSITION12					((void *)(PMU_ALIVE_BASE + 0x0370))
#define SEQ_GNSS_TRANSITION13					((void *)(PMU_ALIVE_BASE + 0x0374))
#define SEQ_GNSS_TRANSITION14					((void *)(PMU_ALIVE_BASE + 0x0378))
#define SEQ_GNSS_TRANSITION15					((void *)(PMU_ALIVE_BASE + 0x037C))
#define CENTRAL_SEQ_WIFI_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x0380))
#define CENTRAL_SEQ_WIFI_STATUS					((void *)(PMU_ALIVE_BASE + 0x0384))
#define CENTRAL_SEQ_WIFI_OPTION					((void *)(PMU_ALIVE_BASE + 0x0388))
#define CENTRAL_SEQ_WIFI_DURATION0				((void *)(PMU_ALIVE_BASE + 0x0390))
#define CENTRAL_SEQ_WIFI_DURATION1				((void *)(PMU_ALIVE_BASE + 0x0394))
#define CENTRAL_SEQ_WIFI_DURATION2				((void *)(PMU_ALIVE_BASE + 0x0398))
#define CENTRAL_SEQ_WIFI_DURATION3				((void *)(PMU_ALIVE_BASE + 0x039C))
#define SEQ_WIFI_TRANSITION0					((void *)(PMU_ALIVE_BASE + 0x03A0))
#define SEQ_WIFI_TRANSITION1					((void *)(PMU_ALIVE_BASE + 0x03A4))
#define SEQ_WIFI_TRANSITION2					((void *)(PMU_ALIVE_BASE + 0x03A8))
#define SEQ_WIFI_TRANSITION3					((void *)(PMU_ALIVE_BASE + 0x03AC))
#define SEQ_WIFI_TRANSITION4					((void *)(PMU_ALIVE_BASE + 0x03B0))
#define SEQ_WIFI_TRANSITION5					((void *)(PMU_ALIVE_BASE + 0x03B4))
#define SEQ_WIFI_TRANSITION6					((void *)(PMU_ALIVE_BASE + 0x03B8))
#define SEQ_WIFI_TRANSITION7					((void *)(PMU_ALIVE_BASE + 0x03BC))
#define SEQ_WIFI_TRANSITION8					((void *)(PMU_ALIVE_BASE + 0x03C0))
#define SEQ_WIFI_TRANSITION9					((void *)(PMU_ALIVE_BASE + 0x03C4))
#define SEQ_WIFI_TRANSITION10					((void *)(PMU_ALIVE_BASE + 0x03C8))
#define SEQ_WIFI_TRANSITION11					((void *)(PMU_ALIVE_BASE + 0x03CC))
#define SEQ_WIFI_TRANSITION12					((void *)(PMU_ALIVE_BASE + 0x03D0))
#define SEQ_WIFI_TRANSITION13					((void *)(PMU_ALIVE_BASE + 0x03D4))
#define SEQ_WIFI_TRANSITION14					((void *)(PMU_ALIVE_BASE + 0x03D8))
#define SEQ_WIFI_TRANSITION15					((void *)(PMU_ALIVE_BASE + 0x03DC))
#define IDLE_IP0						((void *)(PMU_ALIVE_BASE + 0x03E0))
#define IDLE_IP1						((void *)(PMU_ALIVE_BASE + 0x03E4))
#define IDLE_IP2						((void *)(PMU_ALIVE_BASE + 0x03E8))
#define IDLE_IP3						((void *)(PMU_ALIVE_BASE + 0x03EC))
#define IDLE_IP0_MASK						((void *)(PMU_ALIVE_BASE + 0x03F0))
#define IDLE_IP1_MASK						((void *)(PMU_ALIVE_BASE + 0x03F4))
#define IDLE_IP2_MASK						((void *)(PMU_ALIVE_BASE + 0x03F8))
#define IDLE_IP3_MASK						((void *)(PMU_ALIVE_BASE + 0x03FC))
#define SWRESET							((void *)(PMU_ALIVE_BASE + 0x0400))
#define RST_STAT						((void *)(PMU_ALIVE_BASE + 0x0404))
#define AUTOMATIC_DISABLE_WDT					((void *)(PMU_ALIVE_BASE + 0x0408))
#define MASK_WDT_RESET_REQUEST					((void *)(PMU_ALIVE_BASE + 0x040C))
#define MASK_WRESET_REQUEST					((void *)(PMU_ALIVE_BASE + 0x0410))
#define CPU_RESET_DISABLE_FROM_WDTRESET				((void *)(PMU_ALIVE_BASE + 0x0414))
#define WDTRESET_LPI						((void *)(PMU_ALIVE_BASE + 0x0418))
#define CPU_RESET_DISABLE_FROM_SOFTRESET			((void *)(PMU_ALIVE_BASE + 0x041C))
#define RESET_LPI_TIMEOUT					((void *)(PMU_ALIVE_BASE + 0x0420))
#define RESET_LPI_TIMEOUT_QCH					((void *)(PMU_ALIVE_BASE + 0x0424))
#define PMU_PCH_DRAM_STATUS					((void *)(PMU_ALIVE_BASE + 0x0428))
#define PMU_PCH_DRAM_DURATION					((void *)(PMU_ALIVE_BASE + 0x042C))
#define RESET_SEQUENCER_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x0500))

/* temporary definition for dump_pc.c */
/* It will be deleted after fixing Joshua PMUSFR header file */
#define PMU_RESET_SEQUENCER_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x0500))

#define RESET_SEQUENCER_STATUS					((void *)(PMU_ALIVE_BASE + 0x0504))
#define RESET_SEQUENCER_OPTION					((void *)(PMU_ALIVE_BASE + 0x0508))
#define RESET_SEQUENCER_DURATION0				((void *)(PMU_ALIVE_BASE + 0x0510))
#define RESET_SEQUENCER_DURATION1				((void *)(PMU_ALIVE_BASE + 0x0514))
#define RESET_SEQUENCER_DURATION2				((void *)(PMU_ALIVE_BASE + 0x0518))
#define RESET_SEQUENCER_DURATION3				((void *)(PMU_ALIVE_BASE + 0x051C))
#define WAKEUP_STAT						((void *)(PMU_ALIVE_BASE + 0x0600))
#define WAKEUP_STAT2						((void *)(PMU_ALIVE_BASE + 0x0604))
#define WAKEUP_STAT3						((void *)(PMU_ALIVE_BASE + 0x0608))
#define EINT_WAKEUP_MASK					((void *)(PMU_ALIVE_BASE + 0x060C))
#define WAKEUP_MASK						((void *)(PMU_ALIVE_BASE + 0x0610))
#define WAKEUP_MASK2						((void *)(PMU_ALIVE_BASE + 0x0614))
#define WAKEUP_MASK3						((void *)(PMU_ALIVE_BASE + 0x0618))
#define WAKEUP_INTERRUPT					((void *)(PMU_ALIVE_BASE + 0x061C))
#define WAKEUP_STAT_MIF						((void *)(PMU_ALIVE_BASE + 0x0620))
#define EINT_WAKEUP_MASK_MIF					((void *)(PMU_ALIVE_BASE + 0x0624))
#define WAKEUP_MASK_MIF						((void *)(PMU_ALIVE_BASE + 0x0628))
#define EINT_WAKEUP_MASK1					((void *)(PMU_ALIVE_BASE + 0x062C))
#define WAKEUP_SRC_CORTEXM0_APM					((void *)(PMU_ALIVE_BASE + 0x0630))
#define MIF_REQ_CORTEXM0_APM					((void *)(PMU_ALIVE_BASE + 0x0634))
#define MMC_CONWKUP_CTRL					((void *)(PMU_ALIVE_BASE + 0x0660))
#define USB30PHY0_UDRD30_WAKEUP					((void *)(PMU_ALIVE_BASE + 0x0680))
#define NFC_CLK_REQ_WAKEUP					((void *)(PMU_ALIVE_BASE + 0x0684))
#define USB20_WAKEUP						((void *)(PMU_ALIVE_BASE + 0x0688))
#define HDMI_PHY_CONTROL					((void *)(PMU_ALIVE_BASE + 0x0700))
#define USBDEV_PHY_CONTROL					((void *)(PMU_ALIVE_BASE + 0x0704))
#define MIPI_PHY_M4S2_CONTROL					((void *)(PMU_ALIVE_BASE + 0x070C))
#define MIPI_PHY_M4S0_CONTROL					((void *)(PMU_ALIVE_BASE + 0x0710))
#define MIPI_PHY_M0S4_CONTROL					((void *)(PMU_ALIVE_BASE + 0x0714))
#define MIPI_PHY_M0S1_CONTROL					((void *)(PMU_ALIVE_BASE + 0x0718))
#define WIFI0_PHY_CONTROL					((void *)(PMU_ALIVE_BASE + 0x071C))
#define WIFI1_PHY_CONTROL					((void *)(PMU_ALIVE_BASE + 0x0720))
#define UFS_PHY_CONTROL						((void *)(PMU_ALIVE_BASE + 0x0724))
#define SDCARD_PHY_CONTROL					((void *)(PMU_ALIVE_BASE + 0x0728))
#define DPTX_PHY_CONTROL					((void *)(PMU_ALIVE_BASE + 0x072C))
#define MIPI_PHY_M1S0_CONTROL					((void *)(PMU_ALIVE_BASE + 0x0730))
#define MIPI_PHY_M0S2_CONTROL					((void *)(PMU_ALIVE_BASE + 0x0734))
#define TRTC_CONTROL						((void *)(PMU_ALIVE_BASE + 0x0738))
#define ALIVEIRAM_WRITE						((void *)(PMU_ALIVE_BASE + 0x0770))
#define UPACG_AT_CMU						((void *)(PMU_ALIVE_BASE + 0x0790))
#define INFORM0							((void *)(PMU_ALIVE_BASE + 0x0800))
#define INFORM1							((void *)(PMU_ALIVE_BASE + 0x0804))
#define INFORM2							((void *)(PMU_ALIVE_BASE + 0x0808))
#define INFORM3							((void *)(PMU_ALIVE_BASE + 0x080C))
#define SYSIP_DAT0						((void *)(PMU_ALIVE_BASE + 0x0810))
#define SYSIP_DAT1						((void *)(PMU_ALIVE_BASE + 0x0814))
#define SYSIP_DAT2						((void *)(PMU_ALIVE_BASE + 0x0818))
#define SYSIP_DAT3						((void *)(PMU_ALIVE_BASE + 0x081C))
#define PS_HOLD_HW_TRIP						((void *)(PMU_ALIVE_BASE + 0x0820))
#define PS_HOLD_SW_TRIP						((void *)(PMU_ALIVE_BASE + 0x0824))
#define INFORM4							((void *)(PMU_ALIVE_BASE + 0x0840))
#define INFORM5							((void *)(PMU_ALIVE_BASE + 0x0844))
#define INFORM6							((void *)(PMU_ALIVE_BASE + 0x0848))
#define INFORM7							((void *)(PMU_ALIVE_BASE + 0x084C))
#define INFORM8							((void *)(PMU_ALIVE_BASE + 0x0850))
#define INFORM9							((void *)(PMU_ALIVE_BASE + 0x0854))
#define INFORM10						((void *)(PMU_ALIVE_BASE + 0x0858))
#define INFORM11						((void *)(PMU_ALIVE_BASE + 0x085C))
#define PMU_SPARE0						((void *)(PMU_ALIVE_BASE + 0x0900))
#define PMU_SPARE1						((void *)(PMU_ALIVE_BASE + 0x0904))
#define PMU_SPARE2						((void *)(PMU_ALIVE_BASE + 0x0908))
#define PMU_SPARE3						((void *)(PMU_ALIVE_BASE + 0x090C))
#define ACK_LAST_CPU						((void *)(PMU_ALIVE_BASE + 0x0940))
#define IROM_DATA_REG0						((void *)(PMU_ALIVE_BASE + 0x0980))
#define IROM_DATA_REG1						((void *)(PMU_ALIVE_BASE + 0x0984))
#define IROM_DATA_REG2						((void *)(PMU_ALIVE_BASE + 0x0988))
#define IROM_DATA_REG3						((void *)(PMU_ALIVE_BASE + 0x098C))
#define DREX_CALIBRATION0					((void *)(PMU_ALIVE_BASE + 0x09A0))
#define DREX_CALIBRATION1					((void *)(PMU_ALIVE_BASE + 0x09A4))
#define DREX_CALIBRATION2					((void *)(PMU_ALIVE_BASE + 0x09A8))
#define DREX_CALIBRATION3					((void *)(PMU_ALIVE_BASE + 0x09AC))
#define DREX_CALIBRATION4					((void *)(PMU_ALIVE_BASE + 0x09B0))
#define DREX_CALIBRATION5					((void *)(PMU_ALIVE_BASE + 0x09B4))
#define DREX_CALIBRATION6					((void *)(PMU_ALIVE_BASE + 0x09B8))
#define DREX_CALIBRATION7					((void *)(PMU_ALIVE_BASE + 0x09BC))
#define PMU_DEBUG						((void *)(PMU_ALIVE_BASE + 0x0A00))
#define ARM_CONTROL_OPTION					((void *)(PMU_ALIVE_BASE + 0x0A04))
#define BURNIN_CTRL						((void *)(PMU_ALIVE_BASE + 0x0A08))
#define PMU_DEBUG1						((void *)(PMU_ALIVE_BASE + 0x0A0C))
#define PPC_TOP0						((void *)(PMU_ALIVE_BASE + 0x0E78))
#define PPC_TOP1						((void *)(PMU_ALIVE_BASE + 0x0E7C))
#define PPC_TOP2						((void *)(PMU_ALIVE_BASE + 0x0E80))
#define PPC_TOP3						((void *)(PMU_ALIVE_BASE + 0x0E84))
#define PPC_TOP4						((void *)(PMU_ALIVE_BASE + 0x0E88))
#define PPC_TOP5						((void *)(PMU_ALIVE_BASE + 0x0E8C))
#define PMUDBG_CENTRAL_SEQ_STATUS				((void *)(PMU_ALIVE_BASE + 0x0F00))
#define PMUDBG_CENTRAL_SEQ_MIF_STATUS				((void *)(PMU_ALIVE_BASE + 0x0F04))
#define PMUDBG_CPUCL0_CPU0_STATUS				((void *)(PMU_ALIVE_BASE + 0x0F08))
#define PMUDBG_CPUCL0_CPU1_STATUS				((void *)(PMU_ALIVE_BASE + 0x0F0C))
#define PMUDBG_CPUCL0_CPU2_STATUS				((void *)(PMU_ALIVE_BASE + 0x0F10))
#define PMUDBG_CPUCL0_CPU3_STATUS				((void *)(PMU_ALIVE_BASE + 0x0F14))
#define PMUDBG_CPUCL1_CPU0_STATUS				((void *)(PMU_ALIVE_BASE + 0x0F20))
#define PMUDBG_CPUCL1_CPU1_STATUS				((void *)(PMU_ALIVE_BASE + 0x0F24))
#define PMUDBG_CPUCL1_CPU2_STATUS				((void *)(PMU_ALIVE_BASE + 0x0F28))
#define PMUDBG_CPUCL1_CPU3_STATUS				((void *)(PMU_ALIVE_BASE + 0x0F2C))
#define PMUDBG_CPUCL0_L2_STATUS					((void *)(PMU_ALIVE_BASE + 0x0F30))
#define PMUDBG_CPUCL1_L2_STATUS					((void *)(PMU_ALIVE_BASE + 0x0F34))
#define PMUDBG_CPUCL0_NONCPU_STATUS				((void *)(PMU_ALIVE_BASE + 0x0F38))
#define PMUDBG_CPUCL1_NONCPU_STATUS				((void *)(PMU_ALIVE_BASE + 0x0F3C))
#define OTP_STATUS						((void *)(PMU_ALIVE_BASE + 0x0F40))
#define PMUDBG_CENTRAL_SEQ_APM_STATUS				((void *)(PMU_ALIVE_BASE + 0x0F44))
#define CPUCL0_CPU0_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x1000))
#define DIS_IRQ_CPUCL0_CPU0_LOCAL_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x1004))
#define DIS_IRQ_CPUCL0_CPU0_CENTRAL_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x1008))
#define DIS_IRQ_CPUCL0_CPU0_CPUSEQUENCER_SYS_PWR_REG		((void *)(PMU_ALIVE_BASE + 0x100C))
#define CPUCL0_CPU1_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x1010))
#define DIS_IRQ_CPUCL0_CPU1_LOCAL_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x1014))
#define DIS_IRQ_CPUCL0_CPU1_CENTRAL_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x1018))
#define DIS_IRQ_CPUCL0_CPU1_CPUSEQUENCER_SYS_PWR_REG		((void *)(PMU_ALIVE_BASE + 0x101C))
#define CPUCL0_CPU2_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x1020))
#define DIS_IRQ_CPUCL0_CPU2_LOCAL_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x1024))
#define DIS_IRQ_CPUCL0_CPU2_CENTRAL_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x1028))
#define DIS_IRQ_CPUCL0_CPU2_CPUSEQUENCER_SYS_PWR_REG		((void *)(PMU_ALIVE_BASE + 0x102C))
#define CPUCL0_CPU3_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x1030))
#define DIS_IRQ_CPUCL0_CPU3_LOCAL_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x1034))
#define DIS_IRQ_CPUCL0_CPU3_CENTRAL_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x1038))
#define DIS_IRQ_CPUCL0_CPU3_CPUSEQUENCER_SYS_PWR_REG		((void *)(PMU_ALIVE_BASE + 0x103C))
#define CPUCL1_CPU0_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x1040))
#define DIS_IRQ_CPUCL1_CPU0_LOCAL_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x1044))
#define DIS_IRQ_CPUCL1_CPU0_CENTRAL_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x1048))
#define DIS_IRQ_CPUCL1_CPU0_CPUSEQUENCER_SYS_PWR_REG		((void *)(PMU_ALIVE_BASE + 0x104C))
#define CPUCL1_CPU1_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x1050))
#define DIS_IRQ_CPUCL1_CPU1_LOCAL_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x1054))
#define DIS_IRQ_CPUCL1_CPU1_CENTRAL_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x1058))
#define DIS_IRQ_CPUCL1_CPU1_CPUSEQUENCER_SYS_PWR_REG		((void *)(PMU_ALIVE_BASE + 0x105C))
#define CPUCL1_CPU2_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x1060))
#define DIS_IRQ_CPUCL1_CPU2_LOCAL_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x1064))
#define DIS_IRQ_CPUCL1_CPU2_CENTRAL_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x1068))
#define DIS_IRQ_CPUCL1_CPU2_CPUSEQUENCER_SYS_PWR_REG		((void *)(PMU_ALIVE_BASE + 0x106C))
#define CPUCL1_CPU3_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x1070))
#define DIS_IRQ_CPUCL1_CPU3_LOCAL_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x1074))
#define DIS_IRQ_CPUCL1_CPU3_CENTRAL_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x1078))
#define DIS_IRQ_CPUCL1_CPU3_CPUSEQUENCER_SYS_PWR_REG		((void *)(PMU_ALIVE_BASE + 0x107C))
#define CPUCL0_NONCPU_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1080))
#define CPUCL1_NONCPU_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1084))
#define CPUCL0_L2_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x10C0))
#define CPUCL1_L2_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x10C4))
#define CLKSTOP_CMU_TOP_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1100))
#define CLKRUN_CMU_TOP_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1104))
#define RETENTION_CMU_TOP_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1108))
#define RESET_CMU_TOP_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x110C))
#define RESET_CPUCLKSTOP_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x111C))
#define CLKSTOP_CMU_MIF_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1120))
#define CLKRUN_CMU_MIF_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1124))
#define RETENTION_CMU_MIF_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1128))
#define RESET_CMU_MIF_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x112C))
#define DDRPHY_CLKSTOP_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1130))
#define DDRPHY_ISO_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x1134))
#define DDRPHY_DLL_CLK_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1138))
#define DISABLE_PLL_CMU_TOP_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1140))
#define DISABLE_PLL_AUD_PLL_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1144))
#define DISABLE_PLL_CMU_MIF_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1160))
#define DISABLE_PLL_APM_MIF_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1164))
#define RESET_AHEAD_CP_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1170))
#define RESET_AHEAD_GNSS_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1174))
#define RESET_AHEAD_WIFI_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1178))
#define TOP_BUS_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x1180))
#define TOP_RETENTION_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1184))
#define TOP_PWR_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x1188))
#define TOP_BUS_MIF_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x1190))
#define TOP_RETENTION_MIF_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1194))
#define TOP_PWR_MIF_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x1198))
#define LOGIC_RESET_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x11A0))
#define OSCCLK_GATE_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x11A4))
#define SLEEP_RESET_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x11A8))
#define RESET_ASB_MIF_WIFI_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x11AC))
#define LOGIC_RESET_MIF_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x11B0))
#define OSCCLK_GATE_MIF_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x11B4))
#define SLEEP_RESET_MIF_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x11B8))
#define RESET_ASB_MIF_GNSS_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x11BC))
#define MEMORY_TOP_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x11C0))
#define TCXO_GATE_GNSS_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x11C4))
#define RESET_ASB_GNSS_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x11C8))
#define CLEANY_BUS_CP_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x11CC))
#define LOGIC_RESET_CP_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x11D0))
#define TCXO_GATE_CP_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x11D4))
#define RESET_ASB_CP_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x11D8))
#define RESET_ASB_MIF_CP_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x11DC))
#define MEMORY_MIF_ALIVEIRAM_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x11E0))
#define MEMORY_MIF_TOP_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x11E4))
#define CLEANY_BUS_GNSS_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x11E8))
#define LOGIC_RESET_GNSS_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x11EC))
#define TCXO_GATE_WIFI_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x11F0))
#define RESET_ASB_WIFI_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x11F4))
#define LOGIC_RESET_WIFI_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x11F8))
#define CLEANY_BUS_WIFI_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x11FC))
#define PAD_RETENTION_LPDDR3_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x1200))
#define PAD_RETENTION_AUD_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1204))
#define PAD_RETENTION_PEDOMETER_TOP_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x1208))
#define PAD_RETENTION_MMC2_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1218))
#define PAD_RETENTION_TOP_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1220))
#define PAD_RETENTION_UART_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1224))
#define PAD_RETENTION_MMC0_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1228))
#define PAD_RETENTION_MMC1_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x122C))
#define PAD_RETENTION_SPI_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1230))
#define PAD_RETENTION_MIF_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1234))
#define PAD_ISOLATION_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1240))
#define PAD_RETENTION_BOOTLDO_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x1248))
#define PAD_ISOLATION_MIF_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1250))
#define EXT_REGULATOR_MIF_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x12C4))
#define GPIO_MODE_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x1300))
#define GPIO_MODE_MIF_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1320))
#define GPIO_MODE_DISPAUD_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1340))
#define CLKSTOP_OPEN_CMU_TOP_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x1380))
#define CLKSTOP_OPEN_CMU_MIF_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x1384))
#define CLKSTOP_OPEN_CMU_G3D_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x1388))
#define CLKSTOP_OPEN_CMU_DISPAUD_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x138C))
#define CLKSTOP_OPEN_CMU_ISP_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x1390))
#define CLKSTOP_OPEN_CMU_MFCMSCL_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x1394))
#define G3D_SYS_PWR_REG						((void *)(PMU_ALIVE_BASE + 0x1400))
#define DISPAUD_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x1404))
#define ISP_SYS_PWR_REG						((void *)(PMU_ALIVE_BASE + 0x1408))
#define MFCMSCL_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x140C))
#define CLKRUN_CMU_G3D_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1440))
#define CLKRUN_CMU_DISPAUD_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1444))
#define CLKRUN_CMU_ISP_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1448))
#define CLKRUN_CMU_MFCMSCL_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x144C))
#define CLKSTOP_CMU_G3D_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1480))
#define CLKSTOP_CMU_DISPAUD_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1484))
#define CLKSTOP_CMU_ISP_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1488))
#define CLKSTOP_CMU_MFCMSCL_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x148C))
#define DISABLE_PLL_CMU_G3D_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x14C0))
#define DISABLE_PLL_CMU_DISPAUD_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x14C4))
#define DISABLE_PLL_CMU_ISP_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x14C8))
#define DISABLE_PLL_CMU_MFCMSCL_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x14CC))
#define RESET_LOGIC_G3D_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1500))
#define RESET_LOGIC_DISPAUD_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1504))
#define RESET_LOGIC_ISP_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1508))
#define RESET_LOGIC_MFCMSCL_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x150C))
#define MEMORY_G3D_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x1540))
#define MEMORY_DISPAUD_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1544))
#define MEMORY_ISP_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x1548))
#define MEMORY_MFCMSCL_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x154C))
#define RESET_CMU_G3D_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1580))
#define RESET_CMU_DISPAUD_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1584))
#define RESET_CMU_ISP_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x1588))
#define RESET_CMU_MFCMSCL_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x158C))
#define CPUCL0_CPU0_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2000))
#define CPUCL0_CPU0_STATUS					((void *)(PMU_ALIVE_BASE + 0x2004))
#define CPUCL0_CPU0_OPTION					((void *)(PMU_ALIVE_BASE + 0x2008))
#define CPUCL0_CPU0_RESET					((void *)(PMU_ALIVE_BASE + 0x200C))
#define CPUCL0_CPU0_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2010))
#define CPUCL0_CPU0_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2014))
#define CPUCL0_CPU0_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2018))
#define CPUCL0_CPU0_DURATION3					((void *)(PMU_ALIVE_BASE + 0x201C))
#define DIS_IRQ_CPUCL0_CPU0_LOCAL_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x2020))
#define DIS_IRQ_CPUCL0_CPU0_LOCAL_STATUS			((void *)(PMU_ALIVE_BASE + 0x2024))
#define DIS_IRQ_CPUCL0_CPU0_LOCAL_OPTION			((void *)(PMU_ALIVE_BASE + 0x2028))
#define DIS_IRQ_CPUCL0_CPU0_LOCAL_DURATION0			((void *)(PMU_ALIVE_BASE + 0x2030))
#define DIS_IRQ_CPUCL0_CPU0_LOCAL_DURATION1			((void *)(PMU_ALIVE_BASE + 0x2034))
#define DIS_IRQ_CPUCL0_CPU0_LOCAL_DURATION2			((void *)(PMU_ALIVE_BASE + 0x2038))
#define DIS_IRQ_CPUCL0_CPU0_LOCAL_DURATION3			((void *)(PMU_ALIVE_BASE + 0x203C))
#define DIS_IRQ_CPUCL0_CPU0_CENTRAL_CONFIGURATION		((void *)(PMU_ALIVE_BASE + 0x2040))
#define DIS_IRQ_CPUCL0_CPU0_CENTRAL_STATUS			((void *)(PMU_ALIVE_BASE + 0x2044))
#define DIS_IRQ_CPUCL0_CPU0_CENTRAL_OPTION			((void *)(PMU_ALIVE_BASE + 0x2048))
#define DIS_IRQ_CPUCL0_CPU0_CENTRAL_DURATION0			((void *)(PMU_ALIVE_BASE + 0x2050))
#define DIS_IRQ_CPUCL0_CPU0_CENTRAL_DURATION1			((void *)(PMU_ALIVE_BASE + 0x2054))
#define DIS_IRQ_CPUCL0_CPU0_CENTRAL_DURATION2			((void *)(PMU_ALIVE_BASE + 0x2058))
#define DIS_IRQ_CPUCL0_CPU0_CENTRAL_DURATION3			((void *)(PMU_ALIVE_BASE + 0x205C))
#define DIS_IRQ_CPUCL0_CPU0_CPUSEQUENCER_CONFIGURATION		((void *)(PMU_ALIVE_BASE + 0x2060))
#define DIS_IRQ_CPUCL0_CPU0_CPUSEQUENCER_STATUS			((void *)(PMU_ALIVE_BASE + 0x2064))
#define DIS_IRQ_CPUCL0_CPU0_CPUSEQUENCER_OPTION			((void *)(PMU_ALIVE_BASE + 0x2068))
#define DIS_IRQ_CPUCL0_CPU0_CPUSEQUENCER_DURATION0		((void *)(PMU_ALIVE_BASE + 0x2070))
#define DIS_IRQ_CPUCL0_CPU0_CPUSEQUENCER_DURATION1		((void *)(PMU_ALIVE_BASE + 0x2074))
#define DIS_IRQ_CPUCL0_CPU0_CPUSEQUENCER_DURATION2		((void *)(PMU_ALIVE_BASE + 0x2078))
#define DIS_IRQ_CPUCL0_CPU0_CPUSEQUENCER_DURATION3		((void *)(PMU_ALIVE_BASE + 0x207C))
#define CPUCL0_CPU1_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2080))
#define CPUCL0_CPU1_STATUS					((void *)(PMU_ALIVE_BASE + 0x2084))
#define CPUCL0_CPU1_OPTION					((void *)(PMU_ALIVE_BASE + 0x2088))
#define CPUCL0_CPU1_RESET					((void *)(PMU_ALIVE_BASE + 0x208C))
#define CPUCL0_CPU1_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2090))
#define CPUCL0_CPU1_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2094))
#define CPUCL0_CPU1_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2098))
#define CPUCL0_CPU1_DURATION3					((void *)(PMU_ALIVE_BASE + 0x209C))
#define DIS_IRQ_CPUCL0_CPU1_LOCAL_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x20A0))
#define DIS_IRQ_CPUCL0_CPU1_LOCAL_STATUS			((void *)(PMU_ALIVE_BASE + 0x20A4))
#define DIS_IRQ_CPUCL0_CPU1_LOCAL_OPTION			((void *)(PMU_ALIVE_BASE + 0x20A8))
#define DIS_IRQ_CPUCL0_CPU1_LOCAL_DURATION0			((void *)(PMU_ALIVE_BASE + 0x20B0))
#define DIS_IRQ_CPUCL0_CPU1_LOCAL_DURATION1			((void *)(PMU_ALIVE_BASE + 0x20B4))
#define DIS_IRQ_CPUCL0_CPU1_LOCAL_DURATION2			((void *)(PMU_ALIVE_BASE + 0x20B8))
#define DIS_IRQ_CPUCL0_CPU1_LOCAL_DURATION3			((void *)(PMU_ALIVE_BASE + 0x20BC))
#define DIS_IRQ_CPUCL0_CPU1_CENTRAL_CONFIGURATION		((void *)(PMU_ALIVE_BASE + 0x20C0))
#define DIS_IRQ_CPUCL0_CPU1_CENTRAL_STATUS			((void *)(PMU_ALIVE_BASE + 0x20C4))
#define DIS_IRQ_CPUCL0_CPU1_CENTRAL_OPTION			((void *)(PMU_ALIVE_BASE + 0x20C8))
#define DIS_IRQ_CPUCL0_CPU1_CENTRAL_DURATION0			((void *)(PMU_ALIVE_BASE + 0x20D0))
#define DIS_IRQ_CPUCL0_CPU1_CENTRAL_DURATION1			((void *)(PMU_ALIVE_BASE + 0x20D4))
#define DIS_IRQ_CPUCL0_CPU1_CENTRAL_DURATION2			((void *)(PMU_ALIVE_BASE + 0x20D8))
#define DIS_IRQ_CPUCL0_CPU1_CENTRAL_DURATION3			((void *)(PMU_ALIVE_BASE + 0x20DC))
#define DIS_IRQ_CPUCL0_CPU1_CPUSEQUENCER_CONFIGURATION		((void *)(PMU_ALIVE_BASE + 0x20E0))
#define DIS_IRQ_CPUCL0_CPU1_CPUSEQUENCER_STATUS			((void *)(PMU_ALIVE_BASE + 0x20E4))
#define DIS_IRQ_CPUCL0_CPU1_CPUSEQUENCER_OPTION			((void *)(PMU_ALIVE_BASE + 0x20E8))
#define DIS_IRQ_CPUCL0_CPU1_CPUSEQUENCER_DURATION0		((void *)(PMU_ALIVE_BASE + 0x20F0))
#define DIS_IRQ_CPUCL0_CPU1_CPUSEQUENCER_DURATION1		((void *)(PMU_ALIVE_BASE + 0x20F4))
#define DIS_IRQ_CPUCL0_CPU1_CPUSEQUENCER_DURATION2		((void *)(PMU_ALIVE_BASE + 0x20F8))
#define DIS_IRQ_CPUCL0_CPU1_CPUSEQUENCER_DURATION3		((void *)(PMU_ALIVE_BASE + 0x20FC))
#define CPUCL0_CPU2_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2100))
#define CPUCL0_CPU2_STATUS					((void *)(PMU_ALIVE_BASE + 0x2104))
#define CPUCL0_CPU2_OPTION					((void *)(PMU_ALIVE_BASE + 0x2108))
#define CPUCL0_CPU2_RESET					((void *)(PMU_ALIVE_BASE + 0x210C))
#define CPUCL0_CPU2_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2110))
#define CPUCL0_CPU2_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2114))
#define CPUCL0_CPU2_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2118))
#define CPUCL0_CPU2_DURATION3					((void *)(PMU_ALIVE_BASE + 0x211C))
#define DIS_IRQ_CPUCL0_CPU2_LOCAL_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x2120))
#define DIS_IRQ_CPUCL0_CPU2_LOCAL_STATUS			((void *)(PMU_ALIVE_BASE + 0x2124))
#define DIS_IRQ_CPUCL0_CPU2_LOCAL_OPTION			((void *)(PMU_ALIVE_BASE + 0x2128))
#define DIS_IRQ_CPUCL0_CPU2_LOCAL_DURATION0			((void *)(PMU_ALIVE_BASE + 0x2130))
#define DIS_IRQ_CPUCL0_CPU2_LOCAL_DURATION1			((void *)(PMU_ALIVE_BASE + 0x2134))
#define DIS_IRQ_CPUCL0_CPU2_LOCAL_DURATION2			((void *)(PMU_ALIVE_BASE + 0x2138))
#define DIS_IRQ_CPUCL0_CPU2_LOCAL_DURATION3			((void *)(PMU_ALIVE_BASE + 0x213C))
#define DIS_IRQ_CPUCL0_CPU2_CENTRAL_CONFIGURATION		((void *)(PMU_ALIVE_BASE + 0x2140))
#define DIS_IRQ_CPUCL0_CPU2_CENTRAL_STATUS			((void *)(PMU_ALIVE_BASE + 0x2144))
#define DIS_IRQ_CPUCL0_CPU2_CENTRAL_OPTION			((void *)(PMU_ALIVE_BASE + 0x2148))
#define DIS_IRQ_CPUCL0_CPU2_CENTRAL_DURATION0			((void *)(PMU_ALIVE_BASE + 0x2150))
#define DIS_IRQ_CPUCL0_CPU2_CENTRAL_DURATION1			((void *)(PMU_ALIVE_BASE + 0x2154))
#define DIS_IRQ_CPUCL0_CPU2_CENTRAL_DURATION2			((void *)(PMU_ALIVE_BASE + 0x2158))
#define DIS_IRQ_CPUCL0_CPU2_CENTRAL_DURATION3			((void *)(PMU_ALIVE_BASE + 0x215C))
#define DIS_IRQ_CPUCL0_CPU2_CPUSEQUENCER_CONFIGURATION		((void *)(PMU_ALIVE_BASE + 0x2160))
#define DIS_IRQ_CPUCL0_CPU2_CPUSEQUENCER_STATUS			((void *)(PMU_ALIVE_BASE + 0x2164))
#define DIS_IRQ_CPUCL0_CPU2_CPUSEQUENCER_OPTION			((void *)(PMU_ALIVE_BASE + 0x2168))
#define DIS_IRQ_CPUCL0_CPU2_CPUSEQUENCER_DURATION0		((void *)(PMU_ALIVE_BASE + 0x2170))
#define DIS_IRQ_CPUCL0_CPU2_CPUSEQUENCER_DURATION1		((void *)(PMU_ALIVE_BASE + 0x2174))
#define DIS_IRQ_CPUCL0_CPU2_CPUSEQUENCER_DURATION2		((void *)(PMU_ALIVE_BASE + 0x2178))
#define DIS_IRQ_CPUCL0_CPU2_CPUSEQUENCER_DURATION3		((void *)(PMU_ALIVE_BASE + 0x217C))
#define CPUCL0_CPU3_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2180))
#define CPUCL0_CPU3_STATUS					((void *)(PMU_ALIVE_BASE + 0x2184))
#define CPUCL0_CPU3_OPTION					((void *)(PMU_ALIVE_BASE + 0x2188))
#define CPUCL0_CPU3_RESET					((void *)(PMU_ALIVE_BASE + 0x218C))
#define CPUCL0_CPU3_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2190))
#define CPUCL0_CPU3_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2194))
#define CPUCL0_CPU3_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2198))
#define CPUCL0_CPU3_DURATION3					((void *)(PMU_ALIVE_BASE + 0x219C))
#define DIS_IRQ_CPUCL0_CPU3_LOCAL_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x21A0))
#define DIS_IRQ_CPUCL0_CPU3_LOCAL_STATUS			((void *)(PMU_ALIVE_BASE + 0x21A4))
#define DIS_IRQ_CPUCL0_CPU3_LOCAL_OPTION			((void *)(PMU_ALIVE_BASE + 0x21A8))
#define DIS_IRQ_CPUCL0_CPU3_LOCAL_DURATION0			((void *)(PMU_ALIVE_BASE + 0x21B0))
#define DIS_IRQ_CPUCL0_CPU3_LOCAL_DURATION1			((void *)(PMU_ALIVE_BASE + 0x21B4))
#define DIS_IRQ_CPUCL0_CPU3_LOCAL_DURATION2			((void *)(PMU_ALIVE_BASE + 0x21B8))
#define DIS_IRQ_CPUCL0_CPU3_LOCAL_DURATION3			((void *)(PMU_ALIVE_BASE + 0x21BC))
#define DIS_IRQ_CPUCL0_CPU3_CENTRAL_CONFIGURATION		((void *)(PMU_ALIVE_BASE + 0x21C0))
#define DIS_IRQ_CPUCL0_CPU3_CENTRAL_STATUS			((void *)(PMU_ALIVE_BASE + 0x21C4))
#define DIS_IRQ_CPUCL0_CPU3_CENTRAL_OPTION			((void *)(PMU_ALIVE_BASE + 0x21C8))
#define DIS_IRQ_CPUCL0_CPU3_CENTRAL_DURATION0			((void *)(PMU_ALIVE_BASE + 0x21D0))
#define DIS_IRQ_CPUCL0_CPU3_CENTRAL_DURATION1			((void *)(PMU_ALIVE_BASE + 0x21D4))
#define DIS_IRQ_CPUCL0_CPU3_CENTRAL_DURATION2			((void *)(PMU_ALIVE_BASE + 0x21D8))
#define DIS_IRQ_CPUCL0_CPU3_CENTRAL_DURATION3			((void *)(PMU_ALIVE_BASE + 0x21DC))
#define DIS_IRQ_CPUCL0_CPU3_CPUSEQUENCER_CONFIGURATION		((void *)(PMU_ALIVE_BASE + 0x21E0))
#define DIS_IRQ_CPUCL0_CPU3_CPUSEQUENCER_STATUS			((void *)(PMU_ALIVE_BASE + 0x21E4))
#define DIS_IRQ_CPUCL0_CPU3_CPUSEQUENCER_OPTION			((void *)(PMU_ALIVE_BASE + 0x21E8))
#define DIS_IRQ_CPUCL0_CPU3_CPUSEQUENCER_DURATION0		((void *)(PMU_ALIVE_BASE + 0x21F0))
#define DIS_IRQ_CPUCL0_CPU3_CPUSEQUENCER_DURATION1		((void *)(PMU_ALIVE_BASE + 0x21F4))
#define DIS_IRQ_CPUCL0_CPU3_CPUSEQUENCER_DURATION2		((void *)(PMU_ALIVE_BASE + 0x21F8))
#define DIS_IRQ_CPUCL0_CPU3_CPUSEQUENCER_DURATION3		((void *)(PMU_ALIVE_BASE + 0x21FC))
#define CPUCL1_CPU0_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2200))
#define CPUCL1_CPU0_STATUS					((void *)(PMU_ALIVE_BASE + 0x2204))
#define CPUCL1_CPU0_OPTION					((void *)(PMU_ALIVE_BASE + 0x2208))
#define CPUCL1_CPU0_RESET					((void *)(PMU_ALIVE_BASE + 0x220C))
#define CPUCL1_CPU0_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2210))
#define CPUCL1_CPU0_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2214))
#define CPUCL1_CPU0_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2218))
#define CPUCL1_CPU0_DURATION3					((void *)(PMU_ALIVE_BASE + 0x221C))
#define DIS_IRQ_CPUCL1_CPU0_LOCAL_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x2220))
#define DIS_IRQ_CPUCL1_CPU0_LOCAL_STATUS			((void *)(PMU_ALIVE_BASE + 0x2224))
#define DIS_IRQ_CPUCL1_CPU0_LOCAL_OPTION			((void *)(PMU_ALIVE_BASE + 0x2228))
#define DIS_IRQ_CPUCL1_CPU0_LOCAL_DURATION0			((void *)(PMU_ALIVE_BASE + 0x2230))
#define DIS_IRQ_CPUCL1_CPU0_LOCAL_DURATION1			((void *)(PMU_ALIVE_BASE + 0x2234))
#define DIS_IRQ_CPUCL1_CPU0_LOCAL_DURATION2			((void *)(PMU_ALIVE_BASE + 0x2238))
#define DIS_IRQ_CPUCL1_CPU0_LOCAL_DURATION3			((void *)(PMU_ALIVE_BASE + 0x223C))
#define DIS_IRQ_CPUCL1_CPU0_CENTRAL_CONFIGURATION		((void *)(PMU_ALIVE_BASE + 0x2240))
#define DIS_IRQ_CPUCL1_CPU0_CENTRAL_STATUS			((void *)(PMU_ALIVE_BASE + 0x2244))
#define DIS_IRQ_CPUCL1_CPU0_CENTRAL_OPTION			((void *)(PMU_ALIVE_BASE + 0x2248))
#define DIS_IRQ_CPUCL1_CPU0_CENTRAL_DURATION0			((void *)(PMU_ALIVE_BASE + 0x2250))
#define DIS_IRQ_CPUCL1_CPU0_CENTRAL_DURATION1			((void *)(PMU_ALIVE_BASE + 0x2254))
#define DIS_IRQ_CPUCL1_CPU0_CENTRAL_DURATION2			((void *)(PMU_ALIVE_BASE + 0x2258))
#define DIS_IRQ_CPUCL1_CPU0_CENTRAL_DURATION3			((void *)(PMU_ALIVE_BASE + 0x225C))
#define DIS_IRQ_CPUCL1_CPU0_CPUSEQUENCER_CONFIGURATION		((void *)(PMU_ALIVE_BASE + 0x2260))
#define DIS_IRQ_CPUCL1_CPU0_CPUSEQUENCER_STATUS			((void *)(PMU_ALIVE_BASE + 0x2264))
#define DIS_IRQ_CPUCL1_CPU0_CPUSEQUENCER_OPTION			((void *)(PMU_ALIVE_BASE + 0x2268))
#define DIS_IRQ_CPUCL1_CPU0_CPUSEQUENCER_DURATION0		((void *)(PMU_ALIVE_BASE + 0x2270))
#define DIS_IRQ_CPUCL1_CPU0_CPUSEQUENCER_DURATION1		((void *)(PMU_ALIVE_BASE + 0x2274))
#define DIS_IRQ_CPUCL1_CPU0_CPUSEQUENCER_DURATION2		((void *)(PMU_ALIVE_BASE + 0x2278))
#define DIS_IRQ_CPUCL1_CPU0_CPUSEQUENCER_DURATION3		((void *)(PMU_ALIVE_BASE + 0x227C))
#define CPUCL1_CPU1_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2280))
#define CPUCL1_CPU1_STATUS					((void *)(PMU_ALIVE_BASE + 0x2284))
#define CPUCL1_CPU1_OPTION					((void *)(PMU_ALIVE_BASE + 0x2288))
#define CPUCL1_CPU1_RESET					((void *)(PMU_ALIVE_BASE + 0x228C))
#define CPUCL1_CPU1_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2290))
#define CPUCL1_CPU1_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2294))
#define CPUCL1_CPU1_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2298))
#define CPUCL1_CPU1_DURATION3					((void *)(PMU_ALIVE_BASE + 0x229C))
#define DIS_IRQ_CPUCL1_CPU1_LOCAL_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x22A0))
#define DIS_IRQ_CPUCL1_CPU1_LOCAL_STATUS			((void *)(PMU_ALIVE_BASE + 0x22A4))
#define DIS_IRQ_CPUCL1_CPU1_LOCAL_OPTION			((void *)(PMU_ALIVE_BASE + 0x22A8))
#define DIS_IRQ_CPUCL1_CPU1_LOCAL_DURATION0			((void *)(PMU_ALIVE_BASE + 0x22B0))
#define DIS_IRQ_CPUCL1_CPU1_LOCAL_DURATION1			((void *)(PMU_ALIVE_BASE + 0x22B4))
#define DIS_IRQ_CPUCL1_CPU1_LOCAL_DURATION2			((void *)(PMU_ALIVE_BASE + 0x22B8))
#define DIS_IRQ_CPUCL1_CPU1_LOCAL_DURATION3			((void *)(PMU_ALIVE_BASE + 0x22BC))
#define DIS_IRQ_CPUCL1_CPU1_CENTRAL_CONFIGURATION		((void *)(PMU_ALIVE_BASE + 0x22C0))
#define DIS_IRQ_CPUCL1_CPU1_CENTRAL_STATUS			((void *)(PMU_ALIVE_BASE + 0x22C4))
#define DIS_IRQ_CPUCL1_CPU1_CENTRAL_OPTION			((void *)(PMU_ALIVE_BASE + 0x22C8))
#define DIS_IRQ_CPUCL1_CPU1_CENTRAL_DURATION0			((void *)(PMU_ALIVE_BASE + 0x22D0))
#define DIS_IRQ_CPUCL1_CPU1_CENTRAL_DURATION1			((void *)(PMU_ALIVE_BASE + 0x22D4))
#define DIS_IRQ_CPUCL1_CPU1_CENTRAL_DURATION2			((void *)(PMU_ALIVE_BASE + 0x22D8))
#define DIS_IRQ_CPUCL1_CPU1_CENTRAL_DURATION3			((void *)(PMU_ALIVE_BASE + 0x22DC))
#define DIS_IRQ_CPUCL1_CPU1_CPUSEQUENCER_CONFIGURATION		((void *)(PMU_ALIVE_BASE + 0x22E0))
#define DIS_IRQ_CPUCL1_CPU1_CPUSEQUENCER_STATUS			((void *)(PMU_ALIVE_BASE + 0x22E4))
#define DIS_IRQ_CPUCL1_CPU1_CPUSEQUENCER_OPTION			((void *)(PMU_ALIVE_BASE + 0x22E8))
#define DIS_IRQ_CPUCL1_CPU1_CPUSEQUENCER_DURATION0		((void *)(PMU_ALIVE_BASE + 0x22F0))
#define DIS_IRQ_CPUCL1_CPU1_CPUSEQUENCER_DURATION1		((void *)(PMU_ALIVE_BASE + 0x22F4))
#define DIS_IRQ_CPUCL1_CPU1_CPUSEQUENCER_DURATION2		((void *)(PMU_ALIVE_BASE + 0x22F8))
#define DIS_IRQ_CPUCL1_CPU1_CPUSEQUENCER_DURATION3		((void *)(PMU_ALIVE_BASE + 0x22FC))
#define CPUCL1_CPU2_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2300))
#define CPUCL1_CPU2_STATUS					((void *)(PMU_ALIVE_BASE + 0x2304))
#define CPUCL1_CPU2_OPTION					((void *)(PMU_ALIVE_BASE + 0x2308))
#define CPUCL1_CPU2_RESET					((void *)(PMU_ALIVE_BASE + 0x230C))
#define CPUCL1_CPU2_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2310))
#define CPUCL1_CPU2_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2314))
#define CPUCL1_CPU2_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2318))
#define CPUCL1_CPU2_DURATION3					((void *)(PMU_ALIVE_BASE + 0x231C))
#define DIS_IRQ_CPUCL1_CPU2_LOCAL_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x2320))
#define DIS_IRQ_CPUCL1_CPU2_LOCAL_STATUS			((void *)(PMU_ALIVE_BASE + 0x2324))
#define DIS_IRQ_CPUCL1_CPU2_LOCAL_OPTION			((void *)(PMU_ALIVE_BASE + 0x2328))
#define DIS_IRQ_CPUCL1_CPU2_LOCAL_DURATION0			((void *)(PMU_ALIVE_BASE + 0x2330))
#define DIS_IRQ_CPUCL1_CPU2_LOCAL_DURATION1			((void *)(PMU_ALIVE_BASE + 0x2334))
#define DIS_IRQ_CPUCL1_CPU2_LOCAL_DURATION2			((void *)(PMU_ALIVE_BASE + 0x2338))
#define DIS_IRQ_CPUCL1_CPU2_LOCAL_DURATION3			((void *)(PMU_ALIVE_BASE + 0x233C))
#define DIS_IRQ_CPUCL1_CPU2_CENTRAL_CONFIGURATION		((void *)(PMU_ALIVE_BASE + 0x2340))
#define DIS_IRQ_CPUCL1_CPU2_CENTRAL_STATUS			((void *)(PMU_ALIVE_BASE + 0x2344))
#define DIS_IRQ_CPUCL1_CPU2_CENTRAL_OPTION			((void *)(PMU_ALIVE_BASE + 0x2348))
#define DIS_IRQ_CPUCL1_CPU2_CENTRAL_DURATION0			((void *)(PMU_ALIVE_BASE + 0x2350))
#define DIS_IRQ_CPUCL1_CPU2_CENTRAL_DURATION1			((void *)(PMU_ALIVE_BASE + 0x2354))
#define DIS_IRQ_CPUCL1_CPU2_CENTRAL_DURATION2			((void *)(PMU_ALIVE_BASE + 0x2358))
#define DIS_IRQ_CPUCL1_CPU2_CENTRAL_DURATION3			((void *)(PMU_ALIVE_BASE + 0x235C))
#define DIS_IRQ_CPUCL1_CPU2_CPUSEQUENCER_CONFIGURATION		((void *)(PMU_ALIVE_BASE + 0x2360))
#define DIS_IRQ_CPUCL1_CPU2_CPUSEQUENCER_STATUS			((void *)(PMU_ALIVE_BASE + 0x2364))
#define DIS_IRQ_CPUCL1_CPU2_CPUSEQUENCER_OPTION			((void *)(PMU_ALIVE_BASE + 0x2368))
#define DIS_IRQ_CPUCL1_CPU2_CPUSEQUENCER_DURATION0		((void *)(PMU_ALIVE_BASE + 0x2370))
#define DIS_IRQ_CPUCL1_CPU2_CPUSEQUENCER_DURATION1		((void *)(PMU_ALIVE_BASE + 0x2374))
#define DIS_IRQ_CPUCL1_CPU2_CPUSEQUENCER_DURATION2		((void *)(PMU_ALIVE_BASE + 0x2378))
#define DIS_IRQ_CPUCL1_CPU2_CPUSEQUENCER_DURATION3		((void *)(PMU_ALIVE_BASE + 0x237C))
#define CPUCL1_CPU3_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2380))
#define CPUCL1_CPU3_STATUS					((void *)(PMU_ALIVE_BASE + 0x2384))
#define CPUCL1_CPU3_OPTION					((void *)(PMU_ALIVE_BASE + 0x2388))
#define CPUCL1_CPU3_RESET					((void *)(PMU_ALIVE_BASE + 0x238C))
#define CPUCL1_CPU3_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2390))
#define CPUCL1_CPU3_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2394))
#define CPUCL1_CPU3_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2398))
#define CPUCL1_CPU3_DURATION3					((void *)(PMU_ALIVE_BASE + 0x239C))
#define DIS_IRQ_CPUCL1_CPU3_LOCAL_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x23A0))
#define DIS_IRQ_CPUCL1_CPU3_LOCAL_STATUS			((void *)(PMU_ALIVE_BASE + 0x23A4))
#define DIS_IRQ_CPUCL1_CPU3_LOCAL_OPTION			((void *)(PMU_ALIVE_BASE + 0x23A8))
#define DIS_IRQ_CPUCL1_CPU3_LOCAL_DURATION0			((void *)(PMU_ALIVE_BASE + 0x23B0))
#define DIS_IRQ_CPUCL1_CPU3_LOCAL_DURATION1			((void *)(PMU_ALIVE_BASE + 0x23B4))
#define DIS_IRQ_CPUCL1_CPU3_LOCAL_DURATION2			((void *)(PMU_ALIVE_BASE + 0x23B8))
#define DIS_IRQ_CPUCL1_CPU3_LOCAL_DURATION3			((void *)(PMU_ALIVE_BASE + 0x23BC))
#define DIS_IRQ_CPUCL1_CPU3_CENTRAL_CONFIGURATION		((void *)(PMU_ALIVE_BASE + 0x23C0))
#define DIS_IRQ_CPUCL1_CPU3_CENTRAL_STATUS			((void *)(PMU_ALIVE_BASE + 0x23C4))
#define DIS_IRQ_CPUCL1_CPU3_CENTRAL_OPTION			((void *)(PMU_ALIVE_BASE + 0x23C8))
#define DIS_IRQ_CPUCL1_CPU3_CENTRAL_DURATION0			((void *)(PMU_ALIVE_BASE + 0x23D0))
#define DIS_IRQ_CPUCL1_CPU3_CENTRAL_DURATION1			((void *)(PMU_ALIVE_BASE + 0x23D4))
#define DIS_IRQ_CPUCL1_CPU3_CENTRAL_DURATION2			((void *)(PMU_ALIVE_BASE + 0x23D8))
#define DIS_IRQ_CPUCL1_CPU3_CENTRAL_DURATION3			((void *)(PMU_ALIVE_BASE + 0x23DC))
#define DIS_IRQ_CPUCL1_CPU3_CPUSEQUENCER_CONFIGURATION		((void *)(PMU_ALIVE_BASE + 0x23E0))
#define DIS_IRQ_CPUCL1_CPU3_CPUSEQUENCER_STATUS			((void *)(PMU_ALIVE_BASE + 0x23E4))
#define DIS_IRQ_CPUCL1_CPU3_CPUSEQUENCER_OPTION			((void *)(PMU_ALIVE_BASE + 0x23E8))
#define DIS_IRQ_CPUCL1_CPU3_CPUSEQUENCER_DURATION0		((void *)(PMU_ALIVE_BASE + 0x23F0))
#define DIS_IRQ_CPUCL1_CPU3_CPUSEQUENCER_DURATION1		((void *)(PMU_ALIVE_BASE + 0x23F4))
#define DIS_IRQ_CPUCL1_CPU3_CPUSEQUENCER_DURATION2		((void *)(PMU_ALIVE_BASE + 0x23F8))
#define DIS_IRQ_CPUCL1_CPU3_CPUSEQUENCER_DURATION3		((void *)(PMU_ALIVE_BASE + 0x23FC))
#define CPUCL0_NONCPU_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2400))
#define CPUCL0_NONCPU_STATUS					((void *)(PMU_ALIVE_BASE + 0x2404))
#define CPUCL0_NONCPU_OPTION					((void *)(PMU_ALIVE_BASE + 0x2408))
#define CPUCL0_NONCPU_RESET					((void *)(PMU_ALIVE_BASE + 0x240C))
#define CPUCL0_NONCPU_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2410))
#define CPUCL0_NONCPU_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2414))
#define CPUCL0_NONCPU_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2418))
#define CPUCL0_NONCPU_DURATION3					((void *)(PMU_ALIVE_BASE + 0x241C))
#define CPUCL1_NONCPU_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2420))
#define CPUCL1_NONCPU_STATUS					((void *)(PMU_ALIVE_BASE + 0x2424))
#define CPUCL1_NONCPU_OPTION					((void *)(PMU_ALIVE_BASE + 0x2428))
#define CPUCL1_NONCPU_RESET					((void *)(PMU_ALIVE_BASE + 0x242C))
#define CPUCL1_NONCPU_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2430))
#define CPUCL1_NONCPU_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2434))
#define CPUCL1_NONCPU_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2438))
#define CPUCL1_NONCPU_DURATION3					((void *)(PMU_ALIVE_BASE + 0x243C))
#define CPUCL0_CPUSEQUENCER_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x2480))
#define CPUCL0_CPUSEQUENCER_STATUS				((void *)(PMU_ALIVE_BASE + 0x2484))
#define CPUCL0_CPUSEQUENCER_OPTION				((void *)(PMU_ALIVE_BASE + 0x2488))
#define CPUCL0_CPUSEQUENCER_RESET				((void *)(PMU_ALIVE_BASE + 0x248C))
#define CPUCL0_CPUSEQUENCER_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2490))
#define CPUCL0_CPUSEQUENCER_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2494))
#define CPUCL0_CPUSEQUENCER_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2498))
#define CPUCL0_CPUSEQUENCER_DURATION3				((void *)(PMU_ALIVE_BASE + 0x249C))
#define CPUCL1_CPUSEQUENCER_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x24A0))
#define CPUCL1_CPUSEQUENCER_STATUS				((void *)(PMU_ALIVE_BASE + 0x24A4))
#define CPUCL1_CPUSEQUENCER_OPTION				((void *)(PMU_ALIVE_BASE + 0x24A8))
#define CPUCL1_CPUSEQUENCER_RESET				((void *)(PMU_ALIVE_BASE + 0x24AC))
#define CPUCL1_CPUSEQUENCER_DURATION0				((void *)(PMU_ALIVE_BASE + 0x24B0))
#define CPUCL1_CPUSEQUENCER_DURATION1				((void *)(PMU_ALIVE_BASE + 0x24B4))
#define CPUCL1_CPUSEQUENCER_DURATION2				((void *)(PMU_ALIVE_BASE + 0x24B8))
#define CPUCL1_CPUSEQUENCER_DURATION3				((void *)(PMU_ALIVE_BASE + 0x24BC))
#define CPUCL0_L2_CONFIGURATION					((void *)(PMU_ALIVE_BASE + 0x2600))
#define CPUCL0_L2_STATUS					((void *)(PMU_ALIVE_BASE + 0x2604))
#define CPUCL0_L2_OPTION					((void *)(PMU_ALIVE_BASE + 0x2608))
#define CPUCL0_L2_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2610))
#define CPUCL0_L2_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2614))
#define CPUCL0_L2_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2618))
#define CPUCL0_L2_DURATION3					((void *)(PMU_ALIVE_BASE + 0x261C))
#define CPUCL1_L2_CONFIGURATION					((void *)(PMU_ALIVE_BASE + 0x2620))
#define CPUCL1_L2_STATUS					((void *)(PMU_ALIVE_BASE + 0x2624))
#define CPUCL1_L2_OPTION					((void *)(PMU_ALIVE_BASE + 0x2628))
#define CPUCL1_L2_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2630))
#define CPUCL1_L2_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2634))
#define CPUCL1_L2_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2638))
#define CPUCL1_L2_DURATION3					((void *)(PMU_ALIVE_BASE + 0x263C))
#define CLKSTOP_CMU_TOP_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2800))
#define CLKSTOP_CMU_TOP_STATUS					((void *)(PMU_ALIVE_BASE + 0x2804))
#define CLKSTOP_CMU_TOP_OPTION					((void *)(PMU_ALIVE_BASE + 0x2808))
#define CLKSTOP_CMU_TOP_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2810))
#define CLKSTOP_CMU_TOP_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2814))
#define CLKSTOP_CMU_TOP_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2818))
#define CLKSTOP_CMU_TOP_DURATION3				((void *)(PMU_ALIVE_BASE + 0x281C))
#define CLKRUN_CMU_TOP_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2820))
#define CLKRUN_CMU_TOP_STATUS					((void *)(PMU_ALIVE_BASE + 0x2824))
#define CLKRUN_CMU_TOP_OPTION					((void *)(PMU_ALIVE_BASE + 0x2828))
#define CLKRUN_CMU_TOP_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2830))
#define CLKRUN_CMU_TOP_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2834))
#define CLKRUN_CMU_TOP_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2838))
#define CLKRUN_CMU_TOP_DURATION3				((void *)(PMU_ALIVE_BASE + 0x283C))
#define RETENTION_CMU_TOP_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2840))
#define RETENTION_CMU_TOP_STATUS				((void *)(PMU_ALIVE_BASE + 0x2844))
#define RETENTION_CMU_TOP_OPTION				((void *)(PMU_ALIVE_BASE + 0x2848))
#define RETENTION_CMU_TOP_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2850))
#define RETENTION_CMU_TOP_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2854))
#define RETENTION_CMU_TOP_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2858))
#define RETENTION_CMU_TOP_DURATION3				((void *)(PMU_ALIVE_BASE + 0x285C))
#define RESET_CMU_TOP_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2860))
#define RESET_CMU_TOP_STATUS					((void *)(PMU_ALIVE_BASE + 0x2864))
#define RESET_CMU_TOP_OPTION					((void *)(PMU_ALIVE_BASE + 0x2868))
#define RESET_CMU_TOP_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2870))
#define RESET_CMU_TOP_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2874))
#define RESET_CMU_TOP_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2878))
#define RESET_CMU_TOP_DURATION3					((void *)(PMU_ALIVE_BASE + 0x287C))
#define RESET_CPUCLKSTOP_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x28E0))
#define RESET_CPUCLKSTOP_STATUS					((void *)(PMU_ALIVE_BASE + 0x28E4))
#define RESET_CPUCLKSTOP_OPTION					((void *)(PMU_ALIVE_BASE + 0x28E8))
#define RESET_CPUCLKSTOP_DURATION0				((void *)(PMU_ALIVE_BASE + 0x28F0))
#define RESET_CPUCLKSTOP_DURATION1				((void *)(PMU_ALIVE_BASE + 0x28F4))
#define RESET_CPUCLKSTOP_DURATION2				((void *)(PMU_ALIVE_BASE + 0x28F8))
#define RESET_CPUCLKSTOP_DURATION3				((void *)(PMU_ALIVE_BASE + 0x28FC))
#define CLKSTOP_CMU_MIF_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2900))
#define CLKSTOP_CMU_MIF_STATUS					((void *)(PMU_ALIVE_BASE + 0x2904))
#define CLKSTOP_CMU_MIF_OPTION					((void *)(PMU_ALIVE_BASE + 0x2908))
#define CLKSTOP_CMU_MIF_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2910))
#define CLKSTOP_CMU_MIF_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2914))
#define CLKSTOP_CMU_MIF_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2918))
#define CLKSTOP_CMU_MIF_DURATION3				((void *)(PMU_ALIVE_BASE + 0x291C))
#define CLKRUN_CMU_MIF_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2920))
#define CLKRUN_CMU_MIF_STATUS					((void *)(PMU_ALIVE_BASE + 0x2924))
#define CLKRUN_CMU_MIF_OPTION					((void *)(PMU_ALIVE_BASE + 0x2928))
#define CLKRUN_CMU_MIF_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2930))
#define CLKRUN_CMU_MIF_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2934))
#define CLKRUN_CMU_MIF_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2938))
#define CLKRUN_CMU_MIF_DURATION3				((void *)(PMU_ALIVE_BASE + 0x293C))
#define RETENTION_CMU_MIF_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2940))
#define RETENTION_CMU_MIF_STATUS				((void *)(PMU_ALIVE_BASE + 0x2944))
#define RETENTION_CMU_MIF_OPTION				((void *)(PMU_ALIVE_BASE + 0x2948))
#define RETENTION_CMU_MIF_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2950))
#define RETENTION_CMU_MIF_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2954))
#define RETENTION_CMU_MIF_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2958))
#define RETENTION_CMU_MIF_DURATION3				((void *)(PMU_ALIVE_BASE + 0x295C))
#define RESET_CMU_MIF_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2960))
#define RESET_CMU_MIF_STATUS					((void *)(PMU_ALIVE_BASE + 0x2964))
#define RESET_CMU_MIF_OPTION					((void *)(PMU_ALIVE_BASE + 0x2968))
#define RESET_CMU_MIF_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2970))
#define RESET_CMU_MIF_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2974))
#define RESET_CMU_MIF_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2978))
#define RESET_CMU_MIF_DURATION3					((void *)(PMU_ALIVE_BASE + 0x297C))
#define DDRPHY_CLKSTOP_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2980))
#define DDRPHY_CLKSTOP_STATUS					((void *)(PMU_ALIVE_BASE + 0x2984))
#define DDRPHY_CLKSTOP_OPTION					((void *)(PMU_ALIVE_BASE + 0x2988))
#define DDRPHY_CLKSTOP_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2990))
#define DDRPHY_CLKSTOP_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2994))
#define DDRPHY_CLKSTOP_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2998))
#define DDRPHY_CLKSTOP_DURATION3				((void *)(PMU_ALIVE_BASE + 0x299C))
#define DDRPHY_ISO_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x29A0))
#define DDRPHY_ISO_STATUS					((void *)(PMU_ALIVE_BASE + 0x29A4))
#define DDRPHY_ISO_OPTION					((void *)(PMU_ALIVE_BASE + 0x29A8))
#define DDRPHY_ISO_DURATION0					((void *)(PMU_ALIVE_BASE + 0x29B0))
#define DDRPHY_ISO_DURATION1					((void *)(PMU_ALIVE_BASE + 0x29B4))
#define DDRPHY_ISO_DURATION2					((void *)(PMU_ALIVE_BASE + 0x29B8))
#define DDRPHY_ISO_DURATION3					((void *)(PMU_ALIVE_BASE + 0x29BC))
#define DDRPHY_DLL_CLK_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x29E0))
#define DDRPHY_DLL_CLK_STATUS					((void *)(PMU_ALIVE_BASE + 0x29E4))
#define DDRPHY_DLL_CLK_OPTION					((void *)(PMU_ALIVE_BASE + 0x29E8))
#define DDRPHY_DLL_CLK_DURATION0				((void *)(PMU_ALIVE_BASE + 0x29F0))
#define DDRPHY_DLL_CLK_DURATION1				((void *)(PMU_ALIVE_BASE + 0x29F4))
#define DDRPHY_DLL_CLK_DURATION2				((void *)(PMU_ALIVE_BASE + 0x29F8))
#define DDRPHY_DLL_CLK_DURATION3				((void *)(PMU_ALIVE_BASE + 0x29FC))
#define DISABLE_PLL_CMU_TOP_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x2A00))
#define DISABLE_PLL_CMU_TOP_STATUS				((void *)(PMU_ALIVE_BASE + 0x2A04))
#define DISABLE_PLL_CMU_TOP_OPTION				((void *)(PMU_ALIVE_BASE + 0x2A08))
#define DISABLE_PLL_CMU_TOP_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2A10))
#define DISABLE_PLL_CMU_TOP_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2A14))
#define DISABLE_PLL_CMU_TOP_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2A18))
#define DISABLE_PLL_CMU_TOP_DURATION3				((void *)(PMU_ALIVE_BASE + 0x2A1C))
#define DISABLE_PLL_AUD_PLL_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x2A20))
#define DISABLE_PLL_AUD_PLL_STATUS				((void *)(PMU_ALIVE_BASE + 0x2A24))
#define DISABLE_PLL_AUD_PLL_OPTION				((void *)(PMU_ALIVE_BASE + 0x2A28))
#define DISABLE_PLL_AUD_PLL_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2A30))
#define DISABLE_PLL_AUD_PLL_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2A34))
#define DISABLE_PLL_AUD_PLL_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2A38))
#define DISABLE_PLL_AUD_PLL_DURATION3				((void *)(PMU_ALIVE_BASE + 0x2A3C))
#define DISABLE_PLL_CMU_MIF_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x2B00))
#define DISABLE_PLL_CMU_MIF_STATUS				((void *)(PMU_ALIVE_BASE + 0x2B04))
#define DISABLE_PLL_CMU_MIF_OPTION				((void *)(PMU_ALIVE_BASE + 0x2B08))
#define DISABLE_PLL_CMU_MIF_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2B10))
#define DISABLE_PLL_CMU_MIF_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2B14))
#define DISABLE_PLL_CMU_MIF_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2B18))
#define DISABLE_PLL_CMU_MIF_DURATION3				((void *)(PMU_ALIVE_BASE + 0x2B1C))
#define DISABLE_PLL_APM_MIF_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x2B20))
#define DISABLE_PLL_APM_MIF_STATUS				((void *)(PMU_ALIVE_BASE + 0x2B24))
#define DISABLE_PLL_APM_MIF_OPTION				((void *)(PMU_ALIVE_BASE + 0x2B28))
#define DISABLE_PLL_APM_MIF_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2B30))
#define DISABLE_PLL_APM_MIF_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2B34))
#define DISABLE_PLL_APM_MIF_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2B38))
#define DISABLE_PLL_APM_MIF_DURATION3				((void *)(PMU_ALIVE_BASE + 0x2B3C))
#define RESET_AHEAD_CP_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2B80))
#define RESET_AHEAD_CP_STATUS					((void *)(PMU_ALIVE_BASE + 0x2B84))
#define RESET_AHEAD_CP_OPTION					((void *)(PMU_ALIVE_BASE + 0x2B88))
#define RESET_AHEAD_CP_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2B90))
#define RESET_AHEAD_CP_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2B94))
#define RESET_AHEAD_CP_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2B98))
#define RESET_AHEAD_CP_DURATION3				((void *)(PMU_ALIVE_BASE + 0x2B9C))
#define RESET_AHEAD_GNSS_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2BA0))
#define RESET_AHEAD_GNSS_STATUS					((void *)(PMU_ALIVE_BASE + 0x2BA4))
#define RESET_AHEAD_GNSS_OPTION					((void *)(PMU_ALIVE_BASE + 0x2BA8))
#define RESET_AHEAD_GNSS_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2BB0))
#define RESET_AHEAD_GNSS_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2BB4))
#define RESET_AHEAD_GNSS_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2BB8))
#define RESET_AHEAD_GNSS_DURATION3				((void *)(PMU_ALIVE_BASE + 0x2BBC))
#define TOP_BUS_CONFIGURATION					((void *)(PMU_ALIVE_BASE + 0x2C00))
#define TOP_BUS_STATUS						((void *)(PMU_ALIVE_BASE + 0x2C04))
#define TOP_BUS_OPTION						((void *)(PMU_ALIVE_BASE + 0x2C08))
#define TOP_BUS_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2C10))
#define TOP_BUS_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2C14))
#define TOP_BUS_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2C18))
#define TOP_BUS_DURATION3					((void *)(PMU_ALIVE_BASE + 0x2C1C))
#define TOP_RETENTION_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2C20))
#define TOP_RETENTION_STATUS					((void *)(PMU_ALIVE_BASE + 0x2C24))
#define TOP_RETENTION_OPTION					((void *)(PMU_ALIVE_BASE + 0x2C28))
#define TOP_RETENTION_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2C30))
#define TOP_RETENTION_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2C34))
#define TOP_RETENTION_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2C38))
#define TOP_RETENTION_DURATION3					((void *)(PMU_ALIVE_BASE + 0x2C3C))
#define TOP_PWR_CONFIGURATION					((void *)(PMU_ALIVE_BASE + 0x2C40))
#define TOP_PWR_STATUS						((void *)(PMU_ALIVE_BASE + 0x2C44))
#define TOP_PWR_OPTION						((void *)(PMU_ALIVE_BASE + 0x2C48))
#define TOP_PWR_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2C50))
#define TOP_PWR_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2C54))
#define TOP_PWR_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2C58))
#define TOP_PWR_DURATION3					((void *)(PMU_ALIVE_BASE + 0x2C5C))
#define TOP_BUS_MIF_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2C80))
#define TOP_BUS_MIF_STATUS					((void *)(PMU_ALIVE_BASE + 0x2C84))
#define TOP_BUS_MIF_OPTION					((void *)(PMU_ALIVE_BASE + 0x2C88))
#define TOP_BUS_MIF_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2C90))
#define TOP_BUS_MIF_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2C94))
#define TOP_BUS_MIF_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2C98))
#define TOP_BUS_MIF_DURATION3					((void *)(PMU_ALIVE_BASE + 0x2C9C))
#define TOP_RETENTION_MIF_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2CA0))
#define TOP_RETENTION_MIF_STATUS				((void *)(PMU_ALIVE_BASE + 0x2CA4))
#define TOP_RETENTION_MIF_OPTION				((void *)(PMU_ALIVE_BASE + 0x2CA8))
#define TOP_RETENTION_MIF_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2CB0))
#define TOP_RETENTION_MIF_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2CB4))
#define TOP_RETENTION_MIF_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2CB8))
#define TOP_RETENTION_MIF_DURATION3				((void *)(PMU_ALIVE_BASE + 0x2CBC))
#define TOP_PWR_MIF_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2CC0))
#define TOP_PWR_MIF_STATUS					((void *)(PMU_ALIVE_BASE + 0x2CC4))
#define TOP_PWR_MIF_OPTION					((void *)(PMU_ALIVE_BASE + 0x2CC8))
#define TOP_PWR_MIF_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2CD0))
#define TOP_PWR_MIF_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2CD4))
#define TOP_PWR_MIF_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2CD8))
#define TOP_PWR_MIF_DURATION3					((void *)(PMU_ALIVE_BASE + 0x2CDC))
#define LOGIC_RESET_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2D00))
#define LOGIC_RESET_STATUS					((void *)(PMU_ALIVE_BASE + 0x2D04))
#define LOGIC_RESET_OPTION					((void *)(PMU_ALIVE_BASE + 0x2D08))
#define LOGIC_RESET_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2D10))
#define LOGIC_RESET_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2D14))
#define LOGIC_RESET_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2D18))
#define LOGIC_RESET_DURATION3					((void *)(PMU_ALIVE_BASE + 0x2D1C))
#define OSCCLK_GATE_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2D20))
#define OSCCLK_GATE_STATUS					((void *)(PMU_ALIVE_BASE + 0x2D24))
#define OSCCLK_GATE_OPTION					((void *)(PMU_ALIVE_BASE + 0x2D28))
#define OSCCLK_GATE_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2D30))
#define OSCCLK_GATE_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2D34))
#define OSCCLK_GATE_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2D38))
#define OSCCLK_GATE_DURATION3					((void *)(PMU_ALIVE_BASE + 0x2D3C))
#define SLEEP_RESET_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2D40))
#define SLEEP_RESET_STATUS					((void *)(PMU_ALIVE_BASE + 0x2D44))
#define SLEEP_RESET_OPTION					((void *)(PMU_ALIVE_BASE + 0x2D48))
#define SLEEP_RESET_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2D50))
#define SLEEP_RESET_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2D54))
#define SLEEP_RESET_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2D58))
#define SLEEP_RESET_DURATION3					((void *)(PMU_ALIVE_BASE + 0x2D5C))
#define LOGIC_RESET_MIF_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2D80))
#define LOGIC_RESET_MIF_STATUS					((void *)(PMU_ALIVE_BASE + 0x2D84))
#define LOGIC_RESET_MIF_OPTION					((void *)(PMU_ALIVE_BASE + 0x2D88))
#define LOGIC_RESET_MIF_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2D90))
#define LOGIC_RESET_MIF_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2D94))
#define LOGIC_RESET_MIF_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2D98))
#define LOGIC_RESET_MIF_DURATION3				((void *)(PMU_ALIVE_BASE + 0x2D9C))
#define OSCCLK_GATE_MIF_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2DA0))
#define OSCCLK_GATE_MIF_STATUS					((void *)(PMU_ALIVE_BASE + 0x2DA4))
#define OSCCLK_GATE_MIF_OPTION					((void *)(PMU_ALIVE_BASE + 0x2DA8))
#define OSCCLK_GATE_MIF_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2DB0))
#define OSCCLK_GATE_MIF_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2DB4))
#define OSCCLK_GATE_MIF_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2DB8))
#define OSCCLK_GATE_MIF_DURATION3				((void *)(PMU_ALIVE_BASE + 0x2DBC))
#define SLEEP_RESET_MIF_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2DC0))
#define SLEEP_RESET_MIF_STATUS					((void *)(PMU_ALIVE_BASE + 0x2DC4))
#define SLEEP_RESET_MIF_OPTION					((void *)(PMU_ALIVE_BASE + 0x2DC8))
#define SLEEP_RESET_MIF_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2DD0))
#define SLEEP_RESET_MIF_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2DD4))
#define SLEEP_RESET_MIF_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2DD8))
#define SLEEP_RESET_MIF_DURATION3				((void *)(PMU_ALIVE_BASE + 0x2DDC))
#define RESET_ASB_MIF_GNSS_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x2DE0))
#define RESET_ASB_MIF_GNSS_STATUS				((void *)(PMU_ALIVE_BASE + 0x2DE4))
#define RESET_ASB_MIF_GNSS_OPTION				((void *)(PMU_ALIVE_BASE + 0x2DE8))
#define RESET_ASB_MIF_GNSS_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2DF0))
#define RESET_ASB_MIF_GNSS_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2DF4))
#define RESET_ASB_MIF_GNSS_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2DF8))
#define RESET_ASB_MIF_GNSS_DURATION3				((void *)(PMU_ALIVE_BASE + 0x2DFC))
#define MEMORY_TOP_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2E00))
#define MEMORY_TOP_STATUS					((void *)(PMU_ALIVE_BASE + 0x2E04))
#define MEMORY_TOP_OPTION					((void *)(PMU_ALIVE_BASE + 0x2E08))
#define MEMORY_TOP_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2E10))
#define MEMORY_TOP_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2E14))
#define MEMORY_TOP_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2E18))
#define MEMORY_TOP_DURATION3					((void *)(PMU_ALIVE_BASE + 0x2E1C))
#define TCXO_GATE_GNSS_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2E20))
#define TCXO_GATE_GNSS_STATUS					((void *)(PMU_ALIVE_BASE + 0x2E24))
#define TCXO_GATE_GNSS_OPTION					((void *)(PMU_ALIVE_BASE + 0x2E28))
#define TCXO_GATE_GNSS_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2E30))
#define TCXO_GATE_GNSS_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2E34))
#define TCXO_GATE_GNSS_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2E38))
#define TCXO_GATE_GNSS_DURATION3				((void *)(PMU_ALIVE_BASE + 0x2E3C))
#define RESET_ASB_GNSS_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2E40))
#define RESET_ASB_GNSS_STATUS					((void *)(PMU_ALIVE_BASE + 0x2E44))
#define RESET_ASB_GNSS_OPTION					((void *)(PMU_ALIVE_BASE + 0x2E48))
#define RESET_ASB_GNSS_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2E50))
#define RESET_ASB_GNSS_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2E54))
#define RESET_ASB_GNSS_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2E58))
#define RESET_ASB_GNSS_DURATION3				((void *)(PMU_ALIVE_BASE + 0x2E5C))
#define CLEANY_BUS_CP_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2E60))
#define CLEANY_BUS_CP_STATUS					((void *)(PMU_ALIVE_BASE + 0x2E64))
#define CLEANY_BUS_CP_OPTION					((void *)(PMU_ALIVE_BASE + 0x2E68))
#define CLEANY_BUS_CP_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2E70))
#define CLEANY_BUS_CP_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2E74))
#define CLEANY_BUS_CP_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2E78))
#define CLEANY_BUS_CP_DURATION3					((void *)(PMU_ALIVE_BASE + 0x2E7C))
#define LOGIC_RESET_CP_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2E80))
#define LOGIC_RESET_CP_STATUS					((void *)(PMU_ALIVE_BASE + 0x2E84))
#define LOGIC_RESET_CP_OPTION					((void *)(PMU_ALIVE_BASE + 0x2E88))
#define LOGIC_RESET_CP_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2E90))
#define LOGIC_RESET_CP_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2E94))
#define LOGIC_RESET_CP_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2E98))
#define LOGIC_RESET_CP_DURATION3				((void *)(PMU_ALIVE_BASE + 0x2E9C))
#define TCXO_GATE_CP_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2EA0))
#define TCXO_GATE_CP_STATUS					((void *)(PMU_ALIVE_BASE + 0x2EA4))
#define TCXO_GATE_CP_OPTION					((void *)(PMU_ALIVE_BASE + 0x2EA8))
#define TCXO_GATE_CP_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2EB0))
#define TCXO_GATE_CP_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2EB4))
#define TCXO_GATE_CP_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2EB8))
#define TCXO_GATE_CP_DURATION3					((void *)(PMU_ALIVE_BASE + 0x2EBC))
#define RESET_ASB_CP_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2EC0))
#define RESET_ASB_CP_STATUS					((void *)(PMU_ALIVE_BASE + 0x2EC4))
#define RESET_ASB_CP_OPTION					((void *)(PMU_ALIVE_BASE + 0x2EC8))
#define RESET_ASB_CP_DURATION0					((void *)(PMU_ALIVE_BASE + 0x2ED0))
#define RESET_ASB_CP_DURATION1					((void *)(PMU_ALIVE_BASE + 0x2ED4))
#define RESET_ASB_CP_DURATION2					((void *)(PMU_ALIVE_BASE + 0x2ED8))
#define RESET_ASB_CP_DURATION3					((void *)(PMU_ALIVE_BASE + 0x2EDC))
#define RESET_ASB_MIF_CP_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2EE0))
#define RESET_ASB_MIF_CP_STATUS					((void *)(PMU_ALIVE_BASE + 0x2EE4))
#define RESET_ASB_MIF_CP_OPTION					((void *)(PMU_ALIVE_BASE + 0x2EE8))
#define RESET_ASB_MIF_CP_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2EF0))
#define RESET_ASB_MIF_CP_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2EF4))
#define RESET_ASB_MIF_CP_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2EF8))
#define RESET_ASB_MIF_CP_DURATION3				((void *)(PMU_ALIVE_BASE + 0x2EFC))
#define MEMORY_MIF_ALIVEIRAM_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x2F00))
#define MEMORY_MIF_ALIVEIRAM_STATUS				((void *)(PMU_ALIVE_BASE + 0x2F04))
#define MEMORY_MIF_ALIVEIRAM_OPTION				((void *)(PMU_ALIVE_BASE + 0x2F08))
#define MEMORY_MIF_ALIVEIRAM_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2F10))
#define MEMORY_MIF_ALIVEIRAM_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2F14))
#define MEMORY_MIF_ALIVEIRAM_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2F18))
#define MEMORY_MIF_ALIVEIRAM_DURATION3				((void *)(PMU_ALIVE_BASE + 0x2F1C))
#define MEMORY_MIF_TOP_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2F20))
#define MEMORY_MIF_TOP_STATUS					((void *)(PMU_ALIVE_BASE + 0x2F24))
#define MEMORY_MIF_TOP_OPTION					((void *)(PMU_ALIVE_BASE + 0x2F28))
#define MEMORY_MIF_TOP_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2F30))
#define MEMORY_MIF_TOP_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2F34))
#define MEMORY_MIF_TOP_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2F38))
#define MEMORY_MIF_TOP_DURATION3				((void *)(PMU_ALIVE_BASE + 0x2F3C))
#define CLEANY_BUS_GNSS_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2F40))
#define CLEANY_BUS_GNSS_STATUS					((void *)(PMU_ALIVE_BASE + 0x2F44))
#define CLEANY_BUS_GNSS_OPTION					((void *)(PMU_ALIVE_BASE + 0x2F48))
#define CLEANY_BUS_GNSS_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2F50))
#define CLEANY_BUS_GNSS_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2F54))
#define CLEANY_BUS_GNSS_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2F58))
#define CLEANY_BUS_GNSS_DURATION3				((void *)(PMU_ALIVE_BASE + 0x2F5C))
#define LOGIC_RESET_GNSS_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x2F60))
#define LOGIC_RESET_GNSS_STATUS					((void *)(PMU_ALIVE_BASE + 0x2F64))
#define LOGIC_RESET_GNSS_OPTION					((void *)(PMU_ALIVE_BASE + 0x2F68))
#define LOGIC_RESET_GNSS_DURATION0				((void *)(PMU_ALIVE_BASE + 0x2F70))
#define LOGIC_RESET_GNSS_DURATION1				((void *)(PMU_ALIVE_BASE + 0x2F74))
#define LOGIC_RESET_GNSS_DURATION2				((void *)(PMU_ALIVE_BASE + 0x2F78))
#define LOGIC_RESET_GNSS_DURATION3				((void *)(PMU_ALIVE_BASE + 0x2F7C))
#define PAD_RETENTION_LPDDR3_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x3000))
#define PAD_RETENTION_LPDDR3_STATUS				((void *)(PMU_ALIVE_BASE + 0x3004))
#define PAD_RETENTION_LPDDR3_OPTION				((void *)(PMU_ALIVE_BASE + 0x3008))
#define PAD_RETENTION_LPDDR3_DURATION0				((void *)(PMU_ALIVE_BASE + 0x3010))
#define PAD_RETENTION_LPDDR3_DURATION1				((void *)(PMU_ALIVE_BASE + 0x3014))
#define PAD_RETENTION_LPDDR3_DURATION2				((void *)(PMU_ALIVE_BASE + 0x3018))
#define PAD_RETENTION_LPDDR3_DURATION3				((void *)(PMU_ALIVE_BASE + 0x301C))
#define PAD_RETENTION_AUD_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x3020))
#define PAD_RETENTION_AUD_STATUS				((void *)(PMU_ALIVE_BASE + 0x3024))
#define PAD_RETENTION_AUD_OPTION				((void *)(PMU_ALIVE_BASE + 0x3028))
#define PAD_RETENTION_AUD_DURATION0				((void *)(PMU_ALIVE_BASE + 0x3030))
#define PAD_RETENTION_AUD_DURATION1				((void *)(PMU_ALIVE_BASE + 0x3034))
#define PAD_RETENTION_AUD_DURATION2				((void *)(PMU_ALIVE_BASE + 0x3038))
#define PAD_RETENTION_AUD_DURATION3				((void *)(PMU_ALIVE_BASE + 0x303C))
#define PAD_RETENTION_PEDOMETER_TOP_CONFIGURATION		((void *)(PMU_ALIVE_BASE + 0x3040))
#define PAD_RETENTION_PEDOMETER_TOP_STATUS			((void *)(PMU_ALIVE_BASE + 0x3044))
#define PAD_RETENTION_PEDOMETER_TOP_OPTION			((void *)(PMU_ALIVE_BASE + 0x3048))
#define PAD_RETENTION_PEDOMETER_TOP_DURATION0			((void *)(PMU_ALIVE_BASE + 0x3050))
#define PAD_RETENTION_PEDOMETER_TOP_DURATION1			((void *)(PMU_ALIVE_BASE + 0x3054))
#define PAD_RETENTION_PEDOMETER_TOP_DURATION2			((void *)(PMU_ALIVE_BASE + 0x3058))
#define PAD_RETENTION_PEDOMETER_TOP_DURATION3			((void *)(PMU_ALIVE_BASE + 0x305C))
#define PAD_RETENTION_MMC2_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x30C0))
#define PAD_RETENTION_MMC2_STATUS				((void *)(PMU_ALIVE_BASE + 0x30C4))
#define PAD_RETENTION_MMC2_OPTION				((void *)(PMU_ALIVE_BASE + 0x30C8))
#define PAD_RETENTION_MMC2_DURATION0				((void *)(PMU_ALIVE_BASE + 0x30D0))
#define PAD_RETENTION_MMC2_DURATION1				((void *)(PMU_ALIVE_BASE + 0x30D4))
#define PAD_RETENTION_MMC2_DURATION2				((void *)(PMU_ALIVE_BASE + 0x30D8))
#define PAD_RETENTION_MMC2_DURATION3				((void *)(PMU_ALIVE_BASE + 0x30DC))
#define PAD_RETENTION_TOP_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x3100))
#define PAD_RETENTION_TOP_STATUS				((void *)(PMU_ALIVE_BASE + 0x3104))
#define PAD_RETENTION_TOP_OPTION				((void *)(PMU_ALIVE_BASE + 0x3108))
#define PAD_RETENTION_TOP_DURATION0				((void *)(PMU_ALIVE_BASE + 0x3110))
#define PAD_RETENTION_TOP_DURATION1				((void *)(PMU_ALIVE_BASE + 0x3114))
#define PAD_RETENTION_TOP_DURATION2				((void *)(PMU_ALIVE_BASE + 0x3118))
#define PAD_RETENTION_TOP_DURATION3				((void *)(PMU_ALIVE_BASE + 0x311C))
#define PAD_RETENTION_UART_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x3120))
#define PAD_RETENTION_UART_STATUS				((void *)(PMU_ALIVE_BASE + 0x3124))
#define PAD_RETENTION_UART_OPTION				((void *)(PMU_ALIVE_BASE + 0x3128))
#define PAD_RETENTION_UART_DURATION0				((void *)(PMU_ALIVE_BASE + 0x3130))
#define PAD_RETENTION_UART_DURATION1				((void *)(PMU_ALIVE_BASE + 0x3134))
#define PAD_RETENTION_UART_DURATION2				((void *)(PMU_ALIVE_BASE + 0x3138))
#define PAD_RETENTION_UART_DURATION3				((void *)(PMU_ALIVE_BASE + 0x313C))
#define PAD_RETENTION_MMC0_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x3140))
#define PAD_RETENTION_MMC0_STATUS				((void *)(PMU_ALIVE_BASE + 0x3144))
#define PAD_RETENTION_MMC0_OPTION				((void *)(PMU_ALIVE_BASE + 0x3148))
#define PAD_RETENTION_MMC0_DURATION0				((void *)(PMU_ALIVE_BASE + 0x3150))
#define PAD_RETENTION_MMC0_DURATION1				((void *)(PMU_ALIVE_BASE + 0x3154))
#define PAD_RETENTION_MMC0_DURATION2				((void *)(PMU_ALIVE_BASE + 0x3158))
#define PAD_RETENTION_MMC0_DURATION3				((void *)(PMU_ALIVE_BASE + 0x315C))
#define PAD_RETENTION_MMC1_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x3160))
#define PAD_RETENTION_MMC1_STATUS				((void *)(PMU_ALIVE_BASE + 0x3164))
#define PAD_RETENTION_MMC1_OPTION				((void *)(PMU_ALIVE_BASE + 0x3168))
#define PAD_RETENTION_MMC1_DURATION0				((void *)(PMU_ALIVE_BASE + 0x3170))
#define PAD_RETENTION_MMC1_DURATION1				((void *)(PMU_ALIVE_BASE + 0x3174))
#define PAD_RETENTION_MMC1_DURATION2				((void *)(PMU_ALIVE_BASE + 0x3178))
#define PAD_RETENTION_MMC1_DURATION3				((void *)(PMU_ALIVE_BASE + 0x317C))
#define PAD_RETENTION_SPI_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x31C0))
#define PAD_RETENTION_SPI_STATUS				((void *)(PMU_ALIVE_BASE + 0x31C4))
#define PAD_RETENTION_SPI_OPTION				((void *)(PMU_ALIVE_BASE + 0x31C8))
#define PAD_RETENTION_SPI_DURATION0				((void *)(PMU_ALIVE_BASE + 0x31D0))
#define PAD_RETENTION_SPI_DURATION1				((void *)(PMU_ALIVE_BASE + 0x31D4))
#define PAD_RETENTION_SPI_DURATION2				((void *)(PMU_ALIVE_BASE + 0x31D8))
#define PAD_RETENTION_SPI_DURATION3				((void *)(PMU_ALIVE_BASE + 0x31DC))
#define PAD_RETENTION_MIF_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x31E0))
#define PAD_RETENTION_MIF_STATUS				((void *)(PMU_ALIVE_BASE + 0x31E4))
#define PAD_RETENTION_MIF_OPTION				((void *)(PMU_ALIVE_BASE + 0x31E8))
#define PAD_RETENTION_MIF_DURATION0				((void *)(PMU_ALIVE_BASE + 0x31F0))
#define PAD_RETENTION_MIF_DURATION1				((void *)(PMU_ALIVE_BASE + 0x31F4))
#define PAD_RETENTION_MIF_DURATION2				((void *)(PMU_ALIVE_BASE + 0x31F8))
#define PAD_RETENTION_MIF_DURATION3				((void *)(PMU_ALIVE_BASE + 0x31FC))
#define PAD_ISOLATION_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x3200))
#define PAD_ISOLATION_STATUS					((void *)(PMU_ALIVE_BASE + 0x3204))
#define PAD_ISOLATION_OPTION					((void *)(PMU_ALIVE_BASE + 0x3208))
#define PAD_ISOLATION_DURATION0					((void *)(PMU_ALIVE_BASE + 0x3210))
#define PAD_ISOLATION_DURATION1					((void *)(PMU_ALIVE_BASE + 0x3214))
#define PAD_ISOLATION_DURATION2					((void *)(PMU_ALIVE_BASE + 0x3218))
#define PAD_ISOLATION_DURATION3					((void *)(PMU_ALIVE_BASE + 0x321C))
#define PAD_RETENTION_BOOTLDO_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x3240))
#define PAD_RETENTION_BOOTLDO_STATUS				((void *)(PMU_ALIVE_BASE + 0x3244))
#define PAD_RETENTION_BOOTLDO_OPTION				((void *)(PMU_ALIVE_BASE + 0x3248))
#define PAD_RETENTION_BOOTLDO_DURATION0				((void *)(PMU_ALIVE_BASE + 0x3250))
#define PAD_RETENTION_BOOTLDO_DURATION1				((void *)(PMU_ALIVE_BASE + 0x3254))
#define PAD_RETENTION_BOOTLDO_DURATION2				((void *)(PMU_ALIVE_BASE + 0x3258))
#define PAD_RETENTION_BOOTLDO_DURATION3				((void *)(PMU_ALIVE_BASE + 0x325C))
#define PAD_ISOLATION_MIF_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x3280))
#define PAD_ISOLATION_MIF_STATUS				((void *)(PMU_ALIVE_BASE + 0x3284))
#define PAD_ISOLATION_MIF_OPTION				((void *)(PMU_ALIVE_BASE + 0x3288))
#define PAD_ISOLATION_MIF_DURATION0				((void *)(PMU_ALIVE_BASE + 0x3290))
#define PAD_ISOLATION_MIF_DURATION1				((void *)(PMU_ALIVE_BASE + 0x3294))
#define PAD_ISOLATION_MIF_DURATION2				((void *)(PMU_ALIVE_BASE + 0x3298))
#define PAD_ISOLATION_MIF_DURATION3				((void *)(PMU_ALIVE_BASE + 0x329C))
#define PS_HOLD_CONTROL						((void *)(PMU_ALIVE_BASE + 0x330C))
#define EXT_REGULATOR_MIF_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x3620))
#define EXT_REGULATOR_MIF_STATUS				((void *)(PMU_ALIVE_BASE + 0x3624))
#define EXT_REGULATOR_MIF_OPTION				((void *)(PMU_ALIVE_BASE + 0x3628))
#define EXT_REGULATOR_MIF_DURATION0				((void *)(PMU_ALIVE_BASE + 0x3630))
#define EXT_REGULATOR_MIF_DURATION1				((void *)(PMU_ALIVE_BASE + 0x3634))
#define EXT_REGULATOR_MIF_DURATION2				((void *)(PMU_ALIVE_BASE + 0x3638))
#define GPIO_MODE_CONFIGURATION					((void *)(PMU_ALIVE_BASE + 0x3800))
#define GPIO_MODE_STATUS					((void *)(PMU_ALIVE_BASE + 0x3804))
#define GPIO_MODE_OPTION					((void *)(PMU_ALIVE_BASE + 0x3808))
#define GPIO_MODE_DURATION0					((void *)(PMU_ALIVE_BASE + 0x3810))
#define GPIO_MODE_DURATION1					((void *)(PMU_ALIVE_BASE + 0x3814))
#define GPIO_MODE_DURATION2					((void *)(PMU_ALIVE_BASE + 0x3818))
#define GPIO_MODE_DURATION3					((void *)(PMU_ALIVE_BASE + 0x381C))
#define GPIO_MODE_MIF_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x3900))
#define GPIO_MODE_MIF_STATUS					((void *)(PMU_ALIVE_BASE + 0x3904))
#define GPIO_MODE_MIF_OPTION					((void *)(PMU_ALIVE_BASE + 0x3908))
#define GPIO_MODE_MIF_DURATION0					((void *)(PMU_ALIVE_BASE + 0x3910))
#define GPIO_MODE_MIF_DURATION1					((void *)(PMU_ALIVE_BASE + 0x3914))
#define GPIO_MODE_MIF_DURATION2					((void *)(PMU_ALIVE_BASE + 0x3918))
#define GPIO_MODE_MIF_DURATION3					((void *)(PMU_ALIVE_BASE + 0x391C))
#define GPIO_MODE_DISPAUD_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x39E0))
#define GPIO_MODE_DISPAUD_STATUS				((void *)(PMU_ALIVE_BASE + 0x39E4))
#define GPIO_MODE_DISPAUD_OPTION				((void *)(PMU_ALIVE_BASE + 0x39E8))
#define GPIO_MODE_DISPAUD_DURATION0				((void *)(PMU_ALIVE_BASE + 0x39F0))
#define GPIO_MODE_DISPAUD_DURATION1				((void *)(PMU_ALIVE_BASE + 0x39F4))
#define GPIO_MODE_DISPAUD_DURATION2				((void *)(PMU_ALIVE_BASE + 0x39F8))
#define GPIO_MODE_DISPAUD_DURATION3				((void *)(PMU_ALIVE_BASE + 0x39FC))
#define CLKSTOP_OPEN_CMU_TOP_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x3C00))
#define CLKSTOP_OPEN_CMU_TOP_STATUS				((void *)(PMU_ALIVE_BASE + 0x3C04))
#define CLKSTOP_OPEN_CMU_TOP_OPTION				((void *)(PMU_ALIVE_BASE + 0x3C08))
#define CLKSTOP_OPEN_CMU_TOP_DURATION0				((void *)(PMU_ALIVE_BASE + 0x3C10))
#define CLKSTOP_OPEN_CMU_TOP_DURATION1				((void *)(PMU_ALIVE_BASE + 0x3C14))
#define CLKSTOP_OPEN_CMU_TOP_DURATION2				((void *)(PMU_ALIVE_BASE + 0x3C18))
#define CLKSTOP_OPEN_CMU_TOP_DURATION3				((void *)(PMU_ALIVE_BASE + 0x3C1C))
#define CLKSTOP_OPEN_CMU_MIF_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x3C20))
#define CLKSTOP_OPEN_CMU_MIF_STATUS				((void *)(PMU_ALIVE_BASE + 0x3C24))
#define CLKSTOP_OPEN_CMU_MIF_OPTION				((void *)(PMU_ALIVE_BASE + 0x3C28))
#define CLKSTOP_OPEN_CMU_MIF_DURATION0				((void *)(PMU_ALIVE_BASE + 0x3C30))
#define CLKSTOP_OPEN_CMU_MIF_DURATION1				((void *)(PMU_ALIVE_BASE + 0x3C34))
#define CLKSTOP_OPEN_CMU_MIF_DURATION2				((void *)(PMU_ALIVE_BASE + 0x3C38))
#define CLKSTOP_OPEN_CMU_MIF_DURATION3				((void *)(PMU_ALIVE_BASE + 0x3C3C))
#define CLKSTOP_OPEN_CMU_G3D_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x3C40))
#define CLKSTOP_OPEN_CMU_G3D_STATUS				((void *)(PMU_ALIVE_BASE + 0x3C44))
#define CLKSTOP_OPEN_CMU_G3D_OPTION				((void *)(PMU_ALIVE_BASE + 0x3C48))
#define CLKSTOP_OPEN_CMU_G3D_DURATION0				((void *)(PMU_ALIVE_BASE + 0x3C50))
#define CLKSTOP_OPEN_CMU_G3D_DURATION1				((void *)(PMU_ALIVE_BASE + 0x3C54))
#define CLKSTOP_OPEN_CMU_G3D_DURATION2				((void *)(PMU_ALIVE_BASE + 0x3C58))
#define CLKSTOP_OPEN_CMU_G3D_DURATION3				((void *)(PMU_ALIVE_BASE + 0x3C5C))
#define CLKSTOP_OPEN_CMU_DISPAUD_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x3C60))
#define CLKSTOP_OPEN_CMU_DISPAUD_STATUS				((void *)(PMU_ALIVE_BASE + 0x3C64))
#define CLKSTOP_OPEN_CMU_DISPAUD_OPTION				((void *)(PMU_ALIVE_BASE + 0x3C68))
#define CLKSTOP_OPEN_CMU_DISPAUD_DURATION0			((void *)(PMU_ALIVE_BASE + 0x3C70))
#define CLKSTOP_OPEN_CMU_DISPAUD_DURATION1			((void *)(PMU_ALIVE_BASE + 0x3C74))
#define CLKSTOP_OPEN_CMU_DISPAUD_DURATION2			((void *)(PMU_ALIVE_BASE + 0x3C78))
#define CLKSTOP_OPEN_CMU_DISPAUD_DURATION3			((void *)(PMU_ALIVE_BASE + 0x3C7C))
#define CLKSTOP_OPEN_CMU_ISP_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x3C80))
#define CLKSTOP_OPEN_CMU_ISP_STATUS				((void *)(PMU_ALIVE_BASE + 0x3C84))
#define CLKSTOP_OPEN_CMU_ISP_OPTION				((void *)(PMU_ALIVE_BASE + 0x3C88))
#define CLKSTOP_OPEN_CMU_ISP_DURATION0				((void *)(PMU_ALIVE_BASE + 0x3C90))
#define CLKSTOP_OPEN_CMU_ISP_DURATION1				((void *)(PMU_ALIVE_BASE + 0x3C94))
#define CLKSTOP_OPEN_CMU_ISP_DURATION2				((void *)(PMU_ALIVE_BASE + 0x3C98))
#define CLKSTOP_OPEN_CMU_ISP_DURATION3				((void *)(PMU_ALIVE_BASE + 0x3C9C))
#define CLKSTOP_OPEN_CMU_MFCMSCL_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x3CA0))
#define CLKSTOP_OPEN_CMU_MFCMSCL_STATUS				((void *)(PMU_ALIVE_BASE + 0x3CA4))
#define CLKSTOP_OPEN_CMU_MFCMSCL_OPTION				((void *)(PMU_ALIVE_BASE + 0x3CA8))
#define CLKSTOP_OPEN_CMU_MFCMSCL_DURATION0			((void *)(PMU_ALIVE_BASE + 0x3CB0))
#define CLKSTOP_OPEN_CMU_MFCMSCL_DURATION1			((void *)(PMU_ALIVE_BASE + 0x3CB4))
#define CLKSTOP_OPEN_CMU_MFCMSCL_DURATION2			((void *)(PMU_ALIVE_BASE + 0x3CB8))
#define CLKSTOP_OPEN_CMU_MFCMSCL_DURATION3			((void *)(PMU_ALIVE_BASE + 0x3CBC))
#define G3D_CONFIGURATION					((void *)(PMU_ALIVE_BASE + 0x4000))
#define G3D_STATUS						((void *)(PMU_ALIVE_BASE + 0x4004))
#define G3D_OPTION						((void *)(PMU_ALIVE_BASE + 0x4008))
#define G3D_DURATION0						((void *)(PMU_ALIVE_BASE + 0x4010))
#define G3D_DURATION1						((void *)(PMU_ALIVE_BASE + 0x4014))
#define G3D_DURATION2						((void *)(PMU_ALIVE_BASE + 0x4018))
#define G3D_DURATION3						((void *)(PMU_ALIVE_BASE + 0x401C))
#define DISPAUD_CONFIGURATION					((void *)(PMU_ALIVE_BASE + 0x4020))
#define DISPAUD_STATUS						((void *)(PMU_ALIVE_BASE + 0x4024))
#define DISPAUD_OPTION						((void *)(PMU_ALIVE_BASE + 0x4028))
#define DISPAUD_DURATION0					((void *)(PMU_ALIVE_BASE + 0x4030))
#define DISPAUD_DURATION1					((void *)(PMU_ALIVE_BASE + 0x4034))
#define DISPAUD_DURATION2					((void *)(PMU_ALIVE_BASE + 0x4038))
#define DISPAUD_DURATION3					((void *)(PMU_ALIVE_BASE + 0x403C))
#define ISP_CONFIGURATION					((void *)(PMU_ALIVE_BASE + 0x4040))
#define ISP_STATUS						((void *)(PMU_ALIVE_BASE + 0x4044))
#define ISP_OPTION						((void *)(PMU_ALIVE_BASE + 0x4048))
#define ISP_DURATION0						((void *)(PMU_ALIVE_BASE + 0x4050))
#define ISP_DURATION1						((void *)(PMU_ALIVE_BASE + 0x4054))
#define ISP_DURATION2						((void *)(PMU_ALIVE_BASE + 0x4058))
#define ISP_DURATION3						((void *)(PMU_ALIVE_BASE + 0x405C))
#define MFCMSCL_CONFIGURATION					((void *)(PMU_ALIVE_BASE + 0x4060))
#define MFCMSCL_STATUS						((void *)(PMU_ALIVE_BASE + 0x4064))
#define MFCMSCL_OPTION						((void *)(PMU_ALIVE_BASE + 0x4068))
#define MFCMSCL_DURATION0					((void *)(PMU_ALIVE_BASE + 0x4070))
#define MFCMSCL_DURATION1					((void *)(PMU_ALIVE_BASE + 0x4074))
#define MFCMSCL_DURATION2					((void *)(PMU_ALIVE_BASE + 0x4078))
#define MFCMSCL_DURATION3					((void *)(PMU_ALIVE_BASE + 0x407C))
#define CLKRUN_CMU_G3D_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x4200))
#define CLKRUN_CMU_G3D_STATUS					((void *)(PMU_ALIVE_BASE + 0x4204))
#define CLKRUN_CMU_G3D_OPTION					((void *)(PMU_ALIVE_BASE + 0x4208))
#define CLKRUN_CMU_G3D_DURATION0				((void *)(PMU_ALIVE_BASE + 0x4210))
#define CLKRUN_CMU_G3D_DURATION1				((void *)(PMU_ALIVE_BASE + 0x4214))
#define CLKRUN_CMU_G3D_DURATION2				((void *)(PMU_ALIVE_BASE + 0x4218))
#define CLKRUN_CMU_G3D_DURATION3				((void *)(PMU_ALIVE_BASE + 0x421C))
#define CLKRUN_CMU_DISPAUD_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x4220))
#define CLKRUN_CMU_DISPAUD_STATUS				((void *)(PMU_ALIVE_BASE + 0x4224))
#define CLKRUN_CMU_DISPAUD_OPTION				((void *)(PMU_ALIVE_BASE + 0x4228))
#define CLKRUN_CMU_DISPAUD_DURATION0				((void *)(PMU_ALIVE_BASE + 0x4230))
#define CLKRUN_CMU_DISPAUD_DURATION1				((void *)(PMU_ALIVE_BASE + 0x4234))
#define CLKRUN_CMU_DISPAUD_DURATION2				((void *)(PMU_ALIVE_BASE + 0x4238))
#define CLKRUN_CMU_DISPAUD_DURATION3				((void *)(PMU_ALIVE_BASE + 0x423C))
#define CLKRUN_CMU_ISP_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x4240))
#define CLKRUN_CMU_ISP_STATUS					((void *)(PMU_ALIVE_BASE + 0x4244))
#define CLKRUN_CMU_ISP_OPTION					((void *)(PMU_ALIVE_BASE + 0x4248))
#define CLKRUN_CMU_ISP_DURATION0				((void *)(PMU_ALIVE_BASE + 0x4250))
#define CLKRUN_CMU_ISP_DURATION1				((void *)(PMU_ALIVE_BASE + 0x4254))
#define CLKRUN_CMU_ISP_DURATION2				((void *)(PMU_ALIVE_BASE + 0x4258))
#define CLKRUN_CMU_ISP_DURATION3				((void *)(PMU_ALIVE_BASE + 0x425C))
#define CLKRUN_CMU_MFCMSCL_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x4260))
#define CLKRUN_CMU_MFCMSCL_STATUS				((void *)(PMU_ALIVE_BASE + 0x4264))
#define CLKRUN_CMU_MFCMSCL_OPTION				((void *)(PMU_ALIVE_BASE + 0x4268))
#define CLKRUN_CMU_MFCMSCL_DURATION0				((void *)(PMU_ALIVE_BASE + 0x4270))
#define CLKRUN_CMU_MFCMSCL_DURATION1				((void *)(PMU_ALIVE_BASE + 0x4274))
#define CLKRUN_CMU_MFCMSCL_DURATION2				((void *)(PMU_ALIVE_BASE + 0x4278))
#define CLKRUN_CMU_MFCMSCL_DURATION3				((void *)(PMU_ALIVE_BASE + 0x427C))
#define CLKSTOP_CMU_G3D_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x4400))
#define CLKSTOP_CMU_G3D_STATUS					((void *)(PMU_ALIVE_BASE + 0x4404))
#define CLKSTOP_CMU_G3D_OPTION					((void *)(PMU_ALIVE_BASE + 0x4408))
#define CLKSTOP_CMU_G3D_DURATION0				((void *)(PMU_ALIVE_BASE + 0x4410))
#define CLKSTOP_CMU_G3D_DURATION1				((void *)(PMU_ALIVE_BASE + 0x4414))
#define CLKSTOP_CMU_G3D_DURATION2				((void *)(PMU_ALIVE_BASE + 0x4418))
#define CLKSTOP_CMU_G3D_DURATION3				((void *)(PMU_ALIVE_BASE + 0x441C))
#define CLKSTOP_CMU_DISPAUD_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x4420))
#define CLKSTOP_CMU_DISPAUD_STATUS				((void *)(PMU_ALIVE_BASE + 0x4424))
#define CLKSTOP_CMU_DISPAUD_OPTION				((void *)(PMU_ALIVE_BASE + 0x4428))
#define CLKSTOP_CMU_DISPAUD_DURATION0				((void *)(PMU_ALIVE_BASE + 0x4430))
#define CLKSTOP_CMU_DISPAUD_DURATION1				((void *)(PMU_ALIVE_BASE + 0x4434))
#define CLKSTOP_CMU_DISPAUD_DURATION2				((void *)(PMU_ALIVE_BASE + 0x4438))
#define CLKSTOP_CMU_DISPAUD_DURATION3				((void *)(PMU_ALIVE_BASE + 0x443C))
#define CLKSTOP_CMU_ISP_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x4440))
#define CLKSTOP_CMU_ISP_STATUS					((void *)(PMU_ALIVE_BASE + 0x4444))
#define CLKSTOP_CMU_ISP_OPTION					((void *)(PMU_ALIVE_BASE + 0x4448))
#define CLKSTOP_CMU_ISP_DURATION0				((void *)(PMU_ALIVE_BASE + 0x4450))
#define CLKSTOP_CMU_ISP_DURATION1				((void *)(PMU_ALIVE_BASE + 0x4454))
#define CLKSTOP_CMU_ISP_DURATION2				((void *)(PMU_ALIVE_BASE + 0x4458))
#define CLKSTOP_CMU_ISP_DURATION3				((void *)(PMU_ALIVE_BASE + 0x445C))
#define CLKSTOP_CMU_MFCMSCL_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x4460))
#define CLKSTOP_CMU_MFCMSCL_STATUS				((void *)(PMU_ALIVE_BASE + 0x4464))
#define CLKSTOP_CMU_MFCMSCL_OPTION				((void *)(PMU_ALIVE_BASE + 0x4468))
#define CLKSTOP_CMU_MFCMSCL_DURATION0				((void *)(PMU_ALIVE_BASE + 0x4470))
#define CLKSTOP_CMU_MFCMSCL_DURATION1				((void *)(PMU_ALIVE_BASE + 0x4474))
#define CLKSTOP_CMU_MFCMSCL_DURATION2				((void *)(PMU_ALIVE_BASE + 0x4478))
#define CLKSTOP_CMU_MFCMSCL_DURATION3				((void *)(PMU_ALIVE_BASE + 0x447C))
#define DISABLE_PLL_CMU_G3D_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x4600))
#define DISABLE_PLL_CMU_G3D_STATUS				((void *)(PMU_ALIVE_BASE + 0x4604))
#define DISABLE_PLL_CMU_G3D_OPTION				((void *)(PMU_ALIVE_BASE + 0x4608))
#define DISABLE_PLL_CMU_G3D_DURATION0				((void *)(PMU_ALIVE_BASE + 0x4610))
#define DISABLE_PLL_CMU_G3D_DURATION1				((void *)(PMU_ALIVE_BASE + 0x4614))
#define DISABLE_PLL_CMU_G3D_DURATION2				((void *)(PMU_ALIVE_BASE + 0x4618))
#define DISABLE_PLL_CMU_G3D_DURATION3				((void *)(PMU_ALIVE_BASE + 0x461C))
#define DISABLE_PLL_CMU_DISPAUD_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x4620))
#define DISABLE_PLL_CMU_DISPAUD_STATUS				((void *)(PMU_ALIVE_BASE + 0x4624))
#define DISABLE_PLL_CMU_DISPAUD_OPTION				((void *)(PMU_ALIVE_BASE + 0x4628))
#define DISABLE_PLL_CMU_DISPAUD_DURATION0			((void *)(PMU_ALIVE_BASE + 0x4630))
#define DISABLE_PLL_CMU_DISPAUD_DURATION1			((void *)(PMU_ALIVE_BASE + 0x4634))
#define DISABLE_PLL_CMU_DISPAUD_DURATION2			((void *)(PMU_ALIVE_BASE + 0x4638))
#define DISABLE_PLL_CMU_DISPAUD_DURATION3			((void *)(PMU_ALIVE_BASE + 0x463C))
#define DISABLE_PLL_CMU_ISP_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x4640))
#define DISABLE_PLL_CMU_ISP_STATUS				((void *)(PMU_ALIVE_BASE + 0x4644))
#define DISABLE_PLL_CMU_ISP_OPTION				((void *)(PMU_ALIVE_BASE + 0x4648))
#define DISABLE_PLL_CMU_ISP_DURATION0				((void *)(PMU_ALIVE_BASE + 0x4650))
#define DISABLE_PLL_CMU_ISP_DURATION1				((void *)(PMU_ALIVE_BASE + 0x4654))
#define DISABLE_PLL_CMU_ISP_DURATION2				((void *)(PMU_ALIVE_BASE + 0x4658))
#define DISABLE_PLL_CMU_ISP_DURATION3				((void *)(PMU_ALIVE_BASE + 0x465C))
#define DISABLE_PLL_CMU_MFCMSCL_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x4660))
#define DISABLE_PLL_CMU_MFCMSCL_STATUS				((void *)(PMU_ALIVE_BASE + 0x4664))
#define DISABLE_PLL_CMU_MFCMSCL_OPTION				((void *)(PMU_ALIVE_BASE + 0x4668))
#define DISABLE_PLL_CMU_MFCMSCL_DURATION0			((void *)(PMU_ALIVE_BASE + 0x4670))
#define DISABLE_PLL_CMU_MFCMSCL_DURATION1			((void *)(PMU_ALIVE_BASE + 0x4674))
#define DISABLE_PLL_CMU_MFCMSCL_DURATION2			((void *)(PMU_ALIVE_BASE + 0x4678))
#define DISABLE_PLL_CMU_MFCMSCL_DURATION3			((void *)(PMU_ALIVE_BASE + 0x467C))
#define RESET_LOGIC_G3D_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x4800))
#define RESET_LOGIC_G3D_STATUS					((void *)(PMU_ALIVE_BASE + 0x4804))
#define RESET_LOGIC_G3D_OPTION					((void *)(PMU_ALIVE_BASE + 0x4808))
#define RESET_LOGIC_G3D_DURATION0				((void *)(PMU_ALIVE_BASE + 0x4810))
#define RESET_LOGIC_G3D_DURATION1				((void *)(PMU_ALIVE_BASE + 0x4814))
#define RESET_LOGIC_G3D_DURATION2				((void *)(PMU_ALIVE_BASE + 0x4818))
#define RESET_LOGIC_G3D_DURATION3				((void *)(PMU_ALIVE_BASE + 0x481C))
#define RESET_LOGIC_DISPAUD_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x4820))
#define RESET_LOGIC_DISPAUD_STATUS				((void *)(PMU_ALIVE_BASE + 0x4824))
#define RESET_LOGIC_DISPAUD_OPTION				((void *)(PMU_ALIVE_BASE + 0x4828))
#define RESET_LOGIC_DISPAUD_DURATION0				((void *)(PMU_ALIVE_BASE + 0x4830))
#define RESET_LOGIC_DISPAUD_DURATION1				((void *)(PMU_ALIVE_BASE + 0x4834))
#define RESET_LOGIC_DISPAUD_DURATION2				((void *)(PMU_ALIVE_BASE + 0x4838))
#define RESET_LOGIC_DISPAUD_DURATION3				((void *)(PMU_ALIVE_BASE + 0x483C))
#define RESET_LOGIC_ISP_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x4840))
#define RESET_LOGIC_ISP_STATUS					((void *)(PMU_ALIVE_BASE + 0x4844))
#define RESET_LOGIC_ISP_OPTION					((void *)(PMU_ALIVE_BASE + 0x4848))
#define RESET_LOGIC_ISP_DURATION0				((void *)(PMU_ALIVE_BASE + 0x4850))
#define RESET_LOGIC_ISP_DURATION1				((void *)(PMU_ALIVE_BASE + 0x4854))
#define RESET_LOGIC_ISP_DURATION2				((void *)(PMU_ALIVE_BASE + 0x4858))
#define RESET_LOGIC_ISP_DURATION3				((void *)(PMU_ALIVE_BASE + 0x485C))
#define RESET_LOGIC_MFCMSCL_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x4860))
#define RESET_LOGIC_MFCMSCL_STATUS				((void *)(PMU_ALIVE_BASE + 0x4864))
#define RESET_LOGIC_MFCMSCL_OPTION				((void *)(PMU_ALIVE_BASE + 0x4868))
#define RESET_LOGIC_MFCMSCL_DURATION0				((void *)(PMU_ALIVE_BASE + 0x4870))
#define RESET_LOGIC_MFCMSCL_DURATION1				((void *)(PMU_ALIVE_BASE + 0x4874))
#define RESET_LOGIC_MFCMSCL_DURATION2				((void *)(PMU_ALIVE_BASE + 0x4878))
#define RESET_LOGIC_MFCMSCL_DURATION3				((void *)(PMU_ALIVE_BASE + 0x487C))
#define MEMORY_G3D_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x4A00))
#define MEMORY_G3D_STATUS					((void *)(PMU_ALIVE_BASE + 0x4A04))
#define MEMORY_G3D_OPTION					((void *)(PMU_ALIVE_BASE + 0x4A08))
#define MEMORY_G3D_DURATION0					((void *)(PMU_ALIVE_BASE + 0x4A10))
#define MEMORY_G3D_DURATION1					((void *)(PMU_ALIVE_BASE + 0x4A14))
#define MEMORY_G3D_DURATION2					((void *)(PMU_ALIVE_BASE + 0x4A18))
#define MEMORY_G3D_DURATION3					((void *)(PMU_ALIVE_BASE + 0x4A1C))
#define MEMORY_DISPAUD_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x4A20))
#define MEMORY_DISPAUD_STATUS					((void *)(PMU_ALIVE_BASE + 0x4A24))
#define MEMORY_DISPAUD_OPTION					((void *)(PMU_ALIVE_BASE + 0x4A28))
#define MEMORY_DISPAUD_DURATION0				((void *)(PMU_ALIVE_BASE + 0x4A30))
#define MEMORY_DISPAUD_DURATION1				((void *)(PMU_ALIVE_BASE + 0x4A34))
#define MEMORY_DISPAUD_DURATION2				((void *)(PMU_ALIVE_BASE + 0x4A38))
#define MEMORY_DISPAUD_DURATION3				((void *)(PMU_ALIVE_BASE + 0x4A3C))
#define MEMORY_ISP_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x4A40))
#define MEMORY_ISP_STATUS					((void *)(PMU_ALIVE_BASE + 0x4A44))
#define MEMORY_ISP_OPTION					((void *)(PMU_ALIVE_BASE + 0x4A48))
#define MEMORY_ISP_DURATION0					((void *)(PMU_ALIVE_BASE + 0x4A50))
#define MEMORY_ISP_DURATION1					((void *)(PMU_ALIVE_BASE + 0x4A54))
#define MEMORY_ISP_DURATION2					((void *)(PMU_ALIVE_BASE + 0x4A58))
#define MEMORY_ISP_DURATION3					((void *)(PMU_ALIVE_BASE + 0x4A5C))
#define MEMORY_MFCMSCL_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x4A60))
#define MEMORY_MFCMSCL_STATUS					((void *)(PMU_ALIVE_BASE + 0x4A64))
#define MEMORY_MFCMSCL_OPTION					((void *)(PMU_ALIVE_BASE + 0x4A68))
#define MEMORY_MFCMSCL_DURATION0				((void *)(PMU_ALIVE_BASE + 0x4A70))
#define MEMORY_MFCMSCL_DURATION1				((void *)(PMU_ALIVE_BASE + 0x4A74))
#define MEMORY_MFCMSCL_DURATION2				((void *)(PMU_ALIVE_BASE + 0x4A78))
#define MEMORY_MFCMSCL_DURATION3				((void *)(PMU_ALIVE_BASE + 0x4A7C))
#define RESET_CMU_G3D_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x4C00))
#define RESET_CMU_G3D_STATUS					((void *)(PMU_ALIVE_BASE + 0x4C04))
#define RESET_CMU_G3D_OPTION					((void *)(PMU_ALIVE_BASE + 0x4C08))
#define RESET_CMU_G3D_DURATION0					((void *)(PMU_ALIVE_BASE + 0x4C10))
#define RESET_CMU_G3D_DURATION1					((void *)(PMU_ALIVE_BASE + 0x4C14))
#define RESET_CMU_G3D_DURATION2					((void *)(PMU_ALIVE_BASE + 0x4C18))
#define RESET_CMU_G3D_DURATION3					((void *)(PMU_ALIVE_BASE + 0x4C1C))
#define RESET_CMU_DISPAUD_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x4C20))
#define RESET_CMU_DISPAUD_STATUS				((void *)(PMU_ALIVE_BASE + 0x4C24))
#define RESET_CMU_DISPAUD_OPTION				((void *)(PMU_ALIVE_BASE + 0x4C28))
#define RESET_CMU_DISPAUD_DURATION0				((void *)(PMU_ALIVE_BASE + 0x4C30))
#define RESET_CMU_DISPAUD_DURATION1				((void *)(PMU_ALIVE_BASE + 0x4C34))
#define RESET_CMU_DISPAUD_DURATION2				((void *)(PMU_ALIVE_BASE + 0x4C38))
#define RESET_CMU_DISPAUD_DURATION3				((void *)(PMU_ALIVE_BASE + 0x4C3C))
#define RESET_CMU_ISP_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x4C40))
#define RESET_CMU_ISP_STATUS					((void *)(PMU_ALIVE_BASE + 0x4C44))
#define RESET_CMU_ISP_OPTION					((void *)(PMU_ALIVE_BASE + 0x4C48))
#define RESET_CMU_ISP_DURATION0					((void *)(PMU_ALIVE_BASE + 0x4C50))
#define RESET_CMU_ISP_DURATION1					((void *)(PMU_ALIVE_BASE + 0x4C54))
#define RESET_CMU_ISP_DURATION2					((void *)(PMU_ALIVE_BASE + 0x4C58))
#define RESET_CMU_ISP_DURATION3					((void *)(PMU_ALIVE_BASE + 0x4C5C))
#define RESET_CMU_MFCMSCL_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x4C60))
#define RESET_CMU_MFCMSCL_STATUS				((void *)(PMU_ALIVE_BASE + 0x4C64))
#define RESET_CMU_MFCMSCL_OPTION				((void *)(PMU_ALIVE_BASE + 0x4C68))
#define RESET_CMU_MFCMSCL_DURATION0				((void *)(PMU_ALIVE_BASE + 0x4C70))
#define RESET_CMU_MFCMSCL_DURATION1				((void *)(PMU_ALIVE_BASE + 0x4C74))
#define RESET_CMU_MFCMSCL_DURATION2				((void *)(PMU_ALIVE_BASE + 0x4C78))
#define RESET_CMU_MFCMSCL_DURATION3				((void *)(PMU_ALIVE_BASE + 0x4C7C))
#define SYSTEM_INFO						((void *)(PMU_ALIVE_BASE + 0x5008))
#define RESET_AHEAD_WIFI_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x5020))
#define RESET_AHEAD_WIFI_STATUS					((void *)(PMU_ALIVE_BASE + 0x5024))
#define RESET_AHEAD_WIFI_OPTION					((void *)(PMU_ALIVE_BASE + 0x5028))
#define RESET_AHEAD_WIFI_DURATION0				((void *)(PMU_ALIVE_BASE + 0x5030))
#define RESET_AHEAD_WIFI_DURATION1				((void *)(PMU_ALIVE_BASE + 0x5034))
#define RESET_AHEAD_WIFI_DURATION2				((void *)(PMU_ALIVE_BASE + 0x5038))
#define RESET_AHEAD_WIFI_DURATION3				((void *)(PMU_ALIVE_BASE + 0x503C))
#define CLEANY_BUS_WIFI_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x5040))
#define CLEANY_BUS_WIFI_STATUS					((void *)(PMU_ALIVE_BASE + 0x5044))
#define CLEANY_BUS_WIFI_OPTION					((void *)(PMU_ALIVE_BASE + 0x5048))
#define CLEANY_BUS_WIFI_DURATION0				((void *)(PMU_ALIVE_BASE + 0x5050))
#define CLEANY_BUS_WIFI_DURATION1				((void *)(PMU_ALIVE_BASE + 0x5054))
#define CLEANY_BUS_WIFI_DURATION2				((void *)(PMU_ALIVE_BASE + 0x5058))
#define CLEANY_BUS_WIFI_DURATION3				((void *)(PMU_ALIVE_BASE + 0x505C))
#define LOGIC_RESET_WIFI_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x5060))
#define LOGIC_RESET_WIFI_STATUS					((void *)(PMU_ALIVE_BASE + 0x5064))
#define LOGIC_RESET_WIFI_OPTION					((void *)(PMU_ALIVE_BASE + 0x5068))
#define LOGIC_RESET_WIFI_DURATION0				((void *)(PMU_ALIVE_BASE + 0x5070))
#define LOGIC_RESET_WIFI_DURATION1				((void *)(PMU_ALIVE_BASE + 0x5074))
#define LOGIC_RESET_WIFI_DURATION2				((void *)(PMU_ALIVE_BASE + 0x5078))
#define LOGIC_RESET_WIFI_DURATION3				((void *)(PMU_ALIVE_BASE + 0x507C))
#define TCXO_GATE_WIFI_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x5080))
#define TCXO_GATE_WIFI_STATUS					((void *)(PMU_ALIVE_BASE + 0x5084))
#define TCXO_GATE_WIFI_OPTION					((void *)(PMU_ALIVE_BASE + 0x5088))
#define TCXO_GATE_WIFI_DURATION0				((void *)(PMU_ALIVE_BASE + 0x5090))
#define TCXO_GATE_WIFI_DURATION1				((void *)(PMU_ALIVE_BASE + 0x5094))
#define TCXO_GATE_WIFI_DURATION2				((void *)(PMU_ALIVE_BASE + 0x5098))
#define TCXO_GATE_WIFI_DURATION3				((void *)(PMU_ALIVE_BASE + 0x509C))
#define RESET_ASB_WIFI_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x50A0))
#define RESET_ASB_WIFI_STATUS					((void *)(PMU_ALIVE_BASE + 0x50A4))
#define RESET_ASB_WIFI_OPTION					((void *)(PMU_ALIVE_BASE + 0x50A8))
#define RESET_ASB_WIFI_DURATION0				((void *)(PMU_ALIVE_BASE + 0x50B0))
#define RESET_ASB_WIFI_DURATION1				((void *)(PMU_ALIVE_BASE + 0x50B4))
#define RESET_ASB_WIFI_DURATION2				((void *)(PMU_ALIVE_BASE + 0x50B8))
#define RESET_ASB_WIFI_DURATION3				((void *)(PMU_ALIVE_BASE + 0x50BC))
#define RESET_ASB_MIF_WIFI_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x50C0))
#define RESET_ASB_MIF_WIFI_STATUS				((void *)(PMU_ALIVE_BASE + 0x50C4))
#define RESET_ASB_MIF_WIFI_OPTION				((void *)(PMU_ALIVE_BASE + 0x50C8))
#define RESET_ASB_MIF_WIFI_DURATION0				((void *)(PMU_ALIVE_BASE + 0x50D0))
#define RESET_ASB_MIF_WIFI_DURATION1				((void *)(PMU_ALIVE_BASE + 0x50D4))
#define RESET_ASB_MIF_WIFI_DURATION2				((void *)(PMU_ALIVE_BASE + 0x50D8))
#define RESET_ASB_MIF_WIFI_DURATION3				((void *)(PMU_ALIVE_BASE + 0x50DC))
#define JTAG_DBG_DET						((void *)(PMU_ALIVE_BASE + 0x6000))
#define CPUCL0_CORERST_LOCK					((void *)(PMU_ALIVE_BASE + 0x6004))
#define CPUCL1_CORERST_LOCK					((void *)(PMU_ALIVE_BASE + 0x6008))
#define NFC_CLK_CTRL						((void *)(PMU_ALIVE_BASE + 0x600C))
#define GPU_DVS_CTRL						((void *)(PMU_ALIVE_BASE + 0x6100))
#define GPU_DVS_STATUS						((void *)(PMU_ALIVE_BASE + 0x6104))
#define GPU_DVS_COUNTER						((void *)(PMU_ALIVE_BASE + 0x6108))
#define GPU_DVS_CLK_CTRL					((void *)(PMU_ALIVE_BASE + 0x610C))
#define UART_IO_SHARE_CTRL					((void *)(PMU_ALIVE_BASE + 0x6200))
#define CP_DVS_CTRL						((void *)(PMU_ALIVE_BASE + 0x6300))
#define CP_DVS_STATUS						((void *)(PMU_ALIVE_BASE + 0x6304))
#define CP_DVS_COUNTER						((void *)(PMU_ALIVE_BASE + 0x6308))
#define AP_DVS_CTRL						((void *)(PMU_ALIVE_BASE + 0x6400))
#define MIF_TZPC_CONFIG0					((void *)(PMU_ALIVE_BASE + 0x6500))
#define MIF_TZPC_CONFIG1					((void *)(PMU_ALIVE_BASE + 0x6504))
#define APM_TZPC_CONFIG						((void *)(PMU_ALIVE_BASE + 0x6508))
#define IRQ_SELECTION						((void *)(PMU_ALIVE_BASE + 0x6800))
#define SIGNAL_TO_DATA_CONV					((void *)(PMU_ALIVE_BASE + 0x6820))
#define DEK0							((void *)(PMU_ALIVE_BASE + 0x7000))
#define DEK1							((void *)(PMU_ALIVE_BASE + 0x7004))
#define DEK2							((void *)(PMU_ALIVE_BASE + 0x7008))
#define DEK3							((void *)(PMU_ALIVE_BASE + 0x700C))
#define DEK4							((void *)(PMU_ALIVE_BASE + 0x7010))
#define DEK5							((void *)(PMU_ALIVE_BASE + 0x7014))
#define DEK6							((void *)(PMU_ALIVE_BASE + 0x7018))
#define DEK7							((void *)(PMU_ALIVE_BASE + 0x701C))
#define DEK8							((void *)(PMU_ALIVE_BASE + 0x7020))
#define DEK9							((void *)(PMU_ALIVE_BASE + 0x7024))
#define DEK10							((void *)(PMU_ALIVE_BASE + 0x7028))
#define DEK11							((void *)(PMU_ALIVE_BASE + 0x702C))
#define DEK12							((void *)(PMU_ALIVE_BASE + 0x7030))
#define DEK13							((void *)(PMU_ALIVE_BASE + 0x7034))
#define DEK14							((void *)(PMU_ALIVE_BASE + 0x7038))
#define DEK15							((void *)(PMU_ALIVE_BASE + 0x703C))
#define EXT_MEMCFG0						((void *)(PMU_ALIVE_BASE + 0x7100))
#define EXT_MEMCFG1						((void *)(PMU_ALIVE_BASE + 0x7104))
#define EXT_MEMCFG2						((void *)(PMU_ALIVE_BASE + 0x7108))
#define INTMEM_CFG						((void *)(PMU_ALIVE_BASE + 0x710C))
#define EXT_REGULATOR_SHARED_CONFIGURATION		((void *)(PMU_ALIVE_BASE + 0x7800))
#define EXT_REGULATOR_SHARED_STATUS				((void *)(PMU_ALIVE_BASE + 0x7804))
#define EXT_REGULATOR_SHARED_OPTION				((void *)(PMU_ALIVE_BASE + 0x7808))
#define EXT_REGULATOR_SHARED_DURATION1				((void *)(PMU_ALIVE_BASE + 0x7814))
#define EXT_REGULATOR_SHARED_DURATION2				((void *)(PMU_ALIVE_BASE + 0x7818))
#define EXT_REGULATOR_SHARED_DURATION3				((void *)(PMU_ALIVE_BASE + 0x781C))
#define TCXO_SHARED_CONFIGURATION					((void *)(PMU_ALIVE_BASE + 0x7820))
#define TCXO_SHARED_STATUS					((void *)(PMU_ALIVE_BASE + 0x7824))
#define TCXO_SHARED_OPTION					((void *)(PMU_ALIVE_BASE + 0x7828))
#define TCXO_SHARED_DURATION0					((void *)(PMU_ALIVE_BASE + 0x7830))
#define TCXO_SHARED_DURATION1					((void *)(PMU_ALIVE_BASE + 0x7834))
#define TCXO_SHARED_DURATION2					((void *)(PMU_ALIVE_BASE + 0x7838))
#define TCXO_SHARED_DURATION3					((void *)(PMU_ALIVE_BASE + 0x783C))
#define CENTRAL_SEQ_APM_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x8000))
#define CENTRAL_SEQ_APM_STATUS					((void *)(PMU_ALIVE_BASE + 0x8004))
#define CENTRAL_SEQ_APM_OPTION					((void *)(PMU_ALIVE_BASE + 0x8008))
#define CENTRAL_SEQ_APM_DURATION0				((void *)(PMU_ALIVE_BASE + 0x8010))
#define CENTRAL_SEQ_APM_DURATION1				((void *)(PMU_ALIVE_BASE + 0x8014))
#define CENTRAL_SEQ_APM_DURATION2				((void *)(PMU_ALIVE_BASE + 0x8018))
#define CENTRAL_SEQ_APM_DURATION3				((void *)(PMU_ALIVE_BASE + 0x801C))
#define SEQ_APM_TRANSITION0					((void *)(PMU_ALIVE_BASE + 0x8020))
#define SEQ_APM_TRANSITION1					((void *)(PMU_ALIVE_BASE + 0x8024))
#define SEQ_APM_TRANSITION2					((void *)(PMU_ALIVE_BASE + 0x8028))
#define SEQ_APM_TRANSITION3					((void *)(PMU_ALIVE_BASE + 0x802C))
#define SEQ_APM_TRANSITION4					((void *)(PMU_ALIVE_BASE + 0x8030))
#define SEQ_APM_TRANSITION5					((void *)(PMU_ALIVE_BASE + 0x8034))
#define SEQ_APM_TRANSITION6					((void *)(PMU_ALIVE_BASE + 0x8038))
#define SEQ_APM_TRANSITION7					((void *)(PMU_ALIVE_BASE + 0x803C))
#define SEQ_APM_TRANSITION8					((void *)(PMU_ALIVE_BASE + 0x8040))
#define SEQ_APM_TRANSITION9					((void *)(PMU_ALIVE_BASE + 0x8044))
#define SEQ_APM_TRANSITION10					((void *)(PMU_ALIVE_BASE + 0x8048))
#define SEQ_APM_TRANSITION11					((void *)(PMU_ALIVE_BASE + 0x804C))
#define SEQ_APM_TRANSITION12					((void *)(PMU_ALIVE_BASE + 0x8050))
#define SEQ_APM_TRANSITION13					((void *)(PMU_ALIVE_BASE + 0x8054))
#define SEQ_APM_TRANSITION14					((void *)(PMU_ALIVE_BASE + 0x8058))
#define SEQ_APM_TRANSITION15					((void *)(PMU_ALIVE_BASE + 0x805C))
#define CORTEXM0_APM_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x8080))
#define CLKRUN_CMU_APM_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x8084))
#define TOP_BUS_APM_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x8088))
#define CLKSTOP_CMU_APM_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x808C))
#define CLKSTOP_OPEN_CMU_APM_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x8090))
#define DISABLE_PLL_CMU_APM_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x8094))
#define TOP_RETENTION_APM_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x8098))
#define OSCCLK_GATE_APM_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x80A0))
#define MEMORY_APM_TOP_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x80A4))
#define LOGIC_RESET_APM_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x80A8))
#define SLEEP_RESET_APM_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x80AC))
#define RETENTION_CMU_APM_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x80B0))
#define RESET_CMU_APM_SYS_PWR_REG				((void *)(PMU_ALIVE_BASE + 0x80B4))
#define TOP_PWR_APM_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x80B8))
#define TCXO_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x80BC))
#define PAD_RETENTION_PEDOMETER_APM_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x80C0))
#define CORTEXM0_APM_RESET					((void *)(PMU_ALIVE_BASE + 0x80F0))
#define CORTEXM0_APM_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x8100))
#define CORTEXM0_APM_STATUS					((void *)(PMU_ALIVE_BASE + 0x8104))
#define CORTEXM0_APM_OPTION					((void *)(PMU_ALIVE_BASE + 0x8108))
#define CORTEXM0_APM_DURATION0					((void *)(PMU_ALIVE_BASE + 0x8110))
#define CORTEXM0_APM_DURATION1					((void *)(PMU_ALIVE_BASE + 0x8114))
#define CORTEXM0_APM_DURATION2					((void *)(PMU_ALIVE_BASE + 0x8118))
#define CORTEXM0_APM_DURATION3					((void *)(PMU_ALIVE_BASE + 0x811C))
#define CLKRUN_CMU_APM_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x8120))
#define CLKRUN_CMU_APM_STATUS					((void *)(PMU_ALIVE_BASE + 0x8124))
#define CLKRUN_CMU_APM_OPTION					((void *)(PMU_ALIVE_BASE + 0x8128))
#define CLKRUN_CMU_APM_DURATION0				((void *)(PMU_ALIVE_BASE + 0x8130))
#define CLKRUN_CMU_APM_DURATION1				((void *)(PMU_ALIVE_BASE + 0x8134))
#define CLKRUN_CMU_APM_DURATION2				((void *)(PMU_ALIVE_BASE + 0x8138))
#define CLKRUN_CMU_APM_DURATION3				((void *)(PMU_ALIVE_BASE + 0x813C))
#define TOP_BUS_APM_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x8140))
#define TOP_BUS_APM_STATUS					((void *)(PMU_ALIVE_BASE + 0x8144))
#define TOP_BUS_APM_OPTION					((void *)(PMU_ALIVE_BASE + 0x8148))
#define TOP_BUS_APM_DURATION0					((void *)(PMU_ALIVE_BASE + 0x8150))
#define TOP_BUS_APM_DURATION1					((void *)(PMU_ALIVE_BASE + 0x8154))
#define TOP_BUS_APM_DURATION2					((void *)(PMU_ALIVE_BASE + 0x8158))
#define TOP_BUS_APM_DURATION3					((void *)(PMU_ALIVE_BASE + 0x815C))
#define CLKSTOP_CMU_APM_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x8160))
#define CLKSTOP_CMU_APM_STATUS					((void *)(PMU_ALIVE_BASE + 0x8164))
#define CLKSTOP_CMU_APM_OPTION					((void *)(PMU_ALIVE_BASE + 0x8168))
#define CLKSTOP_CMU_APM_DURATION0				((void *)(PMU_ALIVE_BASE + 0x8170))
#define CLKSTOP_CMU_APM_DURATION1				((void *)(PMU_ALIVE_BASE + 0x8174))
#define CLKSTOP_CMU_APM_DURATION2				((void *)(PMU_ALIVE_BASE + 0x8178))
#define CLKSTOP_CMU_APM_DURATION3				((void *)(PMU_ALIVE_BASE + 0x817C))
#define CLKSTOP_OPEN_CMU_APM_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x8180))
#define CLKSTOP_OPEN_CMU_APM_STATUS				((void *)(PMU_ALIVE_BASE + 0x8184))
#define CLKSTOP_OPEN_CMU_APM_OPTION				((void *)(PMU_ALIVE_BASE + 0x8188))
#define CLKSTOP_OPEN_CMU_APM_DURATION0				((void *)(PMU_ALIVE_BASE + 0x8190))
#define CLKSTOP_OPEN_CMU_APM_DURATION1				((void *)(PMU_ALIVE_BASE + 0x8194))
#define CLKSTOP_OPEN_CMU_APM_DURATION2				((void *)(PMU_ALIVE_BASE + 0x8198))
#define CLKSTOP_OPEN_CMU_APM_DURATION3				((void *)(PMU_ALIVE_BASE + 0x819C))
#define DISABLE_PLL_CMU_APM_CONFIGURATION			((void *)(PMU_ALIVE_BASE + 0x81A0))
#define DISABLE_PLL_CMU_APM_STATUS				((void *)(PMU_ALIVE_BASE + 0x81A4))
#define DISABLE_PLL_CMU_APM_OPTION				((void *)(PMU_ALIVE_BASE + 0x81A8))
#define DISABLE_PLL_CMU_APM_DURATION0				((void *)(PMU_ALIVE_BASE + 0x81B0))
#define DISABLE_PLL_CMU_APM_DURATION1				((void *)(PMU_ALIVE_BASE + 0x81B4))
#define DISABLE_PLL_CMU_APM_DURATION2				((void *)(PMU_ALIVE_BASE + 0x81B8))
#define DISABLE_PLL_CMU_APM_DURATION3				((void *)(PMU_ALIVE_BASE + 0x81BC))
#define TOP_RETENTION_APM_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x81C0))
#define TOP_RETENTION_APM_STATUS				((void *)(PMU_ALIVE_BASE + 0x81C4))
#define TOP_RETENTION_APM_OPTION				((void *)(PMU_ALIVE_BASE + 0x81C8))
#define TOP_RETENTION_APM_DURATION0				((void *)(PMU_ALIVE_BASE + 0x81D0))
#define TOP_RETENTION_APM_DURATION1				((void *)(PMU_ALIVE_BASE + 0x81D4))
#define TOP_RETENTION_APM_DURATION2				((void *)(PMU_ALIVE_BASE + 0x81D8))
#define TOP_RETENTION_APM_DURATION3				((void *)(PMU_ALIVE_BASE + 0x81DC))
#define OSCCLK_GATE_APM_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x8200))
#define OSCCLK_GATE_APM_STATUS					((void *)(PMU_ALIVE_BASE + 0x8204))
#define OSCCLK_GATE_APM_OPTION					((void *)(PMU_ALIVE_BASE + 0x8208))
#define OSCCLK_GATE_APM_DURATION0				((void *)(PMU_ALIVE_BASE + 0x8210))
#define OSCCLK_GATE_APM_DURATION1				((void *)(PMU_ALIVE_BASE + 0x8214))
#define OSCCLK_GATE_APM_DURATION2				((void *)(PMU_ALIVE_BASE + 0x8218))
#define OSCCLK_GATE_APM_DURATION3				((void *)(PMU_ALIVE_BASE + 0x821C))
#define MEMORY_APM_TOP_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x8220))
#define MEMORY_APM_TOP_STATUS					((void *)(PMU_ALIVE_BASE + 0x8224))
#define MEMORY_APM_TOP_OPTION					((void *)(PMU_ALIVE_BASE + 0x8228))
#define MEMORY_APM_TOP_DURATION0				((void *)(PMU_ALIVE_BASE + 0x8230))
#define MEMORY_APM_TOP_DURATION1				((void *)(PMU_ALIVE_BASE + 0x8234))
#define MEMORY_APM_TOP_DURATION2				((void *)(PMU_ALIVE_BASE + 0x8238))
#define MEMORY_APM_TOP_DURATION3				((void *)(PMU_ALIVE_BASE + 0x823C))
#define LOGIC_RESET_APM_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x8240))
#define LOGIC_RESET_APM_STATUS					((void *)(PMU_ALIVE_BASE + 0x8244))
#define LOGIC_RESET_APM_OPTION					((void *)(PMU_ALIVE_BASE + 0x8248))
#define LOGIC_RESET_APM_DURATION0				((void *)(PMU_ALIVE_BASE + 0x8250))
#define LOGIC_RESET_APM_DURATION1				((void *)(PMU_ALIVE_BASE + 0x8254))
#define LOGIC_RESET_APM_DURATION2				((void *)(PMU_ALIVE_BASE + 0x8258))
#define LOGIC_RESET_APM_DURATION3				((void *)(PMU_ALIVE_BASE + 0x825C))
#define SLEEP_RESET_APM_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x8260))
#define SLEEP_RESET_APM_STATUS					((void *)(PMU_ALIVE_BASE + 0x8264))
#define SLEEP_RESET_APM_OPTION					((void *)(PMU_ALIVE_BASE + 0x8268))
#define SLEEP_RESET_APM_DURATION0				((void *)(PMU_ALIVE_BASE + 0x8270))
#define SLEEP_RESET_APM_DURATION1				((void *)(PMU_ALIVE_BASE + 0x8274))
#define SLEEP_RESET_APM_DURATION2				((void *)(PMU_ALIVE_BASE + 0x8278))
#define SLEEP_RESET_APM_DURATION3				((void *)(PMU_ALIVE_BASE + 0x827C))
#define RETENTION_CMU_APM_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x8280))
#define RETENTION_CMU_APM_STATUS				((void *)(PMU_ALIVE_BASE + 0x8284))
#define RETENTION_CMU_APM_OPTION				((void *)(PMU_ALIVE_BASE + 0x8288))
#define RETENTION_CMU_APM_DURATION0				((void *)(PMU_ALIVE_BASE + 0x8290))
#define RETENTION_CMU_APM_DURATION1				((void *)(PMU_ALIVE_BASE + 0x8294))
#define RETENTION_CMU_APM_DURATION2				((void *)(PMU_ALIVE_BASE + 0x8298))
#define RETENTION_CMU_APM_DURATION3				((void *)(PMU_ALIVE_BASE + 0x829C))
#define RESET_CMU_APM_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x82A0))
#define RESET_CMU_APM_STATUS					((void *)(PMU_ALIVE_BASE + 0x82A4))
#define RESET_CMU_APM_OPTION					((void *)(PMU_ALIVE_BASE + 0x82A8))
#define RESET_CMU_APM_DURATION0					((void *)(PMU_ALIVE_BASE + 0x82B0))
#define RESET_CMU_APM_DURATION1					((void *)(PMU_ALIVE_BASE + 0x82B4))
#define RESET_CMU_APM_DURATION2					((void *)(PMU_ALIVE_BASE + 0x82B8))
#define RESET_CMU_APM_DURATION3					((void *)(PMU_ALIVE_BASE + 0x82BC))
#define TOP_PWR_APM_CONFIGURATION				((void *)(PMU_ALIVE_BASE + 0x82C0))
#define TOP_PWR_APM_STATUS					((void *)(PMU_ALIVE_BASE + 0x82C4))
#define TOP_PWR_APM_OPTION					((void *)(PMU_ALIVE_BASE + 0x82C8))
#define TOP_PWR_APM_DURATION0					((void *)(PMU_ALIVE_BASE + 0x82D0))
#define TOP_PWR_APM_DURATION1					((void *)(PMU_ALIVE_BASE + 0x82D4))
#define TOP_PWR_APM_DURATION2					((void *)(PMU_ALIVE_BASE + 0x82D8))
#define TOP_PWR_APM_DURATION3					((void *)(PMU_ALIVE_BASE + 0x82DC))
#define TCXO_CONFIGURATION					((void *)(PMU_ALIVE_BASE + 0x8300))
#define TCXO_STATUS						((void *)(PMU_ALIVE_BASE + 0x8304))
#define TCXO_OPTION						((void *)(PMU_ALIVE_BASE + 0x8308))
#define TCXO_DURATION0						((void *)(PMU_ALIVE_BASE + 0x8310))
#define TCXO_DURATION1						((void *)(PMU_ALIVE_BASE + 0x8314))
#define TCXO_DURATION2						((void *)(PMU_ALIVE_BASE + 0x8318))
#define PAD_RETENTION_PEDOMETER_APM_CONFIGURATION		((void *)(PMU_ALIVE_BASE + 0x8320))
#define PAD_RETENTION_PEDOMETER_APM_STATUS			((void *)(PMU_ALIVE_BASE + 0x8324))
#define PAD_RETENTION_PEDOMETER_APM_OPTION			((void *)(PMU_ALIVE_BASE + 0x8328))
#define PAD_RETENTION_PEDOMETER_APM_DURATION0			((void *)(PMU_ALIVE_BASE + 0x8330))
#define PAD_RETENTION_PEDOMETER_APM_DURATION1			((void *)(PMU_ALIVE_BASE + 0x8334))
#define PAD_RETENTION_PEDOMETER_APM_DURATION2			((void *)(PMU_ALIVE_BASE + 0x8338))
#define WAKEUP_MASK_APM						((void *)(PMU_ALIVE_BASE + 0x8400))
#define WAKEUP_STAT_APM						((void *)(PMU_ALIVE_BASE + 0x8404))
#define WAKEUP_INTERRUPT_APM					((void *)(PMU_ALIVE_BASE + 0x8420))
#define APM_MEM_CONFIG0						((void *)(PMU_ALIVE_BASE + 0x8600))
#define APM_MEM_CONFIG1						((void *)(PMU_ALIVE_BASE + 0x8604))
#define APM_MEM_CONFIG2						((void *)(PMU_ALIVE_BASE + 0x8608))
#define APM_MEM_CONFIG3						((void *)(PMU_ALIVE_BASE + 0x860C))
#define APM_MIF_ACCESS_WIN0					((void *)(PMU_ALIVE_BASE + 0x8610))
#define APM_MIF_ACCESS_WIN1					((void *)(PMU_ALIVE_BASE + 0x8614))
#define APM_MIF_ACCESS_WIN2					((void *)(PMU_ALIVE_BASE + 0x8618))
#define APM_MIF_ACCESS_WIN3					((void *)(PMU_ALIVE_BASE + 0x861C))

#define LPI_MASK_APM_ASB					((void *)(PMU_APM_BASE + 0x0020))
#define LPI_DENIAL_MASK_APM_ASB					((void *)(PMU_APM_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_APM_ASB				((void *)(PMU_APM_BASE + 0x0220))
#define LPI_STATUS_APM_ASB					((void *)(PMU_APM_BASE + 0x0320))

#define LPI_MASK_CPUCL0_ASB					((void *)(PMU_CPUCL0_BASE + 0x0020))
#define LPI_DENIAL_MASK_CPUCL0_ASB				((void *)(PMU_CPUCL0_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_CPUCL0_ASB			((void *)(PMU_CPUCL0_BASE + 0x0220))
#define LPI_STATUS_CPUCL0_ASB					((void *)(PMU_CPUCL0_BASE + 0x0320))

#define LPI_MASK_DISPAUD_BUSMASTER				((void *)(PMU_DISPAUD_BASE + 0x0000))
#define LPI_MASK_DISPAUD_ASB					((void *)(PMU_DISPAUD_BASE + 0x0020))
#define LPI_DENIAL_MASK_DISPAUD_BUSMASTER			((void *)(PMU_DISPAUD_BASE + 0x0100))
#define LPI_DENIAL_MASK_DISPAUD_ASB				((void *)(PMU_DISPAUD_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_DISPAUD_BUSMASTER			((void *)(PMU_DISPAUD_BASE + 0x0200))
#define LPI_AUTOMATIC_CLKGATE_DISPAUD_ASB			((void *)(PMU_DISPAUD_BASE + 0x0220))
#define LPI_STATUS_DISPAUD_BUSMASTER				((void *)(PMU_DISPAUD_BASE + 0x0300))
#define LPI_STATUS_DISPAUD_ASB					((void *)(PMU_DISPAUD_BASE + 0x0320))

#define LPI_MASK_FSYS_BUSMASTER					((void *)(PMU_FSYS_BASE + 0x0000))
#define LPI_MASK_FSYS_ASB					((void *)(PMU_FSYS_BASE + 0x0020))
#define LPI_DENIAL_MASK_FSYS_BUSMASTER				((void *)(PMU_FSYS_BASE + 0x0100))
#define LPI_DENIAL_MASK_FSYS_ASB				((void *)(PMU_FSYS_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_FSYS_BUSMASTER			((void *)(PMU_FSYS_BASE + 0x0200))
#define LPI_AUTOMATIC_CLKGATE_FSYS_ASB				((void *)(PMU_FSYS_BASE + 0x0220))
#define LPI_STATUS_FSYS_BUSMASTER				((void *)(PMU_FSYS_BASE + 0x0300))
#define LPI_STATUS_FSYS_ASB					((void *)(PMU_FSYS_BASE + 0x0320))

#define LPI_MASK_G3D_ASB					((void *)(PMU_G3D_BASE + 0x0020))
#define LPI_DENIAL_MASK_G3D_ASB					((void *)(PMU_G3D_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_G3D_ASB				((void *)(PMU_G3D_BASE + 0x0220))
#define LPI_STATUS_G3D_ASB					((void *)(PMU_G3D_BASE + 0x0320))

#define PMUREQ							((void *)(PMU_IF_BASE + 0x0000))
#define PMUINT							((void *)(PMU_IF_BASE + 0x0004))
#define PMUMSK							((void *)(PMU_IF_BASE + 0x0008))
#define PMUACK							((void *)(PMU_IF_BASE + 0x000C))

#define LPI_MASK_ISP_BUSMASTER					((void *)(PMU_ISP_BASE + 0x0000))
#define LPI_MASK_ISP_ASB					((void *)(PMU_ISP_BASE + 0x0020))
#define LPI_DENIAL_MASK_ISP_BUSMASTER				((void *)(PMU_ISP_BASE + 0x0100))
#define LPI_DENIAL_MASK_ISP_ASB					((void *)(PMU_ISP_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_ISP_BUSMASTER			((void *)(PMU_ISP_BASE + 0x0200))
#define LPI_AUTOMATIC_CLKGATE_ISP_ASB				((void *)(PMU_ISP_BASE + 0x0220))
#define LPI_STATUS_ISP_BUSMASTER				((void *)(PMU_ISP_BASE + 0x0300))
#define LPI_STATUS_ISP_ASB					((void *)(PMU_ISP_BASE + 0x0320))

#define LPI_MASK_MFCMSCL_BUSMASTER				((void *)(PMU_MFCMSCL_BASE + 0x0000))
#define LPI_MASK_MFCMSCL_ASB					((void *)(PMU_MFCMSCL_BASE + 0x0020))
#define LPI_DENIAL_MASK_MFCMSCL_BUSMASTER			((void *)(PMU_MFCMSCL_BASE + 0x0100))
#define LPI_DENIAL_MASK_MFCMSCL_ASB				((void *)(PMU_MFCMSCL_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_MFCMSCL_BUSMASTER			((void *)(PMU_MFCMSCL_BASE + 0x0200))
#define LPI_AUTOMATIC_CLKGATE_MFCMSCL_ASB			((void *)(PMU_MFCMSCL_BASE + 0x0220))
#define LPI_STATUS_MFCMSCL_BUSMASTER				((void *)(PMU_MFCMSCL_BASE + 0x0300))
#define LPI_STATUS_MFCMSCL_ASB					((void *)(PMU_MFCMSCL_BASE + 0x0320))

#define LPI_MASK_MIF_ASB					((void *)(PMU_MIF_BASE + 0x0020))
#define LPI_MASK_MIF_DRAM					((void *)(PMU_MIF_BASE + 0x0060))
#define LPI_DENIAL_MASK_MIF_ASB					((void *)(PMU_MIF_BASE + 0x0120))
#define LPI_DENIAL_MASK_MIF_DRAM				((void *)(PMU_MIF_BASE + 0x0160))
#define LPI_AUTOMATIC_CLKGATE_MIF_ASB				((void *)(PMU_MIF_BASE + 0x0220))
#define LPI_AUTOMATIC_CLKGATE_MIF_DRAM				((void *)(PMU_MIF_BASE + 0x0260))
#define LPI_STATUS_MIF_ASB					((void *)(PMU_MIF_BASE + 0x0320))
#define LPI_STATUS_MIF_DRAM					((void *)(PMU_MIF_BASE + 0x0360))

#define LPI_MASK_MIF_ASB					((void *)(PMU_MIF_BASE + 0x0020))
#define LPI_MASK_MIF_DRAM					((void *)(PMU_MIF_BASE + 0x0060))
#define LPI_DENIAL_MASK_MIF_ASB					((void *)(PMU_MIF_BASE + 0x0120))
#define LPI_DENIAL_MASK_MIF_DRAM				((void *)(PMU_MIF_BASE + 0x0160))
#define LPI_AUTOMATIC_CLKGATE_MIF_ASB				((void *)(PMU_MIF_BASE + 0x0220))
#define LPI_AUTOMATIC_CLKGATE_MIF_DRAM				((void *)(PMU_MIF_BASE + 0x0260))
#define LPI_STATUS_MIF_ASB					((void *)(PMU_MIF_BASE + 0x0320))
#define LPI_STATUS_MIF_DRAM					((void *)(PMU_MIF_BASE + 0x0360))

#define LPI_MASK_MIF_ASB					((void *)(PMU_MIF_BASE + 0x0020))
#define LPI_MASK_MIF_DRAM					((void *)(PMU_MIF_BASE + 0x0060))
#define LPI_DENIAL_MASK_MIF_ASB					((void *)(PMU_MIF_BASE + 0x0120))
#define LPI_DENIAL_MASK_MIF_DRAM				((void *)(PMU_MIF_BASE + 0x0160))
#define LPI_AUTOMATIC_CLKGATE_MIF_ASB				((void *)(PMU_MIF_BASE + 0x0220))
#define LPI_AUTOMATIC_CLKGATE_MIF_DRAM				((void *)(PMU_MIF_BASE + 0x0260))
#define LPI_STATUS_MIF_ASB					((void *)(PMU_MIF_BASE + 0x0320))
#define LPI_STATUS_MIF_DRAM					((void *)(PMU_MIF_BASE + 0x0360))

#define LPI_MASK_MIF_ASB					((void *)(PMU_MIF_BASE + 0x0020))
#define LPI_MASK_MIF_DRAM					((void *)(PMU_MIF_BASE + 0x0060))
#define LPI_DENIAL_MASK_MIF_ASB					((void *)(PMU_MIF_BASE + 0x0120))
#define LPI_DENIAL_MASK_MIF_DRAM				((void *)(PMU_MIF_BASE + 0x0160))
#define LPI_AUTOMATIC_CLKGATE_MIF_ASB				((void *)(PMU_MIF_BASE + 0x0220))
#define LPI_AUTOMATIC_CLKGATE_MIF_DRAM				((void *)(PMU_MIF_BASE + 0x0260))
#define LPI_STATUS_MIF_ASB					((void *)(PMU_MIF_BASE + 0x0320))
#define LPI_STATUS_MIF_DRAM					((void *)(PMU_MIF_BASE + 0x0360))

#define LPI_MASK_PERI_ASB					((void *)(PMU_PERI_BASE + 0x0020))
#define LPI_DENIAL_MASK_PERI_ASB				((void *)(PMU_PERI_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_PERI_ASB				((void *)(PMU_PERI_BASE + 0x0220))
#define LPI_STATUS_PERI_ASB					((void *)(PMU_PERI_BASE + 0x0320))

/* Dummy register define */
#define TCXO_SHARED_SYS_PWR_REG					((void *)(PMU_ALIVE_BASE + 0x8620))
#define EXT_REGULATOR_SHARED_SYS_PWR_REG			((void *)(PMU_ALIVE_BASE + 0x8624))

#endif