/*
 * Device Tree binding constants for Exynos8890 clock controller.
 */

#ifndef _DT_BINDINGS_CLOCK_EXYNOS_8890_H
#define _DT_BINDINGS_CLOCK_EXYNOS_8890_H

#define CLK_SYSMMU_BASE 1100

#define CLK_VCLK_SYSMMU_MFC			(CLK_SYSMMU_BASE + 0)
#define CLK_VCLK_SYSMMU_MSCL			(CLK_SYSMMU_BASE + 1)
#define CLK_VCLK_SYSMMU_ISP0			(CLK_SYSMMU_BASE + 2)
#define CLK_VCLK_SYSMMU_CAM0			(CLK_SYSMMU_BASE + 3)
#define CLK_VCLK_SYSMMU_CAM1			(CLK_SYSMMU_BASE + 4)
#define CLK_VCLK_SYSMMU_AUD			(CLK_SYSMMU_BASE + 5)
#define CLK_VCLK_SYSMMU_DISP0			(CLK_SYSMMU_BASE + 6)
#define CLK_VCLK_SYSMMU_DISP1			(CLK_SYSMMU_BASE + 7)

#define CLK_GATE_SMFC	51
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_8890_H */