#ifndef __EXYNOS7570_SFRBASE_H__
#define __EXYNOS7570_SFRBASE_H__

#include "../pwrcal-env.h"

#ifdef PWRCAL_TARGET_FW

#define	CMU_APM_BASE	0x11CE0000
#define	CMU_MIF_BASE	0x10460000
#define	CMU_PERI_BASE	0x101F0000
#define	CMU_G3D_BASE	0x11460000
#define	CMU_CPUCL0_BASE	0x10900000
#define	CMU_MFCMSCL_BASE	0x12CB0000
#define	CMU_FSYS_BASE	0x13730000
#define	CMU_ISP_BASE	0x144D0000
#define	CMU_DISPAUD_BASE	0x148D0000

#define PMU_CPUCL0_BASE		0x10920000
#define PMU_FSYS_BASE		0x13740000
#define PMU_G3D_BASE		0x11470000
#define PMU_ISP_BASE		0x144E0000
#define PMU_MFCMSCL_BASE	0x12CC0000
#define PMU_MIF_BASE		0x10470000
#define PMU_PERI_BASE		0x101E0000
#define PMU_IF_BASE			0x11C70000
#define PMU_ALIVE_BASE		0x11C80000
#define PMU_APM_BASE		0x11CF0000
#define PMU_DISPAUD_BASE	0x148E0000

#define DREX0_BASE			 0x10400000
#define DREX0_PF_BASE		 0x10410000
#define DREX0_SECURE_BASE	 0x10420000
#define DREX0_PF_SECURE_BASE 0x10430000
#define DREXPHY0_BASE		 0x10440000

#define	SYSREG_CPUCL0_BASE	0x10910000
#define	SYSREG_G3D_BASE	0x11450000
#define	SYSREG_FSYS_BASE	0x13720000
#define	SYSREG_MIF_BASE	0x10450000
#define	SYSREG_PERI_BASE	0x101D0000
#define	SYSREG_MFCMSCL_BASE	0x12CA0000
#define	SYSREG_ISP_BASE	0x144F0000
#define	SYSREG_DISPAUD_BASE	0x148F0000

#endif

#ifdef PWRCAL_TARGET_LINUX

#define	CMU_APM_BASE	0x00010000
#define	CMU_MIF_BASE	0x00020000
#define	CMU_PERI_BASE	0x00030000
#define	CMU_G3D_BASE	0x00040000
#define	CMU_CPUCL0_BASE	0x00050000
#define	CMU_MFCMSCL_BASE	0x00060000
#define	CMU_FSYS_BASE	0x00070000
#define	CMU_ISP_BASE	0x00080000
#define	CMU_DISPAUD_BASE	0x00090000

#define PMU_CPUCL0_BASE		0x000A0000
#define PMU_FSYS_BASE		0x000B0000
#define PMU_G3D_BASE		0x000C0000
#define PMU_ISP_BASE		0x000D0000
#define PMU_MFCMSCL_BASE	0x000E0000
#define PMU_MIF_BASE		0x000F0000
#define PMU_PERI_BASE		0x00100000
#define PMU_IF_BASE		0x00110000
#define PMU_ALIVE_BASE		0x00120000
#define PMU_APM_BASE		0x00130000
#define PMU_DISPAUD_BASE	0x00140000

#define DREX0_BASE		0x00150000
#define DREX0_PF_BASE		0x00160000
#define DREX0_SECURE_BASE	0x00170000
#define DREX0_PF_SECURE_BASE	0x00180000
#define DREXPHY0_BASE		0x00190000

#define	SYSREG_CPUCL0_BASE	0x001A0000
#define	SYSREG_G3D_BASE	0x001B0000
#define	SYSREG_FSYS_BASE	0x001C0000
#define	SYSREG_MIF_BASE	0x001D0000
#define	SYSREG_PERI_BASE	0x001E0000
#define	SYSREG_MFCMSCL_BASE	0x001F0000
#define	SYSREG_ISP_BASE	0x00200000
#define	SYSREG_DISPAUD_BASE	0x00210000

#endif

#endif