#ifndef __EXYNOS8890_PMUSFR_H__
#define __EXYNOS8890_PMUSFR_H__

#include "S5E8890-sfrbase.h"

#define OM_STAT	((void *)(PMU_ALIVE_BASE + 0x0000))
#define RTC_CLKO_SEL	((void *)(PMU_ALIVE_BASE + 0x001C))
#define PMU_SYNC_CTRL	((void *)(PMU_ALIVE_BASE + 0x0020))
#define SFR_ACCESS_CONTROL_REG	((void *)(PMU_ALIVE_BASE + 0x0024))
#define CLKREQ_PAD_CONTROL	((void *)(PMU_ALIVE_BASE + 0x0028))
#define PWREN_G3D_PAD_CONTROL	((void *)(PMU_ALIVE_BASE + 0x002C))
#define CP_CTRL_NS	((void *)(PMU_ALIVE_BASE + 0x0030))
#define CP_CTRL_S	((void *)(PMU_ALIVE_BASE + 0x0034))
#define CP_STAT	((void *)(PMU_ALIVE_BASE + 0x0038))
#define CP_DEBUG	((void *)(PMU_ALIVE_BASE + 0x003C))
#define CP_DURATION	((void *)(PMU_ALIVE_BASE + 0x0040))
#define CP2AP_MEM_CONFIG	((void *)(PMU_ALIVE_BASE + 0x0050))
#define CP2AP_MIF0_PERI_ACCESS_CON	((void *)(PMU_ALIVE_BASE + 0x0054))
#define CP2AP_MIF1_PERI_ACCESS_CON	((void *)(PMU_ALIVE_BASE + 0x0058))
#define CP2AP_MIF2_PERI_ACCESS_CON	((void *)(PMU_ALIVE_BASE + 0x005C))
#define CP2AP_MIF3_PERI_ACCESS_CON	((void *)(PMU_ALIVE_BASE + 0x0060))
#define CP2AP_CCORE_PERI_ACCESS_CON	((void *)(PMU_ALIVE_BASE + 0x0064))
#define CP_BOOT_TEST_RST_CONFIG	((void *)(PMU_ALIVE_BASE + 0x0068))
#define CP2AP_PERI_ACCESS_WIN	((void *)(PMU_ALIVE_BASE + 0x006C))
#define MODAPIF_CONFIG	((void *)(PMU_ALIVE_BASE + 0x0070))
#define CP_CLK_CTRL	((void *)(PMU_ALIVE_BASE + 0x0074))
#define CP_QOS	((void *)(PMU_ALIVE_BASE + 0x0078))
#define ERROR_CODE_DATA	((void *)(PMU_ALIVE_BASE + 0x007C))
#define ERROR_CODE_PERI	((void *)(PMU_ALIVE_BASE + 0x0080))
#define MNGS_INTR_SPREAD_ENABLE	((void *)(PMU_ALIVE_BASE + 0x0100))
#define MNGS_INTR_SPREAD_USE_STANDBYWFI	((void *)(PMU_ALIVE_BASE + 0x0104))
#define MNGS_INTR_SPREAD_BLOCKING_DURATION	((void *)(PMU_ALIVE_BASE + 0x0108))
#define APOLLO_INTR_SPREAD_ENABLE	((void *)(PMU_ALIVE_BASE + 0x0110))
#define APOLLO_INTR_SPREAD_USE_STANDBYWFI	((void *)(PMU_ALIVE_BASE + 0x0114))
#define APOLLO_INTR_SPREAD_BLOCKING_DURATION	((void *)(PMU_ALIVE_BASE + 0x0118))
#define UP_SCHEDULER	((void *)(PMU_ALIVE_BASE + 0x0120))
#define CENTRAL_SEQ_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x0200))
#define CENTRAL_SEQ_STATUS	((void *)(PMU_ALIVE_BASE + 0x0204))
#define CENTRAL_SEQ_OPTION	((void *)(PMU_ALIVE_BASE + 0x0208))
#define CENTRAL_SEQ_OPTION1	((void *)(PMU_ALIVE_BASE + 0x020C))
#define CENTRAL_SEQ_DURATION0	((void *)(PMU_ALIVE_BASE + 0x0210))
#define CENTRAL_SEQ_DURATION1	((void *)(PMU_ALIVE_BASE + 0x0214))
#define CENTRAL_SEQ_DURATION2	((void *)(PMU_ALIVE_BASE + 0x0218))
#define CENTRAL_SEQ_DURATION3	((void *)(PMU_ALIVE_BASE + 0x021C))
#define SEQ_TRANSITION0	((void *)(PMU_ALIVE_BASE + 0x0220))
#define SEQ_TRANSITION1	((void *)(PMU_ALIVE_BASE + 0x0224))
#define SEQ_TRANSITION2	((void *)(PMU_ALIVE_BASE + 0x0228))
#define SEQ_TRANSITION3	((void *)(PMU_ALIVE_BASE + 0x022C))
#define SEQ_TRANSITION4	((void *)(PMU_ALIVE_BASE + 0x0230))
#define SEQ_TRANSITION5	((void *)(PMU_ALIVE_BASE + 0x0234))
#define SEQ_TRANSITION6	((void *)(PMU_ALIVE_BASE + 0x0238))
#define SEQ_TRANSITION7	((void *)(PMU_ALIVE_BASE + 0x023C))
#define CENTRAL_SEQ_MIF_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x0240))
#define CENTRAL_SEQ_MIF_STATUS	((void *)(PMU_ALIVE_BASE + 0x0244))
#define CENTRAL_SEQ_MIF_OPTION	((void *)(PMU_ALIVE_BASE + 0x0248))
#define CENTRAL_SEQ_MIF_DURATION0	((void *)(PMU_ALIVE_BASE + 0x0250))
#define CENTRAL_SEQ_MIF_DURATION1	((void *)(PMU_ALIVE_BASE + 0x0254))
#define CENTRAL_SEQ_MIF_DURATION2	((void *)(PMU_ALIVE_BASE + 0x0258))
#define CENTRAL_SEQ_MIF_DURATION3	((void *)(PMU_ALIVE_BASE + 0x025C))
#define SEQ_MIF_TRANSITION0	((void *)(PMU_ALIVE_BASE + 0x0260))
#define SEQ_MIF_TRANSITION1	((void *)(PMU_ALIVE_BASE + 0x0264))
#define SEQ_MIF_TRANSITION2	((void *)(PMU_ALIVE_BASE + 0x0268))
#define SEQ_MIF_TRANSITION3	((void *)(PMU_ALIVE_BASE + 0x026C))
#define SEQ_MIF_TRANSITION4	((void *)(PMU_ALIVE_BASE + 0x0270))
#define SEQ_MIF_TRANSITION5	((void *)(PMU_ALIVE_BASE + 0x0274))
#define SEQ_MIF_TRANSITION6	((void *)(PMU_ALIVE_BASE + 0x0278))
#define SEQ_MIF_TRANSITION7	((void *)(PMU_ALIVE_BASE + 0x027C))
#define CENTRAL_SEQ_CP_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x0280))
#define CENTRAL_SEQ_CP_STATUS	((void *)(PMU_ALIVE_BASE + 0x0284))
#define CENTRAL_SEQ_CP_OPTION	((void *)(PMU_ALIVE_BASE + 0x0288))
#define CENTRAL_SEQ_CP_DURATION0	((void *)(PMU_ALIVE_BASE + 0x0290))
#define CENTRAL_SEQ_CP_DURATION1	((void *)(PMU_ALIVE_BASE + 0x0294))
#define CENTRAL_SEQ_CP_DURATION2	((void *)(PMU_ALIVE_BASE + 0x0298))
#define CENTRAL_SEQ_CP_DURATION3	((void *)(PMU_ALIVE_BASE + 0x029C))
#define SEQ_CP_TRANSITION0	((void *)(PMU_ALIVE_BASE + 0x02A0))
#define SEQ_CP_TRANSITION1	((void *)(PMU_ALIVE_BASE + 0x02A4))
#define SEQ_CP_TRANSITION2	((void *)(PMU_ALIVE_BASE + 0x02A8))
#define SEQ_CP_TRANSITION3	((void *)(PMU_ALIVE_BASE + 0x02AC))
#define SEQ_CP_TRANSITION4	((void *)(PMU_ALIVE_BASE + 0x02B0))
#define SEQ_CP_TRANSITION5	((void *)(PMU_ALIVE_BASE + 0x02B4))
#define SEQ_CP_TRANSITION6	((void *)(PMU_ALIVE_BASE + 0x02B8))
#define SEQ_CP_TRANSITION7	((void *)(PMU_ALIVE_BASE + 0x02BC))
#define SEQ_TRANSITION8	((void *)(PMU_ALIVE_BASE + 0x02C0))
#define SEQ_TRANSITION9	((void *)(PMU_ALIVE_BASE + 0x02C4))
#define SEQ_TRANSITION10	((void *)(PMU_ALIVE_BASE + 0x02C8))
#define SEQ_TRANSITION11	((void *)(PMU_ALIVE_BASE + 0x02CC))
#define SEQ_TRANSITION12	((void *)(PMU_ALIVE_BASE + 0x02D0))
#define SEQ_TRANSITION13	((void *)(PMU_ALIVE_BASE + 0x02D4))
#define SEQ_TRANSITION14	((void *)(PMU_ALIVE_BASE + 0x02D8))
#define SEQ_TRANSITION15	((void *)(PMU_ALIVE_BASE + 0x02DC))
#define SEQ_MIF_TRANSITION8	((void *)(PMU_ALIVE_BASE + 0x02E0))
#define SEQ_MIF_TRANSITION9	((void *)(PMU_ALIVE_BASE + 0x02E4))
#define SEQ_MIF_TRANSITION10	((void *)(PMU_ALIVE_BASE + 0x02E8))
#define SEQ_MIF_TRANSITION11	((void *)(PMU_ALIVE_BASE + 0x02EC))
#define SEQ_MIF_TRANSITION12	((void *)(PMU_ALIVE_BASE + 0x02F0))
#define SEQ_MIF_TRANSITION13	((void *)(PMU_ALIVE_BASE + 0x02F4))
#define SEQ_MIF_TRANSITION14	((void *)(PMU_ALIVE_BASE + 0x02F8))
#define SEQ_MIF_TRANSITION15	((void *)(PMU_ALIVE_BASE + 0x02FC))
#define SEQ_CP_TRANSITION8	((void *)(PMU_ALIVE_BASE + 0x0300))
#define SEQ_CP_TRANSITION9	((void *)(PMU_ALIVE_BASE + 0x0304))
#define SEQ_CP_TRANSITION10	((void *)(PMU_ALIVE_BASE + 0x0308))
#define SEQ_CP_TRANSITION11	((void *)(PMU_ALIVE_BASE + 0x030C))
#define SEQ_CP_TRANSITION12	((void *)(PMU_ALIVE_BASE + 0x0310))
#define SEQ_CP_TRANSITION13	((void *)(PMU_ALIVE_BASE + 0x0314))
#define SEQ_CP_TRANSITION14	((void *)(PMU_ALIVE_BASE + 0x0318))
#define SEQ_CP_TRANSITION15	((void *)(PMU_ALIVE_BASE + 0x031C))
#define IDLE_IP0	((void *)(PMU_ALIVE_BASE + 0x03E0))
#define IDLE_IP1	((void *)(PMU_ALIVE_BASE + 0x03E4))
#define IDLE_IP2	((void *)(PMU_ALIVE_BASE + 0x03E8))
#define IDLE_IP3	((void *)(PMU_ALIVE_BASE + 0x03EC))
#define IDLE_IP0_MASK	((void *)(PMU_ALIVE_BASE + 0x03F0))
#define IDLE_IP1_MASK	((void *)(PMU_ALIVE_BASE + 0x03F4))
#define IDLE_IP2_MASK	((void *)(PMU_ALIVE_BASE + 0x03F8))
#define IDLE_IP3_MASK	((void *)(PMU_ALIVE_BASE + 0x03FC))
#define SWRESET	((void *)(PMU_ALIVE_BASE + 0x0400))
#define RST_STAT	((void *)(PMU_ALIVE_BASE + 0x0404))
#define AUTOMATIC_DISABLE_WDT	((void *)(PMU_ALIVE_BASE + 0x0408))
#define MASK_WDT_RESET_REQUEST	((void *)(PMU_ALIVE_BASE + 0x040C))
#define MASK_WRESET_REQUEST	((void *)(PMU_ALIVE_BASE + 0x0410))
#define CPU_RESET_DISABLE_FROM_WDTRESET	((void *)(PMU_ALIVE_BASE + 0x0414))
#define WDTRESET_LPI	((void *)(PMU_ALIVE_BASE + 0x0418))
#define CPU_RESET_DISABLE_FROM_SOFTRESET	((void *)(PMU_ALIVE_BASE + 0x041C))
#define RESET_LPI_TIMEOUT	((void *)(PMU_ALIVE_BASE + 0x0420))
#define RESET_SEQUENCER_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x0500))
#define RESET_SEQUENCER_STATUS	((void *)(PMU_ALIVE_BASE + 0x0504))
#define RESET_SEQUENCER_OPTION	((void *)(PMU_ALIVE_BASE + 0x0508))
#define RESET_SEQUENCER_DURATION0	((void *)(PMU_ALIVE_BASE + 0x0510))
#define RESET_SEQUENCER_DURATION1	((void *)(PMU_ALIVE_BASE + 0x0514))
#define RESET_SEQUENCER_DURATION2	((void *)(PMU_ALIVE_BASE + 0x0518))
#define RESET_SEQUENCER_DURATION3	((void *)(PMU_ALIVE_BASE + 0x051C))
#define WAKEUP_STAT	((void *)(PMU_ALIVE_BASE + 0x0600))
#define WAKEUP_STAT2	((void *)(PMU_ALIVE_BASE + 0x0604))
#define WAKEUP_STAT3	((void *)(PMU_ALIVE_BASE + 0x0608))
#define EINT_WAKEUP_MASK	((void *)(PMU_ALIVE_BASE + 0x060C))
#define WAKEUP_MASK	((void *)(PMU_ALIVE_BASE + 0x0610))
#define WAKEUP_MASK2	((void *)(PMU_ALIVE_BASE + 0x0614))
#define WAKEUP_MASK3	((void *)(PMU_ALIVE_BASE + 0x0618))
#define WAKEUP_INTERRUPT	((void *)(PMU_ALIVE_BASE + 0x061C))
#define WAKEUP_STAT_MIF	((void *)(PMU_ALIVE_BASE + 0x0620))
#define EINT_WAKEUP_MASK_MIF	((void *)(PMU_ALIVE_BASE + 0x0624))
#define WAKEUP_MASK_MIF	((void *)(PMU_ALIVE_BASE + 0x0628))
#define EINT_WAKEUP_MASK1	((void *)(PMU_ALIVE_BASE + 0x062C))
#define MMC_CONWKUP_CTRL	((void *)(PMU_ALIVE_BASE + 0x0660))
#define USB30PHY0_UDRD30_WAKEUP	((void *)(PMU_ALIVE_BASE + 0x0680))
#define HSIC_WAKEUP	((void *)(PMU_ALIVE_BASE + 0x0684))
#define USB20_WAKEUP	((void *)(PMU_ALIVE_BASE + 0x0688))
#define HDMI_PHY_CONTROL	((void *)(PMU_ALIVE_BASE + 0x0700))
#define USBDEV_PHY_CONTROL	((void *)(PMU_ALIVE_BASE + 0x0704))
#define MIPI_PHY_M4S4_CONTROL	((void *)(PMU_ALIVE_BASE + 0x070C))
#define MIPI_PHY_M4S0_CONTROL	((void *)(PMU_ALIVE_BASE + 0x0710))
#define MIPI_PHY_M0S4C_CONTROL	((void *)(PMU_ALIVE_BASE + 0x0714))
#define MIPI_PHY_M0S1_CONTROL	((void *)(PMU_ALIVE_BASE + 0x0718))
#define WIFI0_PHY_CONTROL	((void *)(PMU_ALIVE_BASE + 0x071C))
#define WIFI1_PHY_CONTROL	((void *)(PMU_ALIVE_BASE + 0x0720))
#define UFS_PHY_CONTROL	((void *)(PMU_ALIVE_BASE + 0x0724))
#define SDCARD_PHY_CONTROL	((void *)(PMU_ALIVE_BASE + 0x0728))
#define DPTX_PHY_CONTROL	((void *)(PMU_ALIVE_BASE + 0x072C))
#define MIPI_PHY_M1S0_CONTROL	((void *)(PMU_ALIVE_BASE + 0x0730))
#define MIPI_PHY_M0S2_CONTROL	((void *)(PMU_ALIVE_BASE + 0x0734))
#define PPC_APOLLO	((void *)(PMU_ALIVE_BASE + 0x0740))
#define PPC_G3D	((void *)(PMU_ALIVE_BASE + 0x0744))
#define PPC_MIF0	((void *)(PMU_ALIVE_BASE + 0x0748))
#define PPC_MIF1	((void *)(PMU_ALIVE_BASE + 0x074C))
#define PPC_MIF2	((void *)(PMU_ALIVE_BASE + 0x0750))
#define PPC_INT0	((void *)(PMU_ALIVE_BASE + 0x0754))
#define PPC_INT1	((void *)(PMU_ALIVE_BASE + 0x0758))
#define PPC_INT2	((void *)(PMU_ALIVE_BASE + 0x075C))
#define PPC_DISP	((void *)(PMU_ALIVE_BASE + 0x0760))
#define ALIVEIRAM_WRITE	((void *)(PMU_ALIVE_BASE + 0x0770))
#define UPACG_AT_CMU	((void *)(PMU_ALIVE_BASE + 0x0790))
#define INFORM0	((void *)(PMU_ALIVE_BASE + 0x0800))
#define INFORM1	((void *)(PMU_ALIVE_BASE + 0x0804))
#define INFORM2	((void *)(PMU_ALIVE_BASE + 0x0808))
#define INFORM3	((void *)(PMU_ALIVE_BASE + 0x080C))
#define SYSIP_DAT0	((void *)(PMU_ALIVE_BASE + 0x0810))
#define SYSIP_DAT1	((void *)(PMU_ALIVE_BASE + 0x0814))
#define SYSIP_DAT2	((void *)(PMU_ALIVE_BASE + 0x0818))
#define SYSIP_DAT3	((void *)(PMU_ALIVE_BASE + 0x081C))
#define PS_HOLD_HW_TRIP	((void *)(PMU_ALIVE_BASE + 0x0820))
#define PS_HOLD_SW_TRIP	((void *)(PMU_ALIVE_BASE + 0x0824))
#define PMU_SPARE0	((void *)(PMU_ALIVE_BASE + 0x0900))
#define PMU_SPARE1	((void *)(PMU_ALIVE_BASE + 0x0904))
#define PMU_SPARE2	((void *)(PMU_ALIVE_BASE + 0x0908))
#define PMU_SPARE3	((void *)(PMU_ALIVE_BASE + 0x090C))
#define ACK_LAST_CPU	((void *)(PMU_ALIVE_BASE + 0x0940))
#define IROM_DATA_REG0	((void *)(PMU_ALIVE_BASE + 0x0980))
#define IROM_DATA_REG1	((void *)(PMU_ALIVE_BASE + 0x0984))
#define IROM_DATA_REG2	((void *)(PMU_ALIVE_BASE + 0x0988))
#define IROM_DATA_REG3	((void *)(PMU_ALIVE_BASE + 0x098C))
#define DREX_CALIBRATION0	((void *)(PMU_ALIVE_BASE + 0x09A0))
#define DREX_CALIBRATION1	((void *)(PMU_ALIVE_BASE + 0x09A4))
#define DREX_CALIBRATION2	((void *)(PMU_ALIVE_BASE + 0x09A8))
#define DREX_CALIBRATION3	((void *)(PMU_ALIVE_BASE + 0x09AC))
#define DREX_CALIBRATION4	((void *)(PMU_ALIVE_BASE + 0x09B0))
#define DREX_CALIBRATION5	((void *)(PMU_ALIVE_BASE + 0x09B4))
#define DREX_CALIBRATION6	((void *)(PMU_ALIVE_BASE + 0x09B8))
#define DREX_CALIBRATION7	((void *)(PMU_ALIVE_BASE + 0x09BC))
#define PMU_DEBUG	((void *)(PMU_ALIVE_BASE + 0x0A00))
#define ARM_CONTROL_OPTION	((void *)(PMU_ALIVE_BASE + 0x0A04))
#define BURNIN_CTRL	((void *)(PMU_ALIVE_BASE + 0x0A08))
#define PMU_DEBUG1	((void *)(PMU_ALIVE_BASE + 0x0A0C))
#define PMUDBG_CENTRAL_SEQ_STATUS	((void *)(PMU_ALIVE_BASE + 0x0F00))
#define PMUDBG_CENTRAL_SEQ_MIF_STATUS	((void *)(PMU_ALIVE_BASE + 0x0F04))
#define PMUDBG_MNGS_CPU0_STATUS	((void *)(PMU_ALIVE_BASE + 0x0F08))
#define PMUDBG_MNGS_CPU1_STATUS	((void *)(PMU_ALIVE_BASE + 0x0F0C))
#define PMUDBG_MNGS_CPU2_STATUS	((void *)(PMU_ALIVE_BASE + 0x0F10))
#define PMUDBG_MNGS_CPU3_STATUS	((void *)(PMU_ALIVE_BASE + 0x0F14))
#define PMUDBG_APOLLO_CPU0_STATUS	((void *)(PMU_ALIVE_BASE + 0x0F20))
#define PMUDBG_APOLLO_CPU1_STATUS	((void *)(PMU_ALIVE_BASE + 0x0F24))
#define PMUDBG_APOLLO_CPU2_STATUS	((void *)(PMU_ALIVE_BASE + 0x0F28))
#define PMUDBG_APOLLO_CPU3_STATUS	((void *)(PMU_ALIVE_BASE + 0x0F2C))
#define PMUDBG_MNGS_L2_STATUS	((void *)(PMU_ALIVE_BASE + 0x0F30))
#define PMUDBG_APOLLO_L2_STATUS	((void *)(PMU_ALIVE_BASE + 0x0F34))
#define PMUDBG_MNGS_NONCPU_STATUS	((void *)(PMU_ALIVE_BASE + 0x0F38))
#define PMUDBG_APOLLO_NONCPU_STATUS	((void *)(PMU_ALIVE_BASE + 0x0F3C))
#define OTP_STATUS	((void *)(PMU_ALIVE_BASE + 0x0F40))
#define MNGS_CPU0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1000))
#define DIS_IRQ_MNGS_CPU0_LOCAL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1004))
#define DIS_IRQ_MNGS_CPU0_CENTRAL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1008))
#define DIS_IRQ_MNGS_CPU0_CPUSEQUENCER_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x100C))
#define MNGS_CPU1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1010))
#define DIS_IRQ_MNGS_CPU1_LOCAL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1014))
#define DIS_IRQ_MNGS_CPU1_CENTRAL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1018))
#define DIS_IRQ_MNGS_CPU1_CPUSEQUENCER_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x101C))
#define MNGS_CPU2_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1020))
#define DIS_IRQ_MNGS_CPU2_LOCAL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1024))
#define DIS_IRQ_MNGS_CPU2_CENTRAL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1028))
#define DIS_IRQ_MNGS_CPU2_CPUSEQUENCER_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x102C))
#define MNGS_CPU3_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1030))
#define DIS_IRQ_MNGS_CPU3_LOCAL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1034))
#define DIS_IRQ_MNGS_CPU3_CENTRAL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1038))
#define DIS_IRQ_MNGS_CPU3_CPUSEQUENCER_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x103C))
#define APOLLO_CPU0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1040))
#define DIS_IRQ_APOLLO_CPU0_LOCAL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1044))
#define DIS_IRQ_APOLLO_CPU0_CENTRAL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1048))
#define DIS_IRQ_APOLLO_CPU0_CPUSEQUENCER_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x104C))
#define APOLLO_CPU1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1050))
#define DIS_IRQ_APOLLO_CPU1_LOCAL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1054))
#define DIS_IRQ_APOLLO_CPU1_CENTRAL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1058))
#define DIS_IRQ_APOLLO_CPU1_CPUSEQUENCER_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x105C))
#define APOLLO_CPU2_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1060))
#define DIS_IRQ_APOLLO_CPU2_LOCAL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1064))
#define DIS_IRQ_APOLLO_CPU2_CENTRAL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1068))
#define DIS_IRQ_APOLLO_CPU2_CPUSEQUENCER_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x106C))
#define APOLLO_CPU3_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1070))
#define DIS_IRQ_APOLLO_CPU3_LOCAL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1074))
#define DIS_IRQ_APOLLO_CPU3_CENTRAL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1078))
#define DIS_IRQ_APOLLO_CPU3_CPUSEQUENCER_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x107C))
#define MNGS_NONCPU_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1080))
#define APOLLO_NONCPU_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1084))
#define MNGS_DBG_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1088))
#define CORTEXM3_APM_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x10A0))
#define A7IS_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x10B0))
#define DIS_IRQ_A7IS_LOCAL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x10B4))
#define DIS_IRQ_A7IS_CENTRAL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x10B8))
#define MNGS_L2_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x10C0))
#define APOLLO_L2_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x10C4))
#define MNGS_L2_PWR_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x10D0))
#define CLKSTOP_CMU_TOP_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1100))
#define CLKRUN_CMU_TOP_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1104))
#define RETENTION_CMU_TOP_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1108))
#define RESET_CMU_TOP_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x110C))
#define RESET_CPUCLKSTOP_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x111C))
#define CLKSTOP_CMU_MIF_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1120))
#define CLKRUN_CMU_MIF_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1124))
#define RETENTION_CMU_MIF_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1128))
#define RESET_CMU_MIF_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x112C))
#define DDRPHY_CLKSTOP_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1130))
#define DDRPHY_ISO_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1134))
#define DDRPHY_SOC2_ISO_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1138))
#define DDRPHY_DLL_CLK_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x113C))
#define DISABLE_PLL_CMU_TOP_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1140))
#define DISABLE_PLL_AUD_PLL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1144))
#define DISABLE_PLL_CMU_MIF_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1160))
#define RESET_AHEAD_CP_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1170))
#define TOP_BUS_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1180))
#define TOP_RETENTION_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1184))
#define TOP_PWR_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1188))
#define CMU_PWR_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x118C))
#define TOP_BUS_MIF_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1190))
#define TOP_RETENTION_MIF_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1194))
#define TOP_PWR_MIF_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1198))
#define PSCDC_MIF_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x119C))
#define LOGIC_RESET_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x11A0))
#define OSCCLK_GATE_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x11A4))
#define SLEEP_RESET_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x11A8))
#define LOGIC_RESET_MIF_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x11B0))
#define OSCCLK_GATE_MIF_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x11B4))
#define SLEEP_RESET_MIF_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x11B8))
#define MEMORY_TOP_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x11C0))
#define CLEANY_BUS_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x11CC))
#define LOGIC_RESET_CP_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x11D0))
#define TCXO_GATE_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x11D4))
#define RESET_ASB_CP_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x11D8))
#define RESET_ASB_MIF_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x11DC))
#define MEMORY_IMEM_ALIVEIRAM_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x11E0))
#define MEMORY_MIF_TOP_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x11E4))
#define LOGIC_RESET_DDRPHY_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x11F0))
#define RETENTION_DDRPHY_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x11F4))
#define PWR_DDRPHY_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x11FC))
#define PAD_RETENTION_LPDDR4_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1200))
#define PAD_RETENTION_AUD_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1204))
#define PAD_RETENTION_JTAG_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1208))
#define PAD_RETENTION_PCIE_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x120C))
#define PAD_RETENTION_UFS_CARD_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1210))
#define PAD_RETENTION_MMC2_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1218))
#define PAD_RETENTION_TOP_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1220))
#define PAD_RETENTION_UART_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1224))
#define PAD_RETENTION_MMC0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1228))
#define PAD_RETENTION_EBIA_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1230))
#define PAD_RETENTION_EBIB_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1234))
#define PAD_RETENTION_SPI_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1238))
#define PAD_RETENTION_MIF_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x123C))
#define PAD_ISOLATION_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1240))
#define PAD_RETENTION_BOOTLDO_0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1248))
#define PAD_RETENTION_UFS_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x124C))
#define PAD_ISOLATION_MIF_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1250))
#define PAD_RETENTION_USB_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1254))
#define PAD_RETENTION_BOOTLDO_1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1258))
#define PAD_ALV_SEL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1260))
#define XXTI_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1284))
#define TCXO_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x128C))
#define EXT_REGULATOR_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x12C0))
#define EXT_REGULATOR_MIF_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x12C4))
#define GPIO_MODE_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1300))
#define GPIO_MODE_FSYS0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1304))
#define GPIO_MODE_FSYS1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1308))
#define GPIO_MODE_MIF_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1320))
#define GPIO_MODE_AUD_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1340))
#define CLKSTOP_OPEN_CMU_TOP_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1380))
#define CLKSTOP_OPEN_CMU_MIF_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1384))
#define CLKSTOP_OPEN_CMU_CAM0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1388))
#define CLKSTOP_OPEN_CMU_MSCL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x138C))
#define CLKSTOP_OPEN_CMU_G3D_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1390))
#define CLKSTOP_OPEN_CMU_DISP0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1394))
#define CLKSTOP_OPEN_CMU_CAM1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1398))
#define CLKSTOP_OPEN_CMU_AUD_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x139C))
#define CLKSTOP_OPEN_CMU_FSYS0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x13A0))
#define CLKSTOP_OPEN_CMU_BUS0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x13A4))
#define CLKSTOP_OPEN_CMU_ISP0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x13A8))
#define CLKSTOP_OPEN_CMU_ISP1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x13AC))
#define CLKSTOP_OPEN_CMU_MFC_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x13B0))
#define CLKSTOP_OPEN_CMU_DISP1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x13B4))
#define CLKSTOP_OPEN_CMU_FSYS1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x13B8))
#define CAM0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1404))
#define MSCL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1408))
#define G3D_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x140C))
#define DISP0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1410))
#define CAM1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1414))
#define AUD_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1418))
#define FSYS0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x141C))
#define BUS0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1420))
#define ISP0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1424))
#define ISP1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1428))
#define MFC_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x142C))
#define DISP1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1430))
#define FSYS1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1434))
#define CLKRUN_CMU_CAM0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1444))
#define CLKRUN_CMU_MSCL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1448))
#define CLKRUN_CMU_G3D_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x144C))
#define CLKRUN_CMU_DISP0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1450))
#define CLKRUN_CMU_CAM1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1454))
#define CLKRUN_CMU_AUD_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1458))
#define CLKRUN_CMU_FSYS0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x145C))
#define CLKRUN_CMU_BUS0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1460))
#define CLKRUN_CMU_ISP0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1468))
#define CLKRUN_CMU_ISP1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x146C))
#define CLKRUN_CMU_MFC_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1470))
#define CLKRUN_CMU_DISP1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1474))
#define CLKRUN_CMU_FSYS1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1478))
#define CLKSTOP_CMU_CAM0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1484))
#define CLKSTOP_CMU_MSCL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1488))
#define CLKSTOP_CMU_G3D_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x148C))
#define CLKSTOP_CMU_DISP0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1490))
#define CLKSTOP_CMU_CAM1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1494))
#define CLKSTOP_CMU_AUD_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1498))
#define CLKSTOP_CMU_FSYS0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x149C))
#define CLKSTOP_CMU_BUS0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x14A0))
#define CLKSTOP_CMU_ISP0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x14A8))
#define CLKSTOP_CMU_ISP1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x14AC))
#define CLKSTOP_CMU_MFC_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x14B0))
#define CLKSTOP_CMU_DISP1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x14B4))
#define CLKSTOP_CMU_FSYS1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x14B8))
#define DISABLE_PLL_CMU_CAM0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x14C4))
#define DISABLE_PLL_CMU_MSCL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x14C8))
#define DISABLE_PLL_CMU_G3D_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x14CC))
#define DISABLE_PLL_CMU_DISP0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x14D0))
#define DISABLE_PLL_CMU_CAM1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x14D4))
#define DISABLE_PLL_CMU_AUD_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x14D8))
#define DISABLE_PLL_CMU_FSYS0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x14DC))
#define DISABLE_PLL_CMU_BUS0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x14E0))
#define DISABLE_PLL_CMU_ISP0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x14E8))
#define DISABLE_PLL_CMU_ISP1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x14EC))
#define DISABLE_PLL_CMU_MFC_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x14F0))
#define DISABLE_PLL_CMU_DISP1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x14F4))
#define DISABLE_PLL_CMU_FSYS1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x14F8))
#define RESET_LOGIC_CAM0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1504))
#define RESET_LOGIC_MSCL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1508))
#define RESET_LOGIC_G3D_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x150C))
#define RESET_LOGIC_DISP0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1510))
#define RESET_LOGIC_CAM1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1514))
#define RESET_LOGIC_AUD_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1518))
#define RESET_LOGIC_FSYS0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x151C))
#define RESET_LOGIC_BUS0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1520))
#define RESET_LOGIC_ISP0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1528))
#define RESET_LOGIC_ISP1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x152C))
#define RESET_LOGIC_MFC_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1530))
#define RESET_LOGIC_DISP1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1534))
#define RESET_LOGIC_FSYS1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1538))
#define MEMORY_CAM0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1544))
#define MEMORY_MSCL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1548))
#define MEMORY_G3D_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x154C))
#define MEMORY_DISP0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1550))
#define MEMORY_CAM1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1554))
#define MEMORY_AUD_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1558))
#define MEMORY_FSYS0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x155C))
#define MEMORY_BUS0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1560))
#define MEMORY_ISP0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1568))
#define MEMORY_ISP1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x156C))
#define MEMORY_MFC_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1570))
#define MEMORY_DISP1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1574))
#define MEMORY_FSYS1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1578))
#define RESET_CMU_CAM0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1584))
#define RESET_CMU_MSCL_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1588))
#define RESET_CMU_G3D_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x158C))
#define RESET_CMU_DISP0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1590))
#define RESET_CMU_CAM1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1594))
#define RESET_CMU_AUD_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x1598))
#define RESET_CMU_FSYS0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x159C))
#define RESET_CMU_BUS0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x15A0))
#define RESET_CMU_ISP0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x15A8))
#define RESET_CMU_ISP1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x15AC))
#define RESET_CMU_MFC_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x15B0))
#define RESET_CMU_DISP1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x15B4))
#define RESET_CMU_FSYS1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x15B8))
#define RESET_SLEEP_FSYS0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x15DC))
#define RESET_SLEEP_BUS0_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x15E0))
#define RESET_SLEEP_FSYS1_SYS_PWR_REG	((void *)(PMU_ALIVE_BASE + 0x15F8))
#define MNGS_CPU0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2000))
#define MNGS_CPU0_STATUS	((void *)(PMU_ALIVE_BASE + 0x2004))
#define MNGS_CPU0_OPTION	((void *)(PMU_ALIVE_BASE + 0x2008))
#define MNGS_CPU0_RESET	((void *)(PMU_ALIVE_BASE + 0x200C))
#define MNGS_CPU0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2010))
#define MNGS_CPU0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2014))
#define MNGS_CPU0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2018))
#define MNGS_CPU0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x201C))
#define DIS_IRQ_MNGS_CPU0_LOCAL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2020))
#define DIS_IRQ_MNGS_CPU0_LOCAL_STATUS	((void *)(PMU_ALIVE_BASE + 0x2024))
#define DIS_IRQ_MNGS_CPU0_LOCAL_OPTION	((void *)(PMU_ALIVE_BASE + 0x2028))
#define DIS_IRQ_MNGS_CPU0_LOCAL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2030))
#define DIS_IRQ_MNGS_CPU0_LOCAL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2034))
#define DIS_IRQ_MNGS_CPU0_LOCAL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2038))
#define DIS_IRQ_MNGS_CPU0_LOCAL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x203C))
#define DIS_IRQ_MNGS_CPU0_CENTRAL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2040))
#define DIS_IRQ_MNGS_CPU0_CENTRAL_STATUS	((void *)(PMU_ALIVE_BASE + 0x2044))
#define DIS_IRQ_MNGS_CPU0_CENTRAL_OPTION	((void *)(PMU_ALIVE_BASE + 0x2048))
#define DIS_IRQ_MNGS_CPU0_CENTRAL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2050))
#define DIS_IRQ_MNGS_CPU0_CENTRAL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2054))
#define DIS_IRQ_MNGS_CPU0_CENTRAL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2058))
#define DIS_IRQ_MNGS_CPU0_CENTRAL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x205C))
#define DIS_IRQ_MNGS_CPU0_CPUSEQUENCER_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2060))
#define DIS_IRQ_MNGS_CPU0_CPUSEQUENCER_STATUS	((void *)(PMU_ALIVE_BASE + 0x2064))
#define DIS_IRQ_MNGS_CPU0_CPUSEQUENCER_OPTION	((void *)(PMU_ALIVE_BASE + 0x2068))
#define DIS_IRQ_MNGS_CPU0_CPUSEQUENCER_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2070))
#define DIS_IRQ_MNGS_CPU0_CPUSEQUENCER_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2074))
#define DIS_IRQ_MNGS_CPU0_CPUSEQUENCER_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2078))
#define DIS_IRQ_MNGS_CPU0_CPUSEQUENCER_DURATION3	((void *)(PMU_ALIVE_BASE + 0x207C))
#define MNGS_CPU1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2080))
#define MNGS_CPU1_STATUS	((void *)(PMU_ALIVE_BASE + 0x2084))
#define MNGS_CPU1_OPTION	((void *)(PMU_ALIVE_BASE + 0x2088))
#define MNGS_CPU1_RESET	((void *)(PMU_ALIVE_BASE + 0x208C))
#define MNGS_CPU1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2090))
#define MNGS_CPU1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2094))
#define MNGS_CPU1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2098))
#define MNGS_CPU1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x209C))
#define DIS_IRQ_MNGS_CPU1_LOCAL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x20A0))
#define DIS_IRQ_MNGS_CPU1_LOCAL_STATUS	((void *)(PMU_ALIVE_BASE + 0x20A4))
#define DIS_IRQ_MNGS_CPU1_LOCAL_OPTION	((void *)(PMU_ALIVE_BASE + 0x20A8))
#define DIS_IRQ_MNGS_CPU1_LOCAL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x20B0))
#define DIS_IRQ_MNGS_CPU1_LOCAL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x20B4))
#define DIS_IRQ_MNGS_CPU1_LOCAL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x20B8))
#define DIS_IRQ_MNGS_CPU1_LOCAL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x20BC))
#define DIS_IRQ_MNGS_CPU1_CENTRAL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x20C0))
#define DIS_IRQ_MNGS_CPU1_CENTRAL_STATUS	((void *)(PMU_ALIVE_BASE + 0x20C4))
#define DIS_IRQ_MNGS_CPU1_CENTRAL_OPTION	((void *)(PMU_ALIVE_BASE + 0x20C8))
#define DIS_IRQ_MNGS_CPU1_CENTRAL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x20D0))
#define DIS_IRQ_MNGS_CPU1_CENTRAL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x20D4))
#define DIS_IRQ_MNGS_CPU1_CENTRAL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x20D8))
#define DIS_IRQ_MNGS_CPU1_CENTRAL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x20DC))
#define DIS_IRQ_MNGS_CPU1_CPUSEQUENCER_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x20E0))
#define DIS_IRQ_MNGS_CPU1_CPUSEQUENCER_STATUS	((void *)(PMU_ALIVE_BASE + 0x20E4))
#define DIS_IRQ_MNGS_CPU1_CPUSEQUENCER_OPTION	((void *)(PMU_ALIVE_BASE + 0x20E8))
#define DIS_IRQ_MNGS_CPU1_CPUSEQUENCER_DURATION0	((void *)(PMU_ALIVE_BASE + 0x20F0))
#define DIS_IRQ_MNGS_CPU1_CPUSEQUENCER_DURATION1	((void *)(PMU_ALIVE_BASE + 0x20F4))
#define DIS_IRQ_MNGS_CPU1_CPUSEQUENCER_DURATION2	((void *)(PMU_ALIVE_BASE + 0x20F8))
#define DIS_IRQ_MNGS_CPU1_CPUSEQUENCER_DURATION3	((void *)(PMU_ALIVE_BASE + 0x20FC))
#define MNGS_CPU2_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2100))
#define MNGS_CPU2_STATUS	((void *)(PMU_ALIVE_BASE + 0x2104))
#define MNGS_CPU2_OPTION	((void *)(PMU_ALIVE_BASE + 0x2108))
#define MNGS_CPU2_RESET	((void *)(PMU_ALIVE_BASE + 0x210C))
#define MNGS_CPU2_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2110))
#define MNGS_CPU2_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2114))
#define MNGS_CPU2_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2118))
#define MNGS_CPU2_DURATION3	((void *)(PMU_ALIVE_BASE + 0x211C))
#define DIS_IRQ_MNGS_CPU2_LOCAL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2120))
#define DIS_IRQ_MNGS_CPU2_LOCAL_STATUS	((void *)(PMU_ALIVE_BASE + 0x2124))
#define DIS_IRQ_MNGS_CPU2_LOCAL_OPTION	((void *)(PMU_ALIVE_BASE + 0x2128))
#define DIS_IRQ_MNGS_CPU2_LOCAL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2130))
#define DIS_IRQ_MNGS_CPU2_LOCAL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2134))
#define DIS_IRQ_MNGS_CPU2_LOCAL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2138))
#define DIS_IRQ_MNGS_CPU2_LOCAL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x213C))
#define DIS_IRQ_MNGS_CPU2_CENTRAL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2140))
#define DIS_IRQ_MNGS_CPU2_CENTRAL_STATUS	((void *)(PMU_ALIVE_BASE + 0x2144))
#define DIS_IRQ_MNGS_CPU2_CENTRAL_OPTION	((void *)(PMU_ALIVE_BASE + 0x2148))
#define DIS_IRQ_MNGS_CPU2_CENTRAL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2150))
#define DIS_IRQ_MNGS_CPU2_CENTRAL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2154))
#define DIS_IRQ_MNGS_CPU2_CENTRAL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2158))
#define DIS_IRQ_MNGS_CPU2_CENTRAL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x215C))
#define DIS_IRQ_MNGS_CPU2_CPUSEQUENCER_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2160))
#define DIS_IRQ_MNGS_CPU2_CPUSEQUENCER_STATUS	((void *)(PMU_ALIVE_BASE + 0x2164))
#define DIS_IRQ_MNGS_CPU2_CPUSEQUENCER_OPTION	((void *)(PMU_ALIVE_BASE + 0x2168))
#define DIS_IRQ_MNGS_CPU2_CPUSEQUENCER_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2170))
#define DIS_IRQ_MNGS_CPU2_CPUSEQUENCER_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2174))
#define DIS_IRQ_MNGS_CPU2_CPUSEQUENCER_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2178))
#define DIS_IRQ_MNGS_CPU2_CPUSEQUENCER_DURATION3	((void *)(PMU_ALIVE_BASE + 0x217C))
#define MNGS_CPU3_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2180))
#define MNGS_CPU3_STATUS	((void *)(PMU_ALIVE_BASE + 0x2184))
#define MNGS_CPU3_OPTION	((void *)(PMU_ALIVE_BASE + 0x2188))
#define MNGS_CPU3_RESET	((void *)(PMU_ALIVE_BASE + 0x218C))
#define MNGS_CPU3_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2190))
#define MNGS_CPU3_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2194))
#define MNGS_CPU3_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2198))
#define MNGS_CPU3_DURATION3	((void *)(PMU_ALIVE_BASE + 0x219C))
#define DIS_IRQ_MNGS_CPU3_LOCAL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x21A0))
#define DIS_IRQ_MNGS_CPU3_LOCAL_STATUS	((void *)(PMU_ALIVE_BASE + 0x21A4))
#define DIS_IRQ_MNGS_CPU3_LOCAL_OPTION	((void *)(PMU_ALIVE_BASE + 0x21A8))
#define DIS_IRQ_MNGS_CPU3_LOCAL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x21B0))
#define DIS_IRQ_MNGS_CPU3_LOCAL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x21B4))
#define DIS_IRQ_MNGS_CPU3_LOCAL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x21B8))
#define DIS_IRQ_MNGS_CPU3_LOCAL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x21BC))
#define DIS_IRQ_MNGS_CPU3_CENTRAL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x21C0))
#define DIS_IRQ_MNGS_CPU3_CENTRAL_STATUS	((void *)(PMU_ALIVE_BASE + 0x21C4))
#define DIS_IRQ_MNGS_CPU3_CENTRAL_OPTION	((void *)(PMU_ALIVE_BASE + 0x21C8))
#define DIS_IRQ_MNGS_CPU3_CENTRAL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x21D0))
#define DIS_IRQ_MNGS_CPU3_CENTRAL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x21D4))
#define DIS_IRQ_MNGS_CPU3_CENTRAL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x21D8))
#define DIS_IRQ_MNGS_CPU3_CENTRAL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x21DC))
#define DIS_IRQ_MNGS_CPU3_CPUSEQUENCER_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x21E0))
#define DIS_IRQ_MNGS_CPU3_CPUSEQUENCER_STATUS	((void *)(PMU_ALIVE_BASE + 0x21E4))
#define DIS_IRQ_MNGS_CPU3_CPUSEQUENCER_OPTION	((void *)(PMU_ALIVE_BASE + 0x21E8))
#define DIS_IRQ_MNGS_CPU3_CPUSEQUENCER_DURATION0	((void *)(PMU_ALIVE_BASE + 0x21F0))
#define DIS_IRQ_MNGS_CPU3_CPUSEQUENCER_DURATION1	((void *)(PMU_ALIVE_BASE + 0x21F4))
#define DIS_IRQ_MNGS_CPU3_CPUSEQUENCER_DURATION2	((void *)(PMU_ALIVE_BASE + 0x21F8))
#define DIS_IRQ_MNGS_CPU3_CPUSEQUENCER_DURATION3	((void *)(PMU_ALIVE_BASE + 0x21FC))
#define APOLLO_CPU0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2200))
#define APOLLO_CPU0_STATUS	((void *)(PMU_ALIVE_BASE + 0x2204))
#define APOLLO_CPU0_OPTION	((void *)(PMU_ALIVE_BASE + 0x2208))
#define APOLLO_CPU0_RESET	((void *)(PMU_ALIVE_BASE + 0x220C))
#define APOLLO_CPU0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2210))
#define APOLLO_CPU0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2214))
#define APOLLO_CPU0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2218))
#define APOLLO_CPU0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x221C))
#define DIS_IRQ_APOLLO_CPU0_LOCAL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2220))
#define DIS_IRQ_APOLLO_CPU0_LOCAL_STATUS	((void *)(PMU_ALIVE_BASE + 0x2224))
#define DIS_IRQ_APOLLO_CPU0_LOCAL_OPTION	((void *)(PMU_ALIVE_BASE + 0x2228))
#define DIS_IRQ_APOLLO_CPU0_LOCAL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2230))
#define DIS_IRQ_APOLLO_CPU0_LOCAL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2234))
#define DIS_IRQ_APOLLO_CPU0_LOCAL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2238))
#define DIS_IRQ_APOLLO_CPU0_LOCAL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x223C))
#define DIS_IRQ_APOLLO_CPU0_CENTRAL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2240))
#define DIS_IRQ_APOLLO_CPU0_CENTRAL_STATUS	((void *)(PMU_ALIVE_BASE + 0x2244))
#define DIS_IRQ_APOLLO_CPU0_CENTRAL_OPTION	((void *)(PMU_ALIVE_BASE + 0x2248))
#define DIS_IRQ_APOLLO_CPU0_CENTRAL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2250))
#define DIS_IRQ_APOLLO_CPU0_CENTRAL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2254))
#define DIS_IRQ_APOLLO_CPU0_CENTRAL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2258))
#define DIS_IRQ_APOLLO_CPU0_CENTRAL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x225C))
#define DIS_IRQ_APOLLO_CPU0_CPUSEQUENCER_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2260))
#define DIS_IRQ_APOLLO_CPU0_CPUSEQUENCER_STATUS	((void *)(PMU_ALIVE_BASE + 0x2264))
#define DIS_IRQ_APOLLO_CPU0_CPUSEQUENCER_OPTION	((void *)(PMU_ALIVE_BASE + 0x2268))
#define DIS_IRQ_APOLLO_CPU0_CPUSEQUENCER_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2270))
#define DIS_IRQ_APOLLO_CPU0_CPUSEQUENCER_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2274))
#define DIS_IRQ_APOLLO_CPU0_CPUSEQUENCER_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2278))
#define DIS_IRQ_APOLLO_CPU0_CPUSEQUENCER_DURATION3	((void *)(PMU_ALIVE_BASE + 0x227C))
#define APOLLO_CPU1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2280))
#define APOLLO_CPU1_STATUS	((void *)(PMU_ALIVE_BASE + 0x2284))
#define APOLLO_CPU1_OPTION	((void *)(PMU_ALIVE_BASE + 0x2288))
#define APOLLO_CPU1_RESET	((void *)(PMU_ALIVE_BASE + 0x228C))
#define APOLLO_CPU1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2290))
#define APOLLO_CPU1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2294))
#define APOLLO_CPU1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2298))
#define APOLLO_CPU1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x229C))
#define DIS_IRQ_APOLLO_CPU1_LOCAL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x22A0))
#define DIS_IRQ_APOLLO_CPU1_LOCAL_STATUS	((void *)(PMU_ALIVE_BASE + 0x22A4))
#define DIS_IRQ_APOLLO_CPU1_LOCAL_OPTION	((void *)(PMU_ALIVE_BASE + 0x22A8))
#define DIS_IRQ_APOLLO_CPU1_LOCAL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x22B0))
#define DIS_IRQ_APOLLO_CPU1_LOCAL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x22B4))
#define DIS_IRQ_APOLLO_CPU1_LOCAL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x22B8))
#define DIS_IRQ_APOLLO_CPU1_LOCAL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x22BC))
#define DIS_IRQ_APOLLO_CPU1_CENTRAL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x22C0))
#define DIS_IRQ_APOLLO_CPU1_CENTRAL_STATUS	((void *)(PMU_ALIVE_BASE + 0x22C4))
#define DIS_IRQ_APOLLO_CPU1_CENTRAL_OPTION	((void *)(PMU_ALIVE_BASE + 0x22C8))
#define DIS_IRQ_APOLLO_CPU1_CENTRAL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x22D0))
#define DIS_IRQ_APOLLO_CPU1_CENTRAL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x22D4))
#define DIS_IRQ_APOLLO_CPU1_CENTRAL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x22D8))
#define DIS_IRQ_APOLLO_CPU1_CENTRAL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x22DC))
#define DIS_IRQ_APOLLO_CPU1_CPUSEQUENCER_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x22E0))
#define DIS_IRQ_APOLLO_CPU1_CPUSEQUENCER_STATUS	((void *)(PMU_ALIVE_BASE + 0x22E4))
#define DIS_IRQ_APOLLO_CPU1_CPUSEQUENCER_OPTION	((void *)(PMU_ALIVE_BASE + 0x22E8))
#define DIS_IRQ_APOLLO_CPU1_CPUSEQUENCER_DURATION0	((void *)(PMU_ALIVE_BASE + 0x22F0))
#define DIS_IRQ_APOLLO_CPU1_CPUSEQUENCER_DURATION1	((void *)(PMU_ALIVE_BASE + 0x22F4))
#define DIS_IRQ_APOLLO_CPU1_CPUSEQUENCER_DURATION2	((void *)(PMU_ALIVE_BASE + 0x22F8))
#define DIS_IRQ_APOLLO_CPU1_CPUSEQUENCER_DURATION3	((void *)(PMU_ALIVE_BASE + 0x22FC))
#define APOLLO_CPU2_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2300))
#define APOLLO_CPU2_STATUS	((void *)(PMU_ALIVE_BASE + 0x2304))
#define APOLLO_CPU2_OPTION	((void *)(PMU_ALIVE_BASE + 0x2308))
#define APOLLO_CPU2_RESET	((void *)(PMU_ALIVE_BASE + 0x230C))
#define APOLLO_CPU2_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2310))
#define APOLLO_CPU2_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2314))
#define APOLLO_CPU2_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2318))
#define APOLLO_CPU2_DURATION3	((void *)(PMU_ALIVE_BASE + 0x231C))
#define DIS_IRQ_APOLLO_CPU2_LOCAL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2320))
#define DIS_IRQ_APOLLO_CPU2_LOCAL_STATUS	((void *)(PMU_ALIVE_BASE + 0x2324))
#define DIS_IRQ_APOLLO_CPU2_LOCAL_OPTION	((void *)(PMU_ALIVE_BASE + 0x2328))
#define DIS_IRQ_APOLLO_CPU2_LOCAL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2330))
#define DIS_IRQ_APOLLO_CPU2_LOCAL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2334))
#define DIS_IRQ_APOLLO_CPU2_LOCAL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2338))
#define DIS_IRQ_APOLLO_CPU2_LOCAL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x233C))
#define DIS_IRQ_APOLLO_CPU2_CENTRAL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2340))
#define DIS_IRQ_APOLLO_CPU2_CENTRAL_STATUS	((void *)(PMU_ALIVE_BASE + 0x2344))
#define DIS_IRQ_APOLLO_CPU2_CENTRAL_OPTION	((void *)(PMU_ALIVE_BASE + 0x2348))
#define DIS_IRQ_APOLLO_CPU2_CENTRAL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2350))
#define DIS_IRQ_APOLLO_CPU2_CENTRAL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2354))
#define DIS_IRQ_APOLLO_CPU2_CENTRAL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2358))
#define DIS_IRQ_APOLLO_CPU2_CENTRAL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x235C))
#define DIS_IRQ_APOLLO_CPU2_CPUSEQUENCER_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2360))
#define DIS_IRQ_APOLLO_CPU2_CPUSEQUENCER_STATUS	((void *)(PMU_ALIVE_BASE + 0x2364))
#define DIS_IRQ_APOLLO_CPU2_CPUSEQUENCER_OPTION	((void *)(PMU_ALIVE_BASE + 0x2368))
#define DIS_IRQ_APOLLO_CPU2_CPUSEQUENCER_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2370))
#define DIS_IRQ_APOLLO_CPU2_CPUSEQUENCER_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2374))
#define DIS_IRQ_APOLLO_CPU2_CPUSEQUENCER_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2378))
#define DIS_IRQ_APOLLO_CPU2_CPUSEQUENCER_DURATION3	((void *)(PMU_ALIVE_BASE + 0x237C))
#define APOLLO_CPU3_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2380))
#define APOLLO_CPU3_STATUS	((void *)(PMU_ALIVE_BASE + 0x2384))
#define APOLLO_CPU3_OPTION	((void *)(PMU_ALIVE_BASE + 0x2388))
#define APOLLO_CPU3_RESET	((void *)(PMU_ALIVE_BASE + 0x238C))
#define APOLLO_CPU3_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2390))
#define APOLLO_CPU3_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2394))
#define APOLLO_CPU3_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2398))
#define APOLLO_CPU3_DURATION3	((void *)(PMU_ALIVE_BASE + 0x239C))
#define DIS_IRQ_APOLLO_CPU3_LOCAL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x23A0))
#define DIS_IRQ_APOLLO_CPU3_LOCAL_STATUS	((void *)(PMU_ALIVE_BASE + 0x23A4))
#define DIS_IRQ_APOLLO_CPU3_LOCAL_OPTION	((void *)(PMU_ALIVE_BASE + 0x23A8))
#define DIS_IRQ_APOLLO_CPU3_LOCAL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x23B0))
#define DIS_IRQ_APOLLO_CPU3_LOCAL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x23B4))
#define DIS_IRQ_APOLLO_CPU3_LOCAL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x23B8))
#define DIS_IRQ_APOLLO_CPU3_LOCAL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x23BC))
#define DIS_IRQ_APOLLO_CPU3_CENTRAL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x23C0))
#define DIS_IRQ_APOLLO_CPU3_CENTRAL_STATUS	((void *)(PMU_ALIVE_BASE + 0x23C4))
#define DIS_IRQ_APOLLO_CPU3_CENTRAL_OPTION	((void *)(PMU_ALIVE_BASE + 0x23C8))
#define DIS_IRQ_APOLLO_CPU3_CENTRAL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x23D0))
#define DIS_IRQ_APOLLO_CPU3_CENTRAL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x23D4))
#define DIS_IRQ_APOLLO_CPU3_CENTRAL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x23D8))
#define DIS_IRQ_APOLLO_CPU3_CENTRAL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x23DC))
#define DIS_IRQ_APOLLO_CPU3_CPUSEQUENCER_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x23E0))
#define DIS_IRQ_APOLLO_CPU3_CPUSEQUENCER_STATUS	((void *)(PMU_ALIVE_BASE + 0x23E4))
#define DIS_IRQ_APOLLO_CPU3_CPUSEQUENCER_OPTION	((void *)(PMU_ALIVE_BASE + 0x23E8))
#define DIS_IRQ_APOLLO_CPU3_CPUSEQUENCER_DURATION0	((void *)(PMU_ALIVE_BASE + 0x23F0))
#define DIS_IRQ_APOLLO_CPU3_CPUSEQUENCER_DURATION1	((void *)(PMU_ALIVE_BASE + 0x23F4))
#define DIS_IRQ_APOLLO_CPU3_CPUSEQUENCER_DURATION2	((void *)(PMU_ALIVE_BASE + 0x23F8))
#define DIS_IRQ_APOLLO_CPU3_CPUSEQUENCER_DURATION3	((void *)(PMU_ALIVE_BASE + 0x23FC))
#define MNGS_NONCPU_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2400))
#define MNGS_NONCPU_STATUS	((void *)(PMU_ALIVE_BASE + 0x2404))
#define MNGS_NONCPU_OPTION	((void *)(PMU_ALIVE_BASE + 0x2408))
#define MNGS_NONCPU_RESET	((void *)(PMU_ALIVE_BASE + 0x240C))
#define MNGS_NONCPU_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2410))
#define MNGS_NONCPU_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2414))
#define MNGS_NONCPU_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2418))
#define MNGS_NONCPU_DURATION3	((void *)(PMU_ALIVE_BASE + 0x241C))
#define APOLLO_NONCPU_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2420))
#define APOLLO_NONCPU_STATUS	((void *)(PMU_ALIVE_BASE + 0x2424))
#define APOLLO_NONCPU_OPTION	((void *)(PMU_ALIVE_BASE + 0x2428))
#define APOLLO_NONCPU_RESET	((void *)(PMU_ALIVE_BASE + 0x242C))
#define APOLLO_NONCPU_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2430))
#define APOLLO_NONCPU_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2434))
#define APOLLO_NONCPU_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2438))
#define APOLLO_NONCPU_DURATION3	((void *)(PMU_ALIVE_BASE + 0x243C))
#define MNGS_DBG_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2440))
#define MNGS_DBG_STATUS	((void *)(PMU_ALIVE_BASE + 0x2444))
#define MNGS_DBG_OPTION	((void *)(PMU_ALIVE_BASE + 0x2448))
#define MNGS_DBG_RESET	((void *)(PMU_ALIVE_BASE + 0x244C))
#define MNGS_DBG_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2450))
#define MNGS_DBG_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2454))
#define MNGS_DBG_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2458))
#define MNGS_DBG_DURATION3	((void *)(PMU_ALIVE_BASE + 0x245C))
#define MNGS_CPUSEQUENCER_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2480))
#define MNGS_CPUSEQUENCER_STATUS	((void *)(PMU_ALIVE_BASE + 0x2484))
#define MNGS_CPUSEQUENCER_OPTION	((void *)(PMU_ALIVE_BASE + 0x2488))
#define MNGS_CPUSEQUENCER_RESET	((void *)(PMU_ALIVE_BASE + 0x248C))
#define MNGS_CPUSEQUENCER_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2490))
#define MNGS_CPUSEQUENCER_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2494))
#define MNGS_CPUSEQUENCER_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2498))
#define MNGS_CPUSEQUENCER_DURATION3	((void *)(PMU_ALIVE_BASE + 0x249C))
#define APOLLO_CPUSEQUENCER_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x24A0))
#define APOLLO_CPUSEQUENCER_STATUS	((void *)(PMU_ALIVE_BASE + 0x24A4))
#define APOLLO_CPUSEQUENCER_OPTION	((void *)(PMU_ALIVE_BASE + 0x24A8))
#define APOLLO_CPUSEQUENCER_RESET	((void *)(PMU_ALIVE_BASE + 0x24AC))
#define APOLLO_CPUSEQUENCER_DURATION0	((void *)(PMU_ALIVE_BASE + 0x24B0))
#define APOLLO_CPUSEQUENCER_DURATION1	((void *)(PMU_ALIVE_BASE + 0x24B4))
#define APOLLO_CPUSEQUENCER_DURATION2	((void *)(PMU_ALIVE_BASE + 0x24B8))
#define APOLLO_CPUSEQUENCER_DURATION3	((void *)(PMU_ALIVE_BASE + 0x24BC))
#define CORTEXM3_APM_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2500))
#define CORTEXM3_APM_STATUS	((void *)(PMU_ALIVE_BASE + 0x2504))
#define CORTEXM3_APM_OPTION	((void *)(PMU_ALIVE_BASE + 0x2508))
#define CORTEXM3_APM_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2510))
#define CORTEXM3_APM_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2514))
#define CORTEXM3_APM_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2518))
#define CORTEXM3_APM_DURATION3	((void *)(PMU_ALIVE_BASE + 0x251C))
#define A7IS_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2580))
#define A7IS_STATUS	((void *)(PMU_ALIVE_BASE + 0x2584))
#define A7IS_OPTION	((void *)(PMU_ALIVE_BASE + 0x2588))
#define A7IS_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2590))
#define A7IS_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2594))
#define A7IS_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2598))
#define A7IS_DURATION3	((void *)(PMU_ALIVE_BASE + 0x259C))
#define DIS_IRQ_A7IS_LOCAL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x25A0))
#define DIS_IRQ_A7IS_LOCAL_STATUS	((void *)(PMU_ALIVE_BASE + 0x25A4))
#define DIS_IRQ_A7IS_LOCAL_OPTION	((void *)(PMU_ALIVE_BASE + 0x25A8))
#define DIS_IRQ_A7IS_LOCAL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x25B0))
#define DIS_IRQ_A7IS_LOCAL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x25B4))
#define DIS_IRQ_A7IS_LOCAL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x25B8))
#define DIS_IRQ_A7IS_LOCAL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x25BC))
#define DIS_IRQ_A7IS_CENTRAL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x25C0))
#define DIS_IRQ_A7IS_CENTRAL_STATUS	((void *)(PMU_ALIVE_BASE + 0x25C4))
#define DIS_IRQ_A7IS_CENTRAL_OPTION	((void *)(PMU_ALIVE_BASE + 0x25C8))
#define DIS_IRQ_A7IS_CENTRAL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x25D0))
#define DIS_IRQ_A7IS_CENTRAL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x25D4))
#define DIS_IRQ_A7IS_CENTRAL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x25D8))
#define DIS_IRQ_A7IS_CENTRAL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x25DC))
#define MNGS_L2_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2600))
#define MNGS_L2_STATUS	((void *)(PMU_ALIVE_BASE + 0x2604))
#define MNGS_L2_OPTION	((void *)(PMU_ALIVE_BASE + 0x2608))
#define MNGS_L2_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2610))
#define MNGS_L2_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2614))
#define MNGS_L2_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2618))
#define MNGS_L2_DURATION3	((void *)(PMU_ALIVE_BASE + 0x261C))
#define APOLLO_L2_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2620))
#define APOLLO_L2_STATUS	((void *)(PMU_ALIVE_BASE + 0x2624))
#define APOLLO_L2_OPTION	((void *)(PMU_ALIVE_BASE + 0x2628))
#define APOLLO_L2_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2630))
#define APOLLO_L2_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2634))
#define APOLLO_L2_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2638))
#define APOLLO_L2_DURATION3	((void *)(PMU_ALIVE_BASE + 0x263C))
#define MNGS_L2_PWR_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2680))
#define MNGS_L2_PWR_STATUS	((void *)(PMU_ALIVE_BASE + 0x2684))
#define MNGS_L2_PWR_OPTION	((void *)(PMU_ALIVE_BASE + 0x2688))
#define MNGS_L2_PWR_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2690))
#define MNGS_L2_PWR_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2694))
#define MNGS_L2_PWR_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2698))
#define MNGS_L2_PWR_DURATION3	((void *)(PMU_ALIVE_BASE + 0x269C))
#define CLKSTOP_CMU_TOP_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2800))
#define CLKSTOP_CMU_TOP_STATUS	((void *)(PMU_ALIVE_BASE + 0x2804))
#define CLKSTOP_CMU_TOP_OPTION	((void *)(PMU_ALIVE_BASE + 0x2808))
#define CLKSTOP_CMU_TOP_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2810))
#define CLKSTOP_CMU_TOP_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2814))
#define CLKSTOP_CMU_TOP_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2818))
#define CLKSTOP_CMU_TOP_DURATION3	((void *)(PMU_ALIVE_BASE + 0x281C))
#define CLKRUN_CMU_TOP_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2820))
#define CLKRUN_CMU_TOP_STATUS	((void *)(PMU_ALIVE_BASE + 0x2824))
#define CLKRUN_CMU_TOP_OPTION	((void *)(PMU_ALIVE_BASE + 0x2828))
#define CLKRUN_CMU_TOP_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2830))
#define CLKRUN_CMU_TOP_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2834))
#define CLKRUN_CMU_TOP_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2838))
#define CLKRUN_CMU_TOP_DURATION3	((void *)(PMU_ALIVE_BASE + 0x283C))
#define RETENTION_CMU_TOP_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2840))
#define RETENTION_CMU_TOP_STATUS	((void *)(PMU_ALIVE_BASE + 0x2844))
#define RETENTION_CMU_TOP_OPTION	((void *)(PMU_ALIVE_BASE + 0x2848))
#define RETENTION_CMU_TOP_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2850))
#define RETENTION_CMU_TOP_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2854))
#define RETENTION_CMU_TOP_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2858))
#define RETENTION_CMU_TOP_DURATION3	((void *)(PMU_ALIVE_BASE + 0x285C))
#define RESET_CMU_TOP_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2860))
#define RESET_CMU_TOP_STATUS	((void *)(PMU_ALIVE_BASE + 0x2864))
#define RESET_CMU_TOP_OPTION	((void *)(PMU_ALIVE_BASE + 0x2868))
#define RESET_CMU_TOP_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2870))
#define RESET_CMU_TOP_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2874))
#define RESET_CMU_TOP_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2878))
#define RESET_CMU_TOP_DURATION3	((void *)(PMU_ALIVE_BASE + 0x287C))
#define RESET_CPUCLKSTOP_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x28E0))
#define RESET_CPUCLKSTOP_STATUS	((void *)(PMU_ALIVE_BASE + 0x28E4))
#define RESET_CPUCLKSTOP_OPTION	((void *)(PMU_ALIVE_BASE + 0x28E8))
#define RESET_CPUCLKSTOP_DURATION0	((void *)(PMU_ALIVE_BASE + 0x28F0))
#define RESET_CPUCLKSTOP_DURATION1	((void *)(PMU_ALIVE_BASE + 0x28F4))
#define RESET_CPUCLKSTOP_DURATION2	((void *)(PMU_ALIVE_BASE + 0x28F8))
#define RESET_CPUCLKSTOP_DURATION3	((void *)(PMU_ALIVE_BASE + 0x28FC))
#define CLKSTOP_CMU_MIF_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2900))
#define CLKSTOP_CMU_MIF_STATUS	((void *)(PMU_ALIVE_BASE + 0x2904))
#define CLKSTOP_CMU_MIF_OPTION	((void *)(PMU_ALIVE_BASE + 0x2908))
#define CLKSTOP_CMU_MIF_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2910))
#define CLKSTOP_CMU_MIF_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2914))
#define CLKSTOP_CMU_MIF_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2918))
#define CLKSTOP_CMU_MIF_DURATION3	((void *)(PMU_ALIVE_BASE + 0x291C))
#define CLKRUN_CMU_MIF_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2920))
#define CLKRUN_CMU_MIF_STATUS	((void *)(PMU_ALIVE_BASE + 0x2924))
#define CLKRUN_CMU_MIF_OPTION	((void *)(PMU_ALIVE_BASE + 0x2928))
#define CLKRUN_CMU_MIF_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2930))
#define CLKRUN_CMU_MIF_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2934))
#define CLKRUN_CMU_MIF_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2938))
#define CLKRUN_CMU_MIF_DURATION3	((void *)(PMU_ALIVE_BASE + 0x293C))
#define RETENTION_CMU_MIF_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2940))
#define RETENTION_CMU_MIF_STATUS	((void *)(PMU_ALIVE_BASE + 0x2944))
#define RETENTION_CMU_MIF_OPTION	((void *)(PMU_ALIVE_BASE + 0x2948))
#define RETENTION_CMU_MIF_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2950))
#define RETENTION_CMU_MIF_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2954))
#define RETENTION_CMU_MIF_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2958))
#define RETENTION_CMU_MIF_DURATION3	((void *)(PMU_ALIVE_BASE + 0x295C))
#define RESET_CMU_MIF_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2960))
#define RESET_CMU_MIF_STATUS	((void *)(PMU_ALIVE_BASE + 0x2964))
#define RESET_CMU_MIF_OPTION	((void *)(PMU_ALIVE_BASE + 0x2968))
#define RESET_CMU_MIF_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2970))
#define RESET_CMU_MIF_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2974))
#define RESET_CMU_MIF_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2978))
#define RESET_CMU_MIF_DURATION3	((void *)(PMU_ALIVE_BASE + 0x297C))
#define DDRPHY_CLKSTOP_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2980))
#define DDRPHY_CLKSTOP_STATUS	((void *)(PMU_ALIVE_BASE + 0x2984))
#define DDRPHY_CLKSTOP_OPTION	((void *)(PMU_ALIVE_BASE + 0x2988))
#define DDRPHY_CLKSTOP_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2990))
#define DDRPHY_CLKSTOP_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2994))
#define DDRPHY_CLKSTOP_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2998))
#define DDRPHY_CLKSTOP_DURATION3	((void *)(PMU_ALIVE_BASE + 0x299C))
#define DDRPHY_ISO_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x29A0))
#define DDRPHY_ISO_STATUS	((void *)(PMU_ALIVE_BASE + 0x29A4))
#define DDRPHY_ISO_OPTION	((void *)(PMU_ALIVE_BASE + 0x29A8))
#define DDRPHY_ISO_DURATION0	((void *)(PMU_ALIVE_BASE + 0x29B0))
#define DDRPHY_ISO_DURATION1	((void *)(PMU_ALIVE_BASE + 0x29B4))
#define DDRPHY_ISO_DURATION2	((void *)(PMU_ALIVE_BASE + 0x29B8))
#define DDRPHY_ISO_DURATION3	((void *)(PMU_ALIVE_BASE + 0x29BC))
#define DDRPHY_SOC2_ISO_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x29C0))
#define DDRPHY_SOC2_ISO_STATUS	((void *)(PMU_ALIVE_BASE + 0x29C4))
#define DDRPHY_SOC2_ISO_OPTION	((void *)(PMU_ALIVE_BASE + 0x29C8))
#define DDRPHY_SOC2_ISO_DURATION0	((void *)(PMU_ALIVE_BASE + 0x29D0))
#define DDRPHY_SOC2_ISO_DURATION1	((void *)(PMU_ALIVE_BASE + 0x29D4))
#define DDRPHY_SOC2_ISO_DURATION2	((void *)(PMU_ALIVE_BASE + 0x29D8))
#define DDRPHY_SOC2_ISO_DURATION3	((void *)(PMU_ALIVE_BASE + 0x29DC))
#define DDRPHY_DLL_CLK_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x29E0))
#define DDRPHY_DLL_CLK_STATUS	((void *)(PMU_ALIVE_BASE + 0x29E4))
#define DDRPHY_DLL_CLK_OPTION	((void *)(PMU_ALIVE_BASE + 0x29E8))
#define DDRPHY_DLL_CLK_DURATION0	((void *)(PMU_ALIVE_BASE + 0x29F0))
#define DDRPHY_DLL_CLK_DURATION1	((void *)(PMU_ALIVE_BASE + 0x29F4))
#define DDRPHY_DLL_CLK_DURATION2	((void *)(PMU_ALIVE_BASE + 0x29F8))
#define DDRPHY_DLL_CLK_DURATION3	((void *)(PMU_ALIVE_BASE + 0x29FC))
#define DISABLE_PLL_CMU_TOP_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2A00))
#define DISABLE_PLL_CMU_TOP_STATUS	((void *)(PMU_ALIVE_BASE + 0x2A04))
#define DISABLE_PLL_CMU_TOP_OPTION	((void *)(PMU_ALIVE_BASE + 0x2A08))
#define DISABLE_PLL_CMU_TOP_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2A10))
#define DISABLE_PLL_CMU_TOP_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2A14))
#define DISABLE_PLL_CMU_TOP_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2A18))
#define DISABLE_PLL_CMU_TOP_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2A1C))
#define DISABLE_PLL_AUD_PLL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2A20))
#define DISABLE_PLL_AUD_PLL_STATUS	((void *)(PMU_ALIVE_BASE + 0x2A24))
#define DISABLE_PLL_AUD_PLL_OPTION	((void *)(PMU_ALIVE_BASE + 0x2A28))
#define DISABLE_PLL_AUD_PLL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2A30))
#define DISABLE_PLL_AUD_PLL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2A34))
#define DISABLE_PLL_AUD_PLL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2A38))
#define DISABLE_PLL_AUD_PLL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2A3C))
#define DISABLE_PLL_CMU_MIF_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2B00))
#define DISABLE_PLL_CMU_MIF_STATUS	((void *)(PMU_ALIVE_BASE + 0x2B04))
#define DISABLE_PLL_CMU_MIF_OPTION	((void *)(PMU_ALIVE_BASE + 0x2B08))
#define DISABLE_PLL_CMU_MIF_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2B10))
#define DISABLE_PLL_CMU_MIF_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2B14))
#define DISABLE_PLL_CMU_MIF_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2B18))
#define DISABLE_PLL_CMU_MIF_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2B1C))
#define RESET_AHEAD_CP_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2B80))
#define RESET_AHEAD_CP_STATUS	((void *)(PMU_ALIVE_BASE + 0x2B84))
#define RESET_AHEAD_CP_OPTION	((void *)(PMU_ALIVE_BASE + 0x2B88))
#define RESET_AHEAD_CP_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2B90))
#define RESET_AHEAD_CP_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2B94))
#define RESET_AHEAD_CP_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2B98))
#define RESET_AHEAD_CP_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2B9C))
#define TOP_BUS_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2C00))
#define TOP_BUS_STATUS	((void *)(PMU_ALIVE_BASE + 0x2C04))
#define TOP_BUS_OPTION	((void *)(PMU_ALIVE_BASE + 0x2C08))
#define TOP_BUS_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2C10))
#define TOP_BUS_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2C14))
#define TOP_BUS_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2C18))
#define TOP_BUS_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2C1C))
#define TOP_RETENTION_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2C20))
#define TOP_RETENTION_STATUS	((void *)(PMU_ALIVE_BASE + 0x2C24))
#define TOP_RETENTION_OPTION	((void *)(PMU_ALIVE_BASE + 0x2C28))
#define TOP_RETENTION_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2C30))
#define TOP_RETENTION_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2C34))
#define TOP_RETENTION_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2C38))
#define TOP_RETENTION_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2C3C))
#define TOP_PWR_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2C40))
#define TOP_PWR_STATUS	((void *)(PMU_ALIVE_BASE + 0x2C44))
#define TOP_PWR_OPTION	((void *)(PMU_ALIVE_BASE + 0x2C48))
#define TOP_PWR_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2C50))
#define TOP_PWR_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2C54))
#define TOP_PWR_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2C58))
#define TOP_PWR_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2C5C))
#define CMU_PWR_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2C60))
#define CMU_PWR_STATUS	((void *)(PMU_ALIVE_BASE + 0x2C60))
#define CMU_PWR_OPTION	((void *)(PMU_ALIVE_BASE + 0x2C60))
#define CMU_PWR_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2C60))
#define CMU_PWR_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2C60))
#define CMU_PWR_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2C60))
#define CMU_PWR_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2C60))
#define TOP_BUS_MIF_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2C80))
#define TOP_BUS_MIF_STATUS	((void *)(PMU_ALIVE_BASE + 0x2C84))
#define TOP_BUS_MIF_OPTION	((void *)(PMU_ALIVE_BASE + 0x2C88))
#define TOP_BUS_MIF_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2C90))
#define TOP_BUS_MIF_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2C94))
#define TOP_BUS_MIF_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2C98))
#define TOP_BUS_MIF_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2C9C))
#define TOP_RETENTION_MIF_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2CA0))
#define TOP_RETENTION_MIF_STATUS	((void *)(PMU_ALIVE_BASE + 0x2CA4))
#define TOP_RETENTION_MIF_OPTION	((void *)(PMU_ALIVE_BASE + 0x2CA8))
#define TOP_RETENTION_MIF_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2CB0))
#define TOP_RETENTION_MIF_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2CB4))
#define TOP_RETENTION_MIF_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2CB8))
#define TOP_RETENTION_MIF_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2CBC))
#define TOP_PWR_MIF_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2CC0))
#define TOP_PWR_MIF_STATUS	((void *)(PMU_ALIVE_BASE + 0x2CC4))
#define TOP_PWR_MIF_OPTION	((void *)(PMU_ALIVE_BASE + 0x2CC8))
#define TOP_PWR_MIF_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2CD0))
#define TOP_PWR_MIF_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2CD4))
#define TOP_PWR_MIF_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2CD8))
#define TOP_PWR_MIF_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2CDC))
#define PSCDC_MIF_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2CE0))
#define PSCDC_MIF_STATUS	((void *)(PMU_ALIVE_BASE + 0x2CE4))
#define PSCDC_MIF_OPTION	((void *)(PMU_ALIVE_BASE + 0x2CE8))
#define PSCDC_MIF_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2CF0))
#define PSCDC_MIF_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2CF4))
#define PSCDC_MIF_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2CF8))
#define PSCDC_MIF_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2CFC))
#define LOGIC_RESET_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2D00))
#define LOGIC_RESET_STATUS	((void *)(PMU_ALIVE_BASE + 0x2D04))
#define LOGIC_RESET_OPTION	((void *)(PMU_ALIVE_BASE + 0x2D08))
#define LOGIC_RESET_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2D10))
#define LOGIC_RESET_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2D14))
#define LOGIC_RESET_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2D18))
#define LOGIC_RESET_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2D1C))
#define OSCCLK_GATE_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2D20))
#define OSCCLK_GATE_STATUS	((void *)(PMU_ALIVE_BASE + 0x2D24))
#define OSCCLK_GATE_OPTION	((void *)(PMU_ALIVE_BASE + 0x2D28))
#define OSCCLK_GATE_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2D30))
#define OSCCLK_GATE_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2D34))
#define OSCCLK_GATE_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2D38))
#define OSCCLK_GATE_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2D3C))
#define SLEEP_RESET_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2D40))
#define SLEEP_RESET_STATUS	((void *)(PMU_ALIVE_BASE + 0x2D44))
#define SLEEP_RESET_OPTION	((void *)(PMU_ALIVE_BASE + 0x2D48))
#define SLEEP_RESET_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2D50))
#define SLEEP_RESET_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2D54))
#define SLEEP_RESET_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2D58))
#define SLEEP_RESET_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2D5C))
#define LOGIC_RESET_MIF_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2D80))
#define LOGIC_RESET_MIF_STATUS	((void *)(PMU_ALIVE_BASE + 0x2D84))
#define LOGIC_RESET_MIF_OPTION	((void *)(PMU_ALIVE_BASE + 0x2D88))
#define LOGIC_RESET_MIF_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2D90))
#define LOGIC_RESET_MIF_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2D94))
#define LOGIC_RESET_MIF_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2D98))
#define LOGIC_RESET_MIF_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2D9C))
#define OSCCLK_GATE_MIF_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2DA0))
#define OSCCLK_GATE_MIF_STATUS	((void *)(PMU_ALIVE_BASE + 0x2DA4))
#define OSCCLK_GATE_MIF_OPTION	((void *)(PMU_ALIVE_BASE + 0x2DA8))
#define OSCCLK_GATE_MIF_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2DB0))
#define OSCCLK_GATE_MIF_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2DB4))
#define OSCCLK_GATE_MIF_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2DB8))
#define OSCCLK_GATE_MIF_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2DBC))
#define SLEEP_RESET_MIF_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2DC0))
#define SLEEP_RESET_MIF_STATUS	((void *)(PMU_ALIVE_BASE + 0x2DC4))
#define SLEEP_RESET_MIF_OPTION	((void *)(PMU_ALIVE_BASE + 0x2DC8))
#define SLEEP_RESET_MIF_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2DD0))
#define SLEEP_RESET_MIF_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2DD4))
#define SLEEP_RESET_MIF_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2DD8))
#define SLEEP_RESET_MIF_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2DDC))
#define MEMORY_TOP_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2E00))
#define MEMORY_TOP_STATUS	((void *)(PMU_ALIVE_BASE + 0x2E04))
#define MEMORY_TOP_OPTION	((void *)(PMU_ALIVE_BASE + 0x2E08))
#define MEMORY_TOP_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2E10))
#define MEMORY_TOP_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2E14))
#define MEMORY_TOP_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2E18))
#define MEMORY_TOP_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2E1C))
#define CLEANY_BUS_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2E60))
#define CLEANY_BUS_STATUS	((void *)(PMU_ALIVE_BASE + 0x2E64))
#define CLEANY_BUS_OPTION	((void *)(PMU_ALIVE_BASE + 0x2E68))
#define CLEANY_BUS_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2E70))
#define CLEANY_BUS_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2E74))
#define CLEANY_BUS_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2E78))
#define CLEANY_BUS_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2E7C))
#define LOGIC_RESET_CP_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2E80))
#define LOGIC_RESET_CP_STATUS	((void *)(PMU_ALIVE_BASE + 0x2E84))
#define LOGIC_RESET_CP_OPTION	((void *)(PMU_ALIVE_BASE + 0x2E88))
#define LOGIC_RESET_CP_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2E90))
#define LOGIC_RESET_CP_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2E94))
#define LOGIC_RESET_CP_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2E98))
#define LOGIC_RESET_CP_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2E9C))
#define TCXO_GATE_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2EA0))
#define TCXO_GATE_STATUS	((void *)(PMU_ALIVE_BASE + 0x2EA4))
#define TCXO_GATE_OPTION	((void *)(PMU_ALIVE_BASE + 0x2EA8))
#define TCXO_GATE_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2EB0))
#define TCXO_GATE_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2EB4))
#define TCXO_GATE_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2EB8))
#define TCXO_GATE_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2EBC))
#define RESET_ASB_CP_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2EC0))
#define RESET_ASB_CP_STATUS	((void *)(PMU_ALIVE_BASE + 0x2EC4))
#define RESET_ASB_CP_OPTION	((void *)(PMU_ALIVE_BASE + 0x2EC8))
#define RESET_ASB_CP_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2ED0))
#define RESET_ASB_CP_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2ED4))
#define RESET_ASB_CP_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2ED8))
#define RESET_ASB_CP_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2EDC))
#define RESET_ASB_MIF_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2EE0))
#define RESET_ASB_MIF_STATUS	((void *)(PMU_ALIVE_BASE + 0x2EE4))
#define RESET_ASB_MIF_OPTION	((void *)(PMU_ALIVE_BASE + 0x2EE8))
#define RESET_ASB_MIF_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2EF0))
#define RESET_ASB_MIF_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2EF4))
#define RESET_ASB_MIF_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2EF8))
#define RESET_ASB_MIF_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2EFC))
#define MEMORY_IMEM_ALIVEIRAM_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2F00))
#define MEMORY_IMEM_ALIVEIRAM_STATUS	((void *)(PMU_ALIVE_BASE + 0x2F04))
#define MEMORY_IMEM_ALIVEIRAM_OPTION	((void *)(PMU_ALIVE_BASE + 0x2F08))
#define MEMORY_IMEM_ALIVEIRAM_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2F10))
#define MEMORY_IMEM_ALIVEIRAM_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2F14))
#define MEMORY_IMEM_ALIVEIRAM_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2F18))
#define MEMORY_IMEM_ALIVEIRAM_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2F1C))
#define MEMORY_MIF_TOP_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2F20))
#define MEMORY_MIF_TOP_STATUS	((void *)(PMU_ALIVE_BASE + 0x2F24))
#define MEMORY_MIF_TOP_OPTION	((void *)(PMU_ALIVE_BASE + 0x2F28))
#define MEMORY_MIF_TOP_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2F30))
#define MEMORY_MIF_TOP_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2F34))
#define MEMORY_MIF_TOP_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2F38))
#define MEMORY_MIF_TOP_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2F3C))
#define LOGIC_RESET_DDRPHY_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2F80))
#define LOGIC_RESET_DDRPHY_STATUS	((void *)(PMU_ALIVE_BASE + 0x2F84))
#define LOGIC_RESET_DDRPHY_OPTION	((void *)(PMU_ALIVE_BASE + 0x2F88))
#define LOGIC_RESET_DDRPHY_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2F90))
#define LOGIC_RESET_DDRPHY_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2F94))
#define LOGIC_RESET_DDRPHY_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2F98))
#define LOGIC_RESET_DDRPHY_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2F9C))
#define RETENTION_DDRPHY_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2FA0))
#define RETENTION_DDRPHY_STATUS	((void *)(PMU_ALIVE_BASE + 0x2FA4))
#define RETENTION_DDRPHY_OPTION	((void *)(PMU_ALIVE_BASE + 0x2FA8))
#define RETENTION_DDRPHY_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2FB0))
#define RETENTION_DDRPHY_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2FB4))
#define RETENTION_DDRPHY_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2FB8))
#define RETENTION_DDRPHY_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2FBC))
#define PWR_DDRPHY_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x2FE0))
#define PWR_DDRPHY_STATUS	((void *)(PMU_ALIVE_BASE + 0x2FE4))
#define PWR_DDRPHY_OPTION	((void *)(PMU_ALIVE_BASE + 0x2FE8))
#define PWR_DDRPHY_DURATION0	((void *)(PMU_ALIVE_BASE + 0x2FF0))
#define PWR_DDRPHY_DURATION1	((void *)(PMU_ALIVE_BASE + 0x2FF4))
#define PWR_DDRPHY_DURATION2	((void *)(PMU_ALIVE_BASE + 0x2FF8))
#define PWR_DDRPHY_DURATION3	((void *)(PMU_ALIVE_BASE + 0x2FFC))
#define PAD_RETENTION_LPDDR4_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3000))
#define PAD_RETENTION_LPDDR4_STATUS	((void *)(PMU_ALIVE_BASE + 0x3004))
#define PAD_RETENTION_LPDDR4_OPTION	((void *)(PMU_ALIVE_BASE + 0x3008))
#define PAD_RETENTION_LPDDR4_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3010))
#define PAD_RETENTION_LPDDR4_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3014))
#define PAD_RETENTION_LPDDR4_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3018))
#define PAD_RETENTION_LPDDR4_DURATION3	((void *)(PMU_ALIVE_BASE + 0x301C))
#define PAD_RETENTION_AUD_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3020))
#define PAD_RETENTION_AUD_STATUS	((void *)(PMU_ALIVE_BASE + 0x3024))
#define PAD_RETENTION_AUD_OPTION	((void *)(PMU_ALIVE_BASE + 0x3028))
#define PAD_RETENTION_AUD_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3030))
#define PAD_RETENTION_AUD_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3034))
#define PAD_RETENTION_AUD_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3038))
#define PAD_RETENTION_AUD_DURATION3	((void *)(PMU_ALIVE_BASE + 0x303C))
#define PAD_RETENTION_JTAG_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3040))
#define PAD_RETENTION_JTAG_STATUS	((void *)(PMU_ALIVE_BASE + 0x3044))
#define PAD_RETENTION_JTAG_OPTION	((void *)(PMU_ALIVE_BASE + 0x3048))
#define PAD_RETENTION_JTAG_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3050))
#define PAD_RETENTION_JTAG_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3054))
#define PAD_RETENTION_JTAG_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3058))
#define PAD_RETENTION_JTAG_DURATION3	((void *)(PMU_ALIVE_BASE + 0x305C))
#define PAD_RETENTION_PCIE_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3060))
#define PAD_RETENTION_PCIE_STATUS	((void *)(PMU_ALIVE_BASE + 0x3064))
#define PAD_RETENTION_PCIE_OPTION	((void *)(PMU_ALIVE_BASE + 0x3068))
#define PAD_RETENTION_PCIE_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3070))
#define PAD_RETENTION_PCIE_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3074))
#define PAD_RETENTION_PCIE_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3078))
#define PAD_RETENTION_PCIE_DURATION3	((void *)(PMU_ALIVE_BASE + 0x307C))
#define PAD_RETENTION_UFS_CARD_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3080))
#define PAD_RETENTION_UFS_CARD_STATUS	((void *)(PMU_ALIVE_BASE + 0x3084))
#define PAD_RETENTION_UFS_CARD_OPTION	((void *)(PMU_ALIVE_BASE + 0x3088))
#define PAD_RETENTION_UFS_CARD_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3090))
#define PAD_RETENTION_UFS_CARD_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3094))
#define PAD_RETENTION_UFS_CARD_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3098))
#define PAD_RETENTION_UFS_CARD_DURATION3	((void *)(PMU_ALIVE_BASE + 0x309C))
#define PAD_RETENTION_MMC2_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x30C0))
#define PAD_RETENTION_MMC2_STATUS	((void *)(PMU_ALIVE_BASE + 0x30C4))
#define PAD_RETENTION_MMC2_OPTION	((void *)(PMU_ALIVE_BASE + 0x30C8))
#define PAD_RETENTION_MMC2_DURATION0	((void *)(PMU_ALIVE_BASE + 0x30D0))
#define PAD_RETENTION_MMC2_DURATION1	((void *)(PMU_ALIVE_BASE + 0x30D4))
#define PAD_RETENTION_MMC2_DURATION2	((void *)(PMU_ALIVE_BASE + 0x30D8))
#define PAD_RETENTION_MMC2_DURATION3	((void *)(PMU_ALIVE_BASE + 0x30DC))
#define PAD_RETENTION_TOP_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3100))
#define PAD_RETENTION_TOP_STATUS	((void *)(PMU_ALIVE_BASE + 0x3104))
#define PAD_RETENTION_TOP_OPTION	((void *)(PMU_ALIVE_BASE + 0x3108))
#define PAD_RETENTION_TOP_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3110))
#define PAD_RETENTION_TOP_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3114))
#define PAD_RETENTION_TOP_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3118))
#define PAD_RETENTION_TOP_DURATION3	((void *)(PMU_ALIVE_BASE + 0x311C))
#define PAD_RETENTION_UART_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3120))
#define PAD_RETENTION_UART_STATUS	((void *)(PMU_ALIVE_BASE + 0x3124))
#define PAD_RETENTION_UART_OPTION	((void *)(PMU_ALIVE_BASE + 0x3128))
#define PAD_RETENTION_UART_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3130))
#define PAD_RETENTION_UART_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3134))
#define PAD_RETENTION_UART_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3138))
#define PAD_RETENTION_UART_DURATION3	((void *)(PMU_ALIVE_BASE + 0x313C))
#define PAD_RETENTION_MMC0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3140))
#define PAD_RETENTION_MMC0_STATUS	((void *)(PMU_ALIVE_BASE + 0x3144))
#define PAD_RETENTION_MMC0_OPTION	((void *)(PMU_ALIVE_BASE + 0x3148))
#define PAD_RETENTION_MMC0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3150))
#define PAD_RETENTION_MMC0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3154))
#define PAD_RETENTION_MMC0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3158))
#define PAD_RETENTION_MMC0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x315C))
#define PAD_RETENTION_EBIA_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3180))
#define PAD_RETENTION_EBIA_STATUS	((void *)(PMU_ALIVE_BASE + 0x3184))
#define PAD_RETENTION_EBIA_OPTION	((void *)(PMU_ALIVE_BASE + 0x3188))
#define PAD_RETENTION_EBIA_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3190))
#define PAD_RETENTION_EBIA_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3194))
#define PAD_RETENTION_EBIA_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3198))
#define PAD_RETENTION_EBIA_DURATION3	((void *)(PMU_ALIVE_BASE + 0x319C))
#define PAD_RETENTION_EBIB_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x31A0))
#define PAD_RETENTION_EBIB_STATUS	((void *)(PMU_ALIVE_BASE + 0x31A4))
#define PAD_RETENTION_EBIB_OPTION	((void *)(PMU_ALIVE_BASE + 0x31A8))
#define PAD_RETENTION_EBIB_DURATION0	((void *)(PMU_ALIVE_BASE + 0x31B0))
#define PAD_RETENTION_EBIB_DURATION1	((void *)(PMU_ALIVE_BASE + 0x31B4))
#define PAD_RETENTION_EBIB_DURATION2	((void *)(PMU_ALIVE_BASE + 0x31B8))
#define PAD_RETENTION_EBIB_DURATION3	((void *)(PMU_ALIVE_BASE + 0x31BC))
#define PAD_RETENTION_SPI_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x31C0))
#define PAD_RETENTION_SPI_STATUS	((void *)(PMU_ALIVE_BASE + 0x31C4))
#define PAD_RETENTION_SPI_OPTION	((void *)(PMU_ALIVE_BASE + 0x31C8))
#define PAD_RETENTION_SPI_DURATION0	((void *)(PMU_ALIVE_BASE + 0x31D0))
#define PAD_RETENTION_SPI_DURATION1	((void *)(PMU_ALIVE_BASE + 0x31D4))
#define PAD_RETENTION_SPI_DURATION2	((void *)(PMU_ALIVE_BASE + 0x31D8))
#define PAD_RETENTION_SPI_DURATION3	((void *)(PMU_ALIVE_BASE + 0x31DC))
#define PAD_RETENTION_MIF_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x31E0))
#define PAD_RETENTION_MIF_STATUS	((void *)(PMU_ALIVE_BASE + 0x31E4))
#define PAD_RETENTION_MIF_OPTION	((void *)(PMU_ALIVE_BASE + 0x31E8))
#define PAD_RETENTION_MIF_DURATION0	((void *)(PMU_ALIVE_BASE + 0x31F0))
#define PAD_RETENTION_MIF_DURATION1	((void *)(PMU_ALIVE_BASE + 0x31F4))
#define PAD_RETENTION_MIF_DURATION2	((void *)(PMU_ALIVE_BASE + 0x31F8))
#define PAD_RETENTION_MIF_DURATION3	((void *)(PMU_ALIVE_BASE + 0x31FC))
#define PAD_ISOLATION_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3200))
#define PAD_ISOLATION_STATUS	((void *)(PMU_ALIVE_BASE + 0x3204))
#define PAD_ISOLATION_OPTION	((void *)(PMU_ALIVE_BASE + 0x3208))
#define PAD_ISOLATION_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3210))
#define PAD_ISOLATION_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3214))
#define PAD_ISOLATION_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3218))
#define PAD_ISOLATION_DURATION3	((void *)(PMU_ALIVE_BASE + 0x321C))
#define PAD_RETENTION_BOOTLDO_0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3240))
#define PAD_RETENTION_BOOTLDO_0_STATUS	((void *)(PMU_ALIVE_BASE + 0x3244))
#define PAD_RETENTION_BOOTLDO_0_OPTION	((void *)(PMU_ALIVE_BASE + 0x3248))
#define PAD_RETENTION_BOOTLDO_0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3250))
#define PAD_RETENTION_BOOTLDO_0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3254))
#define PAD_RETENTION_BOOTLDO_0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3258))
#define PAD_RETENTION_BOOTLDO_0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x325C))
#define PAD_RETENTION_UFS_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3260))
#define PAD_RETENTION_UFS_STATUS	((void *)(PMU_ALIVE_BASE + 0x3264))
#define PAD_RETENTION_UFS_OPTION	((void *)(PMU_ALIVE_BASE + 0x3268))
#define PAD_RETENTION_UFS_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3270))
#define PAD_RETENTION_UFS_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3274))
#define PAD_RETENTION_UFS_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3278))
#define PAD_RETENTION_UFS_DURATION3	((void *)(PMU_ALIVE_BASE + 0x327C))
#define PAD_ISOLATION_MIF_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3280))
#define PAD_ISOLATION_MIF_STATUS	((void *)(PMU_ALIVE_BASE + 0x3284))
#define PAD_ISOLATION_MIF_OPTION	((void *)(PMU_ALIVE_BASE + 0x3288))
#define PAD_ISOLATION_MIF_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3290))
#define PAD_ISOLATION_MIF_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3294))
#define PAD_ISOLATION_MIF_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3298))
#define PAD_ISOLATION_MIF_DURATION3	((void *)(PMU_ALIVE_BASE + 0x329C))
#define PAD_RETENTION_USB_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x32A0))
#define PAD_RETENTION_USB_STATUS	((void *)(PMU_ALIVE_BASE + 0x32A4))
#define PAD_RETENTION_USB_OPTION	((void *)(PMU_ALIVE_BASE + 0x32A8))
#define PAD_RETENTION_USB_DURATION0	((void *)(PMU_ALIVE_BASE + 0x32B0))
#define PAD_RETENTION_USB_DURATION1	((void *)(PMU_ALIVE_BASE + 0x32B4))
#define PAD_RETENTION_USB_DURATION2	((void *)(PMU_ALIVE_BASE + 0x32B8))
#define PAD_RETENTION_USB_DURATION3	((void *)(PMU_ALIVE_BASE + 0x32BC))
#define PAD_RETENTION_BOOTLDO_1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x32C0))
#define PAD_RETENTION_BOOTLDO_1_STATUS	((void *)(PMU_ALIVE_BASE + 0x32C4))
#define PAD_RETENTION_BOOTLDO_1_OPTION	((void *)(PMU_ALIVE_BASE + 0x32C8))
#define PAD_RETENTION_BOOTLDO_1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x32D0))
#define PAD_RETENTION_BOOTLDO_1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x32D4))
#define PAD_RETENTION_BOOTLDO_1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x32D8))
#define PAD_RETENTION_BOOTLDO_1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x32DC))
#define PAD_ALV_SEL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3300))
#define PAD_ALV_SEL_STATUS	((void *)(PMU_ALIVE_BASE + 0x3304))
#define PAD_ALV_SEL_OPTION0	((void *)(PMU_ALIVE_BASE + 0x3308))
#define PS_HOLD_CONTROL	((void *)(PMU_ALIVE_BASE + 0x330C))
#define PAD_ALV_SEL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3310))
#define PAD_ALV_SEL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3314))
#define PAD_ALV_SEL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3318))
#define PAD_ALV_SEL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x331C))
#define XXTI_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3420))
#define XXTI_STATUS	((void *)(PMU_ALIVE_BASE + 0x3424))
#define XXTI_OPTION	((void *)(PMU_ALIVE_BASE + 0x3428))
#define XXTI_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3430))
#define XXTI_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3434))
#define XXTI_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3438))
#define XXTI_DURATION3	((void *)(PMU_ALIVE_BASE + 0x343C))
#define TCXO_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3460))
#define TCXO_STATUS	((void *)(PMU_ALIVE_BASE + 0x3464))
#define TCXO_OPTION	((void *)(PMU_ALIVE_BASE + 0x3468))
#define TCXO_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3470))
#define TCXO_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3474))
#define TCXO_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3478))
#define TCXO_DURATION3	((void *)(PMU_ALIVE_BASE + 0x347C))
#define EXT_REGULATOR_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3600))
#define EXT_REGULATOR_STATUS	((void *)(PMU_ALIVE_BASE + 0x3604))
#define EXT_REGULATOR_OPTION	((void *)(PMU_ALIVE_BASE + 0x3608))
#define EXT_REGULATOR_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3610))
#define EXT_REGULATOR_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3614))
#define EXT_REGULATOR_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3618))
#define EXT_REGULATOR_DURATION3	((void *)(PMU_ALIVE_BASE + 0x361C))
#define EXT_REGULATOR_MIF_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3620))
#define EXT_REGULATOR_MIF_STATUS	((void *)(PMU_ALIVE_BASE + 0x3624))
#define EXT_REGULATOR_MIF_OPTION	((void *)(PMU_ALIVE_BASE + 0x3628))
#define EXT_REGULATOR_MIF_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3630))
#define EXT_REGULATOR_MIF_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3634))
#define EXT_REGULATOR_MIF_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3638))
#define EXT_REGULATOR_MIF_DURATION3	((void *)(PMU_ALIVE_BASE + 0x363C))
#define GPIO_MODE_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3800))
#define GPIO_MODE_STATUS	((void *)(PMU_ALIVE_BASE + 0x3804))
#define GPIO_MODE_OPTION	((void *)(PMU_ALIVE_BASE + 0x3808))
#define GPIO_MODE_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3810))
#define GPIO_MODE_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3814))
#define GPIO_MODE_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3818))
#define GPIO_MODE_DURATION3	((void *)(PMU_ALIVE_BASE + 0x381C))
#define GPIO_MODE_FSYS0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3820))
#define GPIO_MODE_FSYS0_STATUS	((void *)(PMU_ALIVE_BASE + 0x3824))
#define GPIO_MODE_FSYS0_OPTION	((void *)(PMU_ALIVE_BASE + 0x3828))
#define GPIO_MODE_FSYS0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3830))
#define GPIO_MODE_FSYS0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3834))
#define GPIO_MODE_FSYS0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3838))
#define GPIO_MODE_FSYS0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x383C))
#define GPIO_MODE_FSYS1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3840))
#define GPIO_MODE_FSYS1_STATUS	((void *)(PMU_ALIVE_BASE + 0x3844))
#define GPIO_MODE_FSYS1_OPTION	((void *)(PMU_ALIVE_BASE + 0x3848))
#define GPIO_MODE_FSYS1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3850))
#define GPIO_MODE_FSYS1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3854))
#define GPIO_MODE_FSYS1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3858))
#define GPIO_MODE_FSYS1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x385C))
#define GPIO_MODE_MIF_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3900))
#define GPIO_MODE_MIF_STATUS	((void *)(PMU_ALIVE_BASE + 0x3904))
#define GPIO_MODE_MIF_OPTION	((void *)(PMU_ALIVE_BASE + 0x3908))
#define GPIO_MODE_MIF_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3910))
#define GPIO_MODE_MIF_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3914))
#define GPIO_MODE_MIF_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3918))
#define GPIO_MODE_MIF_DURATION3	((void *)(PMU_ALIVE_BASE + 0x391C))
#define GPIO_MODE_AUD_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x39E0))
#define GPIO_MODE_AUD_STATUS	((void *)(PMU_ALIVE_BASE + 0x39E4))
#define GPIO_MODE_AUD_OPTION	((void *)(PMU_ALIVE_BASE + 0x39E8))
#define GPIO_MODE_AUD_DURATION0	((void *)(PMU_ALIVE_BASE + 0x39F0))
#define GPIO_MODE_AUD_DURATION1	((void *)(PMU_ALIVE_BASE + 0x39F4))
#define GPIO_MODE_AUD_DURATION2	((void *)(PMU_ALIVE_BASE + 0x39F8))
#define GPIO_MODE_AUD_DURATION3	((void *)(PMU_ALIVE_BASE + 0x39FC))
#define CLKSTOP_OPEN_CMU_TOP_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3C00))
#define CLKSTOP_OPEN_CMU_TOP_STATUS	((void *)(PMU_ALIVE_BASE + 0x3C04))
#define CLKSTOP_OPEN_CMU_TOP_OPTION	((void *)(PMU_ALIVE_BASE + 0x3C08))
#define CLKSTOP_OPEN_CMU_TOP_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3C10))
#define CLKSTOP_OPEN_CMU_TOP_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3C14))
#define CLKSTOP_OPEN_CMU_TOP_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3C18))
#define CLKSTOP_OPEN_CMU_TOP_DURATION3	((void *)(PMU_ALIVE_BASE + 0x3C1C))
#define CLKSTOP_OPEN_CMU_MIF_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3C20))
#define CLKSTOP_OPEN_CMU_MIF_STATUS	((void *)(PMU_ALIVE_BASE + 0x3C24))
#define CLKSTOP_OPEN_CMU_MIF_OPTION	((void *)(PMU_ALIVE_BASE + 0x3C28))
#define CLKSTOP_OPEN_CMU_MIF_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3C30))
#define CLKSTOP_OPEN_CMU_MIF_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3C34))
#define CLKSTOP_OPEN_CMU_MIF_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3C38))
#define CLKSTOP_OPEN_CMU_MIF_DURATION3	((void *)(PMU_ALIVE_BASE + 0x3C3C))
#define CLKSTOP_OPEN_CMU_CAM0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3C40))
#define CLKSTOP_OPEN_CMU_CAM0_STATUS	((void *)(PMU_ALIVE_BASE + 0x3C44))
#define CLKSTOP_OPEN_CMU_CAM0_OPTION	((void *)(PMU_ALIVE_BASE + 0x3C48))
#define CLKSTOP_OPEN_CMU_CAM0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3C50))
#define CLKSTOP_OPEN_CMU_CAM0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3C54))
#define CLKSTOP_OPEN_CMU_CAM0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3C58))
#define CLKSTOP_OPEN_CMU_CAM0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x3C5C))
#define CLKSTOP_OPEN_CMU_MSCL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3C60))
#define CLKSTOP_OPEN_CMU_MSCL_STATUS	((void *)(PMU_ALIVE_BASE + 0x3C64))
#define CLKSTOP_OPEN_CMU_MSCL_OPTION	((void *)(PMU_ALIVE_BASE + 0x3C68))
#define CLKSTOP_OPEN_CMU_MSCL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3C70))
#define CLKSTOP_OPEN_CMU_MSCL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3C74))
#define CLKSTOP_OPEN_CMU_MSCL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3C78))
#define CLKSTOP_OPEN_CMU_MSCL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x3C7C))
#define CLKSTOP_OPEN_CMU_G3D_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3C80))
#define CLKSTOP_OPEN_CMU_G3D_STATUS	((void *)(PMU_ALIVE_BASE + 0x3C84))
#define CLKSTOP_OPEN_CMU_G3D_OPTION	((void *)(PMU_ALIVE_BASE + 0x3C88))
#define CLKSTOP_OPEN_CMU_G3D_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3C90))
#define CLKSTOP_OPEN_CMU_G3D_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3C94))
#define CLKSTOP_OPEN_CMU_G3D_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3C98))
#define CLKSTOP_OPEN_CMU_G3D_DURATION3	((void *)(PMU_ALIVE_BASE + 0x3C9C))
#define CLKSTOP_OPEN_CMU_DISP0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3CA0))
#define CLKSTOP_OPEN_CMU_DISP0_STATUS	((void *)(PMU_ALIVE_BASE + 0x3CA4))
#define CLKSTOP_OPEN_CMU_DISP0_OPTION	((void *)(PMU_ALIVE_BASE + 0x3CA8))
#define CLKSTOP_OPEN_CMU_DISP0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3CB0))
#define CLKSTOP_OPEN_CMU_DISP0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3CB4))
#define CLKSTOP_OPEN_CMU_DISP0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3CB8))
#define CLKSTOP_OPEN_CMU_DISP0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x3CBC))
#define CLKSTOP_OPEN_CMU_CAM1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3CC0))
#define CLKSTOP_OPEN_CMU_CAM1_STATUS	((void *)(PMU_ALIVE_BASE + 0x3CC4))
#define CLKSTOP_OPEN_CMU_CAM1_OPTION	((void *)(PMU_ALIVE_BASE + 0x3CC8))
#define CLKSTOP_OPEN_CMU_CAM1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3CD0))
#define CLKSTOP_OPEN_CMU_CAM1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3CD4))
#define CLKSTOP_OPEN_CMU_CAM1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3CD8))
#define CLKSTOP_OPEN_CMU_CAM1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x3CDC))
#define CLKSTOP_OPEN_CMU_AUD_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3CE0))
#define CLKSTOP_OPEN_CMU_AUD_STATUS	((void *)(PMU_ALIVE_BASE + 0x3CE4))
#define CLKSTOP_OPEN_CMU_AUD_OPTION	((void *)(PMU_ALIVE_BASE + 0x3CE8))
#define CLKSTOP_OPEN_CMU_AUD_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3CF0))
#define CLKSTOP_OPEN_CMU_AUD_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3CF4))
#define CLKSTOP_OPEN_CMU_AUD_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3CF8))
#define CLKSTOP_OPEN_CMU_AUD_DURATION3	((void *)(PMU_ALIVE_BASE + 0x3CFC))
#define CLKSTOP_OPEN_CMU_FSYS0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3D00))
#define CLKSTOP_OPEN_CMU_FSYS0_STATUS	((void *)(PMU_ALIVE_BASE + 0x3D04))
#define CLKSTOP_OPEN_CMU_FSYS0_OPTION	((void *)(PMU_ALIVE_BASE + 0x3D08))
#define CLKSTOP_OPEN_CMU_FSYS0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3D10))
#define CLKSTOP_OPEN_CMU_FSYS0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3D14))
#define CLKSTOP_OPEN_CMU_FSYS0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3D18))
#define CLKSTOP_OPEN_CMU_FSYS0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x3D1C))
#define CLKSTOP_OPEN_CMU_BUS0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3D20))
#define CLKSTOP_OPEN_CMU_BUS0_STATUS	((void *)(PMU_ALIVE_BASE + 0x3D24))
#define CLKSTOP_OPEN_CMU_BUS0_OPTION	((void *)(PMU_ALIVE_BASE + 0x3D28))
#define CLKSTOP_OPEN_CMU_BUS0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3D30))
#define CLKSTOP_OPEN_CMU_BUS0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3D34))
#define CLKSTOP_OPEN_CMU_BUS0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3D38))
#define CLKSTOP_OPEN_CMU_BUS0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x3D3C))
#define CLKSTOP_OPEN_CMU_ISP0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3D40))
#define CLKSTOP_OPEN_CMU_ISP0_STATUS	((void *)(PMU_ALIVE_BASE + 0x3D44))
#define CLKSTOP_OPEN_CMU_ISP0_OPTION	((void *)(PMU_ALIVE_BASE + 0x3D48))
#define CLKSTOP_OPEN_CMU_ISP0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3D50))
#define CLKSTOP_OPEN_CMU_ISP0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3D54))
#define CLKSTOP_OPEN_CMU_ISP0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3D58))
#define CLKSTOP_OPEN_CMU_ISP0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x3D5C))
#define CLKSTOP_OPEN_CMU_ISP1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3D60))
#define CLKSTOP_OPEN_CMU_ISP1_STATUS	((void *)(PMU_ALIVE_BASE + 0x3D64))
#define CLKSTOP_OPEN_CMU_ISP1_OPTION	((void *)(PMU_ALIVE_BASE + 0x3D68))
#define CLKSTOP_OPEN_CMU_ISP1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3D70))
#define CLKSTOP_OPEN_CMU_ISP1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3D74))
#define CLKSTOP_OPEN_CMU_ISP1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3D78))
#define CLKSTOP_OPEN_CMU_ISP1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x3D7C))
#define CLKSTOP_OPEN_CMU_MFC_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3D80))
#define CLKSTOP_OPEN_CMU_MFC_STATUS	((void *)(PMU_ALIVE_BASE + 0x3D84))
#define CLKSTOP_OPEN_CMU_MFC_OPTION	((void *)(PMU_ALIVE_BASE + 0x3D88))
#define CLKSTOP_OPEN_CMU_MFC_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3D90))
#define CLKSTOP_OPEN_CMU_MFC_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3D94))
#define CLKSTOP_OPEN_CMU_MFC_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3D98))
#define CLKSTOP_OPEN_CMU_MFC_DURATION3	((void *)(PMU_ALIVE_BASE + 0x3D9C))
#define CLKSTOP_OPEN_CMU_DISP1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3DA0))
#define CLKSTOP_OPEN_CMU_DISP1_STATUS	((void *)(PMU_ALIVE_BASE + 0x3DA4))
#define CLKSTOP_OPEN_CMU_DISP1_OPTION	((void *)(PMU_ALIVE_BASE + 0x3DA8))
#define CLKSTOP_OPEN_CMU_DISP1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3DB0))
#define CLKSTOP_OPEN_CMU_DISP1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3DB4))
#define CLKSTOP_OPEN_CMU_DISP1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3DB8))
#define CLKSTOP_OPEN_CMU_DISP1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x3DBC))
#define CLKSTOP_OPEN_CMU_FSYS1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x3DC0))
#define CLKSTOP_OPEN_CMU_FSYS1_STATUS	((void *)(PMU_ALIVE_BASE + 0x3DC4))
#define CLKSTOP_OPEN_CMU_FSYS1_OPTION	((void *)(PMU_ALIVE_BASE + 0x3DC8))
#define CLKSTOP_OPEN_CMU_FSYS1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x3DD0))
#define CLKSTOP_OPEN_CMU_FSYS1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x3DD4))
#define CLKSTOP_OPEN_CMU_FSYS1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x3DD8))
#define CLKSTOP_OPEN_CMU_FSYS1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x3DDC))
#define CAM0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4020))
#define CAM0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4024))
#define CAM0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4028))
#define CAM0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4030))
#define CAM0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4034))
#define CAM0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4038))
#define CAM0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x403C))
#define MSCL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4040))
#define MSCL_STATUS	((void *)(PMU_ALIVE_BASE + 0x4044))
#define MSCL_OPTION	((void *)(PMU_ALIVE_BASE + 0x4048))
#define MSCL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4050))
#define MSCL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4054))
#define MSCL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4058))
#define MSCL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x405C))
#define G3D_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4060))
#define G3D_STATUS	((void *)(PMU_ALIVE_BASE + 0x4064))
#define G3D_OPTION	((void *)(PMU_ALIVE_BASE + 0x4068))
#define G3D_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4070))
#define G3D_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4074))
#define G3D_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4078))
#define G3D_DURATION3	((void *)(PMU_ALIVE_BASE + 0x407C))
#define DISP0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4080))
#define DISP0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4084))
#define DISP0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4088))
#define DISP0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4090))
#define DISP0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4094))
#define DISP0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4098))
#define DISP0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x409C))
#define CAM1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x40A0))
#define CAM1_STATUS	((void *)(PMU_ALIVE_BASE + 0x40A4))
#define CAM1_OPTION	((void *)(PMU_ALIVE_BASE + 0x40A8))
#define CAM1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x40B0))
#define CAM1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x40B4))
#define CAM1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x40B8))
#define CAM1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x40BC))
#define AUD_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x40C0))
#define AUD_STATUS	((void *)(PMU_ALIVE_BASE + 0x40C4))
#define AUD_OPTION	((void *)(PMU_ALIVE_BASE + 0x40C8))
#define AUD_DURATION0	((void *)(PMU_ALIVE_BASE + 0x40D0))
#define AUD_DURATION1	((void *)(PMU_ALIVE_BASE + 0x40D4))
#define AUD_DURATION2	((void *)(PMU_ALIVE_BASE + 0x40D8))
#define AUD_DURATION3	((void *)(PMU_ALIVE_BASE + 0x40DC))
#define FSYS0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x40E0))
#define FSYS0_STATUS	((void *)(PMU_ALIVE_BASE + 0x40E4))
#define FSYS0_OPTION	((void *)(PMU_ALIVE_BASE + 0x40E8))
#define FSYS0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x40F0))
#define FSYS0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x40F4))
#define FSYS0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x40F8))
#define FSYS0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x40FC))
#define BUS0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4100))
#define BUS0_STATUS_	((void *)(PMU_ALIVE_BASE + 0x4104)) //BJ : because of duplicated definition, i added "_".
#define BUS0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4108))
#define BUS0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4110))
#define BUS0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4114))
#define BUS0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4118))
#define BUS0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x411C))
#define ISP0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4140))
#define ISP0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4144))
#define ISP0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4148))
#define ISP0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4150))
#define ISP0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4154))
#define ISP0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4158))
#define ISP0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x415C))
#define ISP1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4160))
#define ISP1_STATUS	((void *)(PMU_ALIVE_BASE + 0x4164))
#define ISP1_OPTION	((void *)(PMU_ALIVE_BASE + 0x4168))
#define ISP1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4170))
#define ISP1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4174))
#define ISP1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4178))
#define ISP1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x417C))
#define MFC_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4180))
#define MFC_STATUS	((void *)(PMU_ALIVE_BASE + 0x4184))
#define MFC_OPTION	((void *)(PMU_ALIVE_BASE + 0x4188))
#define MFC_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4190))
#define MFC_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4194))
#define MFC_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4198))
#define MFC_DURATION3	((void *)(PMU_ALIVE_BASE + 0x419C))
#define DISP1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x41A0))
#define DISP1_STATUS	((void *)(PMU_ALIVE_BASE + 0x41A4))
#define DISP1_OPTION	((void *)(PMU_ALIVE_BASE + 0x41A8))
#define DISP1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x41B0))
#define DISP1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x41B4))
#define DISP1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x41B8))
#define DISP1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x41BC))
#define FSYS1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x41C0))
#define FSYS1_STATUS	((void *)(PMU_ALIVE_BASE + 0x41C4))
#define FSYS1_OPTION	((void *)(PMU_ALIVE_BASE + 0x41C8))
#define FSYS1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x41D0))
#define FSYS1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x41D4))
#define FSYS1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x41D8))
#define FSYS1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x41DC))
#define CLKRUN_CMU_CAM0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4220))
#define CLKRUN_CMU_CAM0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4224))
#define CLKRUN_CMU_CAM0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4228))
#define CLKRUN_CMU_CAM0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4230))
#define CLKRUN_CMU_CAM0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4234))
#define CLKRUN_CMU_CAM0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4238))
#define CLKRUN_CMU_CAM0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x423C))
#define CLKRUN_CMU_MSCL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4240))
#define CLKRUN_CMU_MSCL_STATUS	((void *)(PMU_ALIVE_BASE + 0x4244))
#define CLKRUN_CMU_MSCL_OPTION	((void *)(PMU_ALIVE_BASE + 0x4248))
#define CLKRUN_CMU_MSCL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4250))
#define CLKRUN_CMU_MSCL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4254))
#define CLKRUN_CMU_MSCL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4258))
#define CLKRUN_CMU_MSCL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x425C))
#define CLKRUN_CMU_G3D_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4260))
#define CLKRUN_CMU_G3D_STATUS	((void *)(PMU_ALIVE_BASE + 0x4264))
#define CLKRUN_CMU_G3D_OPTION	((void *)(PMU_ALIVE_BASE + 0x4268))
#define CLKRUN_CMU_G3D_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4270))
#define CLKRUN_CMU_G3D_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4274))
#define CLKRUN_CMU_G3D_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4278))
#define CLKRUN_CMU_G3D_DURATION3	((void *)(PMU_ALIVE_BASE + 0x427C))
#define CLKRUN_CMU_DISP0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4280))
#define CLKRUN_CMU_DISP0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4284))
#define CLKRUN_CMU_DISP0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4288))
#define CLKRUN_CMU_DISP0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4290))
#define CLKRUN_CMU_DISP0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4294))
#define CLKRUN_CMU_DISP0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4298))
#define CLKRUN_CMU_DISP0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x429C))
#define CLKRUN_CMU_CAM1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x42A0))
#define CLKRUN_CMU_CAM1_STATUS	((void *)(PMU_ALIVE_BASE + 0x42A4))
#define CLKRUN_CMU_CAM1_OPTION	((void *)(PMU_ALIVE_BASE + 0x42A8))
#define CLKRUN_CMU_CAM1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x42B0))
#define CLKRUN_CMU_CAM1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x42B4))
#define CLKRUN_CMU_CAM1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x42B8))
#define CLKRUN_CMU_CAM1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x42BC))
#define CLKRUN_CMU_AUD_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x42C0))
#define CLKRUN_CMU_AUD_STATUS	((void *)(PMU_ALIVE_BASE + 0x42C4))
#define CLKRUN_CMU_AUD_OPTION	((void *)(PMU_ALIVE_BASE + 0x42C8))
#define CLKRUN_CMU_AUD_DURATION0	((void *)(PMU_ALIVE_BASE + 0x42D0))
#define CLKRUN_CMU_AUD_DURATION1	((void *)(PMU_ALIVE_BASE + 0x42D4))
#define CLKRUN_CMU_AUD_DURATION2	((void *)(PMU_ALIVE_BASE + 0x42D8))
#define CLKRUN_CMU_AUD_DURATION3	((void *)(PMU_ALIVE_BASE + 0x42DC))
#define CLKRUN_CMU_FSYS0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x42E0))
#define CLKRUN_CMU_FSYS0_STATUS	((void *)(PMU_ALIVE_BASE + 0x42E4))
#define CLKRUN_CMU_FSYS0_OPTION	((void *)(PMU_ALIVE_BASE + 0x42E8))
#define CLKRUN_CMU_FSYS0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x42F0))
#define CLKRUN_CMU_FSYS0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x42F4))
#define CLKRUN_CMU_FSYS0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x42F8))
#define CLKRUN_CMU_FSYS0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x42FC))
#define CLKRUN_CMU_BUS0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4300))
#define CLKRUN_CMU_BUS0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4304))
#define CLKRUN_CMU_BUS0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4308))
#define CLKRUN_CMU_BUS0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4310))
#define CLKRUN_CMU_BUS0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4314))
#define CLKRUN_CMU_BUS0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4318))
#define CLKRUN_CMU_BUS0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x431C))
#define CLKRUN_CMU_ISP0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4340))
#define CLKRUN_CMU_ISP0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4344))
#define CLKRUN_CMU_ISP0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4348))
#define CLKRUN_CMU_ISP0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4350))
#define CLKRUN_CMU_ISP0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4354))
#define CLKRUN_CMU_ISP0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4358))
#define CLKRUN_CMU_ISP0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x435C))
#define CLKRUN_CMU_ISP1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4360))
#define CLKRUN_CMU_ISP1_STATUS	((void *)(PMU_ALIVE_BASE + 0x4364))
#define CLKRUN_CMU_ISP1_OPTION	((void *)(PMU_ALIVE_BASE + 0x4368))
#define CLKRUN_CMU_ISP1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4370))
#define CLKRUN_CMU_ISP1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4374))
#define CLKRUN_CMU_ISP1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4378))
#define CLKRUN_CMU_ISP1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x437C))
#define CLKRUN_CMU_MFC_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4380))
#define CLKRUN_CMU_MFC_STATUS	((void *)(PMU_ALIVE_BASE + 0x4384))
#define CLKRUN_CMU_MFC_OPTION	((void *)(PMU_ALIVE_BASE + 0x4388))
#define CLKRUN_CMU_MFC_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4390))
#define CLKRUN_CMU_MFC_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4394))
#define CLKRUN_CMU_MFC_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4398))
#define CLKRUN_CMU_MFC_DURATION3	((void *)(PMU_ALIVE_BASE + 0x439C))
#define CLKRUN_CMU_DISP1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x43A0))
#define CLKRUN_CMU_DISP1_STATUS	((void *)(PMU_ALIVE_BASE + 0x43A4))
#define CLKRUN_CMU_DISP1_OPTION	((void *)(PMU_ALIVE_BASE + 0x43A8))
#define CLKRUN_CMU_DISP1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x43B0))
#define CLKRUN_CMU_DISP1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x43B4))
#define CLKRUN_CMU_DISP1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x43B8))
#define CLKRUN_CMU_DISP1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x43BC))
#define CLKRUN_CMU_FSYS1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x43C0))
#define CLKRUN_CMU_FSYS1_STATUS	((void *)(PMU_ALIVE_BASE + 0x43C4))
#define CLKRUN_CMU_FSYS1_OPTION	((void *)(PMU_ALIVE_BASE + 0x43C8))
#define CLKRUN_CMU_FSYS1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x43D0))
#define CLKRUN_CMU_FSYS1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x43D4))
#define CLKRUN_CMU_FSYS1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x43D8))
#define CLKRUN_CMU_FSYS1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x43DC))
#define CLKSTOP_CMU_CAM0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4420))
#define CLKSTOP_CMU_CAM0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4424))
#define CLKSTOP_CMU_CAM0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4428))
#define CLKSTOP_CMU_CAM0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4430))
#define CLKSTOP_CMU_CAM0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4434))
#define CLKSTOP_CMU_CAM0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4438))
#define CLKSTOP_CMU_CAM0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x443C))
#define CLKSTOP_CMU_MSCL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4440))
#define CLKSTOP_CMU_MSCL_STATUS	((void *)(PMU_ALIVE_BASE + 0x4444))
#define CLKSTOP_CMU_MSCL_OPTION	((void *)(PMU_ALIVE_BASE + 0x4448))
#define CLKSTOP_CMU_MSCL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4450))
#define CLKSTOP_CMU_MSCL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4454))
#define CLKSTOP_CMU_MSCL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4458))
#define CLKSTOP_CMU_MSCL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x445C))
#define CLKSTOP_CMU_G3D_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4460))
#define CLKSTOP_CMU_G3D_STATUS	((void *)(PMU_ALIVE_BASE + 0x4464))
#define CLKSTOP_CMU_G3D_OPTION	((void *)(PMU_ALIVE_BASE + 0x4468))
#define CLKSTOP_CMU_G3D_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4470))
#define CLKSTOP_CMU_G3D_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4474))
#define CLKSTOP_CMU_G3D_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4478))
#define CLKSTOP_CMU_G3D_DURATION3	((void *)(PMU_ALIVE_BASE + 0x447C))
#define CLKSTOP_CMU_DISP0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4480))
#define CLKSTOP_CMU_DISP0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4484))
#define CLKSTOP_CMU_DISP0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4488))
#define CLKSTOP_CMU_DISP0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4490))
#define CLKSTOP_CMU_DISP0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4494))
#define CLKSTOP_CMU_DISP0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4498))
#define CLKSTOP_CMU_DISP0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x449C))
#define CLKSTOP_CMU_CAM1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x44A0))
#define CLKSTOP_CMU_CAM1_STATUS	((void *)(PMU_ALIVE_BASE + 0x44A4))
#define CLKSTOP_CMU_CAM1_OPTION	((void *)(PMU_ALIVE_BASE + 0x44A8))
#define CLKSTOP_CMU_CAM1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x44B0))
#define CLKSTOP_CMU_CAM1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x44B4))
#define CLKSTOP_CMU_CAM1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x44B8))
#define CLKSTOP_CMU_CAM1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x44BC))
#define CLKSTOP_CMU_AUD_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x44C0))
#define CLKSTOP_CMU_AUD_STATUS	((void *)(PMU_ALIVE_BASE + 0x44C4))
#define CLKSTOP_CMU_AUD_OPTION	((void *)(PMU_ALIVE_BASE + 0x44C8))
#define CLKSTOP_CMU_AUD_DURATION0	((void *)(PMU_ALIVE_BASE + 0x44D0))
#define CLKSTOP_CMU_AUD_DURATION1	((void *)(PMU_ALIVE_BASE + 0x44D4))
#define CLKSTOP_CMU_AUD_DURATION2	((void *)(PMU_ALIVE_BASE + 0x44D8))
#define CLKSTOP_CMU_AUD_DURATION3	((void *)(PMU_ALIVE_BASE + 0x44DC))
#define CLKSTOP_CMU_FSYS0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x44E0))
#define CLKSTOP_CMU_FSYS0_STATUS	((void *)(PMU_ALIVE_BASE + 0x44E4))
#define CLKSTOP_CMU_FSYS0_OPTION	((void *)(PMU_ALIVE_BASE + 0x44E8))
#define CLKSTOP_CMU_FSYS0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x44F0))
#define CLKSTOP_CMU_FSYS0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x44F4))
#define CLKSTOP_CMU_FSYS0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x44F8))
#define CLKSTOP_CMU_FSYS0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x44FC))
#define CLKSTOP_CMU_BUS0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4500))
#define CLKSTOP_CMU_BUS0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4504))
#define CLKSTOP_CMU_BUS0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4508))
#define CLKSTOP_CMU_BUS0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4510))
#define CLKSTOP_CMU_BUS0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4514))
#define CLKSTOP_CMU_BUS0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4518))
#define CLKSTOP_CMU_BUS0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x451C))
#define CLKSTOP_CMU_ISP0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4540))
#define CLKSTOP_CMU_ISP0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4544))
#define CLKSTOP_CMU_ISP0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4548))
#define CLKSTOP_CMU_ISP0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4550))
#define CLKSTOP_CMU_ISP0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4554))
#define CLKSTOP_CMU_ISP0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4558))
#define CLKSTOP_CMU_ISP0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x455C))
#define CLKSTOP_CMU_ISP1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4560))
#define CLKSTOP_CMU_ISP1_STATUS	((void *)(PMU_ALIVE_BASE + 0x4564))
#define CLKSTOP_CMU_ISP1_OPTION	((void *)(PMU_ALIVE_BASE + 0x4568))
#define CLKSTOP_CMU_ISP1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4570))
#define CLKSTOP_CMU_ISP1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4574))
#define CLKSTOP_CMU_ISP1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4578))
#define CLKSTOP_CMU_ISP1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x457C))
#define CLKSTOP_CMU_MFC_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4580))
#define CLKSTOP_CMU_MFC_STATUS	((void *)(PMU_ALIVE_BASE + 0x4584))
#define CLKSTOP_CMU_MFC_OPTION	((void *)(PMU_ALIVE_BASE + 0x4588))
#define CLKSTOP_CMU_MFC_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4590))
#define CLKSTOP_CMU_MFC_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4594))
#define CLKSTOP_CMU_MFC_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4598))
#define CLKSTOP_CMU_MFC_DURATION3	((void *)(PMU_ALIVE_BASE + 0x459C))
#define CLKSTOP_CMU_DISP1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x45A0))
#define CLKSTOP_CMU_DISP1_STATUS	((void *)(PMU_ALIVE_BASE + 0x45A4))
#define CLKSTOP_CMU_DISP1_OPTION	((void *)(PMU_ALIVE_BASE + 0x45A8))
#define CLKSTOP_CMU_DISP1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x45B0))
#define CLKSTOP_CMU_DISP1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x45B4))
#define CLKSTOP_CMU_DISP1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x45B8))
#define CLKSTOP_CMU_DISP1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x45BC))
#define CLKSTOP_CMU_FSYS1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x45C0))
#define CLKSTOP_CMU_FSYS1_STATUS	((void *)(PMU_ALIVE_BASE + 0x45C4))
#define CLKSTOP_CMU_FSYS1_OPTION	((void *)(PMU_ALIVE_BASE + 0x45C8))
#define CLKSTOP_CMU_FSYS1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x45D0))
#define CLKSTOP_CMU_FSYS1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x45D4))
#define CLKSTOP_CMU_FSYS1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x45D8))
#define CLKSTOP_CMU_FSYS1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x45DC))
#define DISABLE_PLL_CMU_CAM0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4620))
#define DISABLE_PLL_CMU_CAM0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4624))
#define DISABLE_PLL_CMU_CAM0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4628))
#define DISABLE_PLL_CMU_CAM0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4630))
#define DISABLE_PLL_CMU_CAM0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4634))
#define DISABLE_PLL_CMU_CAM0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4638))
#define DISABLE_PLL_CMU_CAM0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x463C))
#define DISABLE_PLL_CMU_MSCL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4640))
#define DISABLE_PLL_CMU_MSCL_STATUS	((void *)(PMU_ALIVE_BASE + 0x4644))
#define DISABLE_PLL_CMU_MSCL_OPTION	((void *)(PMU_ALIVE_BASE + 0x4648))
#define DISABLE_PLL_CMU_MSCL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4650))
#define DISABLE_PLL_CMU_MSCL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4654))
#define DISABLE_PLL_CMU_MSCL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4658))
#define DISABLE_PLL_CMU_MSCL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x465C))
#define DISABLE_PLL_CMU_G3D_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4660))
#define DISABLE_PLL_CMU_G3D_STATUS	((void *)(PMU_ALIVE_BASE + 0x4664))
#define DISABLE_PLL_CMU_G3D_OPTION	((void *)(PMU_ALIVE_BASE + 0x4668))
#define DISABLE_PLL_CMU_G3D_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4670))
#define DISABLE_PLL_CMU_G3D_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4674))
#define DISABLE_PLL_CMU_G3D_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4678))
#define DISABLE_PLL_CMU_G3D_DURATION3	((void *)(PMU_ALIVE_BASE + 0x467C))
#define DISABLE_PLL_CMU_DISP0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4680))
#define DISABLE_PLL_CMU_DISP0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4684))
#define DISABLE_PLL_CMU_DISP0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4688))
#define DISABLE_PLL_CMU_DISP0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4690))
#define DISABLE_PLL_CMU_DISP0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4694))
#define DISABLE_PLL_CMU_DISP0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4698))
#define DISABLE_PLL_CMU_DISP0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x469C))
#define DISABLE_PLL_CMU_CAM1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x46A0))
#define DISABLE_PLL_CMU_CAM1_STATUS	((void *)(PMU_ALIVE_BASE + 0x46A4))
#define DISABLE_PLL_CMU_CAM1_OPTION	((void *)(PMU_ALIVE_BASE + 0x46A8))
#define DISABLE_PLL_CMU_CAM1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x46B0))
#define DISABLE_PLL_CMU_CAM1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x46B4))
#define DISABLE_PLL_CMU_CAM1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x46B8))
#define DISABLE_PLL_CMU_CAM1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x46BC))
#define DISABLE_PLL_CMU_AUD_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x46C0))
#define DISABLE_PLL_CMU_AUD_STATUS	((void *)(PMU_ALIVE_BASE + 0x46C4))
#define DISABLE_PLL_CMU_AUD_OPTION	((void *)(PMU_ALIVE_BASE + 0x46C8))
#define DISABLE_PLL_CMU_AUD_DURATION0	((void *)(PMU_ALIVE_BASE + 0x46D0))
#define DISABLE_PLL_CMU_AUD_DURATION1	((void *)(PMU_ALIVE_BASE + 0x46D4))
#define DISABLE_PLL_CMU_AUD_DURATION2	((void *)(PMU_ALIVE_BASE + 0x46D8))
#define DISABLE_PLL_CMU_AUD_DURATION3	((void *)(PMU_ALIVE_BASE + 0x46DC))
#define DISABLE_PLL_CMU_FSYS0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x46E0))
#define DISABLE_PLL_CMU_FSYS0_STATUS	((void *)(PMU_ALIVE_BASE + 0x46E4))
#define DISABLE_PLL_CMU_FSYS0_OPTION	((void *)(PMU_ALIVE_BASE + 0x46E8))
#define DISABLE_PLL_CMU_FSYS0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x46F0))
#define DISABLE_PLL_CMU_FSYS0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x46F4))
#define DISABLE_PLL_CMU_FSYS0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x46F8))
#define DISABLE_PLL_CMU_FSYS0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x46FC))
#define DISABLE_PLL_CMU_BUS0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4700))
#define DISABLE_PLL_CMU_BUS0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4704))
#define DISABLE_PLL_CMU_BUS0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4708))
#define DISABLE_PLL_CMU_BUS0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4710))
#define DISABLE_PLL_CMU_BUS0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4714))
#define DISABLE_PLL_CMU_BUS0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4718))
#define DISABLE_PLL_CMU_BUS0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x471C))
#define DISABLE_PLL_CMU_ISP0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4740))
#define DISABLE_PLL_CMU_ISP0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4744))
#define DISABLE_PLL_CMU_ISP0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4748))
#define DISABLE_PLL_CMU_ISP0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4750))
#define DISABLE_PLL_CMU_ISP0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4754))
#define DISABLE_PLL_CMU_ISP0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4758))
#define DISABLE_PLL_CMU_ISP0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x475C))
#define DISABLE_PLL_CMU_ISP1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4760))
#define DISABLE_PLL_CMU_ISP1_STATUS	((void *)(PMU_ALIVE_BASE + 0x4764))
#define DISABLE_PLL_CMU_ISP1_OPTION	((void *)(PMU_ALIVE_BASE + 0x4768))
#define DISABLE_PLL_CMU_ISP1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4770))
#define DISABLE_PLL_CMU_ISP1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4774))
#define DISABLE_PLL_CMU_ISP1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4778))
#define DISABLE_PLL_CMU_ISP1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x477C))
#define DISABLE_PLL_CMU_MFC_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4780))
#define DISABLE_PLL_CMU_MFC_STATUS	((void *)(PMU_ALIVE_BASE + 0x4784))
#define DISABLE_PLL_CMU_MFC_OPTION	((void *)(PMU_ALIVE_BASE + 0x4788))
#define DISABLE_PLL_CMU_MFC_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4790))
#define DISABLE_PLL_CMU_MFC_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4794))
#define DISABLE_PLL_CMU_MFC_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4798))
#define DISABLE_PLL_CMU_MFC_DURATION3	((void *)(PMU_ALIVE_BASE + 0x479C))
#define DISABLE_PLL_CMU_DISP1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x47A0))
#define DISABLE_PLL_CMU_DISP1_STATUS	((void *)(PMU_ALIVE_BASE + 0x47A4))
#define DISABLE_PLL_CMU_DISP1_OPTION	((void *)(PMU_ALIVE_BASE + 0x47A8))
#define DISABLE_PLL_CMU_DISP1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x47B0))
#define DISABLE_PLL_CMU_DISP1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x47B4))
#define DISABLE_PLL_CMU_DISP1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x47B8))
#define DISABLE_PLL_CMU_DISP1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x47BC))
#define DISABLE_PLL_CMU_FSYS1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x47C0))
#define DISABLE_PLL_CMU_FSYS1_STATUS	((void *)(PMU_ALIVE_BASE + 0x47C4))
#define DISABLE_PLL_CMU_FSYS1_OPTION	((void *)(PMU_ALIVE_BASE + 0x47C8))
#define DISABLE_PLL_CMU_FSYS1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x47D0))
#define DISABLE_PLL_CMU_FSYS1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x47D4))
#define DISABLE_PLL_CMU_FSYS1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x47D8))
#define DISABLE_PLL_CMU_FSYS1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x47DC))
#define RESET_LOGIC_CAM0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4820))
#define RESET_LOGIC_CAM0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4824))
#define RESET_LOGIC_CAM0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4828))
#define RESET_LOGIC_CAM0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4830))
#define RESET_LOGIC_CAM0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4834))
#define RESET_LOGIC_CAM0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4838))
#define RESET_LOGIC_CAM0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x483C))
#define RESET_LOGIC_MSCL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4840))
#define RESET_LOGIC_MSCL_STATUS	((void *)(PMU_ALIVE_BASE + 0x4844))
#define RESET_LOGIC_MSCL_OPTION	((void *)(PMU_ALIVE_BASE + 0x4848))
#define RESET_LOGIC_MSCL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4850))
#define RESET_LOGIC_MSCL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4854))
#define RESET_LOGIC_MSCL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4858))
#define RESET_LOGIC_MSCL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x485C))
#define RESET_LOGIC_G3D_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4860))
#define RESET_LOGIC_G3D_STATUS	((void *)(PMU_ALIVE_BASE + 0x4864))
#define RESET_LOGIC_G3D_OPTION	((void *)(PMU_ALIVE_BASE + 0x4868))
#define RESET_LOGIC_G3D_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4870))
#define RESET_LOGIC_G3D_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4874))
#define RESET_LOGIC_G3D_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4878))
#define RESET_LOGIC_G3D_DURATION3	((void *)(PMU_ALIVE_BASE + 0x487C))
#define RESET_LOGIC_DISP0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4880))
#define RESET_LOGIC_DISP0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4884))
#define RESET_LOGIC_DISP0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4888))
#define RESET_LOGIC_DISP0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4890))
#define RESET_LOGIC_DISP0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4894))
#define RESET_LOGIC_DISP0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4898))
#define RESET_LOGIC_DISP0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x489C))
#define RESET_LOGIC_CAM1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x48A0))
#define RESET_LOGIC_CAM1_STATUS	((void *)(PMU_ALIVE_BASE + 0x48A4))
#define RESET_LOGIC_CAM1_OPTION	((void *)(PMU_ALIVE_BASE + 0x48A8))
#define RESET_LOGIC_CAM1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x48B0))
#define RESET_LOGIC_CAM1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x48B4))
#define RESET_LOGIC_CAM1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x48B8))
#define RESET_LOGIC_CAM1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x48BC))
#define RESET_LOGIC_AUD_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x48C0))
#define RESET_LOGIC_AUD_STATUS	((void *)(PMU_ALIVE_BASE + 0x48C4))
#define RESET_LOGIC_AUD_OPTION	((void *)(PMU_ALIVE_BASE + 0x48C8))
#define RESET_LOGIC_AUD_DURATION0	((void *)(PMU_ALIVE_BASE + 0x48D0))
#define RESET_LOGIC_AUD_DURATION1	((void *)(PMU_ALIVE_BASE + 0x48D4))
#define RESET_LOGIC_AUD_DURATION2	((void *)(PMU_ALIVE_BASE + 0x48D8))
#define RESET_LOGIC_AUD_DURATION3	((void *)(PMU_ALIVE_BASE + 0x48DC))
#define RESET_LOGIC_FSYS0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x48E0))
#define RESET_LOGIC_FSYS0_STATUS	((void *)(PMU_ALIVE_BASE + 0x48E4))
#define RESET_LOGIC_FSYS0_OPTION	((void *)(PMU_ALIVE_BASE + 0x48E8))
#define RESET_LOGIC_FSYS0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x48F0))
#define RESET_LOGIC_FSYS0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x48F4))
#define RESET_LOGIC_FSYS0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x48F8))
#define RESET_LOGIC_FSYS0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x48FC))
#define RESET_LOGIC_BUS0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4900))
#define RESET_LOGIC_BUS0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4904))
#define RESET_LOGIC_BUS0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4908))
#define RESET_LOGIC_BUS0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4910))
#define RESET_LOGIC_BUS0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4914))
#define RESET_LOGIC_BUS0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4918))
#define RESET_LOGIC_BUS0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x491C))
#define RESET_LOGIC_ISP0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4940))
#define RESET_LOGIC_ISP0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4944))
#define RESET_LOGIC_ISP0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4948))
#define RESET_LOGIC_ISP0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4950))
#define RESET_LOGIC_ISP0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4954))
#define RESET_LOGIC_ISP0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4958))
#define RESET_LOGIC_ISP0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x495C))
#define RESET_LOGIC_ISP1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4960))
#define RESET_LOGIC_ISP1_STATUS	((void *)(PMU_ALIVE_BASE + 0x4964))
#define RESET_LOGIC_ISP1_OPTION	((void *)(PMU_ALIVE_BASE + 0x4968))
#define RESET_LOGIC_ISP1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4970))
#define RESET_LOGIC_ISP1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4974))
#define RESET_LOGIC_ISP1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4978))
#define RESET_LOGIC_ISP1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x497C))
#define RESET_LOGIC_MFC_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4980))
#define RESET_LOGIC_MFC_STATUS	((void *)(PMU_ALIVE_BASE + 0x4984))
#define RESET_LOGIC_MFC_OPTION	((void *)(PMU_ALIVE_BASE + 0x4988))
#define RESET_LOGIC_MFC_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4990))
#define RESET_LOGIC_MFC_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4994))
#define RESET_LOGIC_MFC_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4998))
#define RESET_LOGIC_MFC_DURATION3	((void *)(PMU_ALIVE_BASE + 0x499C))
#define RESET_LOGIC_DISP1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x49A0))
#define RESET_LOGIC_DISP1_STATUS	((void *)(PMU_ALIVE_BASE + 0x49A4))
#define RESET_LOGIC_DISP1_OPTION	((void *)(PMU_ALIVE_BASE + 0x49A8))
#define RESET_LOGIC_DISP1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x49B0))
#define RESET_LOGIC_DISP1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x49B4))
#define RESET_LOGIC_DISP1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x49B8))
#define RESET_LOGIC_DISP1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x49BC))
#define RESET_LOGIC_FSYS1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x49C0))
#define RESET_LOGIC_FSYS1_STATUS	((void *)(PMU_ALIVE_BASE + 0x49C4))
#define RESET_LOGIC_FSYS1_OPTION	((void *)(PMU_ALIVE_BASE + 0x49C8))
#define RESET_LOGIC_FSYS1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x49D0))
#define RESET_LOGIC_FSYS1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x49D4))
#define RESET_LOGIC_FSYS1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x49D8))
#define RESET_LOGIC_FSYS1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x49DC))
#define MEMORY_CAM0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4A20))
#define MEMORY_CAM0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4A24))
#define MEMORY_CAM0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4A28))
#define MEMORY_CAM0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4A30))
#define MEMORY_CAM0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4A34))
#define MEMORY_CAM0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4A38))
#define MEMORY_CAM0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4A3C))
#define MEMORY_MSCL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4A40))
#define MEMORY_MSCL_STATUS	((void *)(PMU_ALIVE_BASE + 0x4A44))
#define MEMORY_MSCL_OPTION	((void *)(PMU_ALIVE_BASE + 0x4A48))
#define MEMORY_MSCL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4A50))
#define MEMORY_MSCL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4A54))
#define MEMORY_MSCL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4A58))
#define MEMORY_MSCL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4A5C))
#define MEMORY_G3D_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4A60))
#define MEMORY_G3D_STATUS	((void *)(PMU_ALIVE_BASE + 0x4A64))
#define MEMORY_G3D_OPTION	((void *)(PMU_ALIVE_BASE + 0x4A68))
#define MEMORY_G3D_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4A70))
#define MEMORY_G3D_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4A74))
#define MEMORY_G3D_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4A78))
#define MEMORY_G3D_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4A7C))
#define MEMORY_DISP0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4A80))
#define MEMORY_DISP0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4A84))
#define MEMORY_DISP0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4A88))
#define MEMORY_DISP0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4A90))
#define MEMORY_DISP0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4A94))
#define MEMORY_DISP0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4A98))
#define MEMORY_DISP0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4A9C))
#define MEMORY_CAM1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4AA0))
#define MEMORY_CAM1_STATUS	((void *)(PMU_ALIVE_BASE + 0x4AA4))
#define MEMORY_CAM1_OPTION	((void *)(PMU_ALIVE_BASE + 0x4AA8))
#define MEMORY_CAM1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4AB0))
#define MEMORY_CAM1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4AB4))
#define MEMORY_CAM1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4AB8))
#define MEMORY_CAM1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4ABC))
#define MEMORY_AUD_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4AC0))
#define MEMORY_AUD_STATUS	((void *)(PMU_ALIVE_BASE + 0x4AC4))
#define MEMORY_AUD_OPTION	((void *)(PMU_ALIVE_BASE + 0x4AC8))
#define MEMORY_AUD_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4AD0))
#define MEMORY_AUD_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4AD4))
#define MEMORY_AUD_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4AD8))
#define MEMORY_AUD_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4ADC))
#define MEMORY_FSYS0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4AE0))
#define MEMORY_FSYS0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4AE4))
#define MEMORY_FSYS0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4AE8))
#define MEMORY_FSYS0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4AF0))
#define MEMORY_FSYS0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4AF4))
#define MEMORY_FSYS0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4AF8))
#define MEMORY_FSYS0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4AFC))
#define MEMORY_BUS0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4B00))
#define MEMORY_BUS0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4B04))
#define MEMORY_BUS0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4B08))
#define MEMORY_BUS0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4B10))
#define MEMORY_BUS0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4B14))
#define MEMORY_BUS0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4B18))
#define MEMORY_BUS0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4B1C))
#define MEMORY_ISP0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4B40))
#define MEMORY_ISP0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4B44))
#define MEMORY_ISP0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4B48))
#define MEMORY_ISP0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4B50))
#define MEMORY_ISP0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4B54))
#define MEMORY_ISP0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4B58))
#define MEMORY_ISP0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4B5C))
#define MEMORY_ISP1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4B60))
#define MEMORY_ISP1_STATUS	((void *)(PMU_ALIVE_BASE + 0x4B64))
#define MEMORY_ISP1_OPTION	((void *)(PMU_ALIVE_BASE + 0x4B68))
#define MEMORY_ISP1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4B70))
#define MEMORY_ISP1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4B74))
#define MEMORY_ISP1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4B78))
#define MEMORY_ISP1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4B7C))
#define MEMORY_MFC_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4B80))
#define MEMORY_MFC_STATUS	((void *)(PMU_ALIVE_BASE + 0x4B84))
#define MEMORY_MFC_OPTION	((void *)(PMU_ALIVE_BASE + 0x4B88))
#define MEMORY_MFC_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4B90))
#define MEMORY_MFC_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4B94))
#define MEMORY_MFC_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4B98))
#define MEMORY_MFC_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4B9C))
#define MEMORY_DISP1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4BA0))
#define MEMORY_DISP1_STATUS	((void *)(PMU_ALIVE_BASE + 0x4BA4))
#define MEMORY_DISP1_OPTION	((void *)(PMU_ALIVE_BASE + 0x4BA8))
#define MEMORY_DISP1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4BB0))
#define MEMORY_DISP1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4BB4))
#define MEMORY_DISP1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4BB8))
#define MEMORY_DISP1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4BBC))
#define MEMORY_FSYS1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4BC0))
#define MEMORY_FSYS1_STATUS	((void *)(PMU_ALIVE_BASE + 0x4BC4))
#define MEMORY_FSYS1_OPTION	((void *)(PMU_ALIVE_BASE + 0x4BC8))
#define MEMORY_FSYS1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4BD0))
#define MEMORY_FSYS1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4BD4))
#define MEMORY_FSYS1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4BD8))
#define MEMORY_FSYS1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4BDC))
#define RESET_CMU_CAM0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4C20))
#define RESET_CMU_CAM0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4C24))
#define RESET_CMU_CAM0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4C28))
#define RESET_CMU_CAM0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4C30))
#define RESET_CMU_CAM0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4C34))
#define RESET_CMU_CAM0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4C38))
#define RESET_CMU_CAM0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4C3C))
#define RESET_CMU_MSCL_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4C40))
#define RESET_CMU_MSCL_STATUS	((void *)(PMU_ALIVE_BASE + 0x4C44))
#define RESET_CMU_MSCL_OPTION	((void *)(PMU_ALIVE_BASE + 0x4C48))
#define RESET_CMU_MSCL_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4C50))
#define RESET_CMU_MSCL_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4C54))
#define RESET_CMU_MSCL_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4C58))
#define RESET_CMU_MSCL_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4C5C))
#define RESET_CMU_G3D_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4C60))
#define RESET_CMU_G3D_STATUS	((void *)(PMU_ALIVE_BASE + 0x4C64))
#define RESET_CMU_G3D_OPTION	((void *)(PMU_ALIVE_BASE + 0x4C68))
#define RESET_CMU_G3D_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4C70))
#define RESET_CMU_G3D_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4C74))
#define RESET_CMU_G3D_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4C78))
#define RESET_CMU_G3D_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4C7C))
#define RESET_CMU_DISP0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4C80))
#define RESET_CMU_DISP0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4C84))
#define RESET_CMU_DISP0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4C88))
#define RESET_CMU_DISP0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4C90))
#define RESET_CMU_DISP0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4C94))
#define RESET_CMU_DISP0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4C98))
#define RESET_CMU_DISP0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4C9C))
#define RESET_CMU_CAM1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4CA0))
#define RESET_CMU_CAM1_STATUS	((void *)(PMU_ALIVE_BASE + 0x4CA4))
#define RESET_CMU_CAM1_OPTION	((void *)(PMU_ALIVE_BASE + 0x4CA8))
#define RESET_CMU_CAM1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4CB0))
#define RESET_CMU_CAM1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4CB4))
#define RESET_CMU_CAM1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4CB8))
#define RESET_CMU_CAM1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4CBC))
#define RESET_CMU_AUD_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4CC0))
#define RESET_CMU_AUD_STATUS	((void *)(PMU_ALIVE_BASE + 0x4CC4))
#define RESET_CMU_AUD_OPTION	((void *)(PMU_ALIVE_BASE + 0x4CC8))
#define RESET_CMU_AUD_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4CD0))
#define RESET_CMU_AUD_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4CD4))
#define RESET_CMU_AUD_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4CD8))
#define RESET_CMU_AUD_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4CDC))
#define RESET_CMU_FSYS0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4CE0))
#define RESET_CMU_FSYS0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4CE4))
#define RESET_CMU_FSYS0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4CE8))
#define RESET_CMU_FSYS0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4CF0))
#define RESET_CMU_FSYS0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4CF4))
#define RESET_CMU_FSYS0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4CF8))
#define RESET_CMU_FSYS0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4CFC))
#define RESET_CMU_BUS0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4D00))
#define RESET_CMU_BUS0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4D04))
#define RESET_CMU_BUS0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4D08))
#define RESET_CMU_BUS0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4D10))
#define RESET_CMU_BUS0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4D14))
#define RESET_CMU_BUS0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4D18))
#define RESET_CMU_BUS0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4D1C))
#define RESET_CMU_ISP0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4D40))
#define RESET_CMU_ISP0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4D44))
#define RESET_CMU_ISP0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4D48))
#define RESET_CMU_ISP0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4D50))
#define RESET_CMU_ISP0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4D54))
#define RESET_CMU_ISP0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4D58))
#define RESET_CMU_ISP0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4D5C))
#define RESET_CMU_ISP1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4D60))
#define RESET_CMU_ISP1_STATUS	((void *)(PMU_ALIVE_BASE + 0x4D64))
#define RESET_CMU_ISP1_OPTION	((void *)(PMU_ALIVE_BASE + 0x4D68))
#define RESET_CMU_ISP1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4D70))
#define RESET_CMU_ISP1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4D74))
#define RESET_CMU_ISP1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4D78))
#define RESET_CMU_ISP1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4D7C))
#define RESET_CMU_MFC_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4D80))
#define RESET_CMU_MFC_STATUS	((void *)(PMU_ALIVE_BASE + 0x4D84))
#define RESET_CMU_MFC_OPTION	((void *)(PMU_ALIVE_BASE + 0x4D88))
#define RESET_CMU_MFC_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4D90))
#define RESET_CMU_MFC_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4D94))
#define RESET_CMU_MFC_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4D98))
#define RESET_CMU_MFC_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4D9C))
#define RESET_CMU_DISP1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4DA0))
#define RESET_CMU_DISP1_STATUS	((void *)(PMU_ALIVE_BASE + 0x4DA4))
#define RESET_CMU_DISP1_OPTION	((void *)(PMU_ALIVE_BASE + 0x4DA8))
#define RESET_CMU_DISP1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4DB0))
#define RESET_CMU_DISP1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4DB4))
#define RESET_CMU_DISP1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4DB8))
#define RESET_CMU_DISP1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4DBC))
#define RESET_CMU_FSYS1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4DC0))
#define RESET_CMU_FSYS1_STATUS	((void *)(PMU_ALIVE_BASE + 0x4DC4))
#define RESET_CMU_FSYS1_OPTION	((void *)(PMU_ALIVE_BASE + 0x4DC8))
#define RESET_CMU_FSYS1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4DD0))
#define RESET_CMU_FSYS1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4DD4))
#define RESET_CMU_FSYS1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4DD8))
#define RESET_CMU_FSYS1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4DDC))
#define RESET_SLEEP_FSYS0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4EE0))
#define RESET_SLEEP_FSYS0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4EE4))
#define RESET_SLEEP_FSYS0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4EE8))
#define RESET_SLEEP_FSYS0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4EF0))
#define RESET_SLEEP_FSYS0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4EF4))
#define RESET_SLEEP_FSYS0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4EF8))
#define RESET_SLEEP_FSYS0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4EFC))
#define RESET_SLEEP_BUS0_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4F00))
#define RESET_SLEEP_BUS0_STATUS	((void *)(PMU_ALIVE_BASE + 0x4F04))
#define RESET_SLEEP_BUS0_OPTION	((void *)(PMU_ALIVE_BASE + 0x4F08))
#define RESET_SLEEP_BUS0_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4F10))
#define RESET_SLEEP_BUS0_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4F14))
#define RESET_SLEEP_BUS0_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4F18))
#define RESET_SLEEP_BUS0_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4F1C))
#define RESET_SLEEP_FSYS1_CONFIGURATION	((void *)(PMU_ALIVE_BASE + 0x4FC0))
#define RESET_SLEEP_FSYS1_STATUS	((void *)(PMU_ALIVE_BASE + 0x4FC4))
#define RESET_SLEEP_FSYS1_OPTION	((void *)(PMU_ALIVE_BASE + 0x4FC8))
#define RESET_SLEEP_FSYS1_DURATION0	((void *)(PMU_ALIVE_BASE + 0x4FD0))
#define RESET_SLEEP_FSYS1_DURATION1	((void *)(PMU_ALIVE_BASE + 0x4FD4))
#define RESET_SLEEP_FSYS1_DURATION2	((void *)(PMU_ALIVE_BASE + 0x4FD8))
#define RESET_SLEEP_FSYS1_DURATION3	((void *)(PMU_ALIVE_BASE + 0x4FDC))
#define CLK_MUX_SEL_AUD	((void *)(PMU_ALIVE_BASE + 0x5000))
#define CLK_MUX_STAT_AUD	((void *)(PMU_ALIVE_BASE + 0x5004))
#define SYSTEM_INFO	((void *)(PMU_ALIVE_BASE + 0x5008))
#define JTAG_DBG_DET	((void *)(PMU_ALIVE_BASE + 0x6000))
#define MNGS_CORERST_LOCK	((void *)(PMU_ALIVE_BASE + 0x6004))
#define APOLLO_CORERST_LOCK	((void *)(PMU_ALIVE_BASE + 0x6008))
#define GPU_DVS_CTRL	((void *)(PMU_ALIVE_BASE + 0x6100))
#define GPU_DVS_STATUS	((void *)(PMU_ALIVE_BASE + 0x6104))
#define GPU_DVS_COUNTER	((void *)(PMU_ALIVE_BASE + 0x6108))
#define GPU_DVS_CLK_CTRL	((void *)(PMU_ALIVE_BASE + 0x610C))
#define IRQ_SELECTION	((void *)(PMU_ALIVE_BASE + 0x6800))
#define DEK0	((void *)(PMU_ALIVE_BASE + 0x7000))
#define DEK1	((void *)(PMU_ALIVE_BASE + 0x7004))
#define DEK2	((void *)(PMU_ALIVE_BASE + 0x7008))
#define DEK3	((void *)(PMU_ALIVE_BASE + 0x700C))
#define DEK4	((void *)(PMU_ALIVE_BASE + 0x7010))
#define DEK5	((void *)(PMU_ALIVE_BASE + 0x7014))
#define DEK6	((void *)(PMU_ALIVE_BASE + 0x7018))
#define DEK7	((void *)(PMU_ALIVE_BASE + 0x701C))
#define DEK8	((void *)(PMU_ALIVE_BASE + 0x7020))
#define DEK9	((void *)(PMU_ALIVE_BASE + 0x7024))
#define DEK10	((void *)(PMU_ALIVE_BASE + 0x7028))
#define DEK11	((void *)(PMU_ALIVE_BASE + 0x702C))
#define DEK12	((void *)(PMU_ALIVE_BASE + 0x7030))
#define DEK13	((void *)(PMU_ALIVE_BASE + 0x7034))
#define DEK14	((void *)(PMU_ALIVE_BASE + 0x7038))
#define DEK15	((void *)(PMU_ALIVE_BASE + 0x703C))


#define LPI_MASK_APOLLO_ASB	((void *)(PMU_APOLLO_BASE + 0x0020))
#define LPI_DENIAL_MASK_APOLLO_ASB	((void *)(PMU_APOLLO_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_APOLLO_ASB	((void *)(PMU_APOLLO_BASE + 0x0220))
#define LPI_STATUS_APOLLO_ASB	((void *)(PMU_APOLLO_BASE + 0x0320))


#define LPI_MASK_AUD_ASB	((void *)(PMU_AUD_BASE + 0x0020))
#define LPI_DENIAL_MASK_AUD_ASB	((void *)(PMU_AUD_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_AUD_ASB	((void *)(PMU_AUD_BASE + 0x0220))
#define LPI_STATUS_AUD_ASB	((void *)(PMU_AUD_BASE + 0x0320))


#define LPI_MASK_BUS0_ASB	((void *)(PMU_BUS0_BASE + 0x0020))
#define LPI_DENIAL_MASK_BUS0_ASB	((void *)(PMU_BUS0_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_BUS0_ASB	((void *)(PMU_BUS0_BASE + 0x0220))
#define LPI_STATUS_BUS0_ASB	((void *)(PMU_BUS0_BASE + 0x0320))


#define LPI_MASK_BUS1_ASB	((void *)(PMU_BUS1_BASE + 0x0020))
#define LPI_DENIAL_MASK_BUS1_ASB	((void *)(PMU_BUS1_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_BUS1_ASB	((void *)(PMU_BUS1_BASE + 0x0220))
#define LPI_STATUS_BUS1_ASB	((void *)(PMU_BUS1_BASE + 0x0320))


#define LPI_MASK_CAM0_BUSMASTER	((void *)(PMU_CAM0_BASE + 0x0000))
#define LPI_MASK_CAM0_ASB	((void *)(PMU_CAM0_BASE + 0x0020))
#define LPI_DENIAL_MASK_CAM0_BUSMASTER	((void *)(PMU_CAM0_BASE + 0x0100))
#define LPI_DENIAL_MASK_CAM0_ASB	((void *)(PMU_CAM0_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_CAM0_BUSMASTER	((void *)(PMU_CAM0_BASE + 0x0200))
#define LPI_AUTOMATIC_CLKGATE_CAM0_ASB	((void *)(PMU_CAM0_BASE + 0x0220))
#define LPI_STATUS_CAM0_BUSMASTER	((void *)(PMU_CAM0_BASE + 0x0300))
#define LPI_STATUS_CAM0_ASB	((void *)(PMU_CAM0_BASE + 0x0320))


#define LPI_MASK_CAM1_BUSMASTER	((void *)(PMU_CAM1_BASE + 0x0000))
#define LPI_MASK_CAM1_ASB	((void *)(PMU_CAM1_BASE + 0x0020))
#define LPI_DENIAL_MASK_CAM1_BUSMASTER	((void *)(PMU_CAM1_BASE + 0x0100))
#define LPI_DENIAL_MASK_CAM1_ASB	((void *)(PMU_CAM1_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_CAM1_BUSMASTER	((void *)(PMU_CAM1_BASE + 0x0200))
#define LPI_AUTOMATIC_CLKGATE_CAM1_ASB	((void *)(PMU_CAM1_BASE + 0x0220))
#define LPI_STATUS_CAM1_BUSMASTER	((void *)(PMU_CAM1_BASE + 0x0300))
#define LPI_STATUS_CAM1_ASB	((void *)(PMU_CAM1_BASE + 0x0320))


#define LPI_MASK_CCORE_ASB	((void *)(PMU_CCORE_BASE + 0x0020))
#define LPI_MASK_CCORE_DRAM	((void *)(PMU_CCORE_BASE + 0x0060))
#define LPI_DENIAL_MASK_CCORE_ASB	((void *)(PMU_CCORE_BASE + 0x0120))
#define LPI_DENIAL_MASK_CCORE_DRAM	((void *)(PMU_CCORE_BASE + 0x0160))
#define LPI_AUTOMATIC_CLKGATE_CCORE_ASB	((void *)(PMU_CCORE_BASE + 0x0220))
#define LPI_AUTOMATIC_CLKGATE_CCORE_DRAM	((void *)(PMU_CCORE_BASE + 0x0260))
#define LPI_STATUS_CCORE_ASB	((void *)(PMU_CCORE_BASE + 0x0320))
#define LPI_STATUS_CCORE_DRAM	((void *)(PMU_CCORE_BASE + 0x0360))


#define LPI_MASK_DISP0_BUSMASTER	((void *)(PMU_DISP0_BASE + 0x0000))
#define LPI_MASK_DISP0_ASB	((void *)(PMU_DISP0_BASE + 0x0020))
#define LPI_DENIAL_MASK_DISP0_BUSMASTER	((void *)(PMU_DISP0_BASE + 0x0100))
#define LPI_DENIAL_MASK_DISP0_ASB	((void *)(PMU_DISP0_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_DISP0_BUSMASTER	((void *)(PMU_DISP0_BASE + 0x0200))
#define LPI_AUTOMATIC_CLKGATE_DISP0_ASB	((void *)(PMU_DISP0_BASE + 0x0220))
#define LPI_STATUS_DISP0_BUSMASTER	((void *)(PMU_DISP0_BASE + 0x0300))
#define LPI_STATUS_DISP0_ASB	((void *)(PMU_DISP0_BASE + 0x0320))


#define LPI_MASK_DISP1_BUSMASTER	((void *)(PMU_DISP1_BASE + 0x0000))
#define LPI_MASK_DISP1_ASB	((void *)(PMU_DISP1_BASE + 0x0020))
#define LPI_DENIAL_MASK_DISP1_BUSMASTER	((void *)(PMU_DISP1_BASE + 0x0100))
#define LPI_DENIAL_MASK_DISP1_ASB	((void *)(PMU_DISP1_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_DISP1_BUSMASTER	((void *)(PMU_DISP1_BASE + 0x0200))
#define LPI_AUTOMATIC_CLKGATE_DISP1_ASB	((void *)(PMU_DISP1_BASE + 0x0220))
#define LPI_STATUS_DISP1_BUSMASTER	((void *)(PMU_DISP1_BASE + 0x0300))
#define LPI_STATUS_DISP1_ASB	((void *)(PMU_DISP1_BASE + 0x0320))


#define LPI_MASK_FSYS0_BUSMASTER	((void *)(PMU_FSYS0_BASE + 0x0000))
#define LPI_MASK_FSYS0_ASB	((void *)(PMU_FSYS0_BASE + 0x0020))
#define LPI_DENIAL_MASK_FSYS0_BUSMASTER	((void *)(PMU_FSYS0_BASE + 0x0100))
#define LPI_DENIAL_MASK_FSYS0_ASB	((void *)(PMU_FSYS0_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_FSYS0_BUSMASTER	((void *)(PMU_FSYS0_BASE + 0x0200))
#define LPI_AUTOMATIC_CLKGATE_FSYS0_ASB	((void *)(PMU_FSYS0_BASE + 0x0220))
#define LPI_STATUS_FSYS0_BUSMASTER	((void *)(PMU_FSYS0_BASE + 0x0300))
#define LPI_STATUS_FSYS0_ASB	((void *)(PMU_FSYS0_BASE + 0x0320))


#define LPI_MASK_FSYS1_BUSMASTER	((void *)(PMU_FSYS1_BASE + 0x0000))
#define LPI_MASK_FSYS1_ASB	((void *)(PMU_FSYS1_BASE + 0x0020))
#define LPI_DENIAL_MASK_FSYS1_BUSMASTER	((void *)(PMU_FSYS1_BASE + 0x0100))
#define LPI_DENIAL_MASK_FSYS1_ASB	((void *)(PMU_FSYS1_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_FSYS1_BUSMASTER	((void *)(PMU_FSYS1_BASE + 0x0200))
#define LPI_AUTOMATIC_CLKGATE_FSYS1_ASB	((void *)(PMU_FSYS1_BASE + 0x0220))
#define LPI_STATUS_FSYS1_BUSMASTER	((void *)(PMU_FSYS1_BASE + 0x0300))
#define LPI_STATUS_FSYS1_ASB	((void *)(PMU_FSYS1_BASE + 0x0320))


#define LPI_MASK_G3D_ASB	((void *)(PMU_G3D_BASE + 0x0020))
#define LPI_DENIAL_MASK_G3D_ASB	((void *)(PMU_G3D_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_G3D_ASB	((void *)(PMU_G3D_BASE + 0x0220))
#define LPI_STATUS_G3D_ASB	((void *)(PMU_G3D_BASE + 0x0320))


#define LPI_MASK_IMEM_BUSMASTER	((void *)(PMU_IMEM_BASE + 0x0000))
#define LPI_MASK_IMEM_ASB	((void *)(PMU_IMEM_BASE + 0x0020))
#define LPI_DENIAL_MASK_IMEM_BUSMASTER	((void *)(PMU_IMEM_BASE + 0x0100))
#define LPI_DENIAL_MASK_IMEM_ASB	((void *)(PMU_IMEM_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_IMEM_BUSMASTER	((void *)(PMU_IMEM_BASE + 0x0200))
#define LPI_AUTOMATIC_CLKGATE_IMEM_ASB	((void *)(PMU_IMEM_BASE + 0x0220))
#define LPI_STATUS_IMEM_BUSMASTER	((void *)(PMU_IMEM_BASE + 0x0300))
#define LPI_STATUS_IMEM_ASB	((void *)(PMU_IMEM_BASE + 0x0320))


#define LPI_MASK_ISP0_BUSMASTER	((void *)(PMU_ISP0_BASE + 0x0000))
#define LPI_MASK_ISP0_ASB	((void *)(PMU_ISP0_BASE + 0x0020))
#define LPI_DENIAL_MASK_ISP0_BUSMASTER	((void *)(PMU_ISP0_BASE + 0x0100))
#define LPI_DENIAL_MASK_ISP0_ASB	((void *)(PMU_ISP0_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_ISP0_BUSMASTER	((void *)(PMU_ISP0_BASE + 0x0200))
#define LPI_AUTOMATIC_CLKGATE_ISP0_ASB	((void *)(PMU_ISP0_BASE + 0x0220))
#define LPI_STATUS_ISP0_BUSMASTER	((void *)(PMU_ISP0_BASE + 0x0300))
#define LPI_STATUS_ISP0_ASB	((void *)(PMU_ISP0_BASE + 0x0320))


#define LPI_MASK_ISP1_BUSMASTER	((void *)(PMU_ISP1_BASE + 0x0000))
#define LPI_MASK_ISP1_ASB	((void *)(PMU_ISP1_BASE + 0x0020))
#define LPI_DENIAL_MASK_ISP1_BUSMASTER	((void *)(PMU_ISP1_BASE + 0x0100))
#define LPI_DENIAL_MASK_ISP1_ASB	((void *)(PMU_ISP1_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_ISP1_BUSMASTER	((void *)(PMU_ISP1_BASE + 0x0200))
#define LPI_AUTOMATIC_CLKGATE_ISP1_ASB	((void *)(PMU_ISP1_BASE + 0x0220))
#define LPI_STATUS_ISP1_BUSMASTER	((void *)(PMU_ISP1_BASE + 0x0300))
#define LPI_STATUS_ISP1_ASB	((void *)(PMU_ISP1_BASE + 0x0320))


#define LPI_MASK_MFC_BUSMASTER	((void *)(PMU_MFC_BASE + 0x0000))
#define LPI_MASK_MFC_ASB	((void *)(PMU_MFC_BASE + 0x0020))
#define LPI_DENIAL_MASK_MFC_BUSMASTER	((void *)(PMU_MFC_BASE + 0x0100))
#define LPI_DENIAL_MASK_MFC_ASB	((void *)(PMU_MFC_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_MFC_BUSMASTER	((void *)(PMU_MFC_BASE + 0x0200))
#define LPI_AUTOMATIC_CLKGATE_MFC_ASB	((void *)(PMU_MFC_BASE + 0x0220))
#define LPI_STATUS_MFC_BUSMASTER	((void *)(PMU_MFC_BASE + 0x0300))
#define LPI_STATUS_MFC_ASB	((void *)(PMU_MFC_BASE + 0x0320))


#define LPI_MASK_MIF_ASB_MIF0	((void *)(PMU_MIF0_BASE + 0x0020))
#define LPI_MASK_MIF_DRAM_MIF0	((void *)(PMU_MIF0_BASE + 0x0060))
#define LPI_DENIAL_MASK_MIF_ASB_MIF0	((void *)(PMU_MIF0_BASE + 0x0120))
#define LPI_DENIAL_MASK_MIF_DRAM_MIF0	((void *)(PMU_MIF0_BASE + 0x0160))
#define LPI_AUTOMATIC_CLKGATE_MIF_ASB_MIF0	((void *)(PMU_MIF0_BASE + 0x0220))
#define LPI_AUTOMATIC_CLKGATE_MIF_DRAM_MIF0	((void *)(PMU_MIF0_BASE + 0x0260))
#define LPI_STATUS_MIF_ASB_MIF0	((void *)(PMU_MIF0_BASE + 0x0320))


#define LPI_MASK_MIF_ASB_MIF1	((void *)(PMU_MIF1_BASE + 0x0020))
#define LPI_MASK_MIF_DRAM_MIF1	((void *)(PMU_MIF1_BASE + 0x0060))
#define LPI_DENIAL_MASK_MIF_ASB_MIF1	((void *)(PMU_MIF1_BASE + 0x0120))
#define LPI_DENIAL_MASK_MIF_DRAM_MIF1	((void *)(PMU_MIF1_BASE + 0x0160))
#define LPI_AUTOMATIC_CLKGATE_MIF_ASB_MIF1	((void *)(PMU_MIF1_BASE + 0x0220))
#define LPI_AUTOMATIC_CLKGATE_MIF_DRAM_MIF1	((void *)(PMU_MIF1_BASE + 0x0260))
#define LPI_STATUS_MIF_ASB_MIF1	((void *)(PMU_MIF1_BASE + 0x0320))


#define LPI_MASK_MIF_ASB_MIF2	((void *)(PMU_MIF2_BASE + 0x0020))
#define LPI_MASK_MIF_DRAM_MIF2	((void *)(PMU_MIF2_BASE + 0x0060))
#define LPI_DENIAL_MASK_MIF_ASB_MIF2	((void *)(PMU_MIF2_BASE + 0x0120))
#define LPI_DENIAL_MASK_MIF_DRAM_MIF2	((void *)(PMU_MIF2_BASE + 0x0160))
#define LPI_AUTOMATIC_CLKGATE_MIF_ASB_MIF2	((void *)(PMU_MIF2_BASE + 0x0220))
#define LPI_AUTOMATIC_CLKGATE_MIF_DRAM_MIF2	((void *)(PMU_MIF2_BASE + 0x0260))
#define LPI_STATUS_MIF_ASB_MIF2	((void *)(PMU_MIF2_BASE + 0x0320))


#define LPI_MASK_MIF_ASB_MIF3	((void *)(PMU_MIF3_BASE + 0x0020))
#define LPI_MASK_MIF_DRAM_MIF3	((void *)(PMU_MIF3_BASE + 0x0060))
#define LPI_DENIAL_MASK_MIF_ASB_MIF3	((void *)(PMU_MIF3_BASE + 0x0120))
#define LPI_DENIAL_MASK_MIF_DRAM_MIF3	((void *)(PMU_MIF3_BASE + 0x0160))
#define LPI_AUTOMATIC_CLKGATE_MIF_ASB_MIF3	((void *)(PMU_MIF3_BASE + 0x0220))
#define LPI_AUTOMATIC_CLKGATE_MIF_DRAM_MIF3	((void *)(PMU_MIF3_BASE + 0x0260))
#define LPI_STATUS_MIF_ASB_MIF3	((void *)(PMU_MIF3_BASE + 0x0320))


#define LPI_MASK_MNGS_BUSMASTER	((void *)(PMU_MNGS_BASE + 0x0000))
#define LPI_MASK_MNGS_ASB	((void *)(PMU_MNGS_BASE + 0x0020))
#define LPI_DENIAL_MASK_MNGS_BUSMASTER	((void *)(PMU_MNGS_BASE + 0x0100))
#define LPI_DENIAL_MASK_MNGS_ASB	((void *)(PMU_MNGS_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_MNGS_BUSMASTER	((void *)(PMU_MNGS_BASE + 0x0200))
#define LPI_AUTOMATIC_CLKGATE_MNGS_ASB	((void *)(PMU_MNGS_BASE + 0x0220))
#define LPI_STATUS_MNGS_BUSMASTER	((void *)(PMU_MNGS_BASE + 0x0300))
#define LPI_STATUS_MNGS_ASB	((void *)(PMU_MNGS_BASE + 0x0320))


#define LPI_MASK_MSCL_BUSMASTER	((void *)(PMU_MSCL_BASE + 0x0000))
#define LPI_MASK_MSCL_ASB	((void *)(PMU_MSCL_BASE + 0x0020))
#define LPI_DENIAL_MASK_MSCL_BUSMASTER	((void *)(PMU_MSCL_BASE + 0x0100))
#define LPI_DENIAL_MASK_MSCL_ASB	((void *)(PMU_MSCL_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_MSCL_BUSMASTER	((void *)(PMU_MSCL_BASE + 0x0200))
#define LPI_AUTOMATIC_CLKGATE_MSCL_ASB	((void *)(PMU_MSCL_BASE + 0x0220))
#define LPI_STATUS_MSCL_BUSMASTER	((void *)(PMU_MSCL_BASE + 0x0300))
#define LPI_STATUS_MSCL_ASB	((void *)(PMU_MSCL_BASE + 0x0320))


#define LPI_MASK_PERIC0_ASB	((void *)(PMU_PERIC0_BASE + 0x0020))
#define LPI_DENIAL_MASK_PERIC0_ASB	((void *)(PMU_PERIC0_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_PERIC0_ASB	((void *)(PMU_PERIC0_BASE + 0x0220))
#define LPI_STATUS_PERIC0_ASB	((void *)(PMU_PERIC0_BASE + 0x0320))


#define LPI_MASK_PERIC1_ASB	((void *)(PMU_PERIC1_BASE + 0x0020))
#define LPI_DENIAL_MASK_PERIC1_ASB	((void *)(PMU_PERIC1_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_PERIC1_ASB	((void *)(PMU_PERIC1_BASE + 0x0220))
#define LPI_STATUS_PERIC1_ASB	((void *)(PMU_PERIC1_BASE + 0x0320))

#define LPI_MASK_PERIS_ASB	((void *)(PMU_PERIS_BASE + 0x0020))
#define LPI_DENIAL_MASK_PERIS_ASB	((void *)(PMU_PERIS_BASE + 0x0120))
#define LPI_AUTOMATIC_CLKGATE_PERIS_ASB	((void *)(PMU_PERIS_BASE + 0x0220))
#define LPI_STATUS_PERIS_ASB	((void *)(PMU_PERIS_BASE + 0x0320))



#endif