#ifndef __EXYNOS8890_SFRBASE_H__
#define __EXYNOS8890_SFRBASE_H__

#include "../pwrcal-env.h"

#ifdef PWRCAL_TARGET_FW

#define CMU_PERIS_BASE	0x10040000
#define CMU_TOP_BASE	0x10570000
#define CMU_CCORE_BASE	0x105B0000
#define CMU_MIF0_BASE	0x10850000
#define CMU_MIF1_BASE	0x10950000
#define CMU_MIF2_BASE	0x10A50000
#define CMU_MIF3_BASE	0x10B50000
#define CMU_FSYS0_BASE	0x10E90000
#define CMU_IMEM_BASE	0x11060000
#define CMU_AUD_BASE	0x114C0000
#define CMU_MNGS_BASE	0x11800000
#define CMU_APOLLO_BASE	0x11900000
#define CMU_BUS0_BASE	0x13400000
#define CMU_BUS1_BASE	0x14800000
#define CMU_PERIC0_BASE	0x13610000
#define CMU_DISP0_BASE	0x13AD0000
#define CMU_DISP1_BASE	0x13F00000
#define CMU_CAM0_LOCAL_BASE	0x140F0000
#define CMU_CAM0_BASE	0x144D0000
#define CMU_CAM1_LOCAL_BASE	0x141F0000
#define CMU_CAM1_BASE	0x145D0000
#define CMU_ISP0_LOCAL_BASE	0x14290000
#define CMU_ISP0_BASE	0x146D0000
#define CMU_ISP1_LOCAL_BASE	0x142F0000
#define CMU_ISP1_BASE	0x147D0000
#define CMU_G3D_BASE	0x14AA0000
#define CMU_PERIC1_BASE	0x14C80000
#define CMU_MSCL_BASE	0x150D0000
#define CMU_MFC_BASE	0x15280000
#define CMU_FSYS1_BASE	0x156E0000


#define PMU_PERIS_BASE	0x10010000
#define PMU_ALIVE_BASE	0x105C0000
#define PMU_CCORE_BASE	0x105F0000
#define PMU_MIF0_BASE	0x10840000
#define PMU_MIF1_BASE	0x10940000
#define PMU_MIF2_BASE	0x10A40000
#define PMU_MIF3_BASE	0x10B40000
#define PMU_FSYS0_BASE	0x10E70000
#define PMU_IMEM_BASE	0x11070000
#define PMU_AUD_BASE	0x114D0000
#define PMU_MNGS_BASE	0x11820000
#define PMU_APOLLO_BASE	0x11920000
#define PMU_BUS0_BASE	0x13420000
#define PMU_BUS1_BASE	0x14820000
#define PMU_PERIC0_BASE	0x13600000
#define PMU_DISP0_BASE	0x13AE0000
#define PMU_DISP1_BASE	0x13F10000
#define PMU_CAM0_BASE	0x144E0000
#define PMU_CAM1_BASE	0x145E0000
#define PMU_ISP0_BASE	0x146E0000
#define PMU_ISP1_BASE	0x147E0000
#define PMU_G3D_BASE	0x14A40000
#define PMU_PERIC1_BASE	0x14C70000
#define PMU_MSCL_BASE	0x150F0000
#define PMU_MFC_BASE	0x15290000
#define PMU_FSYS1_BASE	0x156C0000

#define DMC_MISC_CCORE_BASE	0x10520000
#define LPDDR4_PHY0_BASE	0x10820000

#define SYSREG_APOLLO_BASE	0x11940000
#define SYSREG_AUD_BASE	0x11480000
#define SYSREG_BUS0_BASE	0x134C0000
#define SYSREG_BUS1_BASE	0x148C0000
#define SYSREG_CAM0_BASE	0x144F0000
#define SYSREG_CAM1_BASE	0x145F0000
#define SYSREG_CCORE_BASE	0x105D0000
#define SYSREG_DISP0_BASE	0x13A60000
#define SYSREG_DISP1_BASE	0x13F20000
#define SYSREG_FSYS0_BASE	0x10E50000
#define SYSREG_FSYS1_BASE	0x15600000
#define SYSREG_G3D_BASE	0x14AE0000
#define SYSREG_IMEM_BASE	0x11080000
#define SYSREG_ISP0_BASE	0x146F0000
#define SYSREG_ISP1_BASE	0x147F0000
#define SYSREG_MFC_BASE	0x152A0000
#define SYSREG_MIF0_BASE	0x10830000
#define SYSREG_MIF1_BASE	0x10930000
#define SYSREG_MIF2_BASE	0x10A30000
#define SYSREG_MIF3_BASE	0x10B30000
#define SYSREG_MNGS_BASE	0x11850000
#define SYSREG_MSCL_BASE	0x151C0000
#define SYSREG_PERIC0_BASE	0x136E0000
#define SYSREG_PERIC1_BASE	0x14C60000
#define SYSREG_PERIS_BASE	0x10050000

#endif

#ifdef PWRCAL_TARGET_LINUX

#define CMU_PERIS_BASE	0x00010000
#define CMU_TOP_BASE	0x00020000
#define CMU_CCORE_BASE	0x00030000
#define CMU_MIF0_BASE	0x00040000
#define CMU_MIF1_BASE	0x00050000
#define CMU_MIF2_BASE	0x00060000
#define CMU_MIF3_BASE	0x00070000
#define CMU_FSYS0_BASE	0x00080000
#define CMU_IMEM_BASE	0x00090000
#define CMU_AUD_BASE	0x000A0000
#define CMU_MNGS_BASE	0x000B0000
#define CMU_APOLLO_BASE	0x000C0000
#define CMU_BUS0_BASE	0x000D0000
#define CMU_BUS1_BASE	0x000E0000
#define CMU_PERIC0_BASE	0x000F0000
#define CMU_DISP0_BASE	0x00100000
#define CMU_DISP1_BASE	0x00110000
#define CMU_CAM0_LOCAL_BASE	0x00120000
#define CMU_CAM0_BASE	0x00130000
#define CMU_CAM1_LOCAL_BASE	0x00140000
#define CMU_CAM1_BASE	0x00150000
#define CMU_ISP0_LOCAL_BASE	0x00160000
#define CMU_ISP0_BASE	0x00170000
#define CMU_ISP1_LOCAL_BASE	0x00180000
#define CMU_ISP1_BASE	0x00190000
#define CMU_G3D_BASE	0x001A0000
#define CMU_PERIC1_BASE	0x001B0000
#define CMU_MSCL_BASE	0x001C0000
#define CMU_MFC_BASE	0x001D0000
#define CMU_FSYS1_BASE	0x001E0000


#define PMU_PERIS_BASE	0x001F0000
#define PMU_ALIVE_BASE	0x00200000
#define PMU_CCORE_BASE	0x00210000
#define PMU_MIF0_BASE	0x00220000
#define PMU_MIF1_BASE	0x00230000
#define PMU_MIF2_BASE	0x00240000
#define PMU_MIF3_BASE	0x00250000
#define PMU_FSYS0_BASE	0x00260000
#define PMU_IMEM_BASE	0x00270000
#define PMU_AUD_BASE	0x00280000
#define PMU_MNGS_BASE	0x00290000
#define PMU_APOLLO_BASE	0x002A0000
#define PMU_BUS0_BASE	0x002B0000
#define PMU_BUS1_BASE	0x002C0000
#define PMU_PERIC0_BASE	0x002D0000
#define PMU_DISP0_BASE	0x002E0000
#define PMU_DISP1_BASE	0x002F0000
#define PMU_CAM0_BASE	0x00300000
#define PMU_CAM1_BASE	0x00310000
#define PMU_ISP0_BASE	0x00320000
#define PMU_ISP1_BASE	0x00330000
#define PMU_G3D_BASE	0x00340000
#define PMU_PERIC1_BASE	0x00350000
#define PMU_MSCL_BASE	0x00360000
#define PMU_MFC_BASE	0x00370000
#define PMU_FSYS1_BASE	0x00380000

#define DMC_MISC_CCORE_BASE	0x00390000
#define LPDDR4_PHY0_BASE	0x003A0000

#define SYSREG_APOLLO_BASE	0x003B0000
#define SYSREG_AUD_BASE	0x003C0000
#define SYSREG_BUS0_BASE	0x003D0000
#define SYSREG_BUS1_BASE	0x003E0000
#define SYSREG_CAM0_BASE	0x003F0000
#define SYSREG_CAM1_BASE	0x00400000
#define SYSREG_CCORE_BASE	0x00410000
#define SYSREG_DISP0_BASE	0x00420000
#define SYSREG_DISP1_BASE	0x00430000
#define SYSREG_FSYS0_BASE	0x00440000
#define SYSREG_FSYS1_BASE	0x00450000
#define SYSREG_G3D_BASE	0x00460000
#define SYSREG_IMEM_BASE	0x00470000
#define SYSREG_ISP0_BASE	0x00480000
#define SYSREG_ISP1_BASE	0x00490000
#define SYSREG_MFC_BASE	0x004A0000
#define SYSREG_MIF0_BASE	0x004B0000
#define SYSREG_MIF1_BASE	0x004C0000
#define SYSREG_MIF2_BASE	0x004D0000
#define SYSREG_MIF3_BASE	0x004E0000
#define SYSREG_MNGS_BASE	0x004F0000
#define SYSREG_MSCL_BASE	0x00500000
#define SYSREG_PERIC0_BASE	0x00510000
#define SYSREG_PERIC1_BASE	0x00520000
#define SYSREG_PERIS_BASE	0x00530000

#endif

#endif