/*
 * s2mps15.h
 *
 * Copyright (c) 2012 Samsung Electronics Co., Ltd
 *              http://www.samsung.com
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 */

#ifndef __LINUX_MFD_S2MPS15_H
#define __LINUX_MFD_S2MPS15_H

/* S2MPS15 Revision Number */
enum s2mps15_revision_number {
	S2MPS15_REV_0 = 0x00,
	S2MPS15_REV_1 = 0x01,
};

/* S2MPS15 registers */
enum S2MPS15_reg {
	S2MPS15_REG_ID,
	S2MPS15_REG_INT1,
	S2MPS15_REG_INT2,
	S2MPS15_REG_INT3,
	S2MPS15_REG_INT1M,
	S2MPS15_REG_INT2M,
	S2MPS15_REG_INT3M,
	S2MPS15_REG_ST1,
	S2MPS15_REG_ST2,
	S2MPS15_REG_PWRONSRC,
	S2MPS15_REG_OFFSRC,
	S2MPS15_REG_BU_CHG,
	S2MPS15_REG_RTC_BUF,
	S2MPS15_REG_CTRL1,
	S2MPS15_REG_CTRL2,
	S2MPS15_REG_ETC_TEST,
	S2MPS15_REG_OTP_ADRL,
	S2MPS15_REG_OTP_ADRH,
	S2MPS15_REG_OTP_DATA,
	S2MPS15_REG_MON1SEL,
	S2MPS15_REG_MON2SEL,
	S2MPS15_REG_CTRL3,
	S2MPS15_REG_ETC_OTP,
	S2MPS15_REG_UVLO_OTP,
	S2MPS15_REG_LEE,
	S2MPS15_REG_B1CTRL1,
	S2MPS15_REG_B1CTRL2,
	S2MPS15_REG_B2CTRL1,
	S2MPS15_REG_B2CTRL2,
	S2MPS15_REG_B3CTRL1,
	S2MPS15_REG_B3CTRL2,
	S2MPS15_REG_B4CTRL1,
	S2MPS15_REG_B4CTRL2,
	S2MPS15_REG_B5CTRL1,
	S2MPS15_REG_B5CTRL2,
	S2MPS15_REG_B6CTRL1,
	S2MPS15_REG_B6CTRL2,
	S2MPS15_REG_B7CTRL1,
	S2MPS15_REG_B7CTRL2,
	S2MPS15_REG_B8CTRL1,
	S2MPS15_REG_B8CTRL2,
	S2MPS15_REG_B9CTRL1,
	S2MPS15_REG_B9CTRL2,
	S2MPS15_REG_B10CTRL1,
	S2MPS15_REG_B10CTRL2,
	S2MPS15_REG_BB1CTRL1,
	S2MPS15_REG_BB1CTRL2,
	S2MPS15_REG_BUCK_RAMP1,
	S2MPS15_REG_LDO_DVS1,
	S2MPS15_REG_LDO_DVS2,
	S2MPS15_REG_LDO_DVS3,
	S2MPS15_REG_LDO_DVS4,
	S2MPS15_REG_L1CTRL,
	S2MPS15_REG_L2CTRL,
	S2MPS15_REG_L3CTRL,
	S2MPS15_REG_L4CTRL,
	S2MPS15_REG_L5CTRL,
	S2MPS15_REG_L6CTRL,
	S2MPS15_REG_L7CTRL,
	S2MPS15_REG_L8CTRL,
	S2MPS15_REG_L9CTRL,
	S2MPS15_REG_L10CTRL,
	S2MPS15_REG_L11CTRL,
	S2MPS15_REG_L12CTRL,
	S2MPS15_REG_L13CTRL,
	S2MPS15_REG_L14CTRL,
	S2MPS15_REG_L15CTRL,
	S2MPS15_REG_L16CTRL,
	S2MPS15_REG_L17CTRL,
	S2MPS15_REG_L18CTRL,
	S2MPS15_REG_L19CTRL,
	S2MPS15_REG_L20CTRL,
	S2MPS15_REG_L21CTRL,
	S2MPS15_REG_L22CTRL,
	S2MPS15_REG_L23CTRL,
	S2MPS15_REG_L24CTRL,
	S2MPS15_REG_L25CTRL,
	S2MPS15_REG_L26CTRL,
	S2MPS15_REG_L27CTRL,
	S2MPS15_REG_LDO_DSCH1,
	S2MPS15_REG_LDO_DSCH2,
	S2MPS15_REG_LDO_DSCH3,
	S2MPS15_REG_LDO_DSCH4,
	S2MPS15_REG_L26CTRL_REV1	= 0x4C,
	S2MPS15_REG_L25CTRL_REV1	= 0x4D,
	S2MPS15_REG_LDO_RSVD3	= 0x52,
	S2MPS15_REG_B6CTRL3	= 0x57,
	S2MPS15_REG_ADC_CTRL1	= 0x5B,
	S2MPS15_REG_ADC_CTRL2	= 0x5C,
	S2MPS15_REG_ADC_DATA	= 0x5D,
};

/* S2MPS15 regulator ids */
enum S2MPS15_regulators {
	S2MPS15_LDO1,
	S2MPS15_LDO2,
	S2MPS15_LDO3,
	S2MPS15_LDO4,
	S2MPS15_LDO5,
	S2MPS15_LDO6,
	S2MPS15_LDO7,
	S2MPS15_LDO8,
	S2MPS15_LDO9,
	S2MPS15_LDO10,
	S2MPS15_LDO11,
	S2MPS15_LDO12,
	S2MPS15_LDO13,
	S2MPS15_LDO14,
	S2MPS15_LDO15,
	S2MPS15_LDO16,
	S2MPS15_LDO17,
	S2MPS15_LDO18,
	S2MPS15_LDO19,
	S2MPS15_LDO20,
	S2MPS15_LDO21,
	S2MPS15_LDO22,
	S2MPS15_LDO23,
	S2MPS15_LDO24,
	S2MPS15_LDO25,
	S2MPS15_LDO26,
	S2MPS15_LDO27,
	S2MPS15_BUCK1,
	S2MPS15_BUCK2,
	S2MPS15_BUCK3,
	S2MPS15_BUCK4,
	S2MPS15_BUCK5,
	S2MPS15_BUCK6,
	S2MPS15_BUCK7,
	S2MPS15_BUCK8,
	S2MPS15_BUCK9,
	S2MPS15_BUCK10,
	S2MPS15_BB1,
	S2MPS15_AP_EN32KHZ,
	S2MPS15_CP_EN32KHZ,
	S2MPS15_BT_EN32KHZ,

	S2MPS15_REG_MAX,
};

#define S2MPS15_BUCK_MIN1	400000
#define S2MPS15_BUCK_MIN1_REV1	300000
#define S2MPS15_BUCK_MIN2	600000
#define S2MPS15_BUCK_MIN3	2600000
#define S2MPS15_LDO_MIN1	400000
#define S2MPS15_LDO_MIN1_REV1	300000
#define S2MPS15_LDO_MIN2	500000
#define S2MPS15_LDO_MIN3	700000
#define S2MPS15_LDO_MIN4	1800000
#define S2MPS15_BUCK_STEP1	6250
#define S2MPS15_BUCK_STEP2	12500
#define S2MPS15_LDO_STEP1	12500
#define S2MPS15_LDO_STEP2	25000
#define S2MPS15_LDO_VSEL_MASK	0x3F
#define S2MPS15_BUCK_VSEL_MASK	0xFF
#define S2MPS15_ENABLE_MASK	(0x03 << S2MPS15_ENABLE_SHIFT)
#define S2MPS15_SW_ENABLE_MASK	0x03
#define S2MPS15_RAMP_DELAY	12000

#define S2MPS15_ENABLE_TIME_LDO		115
#define S2MPS15_ENABLE_TIME_BUCK1	65
#define S2MPS15_ENABLE_TIME_BUCK2	65
#define S2MPS15_ENABLE_TIME_BUCK3	65
#define S2MPS15_ENABLE_TIME_BUCK4	65
#define S2MPS15_ENABLE_TIME_BUCK5	65
#define S2MPS15_ENABLE_TIME_BUCK6	65
#define S2MPS15_ENABLE_TIME_BUCK7	75
#define S2MPS15_ENABLE_TIME_BUCK8	90
#define S2MPS15_ENABLE_TIME_BUCK9	115
#define S2MPS15_ENABLE_TIME_BUCK10	75
#define S2MPS15_ENABLE_TIME_BB		171

#define S2MPS15_ENABLE_TIME_LDO_REV1	128
#define S2MPS15_ENABLE_TIME_BUCK1_REV1	95
#define S2MPS15_ENABLE_TIME_BUCK2_REV1	95
#define S2MPS15_ENABLE_TIME_BUCK3_REV1	95
#define S2MPS15_ENABLE_TIME_BUCK4_REV1	95
#define S2MPS15_ENABLE_TIME_BUCK5_REV1	95
#define S2MPS15_ENABLE_TIME_BUCK6_REV1	128
#define S2MPS15_ENABLE_TIME_BUCK7_REV1	95
#define S2MPS15_ENABLE_TIME_BUCK8_REV1	106
#define S2MPS15_ENABLE_TIME_BUCK9_REV1	150
#define S2MPS15_ENABLE_TIME_BUCK10_REV1	95
#define S2MPS15_ENABLE_TIME_BB_REV1	217

#define S2MPS15_ENABLE_SHIFT	0x06
#define S2MPS15_LDO_N_VOLTAGES	(S2MPS15_LDO_VSEL_MASK + 1)
#define S2MPS15_BUCK_N_VOLTAGES (S2MPS15_BUCK_VSEL_MASK + 1)

#define S2MPS15_PMIC_EN_SHIFT	6
#define S2MPS15_REGULATOR_MAX (S2MPS15_REG_MAX)

#define S2MPS15_MAX_ADC_CHANNEL		4
#define S2MPS15_BUCK_MAX		11
#define S2MPS15_LDO_START		0x21
#define S2MPS15_LDO_END			0x3b
#define S2MPS15_BUCK_START		0x1
#define S2MPS15_BUCK_END		0xb
#define S2MPS15_ADC_SMP_NUM_MAX		0x3
#define S2MPS15_ADC_DIV_RATIO_MAX	0xf
#define S2MPS15_ADCEN_MASK		0x80
#define S2MPS15_SMP_NUM_MASK		0x30
#define S2MPS15_SMP_NUM_SHIFT		4
#define S2MPS15_DIV_RATIO_MASK		0x0F

#endif /*  __LINUX_MFD_S2MPS15_H */