/** * Copyright 2015 Samsung Electronics Co. Ltd. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #ifndef _AUDMIXER_REGISTERS_H #define _AUDMIXER_REGISTERS_H /** * The register offsets in APB-based Audio Mixers are 4 times those in I2C-based * Audio Mixers. To handle this, we have used SoC type based multiplier. * TODO: Need to find a better way to do this. */ #ifdef CONFIG_SOC_EXYNOS7580 #define AUDMIXER_REG_MULT 1 #else #define AUDMIXER_REG_MULT 4 #endif /** * Register addresses */ #define AUDMIXER_REG_00_SOFT_RSTB (0x00 * AUDMIXER_REG_MULT) #define AUDMIXER_REG_01_IN1_CTL1 (0x01 * AUDMIXER_REG_MULT) #define AUDMIXER_REG_02_IN1_CTL2 (0x02 * AUDMIXER_REG_MULT) #define AUDMIXER_REG_03_IN1_CTL3 (0x03 * AUDMIXER_REG_MULT) #define AUDMIXER_REG_04_IN2_CTL1 (0x04 * AUDMIXER_REG_MULT) #define AUDMIXER_REG_05_IN2_CTL2 (0x05 * AUDMIXER_REG_MULT) #define AUDMIXER_REG_06_IN2_CTL3 (0x06 * AUDMIXER_REG_MULT) #define AUDMIXER_REG_07_IN3_CTL1 (0x07 * AUDMIXER_REG_MULT) #define AUDMIXER_REG_08_IN3_CTL2 (0x08 * AUDMIXER_REG_MULT) #define AUDMIXER_REG_09_IN3_CTL3 (0x09 * AUDMIXER_REG_MULT) #define AUDMIXER_REG_0A_HQ_CTL (0x0a * AUDMIXER_REG_MULT) #define AUDMIXER_REG_0B_SLOT_L (0x0b * AUDMIXER_REG_MULT) #define AUDMIXER_REG_0C_SLOT_R (0x0c * AUDMIXER_REG_MULT) #define AUDMIXER_REG_0D_RMIX_CTL (0x0d * AUDMIXER_REG_MULT) #define AUDMIXER_REG_0E_TSLOT (0x0e * AUDMIXER_REG_MULT) #define AUDMIXER_REG_0F_DIG_EN (0x0f * AUDMIXER_REG_MULT) #define AUDMIXER_REG_10_DMIX1 (0x10 * AUDMIXER_REG_MULT) #define AUDMIXER_REG_11_DMIX2 (0x11 * AUDMIXER_REG_MULT) #define AUDMIXER_REG_16_DOUTMX1 (0x16 * AUDMIXER_REG_MULT) #define AUDMIXER_REG_17_DOUTMX2 (0x17 * AUDMIXER_REG_MULT) #define AUDMIXER_REG_18_INAMP_CTL (0x18 * AUDMIXER_REG_MULT) #define AUDMIXER_REG_19_OUTAP1_CTL (0x19 * AUDMIXER_REG_MULT) #define AUDMIXER_REG_1A_OUTCP1_CTL (0x1a * AUDMIXER_REG_MULT) #define AUDMIXER_REG_68_ALC_CTL (0x68 * AUDMIXER_REG_MULT) #define AUDMIXER_REG_69_ALC_GA1 (0x69 * AUDMIXER_REG_MULT) #define AUDMIXER_REG_6A_ALC_GA2 (0x6a * AUDMIXER_REG_MULT) #define AUDMIXER_REG_6B_ALC_LVL (0x6b * AUDMIXER_REG_MULT) #define AUDMIXER_REG_6C_ALC_LVR (0x6c * AUDMIXER_REG_MULT) #define AUDMIXER_REG_6D_ALC_HLD (0x6d * AUDMIXER_REG_MULT) #define AUDMIXER_REG_6E_ALC_ATK (0x6e * AUDMIXER_REG_MULT) #define AUDMIXER_REG_6F_ALC_DCY (0x6f * AUDMIXER_REG_MULT) #define AUDMIXER_REG_70_ALC_NG (0x70 * AUDMIXER_REG_MULT) #define AUDMIXER_REG_71_ALC_SGL (0x71 * AUDMIXER_REG_MULT) #define AUDMIXER_REG_72_ALC_SGR (0x72 * AUDMIXER_REG_MULT) #define AUDMIXER_MAX_REGISTER AUDMIXER_REG_72_ALC_SGR /** * Description of bit-fields of various registers */ /* AUDMIXER_REG_00_SOFT_RSTB */ #define SOFT_RSTB_DATA_RSTB_SHIFT 1 #define SOFT_RSTB_SYS_RSTB_SHIFT 0 /** * AUDMIXER_REG_01_IN1_CTL1 * AUDMIXER_REG_04_IN2_CTL1 * AUDMIXER_REG_07_IN3_CTL1 */ #define INCTL1_MPCM_SRATE_SHIFT 5 #define INCTL1_MPCM_SRATE_MASK 0x3 #define INCTL1_MASTER_SHIFT 4 #define INCTL1_MPCM_SLOT_SHIFT 2 #define INCTL1_MPCM_SLOT_MASK 0x3 #define INCTL1_BCK_POL_SHIFT 1 #define INCTL1_I2S_PCM_SHIFT 0 #define INCTL1_BT_OSYNC_POL_MASK 1 #define INCTL1_BT_OSYNC_POL_SHIFT 2 #define INCTL1_ISYNC_POL_MASK 1 #define INCTL1_ISYNC_POL_SHIFT 1 #define INCTL1_FM_BT_SEL_MASK 1 #define INCTL1_FM_BT_SEL_SHIFT 0 #define MPCM_SRATE_32KHZ 0x3 #define MPCM_SRATE_24KHZ 0x2 #define MPCM_SRATE_16KHZ 0x1 #define MPCM_SRATE_8KHZ 0x0 #define MIXER_MASTER 1 #define MIXER_SLAVE 0 #define MPCM_SLOT_64BCK 3 #define MPCM_SLOT_48BCK 2 #define MPCM_SLOT_32BCK 1 #define MPCM_SLOT_16BCK 0 #define BCK_POL_INVERTED 1 #define BCK_POL_NORMAL 0 #define I2S_PCM_MODE_PCM 1 #define I2S_PCM_MODE_I2S 0 /* AUDMIXER_REG_02_IN1_CTL2 */ /* AUDMIXER_REG_05_IN2_CTL2 */ /* AUDMIXER_REG_08_IN3_CTL2 */ #define INCTL2_I2S_XFS_SHIFT 5 #define INCTL2_I2S_XFS_MASK 0x3 #define INCTL2_LRCK_POL_SHIFT 4 #define INCTL2_I2S_DF_SHIFT 2 #define INCTL2_I2S_DF_MASK 0x3 #define INCTL2_I2S_DL_SHIFT 0 #define INCTL2_I2S_DL_MASK 0x3 #define I2S_XFS_64FS 2 #define I2S_XFS_48FS 1 #define I2S_XFS_32FS 0 #define LRCLK_POL_RIGHT 1 #define LRCLK_POL_LEFT 0 #define I2S_DF_RJ 2 #define I2S_DF_LJ 1 #define I2S_DF_I2S 0 #define I2S_DL_24BIT 3 #define I2S_DL_20BIT 2 #define I2S_DL_18BIT 1 #define I2S_DL_16BIT 0 /* AUDMIXER_REG_03_IN1_CTL3 */ /* AUDMIXER_REG_06_IN2_CTL3 */ /* AUDMIXER_REG_09_IN3_CTL3 */ #define INCTL3_PCM_DAD_SHIFT 5 #define INCTL3_PCM_DAD_MASK 0x3 #define INCTL3_PCM_DF_SHIFT 0 #define INCTL3_PCM_DF_MASK 0xf #define PCM_DAD_4BCK 6 #define PCM_DAD_3BCK 4 #define PCM_DAD_2BCK 2 #define PCM_DAD_0BCK 1 #define PCM_DAD_1BCK 0 #define PCM_DF_SHORT_FRAME 4 #define PCM_DF_LONG_FRAME 0xc /* AUDMIXER_REG_0A_HQ_CTL */ #define HQ_CTL_CH3_SEL_SHIFT 3 #define HQ_CTL_MCKO_EN_SHIFT 2 #define HQ_CTL_BCK4_MODE_SHIFT 1 #define HQ_CTL_HQ_EN_SHIFT 0 #define HQ_CTL_HQ_EN_MASK BIT(HQ_CTL_HQ_EN_SHIFT) /* AUDMIXER_REG_0B_SLOT_L */ #define SLOT_L_SEL_SHIFT 0 #define SLOT_L_SEL_MASK 0xf /* AUDMIXER_REG_0C_SLOT_R */ #define SLOT_R_SEL_SHIFT 0 #define SLOT_R_SEL_MASK 0xf #define SLOT_SEL_1ST_SLOT 1 #define SLOT_SEL_2ND_SLOT 2 #define SLOT_SEL_3RD_SLOT 4 #define SLOT_SEL_4TH_SLOT 8 /* AUDMIXER_REG_0D_RMIX_CTL */ #define RMIX_CTL_RMIX2_EN_SHIFT 7 #define RMIX_CTL_RMIX2_LVL_SHIFT 4 #define RMIX_CTL_RMIX2_LVL_WIDTH 3 #define RMIX_CTL_RMIX2_LVL_MASK 0x7 #define RMIX_CTL_RMIX1_EN_SHIFT 3 #define RMIX_CTL_RMIX1_LVL_SHIFT 0 #define RMIX_CTL_RMIX1_LVL_WIDTH 3 #define RMIX_CTL_RMIX1_LVL_MASK 0x7 /* AUDMIXER_REG_0E_TSLOT */ #define TSLOT_SLOT_SHIFT 0 #define TSLOT_SLOT_MASK 0x3 #define TSLOT_USED_4 3 #define TSLOT_USED_3 2 #define TSLOT_USED_2 1 #define TSLOT_USED_1 0 /* AUDMIXER_REG_0F_DIG_EN */ #define DIG_EN_CP1_EN_SHIFT 5 #define DIG_EN_AP1_EN_SHIFT 4 #define DIG_EN_MIX_EN_SHIFT 3 #define DIG_EN_SRC3_EN_SHIFT 2 #define DIG_EN_SRC2_EN_SHIFT 1 #define DIG_EN_SRC1_EN_SHIFT 0 #define DIG_EN_AP0_EN_SHIFT 0 #define DIG_EN_MASK 1 /* AUDMIXER_REG_10_DMIX1 */ #define DMIX1_MIX_EN2_SHIFT 7 #define DMIX1_MIX_LVL2_SHIFT 4 #define DMIX1_MIX_LVL2_WIDTH 3 #define DMIX1_MIX_LVL2_MASK 0x7 #define DMIX1_MIX_EN1_SHIFT 3 #define DMIX1_MIX_LVL1_SHIFT 0 #define DMIX1_MIX_LVL1_WIDTH 3 #define DMIX1_MIX_LVL1_MASK 0x7 /* AUDMIXER_REG_11_DMIX2 */ #define DMIX2_MIX_EN4_SHIFT 7 #define DMIX2_MIX_LVL4_SHIFT 4 #define DMIX2_MIX_LVL4_WIDTH 3 #define DMIX2_MIX_LVL4_MASK 0x7 #define DMIX2_MIX_EN3_SHIFT 3 #define DMIX2_MIX_LVL3_SHIFT 0 #define DMIX2_MIX_LVL3_WIDTH 3 #define DMIX2_MIX_LVL3_MASK 0x7 #define DMIX_EN_MASK 0x1 /* AUDMIXER_REG_16_DOUTMX1 */ #define DOUTMX1_DOUT_SEL2_SHIFT 3 #define DOUTMX1_DOUT_SEL2_MASK 0x7 #define DOUTMX1_DOUT_SEL1_SHIFT 0 #define DOUTMX1_DOUT_SEL1_MASK 0x7 #define DOUT_SEL2_BT_DATA 2 #define DOUT_SEL2_ADC_DATA 1 #define DOUT_SEL2_MIX_DATA 0 #define DOUT_SEL1_ADC_CP_DATA 2 #define DOUT_SEL1_ADC_DATA 1 #define DOUT_SEL1_MIX_DATA 0 /* AUDMIXER_REG_17_DOUTMX2 */ #define DOUTMX2_DOUT_SEL3_SHIFT 0 #define DOUTMX2_DOUT_SEL3_MASK 0x7 #define DOUT_SEL3_CP_DATA 2 #define DOUT_SEL3_ADC_DATA 1 #define DOUT_SEL3_MIX_DATA 0 /* AUDMIXER_REG_18_INAMP_CTL */ #define INAMP_CTL_BCK_POL_SHIFT 7 #define INAMP_CTL_BCK_POL_MASK 1 #define INAMP_CTL_LRCLK_POL_SHIFT 6 #define INAMP_CTL_LRCLK_POL_MASK 1 #define INAMP_CTL_I2S_XFS_SHIFT 2 #define INAMP_CTL_I2S_XFS_MASK 0x3 #define INAMP_CTL_I2S_DL_SHIFT 0 #define INAMP_CTL_I2S_DL_MASK 0x3 /* AUDMIXER_REG_19_OUTAP1_CTL */ /* AUDMIXER_REG_1A_OUTCP1_CTL */ #define OUTAMP_CTL_LRCLK_POL_SHIFT 7 #define OUTAMP_CTL_LRCLK_POL_MASK 1 #define OUTAMP_CTL_BCK_POL_SHIFT 6 #define OUTAMP_CTL_BCK_POL_MASK 1 #define OUTAMP_CTL_I2S_DL_SHIFT 4 #define OUTAMP_CTL_I2S_DL_MASK 0x3 #define OUTAMP_CTL_I2S_XFS_SHIFT 0 #define OUTAMP_CTL_I2S_XFS_MASK 0x3 #define AMP_I2S_DL_24BIT 2 #define AMP_I2S_DL_20BIT 1 #define AMP_I2S_DL_16BIT 0 /* AUDMIXER_REG_68_ALC_CTL */ #define ALC_CTL_ALC_NG_HYS_SHIFT 6 #define ALC_CTL_ALC_NG_HYS_WIDTH 2 #define ALC_CTL_ALC_NG_HYS_MASK 0x3 #define ALC_CTL_WINSEL_SHIFT 4 #define ALC_CTL_WINSEL_MASK 0x3 #define ALC_CTL_ALC_EN_SHIFT 3 #define ALC_CTL_ALC_LIM_SHIFT 2 #define ALC_CTL_ALC_MODE_SHIFT 0 #define ALC_CTL_ALC_MODE_MASK 0x3 #define WINSEL_300FS 3 #define WINSEL_2400FS 2 #define WINSEL_1200FS 1 #define WINSEL_600FS 0 #define ALC_MODE_RIGHT_LEFT_IND 3 #define ALC_MODE_LEFT_CHAN 2 #define ALC_MODE_RIGHT_CHAN 1 #define ALC_MODE_STEREO 0 /* AUDMIXER_REG_69_ALC_GA1 */ #define ALC_GA1_ALC_MAX_GAIN_SHIFT 0 #define ALC_GA1_ALC_MAX_GAIN_MASK 0xff #define ALC_GA1_ALC_MAX_GAIN_MAXVAL 0x9c #define ALC_GA1_ALC_MAX_GAIN_MINVAL 0x6c /* AUDMIXER_REG_6A_ALC_GA2 */ #define ALC_GA2_ALC_MIN_GAIN_SHIFT 0 #define ALC_GA2_ALC_MIN_GAIN_MASK 0xff #define ALC_GA2_ALC_MIN_GAIN_MAXVAL 0x6c #define ALC_GA2_ALC_MIN_GAIN_MINVAL 0x0 /* AUDMIXER_REG_6B_ALC_LVL */ #define ALC_LVL_LVL_SHIFT 0 #define ALC_LVL_LVL_WIDTH 5 #define ALC_LVL_LVL_MASK 0x1f /* AUDMIXER_REG_6C_ALC_LVR */ #define ALC_LVR_LVL_SHIFT 0 #define ALC_LVR_LVL_WIDTH 5 #define ALC_LVR_LVL_MASK 0x1f /* AUDMIXER_REG_6D_ALC_HLD */ #define ALC_HLD_ALC_PATH_SEL_SHIFT 7 #define ALC_HLD_ST_GAIN_EN_SHIFT 6 #define ALC_HLD_HOLD_SHIFT 0 #define ALC_HLD_HOLD_MASK 0x1f /* AUDMIXER_REG_6E_ALC_ATK */ #define ALC_ATK_ATTACK_SHIFT 0 #define ALC_ATK_ATTACK_MASK 0x1f /* AUDMIXER_REG_6F_ALC_DCY */ #define ALC_DCY_DECAY_SHIFT 0 #define ALC_DCY_DECAY_MASK 0x1f /* AUDMIXER_REG_70_ALC_NG */ #define ALC_NG_NGAT_SHIFT 7 #define ALC_NG_ALCNGTH_SHIFT 0 #define ALC_NG_ALCNGTH_WIDTH 5 #define ALC_NG_ALCNGTH_MASK 0x1f /* AUDMIXER_REG_71_ALC_SGL */ #define ALC_SGL_START_GAIN_L_SHIFT 0 #define ALC_SGL_START_GAIN_L_MASK 0xff #define ALC_SGL_START_GAIN_L_MAXVAL 0x9c #define ALC_SGL_START_GAIN_L_MINVAL 0x6c /* AUDMIXER_REG_72_ALC_SGR */ #define ALC_SGR_START_GAIN_R_SHIFT 0 #define ALC_SGR_START_GAIN_R_MASK 0xff #define ALC_SGR_START_GAIN_R_MAXVAL 0x9c #define ALC_SGR_START_GAIN_R_MINVAL 0x6c #endif