mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
1497 lines
37 KiB
Text
1497 lines
37 KiB
Text
/*
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* SAMSUNG EXYNOS7570 SoC device tree source
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*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* SAMSUNG EXYNOS7570 SoC device nodes are listed in this file.
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* EXYNOS7570 based board files can include this file and provide
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* values for board specfic bindings.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/memreserve/ 0x7E300000 0x100000;
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#include <dt-bindings/clock/exynos7570.h>
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#include <dt-bindings/sysmmu/sysmmu.h>
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#include <dt-bindings/thermal/thermal.h>
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#include "exynos7570-pinctrl.dtsi"
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#include "exynos7570-itm.dtsi"
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#include "exynos7570-pm-domains.dtsi"
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/ {
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compatible = "samsung,armv8", "samsung,exynos7570";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <1>;
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aliases {
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pinctrl0 = &pinctrl_0;
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pinctrl1 = &pinctrl_1;
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pinctrl2 = &pinctrl_2;
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pinctrl3 = &pinctrl_3;
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pinctrl4 = &pinctrl_4;
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pinctrl5 = &pinctrl_5;
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pinctrl6 = &pinctrl_6;
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pinctrl7 = &pinctrl_7;
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uart1 = &serial_1;
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uart2 = &serial_2;
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uart3 = &serial_3;
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uart4 = &serial_4;
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hsi2c0 = &hsi2c_0;
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hsi2c1 = &hsi2c_1;
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hsi2c2 = &hsi2c_2;
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hsi2c3 = &hsi2c_3;
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hsi2c4 = &hsi2c_4;
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hsi2c5 = &hsi2c_5;
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hsi2c6 = &hsi2c_6;
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hsi2c7 = &hsi2c_7;
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hsi2c8 = &hsi2c_8;
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spi0 = &spi_0;
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spi1 = &spi_1;
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spi2 = &spi_2;
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spi3 = &spi_3;
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mshc0 = &dwmmc_0;
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mshc2 = &dwmmc_2;
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decon0 = &decon_0;
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dsim0 = &dsim_0;
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tmuctrl0 = &tmuctrl_0;
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tmuctrl1 = &tmuctrl_1;
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scaler0 = &scaler_0;
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mfc0 = &mfc_0;
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};
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chipid@10100000 {
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compatible = "samsung,exynos4210-chipid";
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reg = <0x0 0x10100000 0x100>;
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};
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reboot {
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compatible = "exynos,reboot";
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pmu_base = <0x11C80000>;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x1>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x2>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x3>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP>;
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};
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idle-states {
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entry-method = "arm,psci";
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CPU_SLEEP: cpu-sleep {
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desc = "cpu sleep";
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compatible = "exynos,idle-state";
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arm,psci-suspend-param = <0x0010000>;
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entry-latency-us = <35>;
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exit-latency-us = <90>;
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min-residency-us = <750>;
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status = "okay";
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};
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};
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};
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psci {
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compatible = "arm,psci";
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method = "smc";
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cpu_suspend = <0xC4000001>;
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cpu_off = <0x84000002>;
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cpu_on = <0xC4000003>;
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};
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cpufreq {
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compatible = "samsung,exynos-sc-cpufreq";
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cl0_idx_num = <17>;
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cl0_max_support_idx = <5>;
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cl0_min_support_idx = <14>;
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cl0_boot_max_qos = <1378000>;
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cl0_boot_min_qos = <1378000>;
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cl0_boot_lock_time = <40000000>;
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cl0_en_ema = <0>;
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cl0_regulator = "BUCK1";
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cl0_dvfs_domain_name = "dvfs_cpucl0";
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};
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gic:interrupt-controller@104E1000 {
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compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0x104E1000 0x1000>,
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<0x0 0x104E2000 0x1000>,
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<0x0 0x104E4000 0x2000>,
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<0x0 0x104E6000 0x2000>;
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interrupts = <1 9 0xf04>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0xff01>,
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<1 14 0xff01>,
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<1 11 0xff01>,
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<1 10 0xff01>;
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clock-frequency = <26000000>;
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use-clocksource-only;
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};
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clock: clock-controller@0x10460000 {
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compatible = "samsung,exynos7570-clock";
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reg = <0x0 0x10460000 0x1000>;
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#clock-cells = <1>;
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};
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pmu_system_controller: system-controller@11C80000 {
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compatible = "samsung,exynos7570-pmu", "syscon";
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reg = <0x0 0x11C80000 0x10000>;
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};
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exynos-pmu {
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compatible = "samsung,exynos-pmu";
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samsung,syscon-phandle = <&pmu_system_controller>;
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};
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mct@101B0000 {
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compatible = "samsung,exynos4210-mct";
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reg = <0x0 0x101B0000 0x800>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&mct_map>;
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interrupts = <0>, <1>, <2>, <3>,
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<4>, <5>, <6>, <7>,
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<8>, <9>, <10>, <11>;
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clocks = <&clock OSCCLK>, <&clock CLK_MCT>;
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clock-names = "fin_pll", "mct";
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use-clockevent-only;
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mct_map: mct-map {
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = <0 &gic 0 102 0>,
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<1 &gic 0 103 0>,
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<2 &gic 0 104 0>,
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<3 &gic 0 105 0>,
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<4 &gic 0 106 0>,
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<5 &gic 0 107 0>,
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<6 &gic 0 108 0>,
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<7 &gic 0 109 0>,
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<8 &gic 0 110 0>,
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<9 &gic 0 111 0>,
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<10 &gic 0 112 0>,
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<11 &gic 0 113 0>;
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};
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};
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devfreq_0: devfreq_mif@17000010 {
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compatible = "samsung,exynos-devfreq";
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reg = <0x0 0x17000010 0x0>;
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clocks = <&clock CLK_DVFS_MIF>, <&clock CLK_DVFS_MIF_SW>;
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clock-names = "dvfs_mif", "dvfs_mif_sw";
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devfreq_type = "mif";
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devfreq_domain_name = "dvfs_mif";
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/* Delay time */
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use_delay_time = "true";
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delay_time_list = "20";
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/* initial_freq, default_qos, suspend_freq, min_freq, max_freq, reboot_freq */
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freq_info = <666000 415000 415000 415000 666000 415000>;
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/* PM QoS */
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boot_qos_timeout = <40>;
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use_get_dev = "false";
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polling_ms = <0>;
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/* governor data */
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gov_name = "interactive";
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/* regulator */
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use_reg = "true";
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use_pd_off = "false";
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reg_name = "BUCK1";
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/* cold, cold_limit, min_cold, max_uV */
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volt_info = <25000 1250000 0 1300000>;
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use_tmu = "true";
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use_cl_dvfs = "false";
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use_sw_clk = "true";
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};
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devfreq_1: devfreq_int@17000020 {
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compatible = "samsung,exynos-devfreq";
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reg = <0x0 0x17000020 0x0>;
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clocks = <&clock CLK_DVFS_INT>;
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clock-names = "dvfs_int";
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devfreq_type = "int";
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devfreq_domain_name = "dvfs_int";
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/* Delay time */
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use_delay_time = "false";
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/* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
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freq_info = <467000 415000 467000 415000 467000 415000>;
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/* PM QoS */
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boot_qos_timeout = <40>;
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/* default_dev_profile */
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use_get_dev = "false";
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polling_ms = <0>;
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/* governor data */
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gov_name = "interactive";
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/* regulator */
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use_reg = "true";
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use_pd_off = "false";
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reg_name = "BUCK1";
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/* <cold, cold_limit, min_cold, max_uV> */
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volt_info = <25000 1250000 0 1300000>;
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use_tmu = "true";
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use_cl_dvfs = "false";
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use_sw_clk = "false";
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};
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devfreq_2: devfreq_disp@17000030 {
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compatible = "samsung,exynos-devfreq";
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reg = <0x0 0x17000030 0x0>;
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clocks = <&clock CLK_DVFS_DISP>;
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clock-names = "dvfs_disp";
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devfreq_type = "disp";
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devfreq_domain_name = "dvfs_disp";
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/* Delay time */
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use_delay_time = "false";
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/* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
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freq_info = <208000 208000 208000 208000 208000 208000>;
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/* PM QoS */
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boot_qos_timeout = <40>;
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/* default dev profile */
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use_get_dev = "false";
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polling_ms = <0>;
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/* governor data */
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gov_name = "interactive";
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/* regulator */
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use_reg = "true";
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use_pd_off = "false";
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reg_name = "BUCK1";
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/* cold, cold_limit, min_cold, max_uV */
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volt_info = <25000 1250000 0 1300000>;
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use_tmu = "true";
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use_cl_dvfs = "false";
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use_sw_clk = "false";
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};
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devfreq_3: devfreq_cam@17000040 {
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compatible = "samsung,exynos-devfreq";
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reg = <0x0 0x17000040 0x0>;
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clocks = <&clock CLK_DVFS_CAM>;
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clock-names = "dvfs_cam";
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devfreq_type = "cam";
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devfreq_domain_name = "dvfs_cam";
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/* Delay time */
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use_delay_time = "false";
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/* <initial, default_qos, suspend_freq, min, max, reboot_freq> */
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freq_info = <444000 444000 444000 444000 554000 444000>;
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/* PM QoS */
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boot_qos_timeout = <0>;
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/* default dev profile */
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use_get_dev = "false";
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polling_ms = <0>;
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/* governor data */
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gov_name = "interactive";
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/* regulator */
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use_reg = "true";
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use_pd_off = "true";
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reg_name = "BUCK1";
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/* cold, cold_limit, min_cold, max_uV */
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volt_info = <25000 1250000 0 1300000>;
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use_tmu = "true";
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use_cl_dvfs = "false";
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use_sw_clk = "false";
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};
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ect {
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parameter_address = <0x7E0FA000>;
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parameter_size = <0x6000>;
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};
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pinctrl_0: pinctrl@139F0000 {
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compatible = "samsung,exynos7570-pinctrl";
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reg = <0x0 0x139F0000 0x1000>;
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interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
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<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
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<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
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<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
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wakeup-interrupt-controller {
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compatible = "samsung,exynos4210-wakeup-eint";
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interrupt-parent = <&gic>;
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interrupts = <0 16 0>;
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samsung,eint-flt-conf;
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};
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};
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/* DISPAUD */
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pinctrl_1: pinctrl@148C0000 {
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compatible = "samsung,exynos7570-pinctrl";
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reg = <0x0 0x148C0000 0x1000>;
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interrupts = <0 68 0>;
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};
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/* ESE */
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pinctrl_2: pinctrl@139E0000 {
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compatible = "samsung,exynos7570-pinctrl";
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reg = <0x0 0x139E0000 0x1000>;
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interrupts = <0 441 0>;
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};
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/* FSYS0 */
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pinctrl_3: pinctrl@13750000 {
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compatible = "samsung,exynos7570-pinctrl";
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reg = <0x0 0x13750000 0x1000>;
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interrupts = <0 250 0>;
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};
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/* MIF */
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pinctrl_4: pinctrl@10530000 {
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compatible = "samsung,exynos7570-pinctrl";
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reg = <0x0 0x10530000 0x1000>;
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interrupts = <0 392 0>;
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};
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/* NFC */
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pinctrl_5: pinctrl@139C0000 {
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compatible = "samsung,exynos7570-pinctrl";
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reg = <0x0 0x139C0000 0x1000>;
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interrupts = <0 439 0>;
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};
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/* TOP */
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pinctrl_6: pinctrl@139B0000 {
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compatible = "samsung,exynos7570-pinctrl";
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reg = <0x0 0x139B0000 0x1000>;
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interrupts = <0 438 0>;
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};
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/* TOUCH */
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pinctrl_7: pinctrl@139D0000 {
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compatible = "samsung,exynos7570-pinctrl";
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reg = <0x0 0x139D0000 0x1000>;
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interrupts = <0 440 0>;
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};
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/* USI_0 */
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usi_0: usi@101D2000 {
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compatible = "samsung,exynos-usi";
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reg = <0x0 0x101D2000 0x100>;
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/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
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or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
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status = "disabled";
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};
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/* USI_1 */
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usi_1: usi@101D3000 {
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compatible = "samsung,exynos-usi";
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reg = <0x0 0x101D3000 0x100>;
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/* usi_mode = "hsi2c0" or "hsi2c1" or "spi" or "uart"
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or "hsi2c0_hsi2c1" or "uart_hsi2c1" */
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status = "disabled";
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};
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/* UART_SENSOR */
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serial_1: uart@13800000 {
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compatible = "samsung,exynos-uart";
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samsung,separate-uart-clk;
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reg = <0x0 0x13800000 0x100>;
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samsung,fifo-size = <16>;
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interrupts = <0 421 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_bus>;
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clocks = <&clock 361>, <&clock 21>, <&clock 21>;
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clock-names = "gate_pclk1", "gate_uart1", "sclk_uart1";
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status = "disabled";
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};
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/* UART_DEBUG */
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serial_2: uart@13820000 {
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compatible = "samsung,exynos-uart";
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samsung,separate-uart-clk;
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samsung,alive-io;
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reg = <0x0 0x13820000 0x100>;
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samsung,fifo-size = <256>;
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interrupts = <0 423 0>;
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pinctrl-names = "default", "uart_sleep";
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pinctrl-0 = <&uart2_bus>;
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pinctrl-1 = <&uart2_sleep>;
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clocks = <&clock 360>, <&clock 20>, <&clock 20>;
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clock-names = "gate_pclk2", "gate_uart2", "sclk_uart2";
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status = "disabled";
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};
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/* UART SWITCH FOR CP */
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uart_sel {
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compatible = "samsung,exynos-uart-sel";
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int_ap2cp_uart_noti = <15>;
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mbx_ap2cp_united_status = <2>;
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sbi_uart_noti_mask = <0x1>;
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sbi_uart_noti_pos = <16>;
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};
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/* UART_USI_0 */
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serial_3: uart@13910000 {
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compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x0 0x13910000 0x100>;
|
|
/* samsung,fifo-size = <32> or <16>; single mode vs. dual mode*/
|
|
samsung,fifo-size = <32>;
|
|
interrupts = <0 461 0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart3_bus_single>;
|
|
clocks = <&clock 351>, <&clock 40>, <&clock 40>;
|
|
clock-names = "gate_pclk3", "gate_uart3", "sclk_uart3";
|
|
status = "disabled";
|
|
};
|
|
|
|
/* UART_USI_1 */
|
|
serial_4: uart@13930000 {
|
|
compatible = "samsung,exynos-uart";
|
|
samsung,separate-uart-clk;
|
|
reg = <0x0 0x13930000 0x100>;
|
|
/* samsung,fifo-size = <32> or <16>; single mode vs. dual mode*/
|
|
samsung,fifo-size = <32>;
|
|
interrupts = <0 465 0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart4_bus_single>;
|
|
clocks = <&clock 352>, <&clock 41>, <&clock 41>;
|
|
clock-names = "gate_pclk4", "gate_uart4", "sclk_uart4";
|
|
status = "disabled";
|
|
};
|
|
|
|
/* I2C_MUIC */
|
|
i2c_1: i2c@13880000 {
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x0 0x13880000 0x100>;
|
|
interrupts = <0 429 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_bus>;
|
|
clocks = <&clock 312>, <&clock 312>;
|
|
clock-names = "rate_i2c", "gate_i2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
/* I2C_NFC */
|
|
i2c_2: i2c@13890000 {
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x0 0x13890000 0x100>;
|
|
interrupts = <0 430 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_bus>;
|
|
clocks = <&clock 311>, <&clock 311>;
|
|
clock-names = "rate_i2c", "gate_i2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
/* I2C_TSP */
|
|
i2c_3: i2c@13840000 {
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x0 0x13840000 0x100>;
|
|
interrupts = <0 425 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c3_bus>;
|
|
clocks = <&clock 302>, <&clock 302>;
|
|
clock-names = "rate_i2c", "gate_i2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
/* I2C_FUELGAUGE */
|
|
i2c_4: i2c@13830000 {
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x0 0x13830000 0x100>;
|
|
interrupts = <0 424 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c4_bus>;
|
|
clocks = <&clock 310>, <&clock 310>;
|
|
clock-names = "rate_i2c", "gate_i2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
/* I2C_SENSOR1 */
|
|
i2c_5: i2c@138D0000 {
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x0 0x138D0000 0x100>;
|
|
interrupts = <0 453 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c5_bus>;
|
|
clocks = <&clock 300>, <&clock 300>;
|
|
clock-names = "rate_i2c", "gate_i2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
/* I2C_SENSOR2 */
|
|
i2c_6: i2c@138E0000 {
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x0 0x138E0000 0x100>;
|
|
interrupts = <0 454 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c6_bus>;
|
|
clocks = <&clock 301>, <&clock 301>;
|
|
clock-names = "rate_i2c", "gate_i2c";
|
|
status = "disabled";
|
|
};
|
|
|
|
/* HSI2C_MAINCAM */
|
|
hsi2c_0: hsi2c@13950000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
reg = <0x0 0x13950000 0x1000>;
|
|
interrupts = <0 457 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hs_i2c0_bus>;
|
|
clocks = <&clock 332>, <&clock 332>;
|
|
clock-names = "rate_hsi2c", "gate_hsi2c";
|
|
samsung,scl-clk-stretching;
|
|
gpio_sda= <&gpf3 1 0x1>;
|
|
gpio_scl= <&gpf3 0 0x1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* HSI2C_FRONTCAM */
|
|
hsi2c_1: hsi2c@13960000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
reg = <0x0 0x13960000 0x1000>;
|
|
interrupts = <0 458 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hs_i2c1_bus>;
|
|
clocks = <&clock 333>, <&clock 333>;
|
|
clock-names = "rate_hsi2c", "gate_hsi2c";
|
|
samsung,scl-clk-stretching;
|
|
gpio_sda= <&gpf3 3 0x1>;
|
|
gpio_scl= <&gpf3 2 0x1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* HSI2C_REARSENSOR */
|
|
hsi2c_2: hsi2c@138A0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
reg = <0x0 0x138A0000 0x1000>;
|
|
interrupts = <0 449 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hs_i2c2_bus>;
|
|
clocks = <&clock 321>, <&clock 321>;
|
|
clock-names = "rate_hsi2c", "gate_hsi2c";
|
|
samsung,scl-clk-stretching;
|
|
gpio_sda= <&gpf0 0 0x1>;
|
|
gpio_scl= <&gpf0 1 0x1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* HSI2C_FRONTSENSOR */
|
|
hsi2c_3: hsi2c@138C0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
reg = <0x0 0x138C0000 0x1000>;
|
|
interrupts = <0 451 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hs_i2c3_bus>;
|
|
clocks = <&clock 320>, <&clock 320>;
|
|
clock-names = "rate_hsi2c", "gate_hsi2c";
|
|
samsung,scl-clk-stretching;
|
|
gpio_sda= <&gpf0 2 0x1>;
|
|
gpio_scl= <&gpf0 3 0x1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* HSI2C_REARAF */
|
|
hsi2c_4: hsi2c@138B0000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
reg = <0x0 0x138B0000 0x1000>;
|
|
interrupts = <0 450 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hs_i2c4_bus>;
|
|
clocks = <&clock 322>, <&clock 322>;
|
|
clock-names = "rate_hsi2c", "gate_hsi2c";
|
|
samsung,scl-clk-stretching;
|
|
gpio_sda= <&gpf1 0 0x1>;
|
|
gpio_scl= <&gpf1 1 0x1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lpass: lpass@148F0000 {
|
|
compatible = "samsung,exynos7570-lpass";
|
|
reg = <0x0 0x148F0000 0x1040>;
|
|
clocks = <&clock 740>, /* aud_pll */
|
|
<&clock 711>, /* dispaud_mi2s_aud */
|
|
<&clock 703>; /* dispaud_decon */
|
|
|
|
clock-names = "fout_aud_pll", "dout_sclk_mi2s",
|
|
"dispaud_decon";
|
|
|
|
samsung,syscon-phandle = <&pmu_system_controller>;
|
|
samsung,power-domain = <&spd_aud>;
|
|
status = "okay";
|
|
};
|
|
|
|
eax: eax {
|
|
compatible = "samsung,exynos-amixer";
|
|
status = "ok";
|
|
};
|
|
|
|
s1403x: s1403x@14880000 {
|
|
compatible = "samsung,s1403x";
|
|
reg = <0x0 0x14880000 0x200>;
|
|
clocks = <&clock 742>, /* d1_mixer */
|
|
<&clock 710>; /* dispaud_mi2s_aud */
|
|
|
|
clock-names = "audmixer_dout", "audmixer_aclk";
|
|
|
|
samsung,lpass-subip;
|
|
status = "okay";
|
|
};
|
|
|
|
i2s0: i2s@148A0000 {
|
|
compatible = "samsung,i2s-v5";
|
|
reg = <0x0 0x148A0000 0x100>;
|
|
dmas = <&pdma0 29
|
|
&pdma0 30>;
|
|
dma-names = "tx", "rx";
|
|
interrupts = <0 69 0>;
|
|
clocks = <&clock 711>, /* dispaud_mi2s_aud */
|
|
<&clock 741>, /* d1_i2s */
|
|
<&clock 741>; /* d1_i2s */
|
|
clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
|
|
samsung,amixer = <4>;
|
|
samsung,supports-rstclr;
|
|
samsung,supports-secdai;
|
|
samsung,supports-esa-dma;
|
|
samsung,i2s-str;
|
|
samsung,lpass-subip;
|
|
status = "disabled";
|
|
i2s-sec {
|
|
dmas = <&pdma0 28>;
|
|
dma-names = "tx-sec";
|
|
clocks = <&clock 711>, /* dispaud_mi2s_aud */
|
|
<&clock 741>, /* d1_i2s */
|
|
<&clock 741>; /* d1_i2s */
|
|
clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
|
|
};
|
|
};
|
|
|
|
i2s1: i2s@148B0000 {
|
|
compatible = "samsung,i2s-v5";
|
|
reg = <0x0 0x148B0000 0x100>;
|
|
dmas = <&pdma0 31>;
|
|
dma-names = "rx";
|
|
interrupts = <0 71 0>;
|
|
clocks = <&clock 712>, /* dispaud_mi2s_amp */
|
|
<&clock 741>, /* d1_i2s */
|
|
<&clock 741>; /* d1_i2s */
|
|
clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
|
|
samsung,supports-rstclr;
|
|
samsung,i2s-str;
|
|
samsung,supports-i2s-amp;
|
|
samsung,lpass-subip;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* USI_0_CH0_HSI2C */
|
|
hsi2c_5: hsi2c@13910000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
reg = <0x0 0x13910000 0x1000>;
|
|
interrupts = <0 459 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hs_i2c5_bus>;
|
|
clocks = <&clock 351>, <&clock 351>;
|
|
clock-names = "rate_hsi2c", "gate_hsi2c";
|
|
samsung,scl-clk-stretching;
|
|
gpio_sda= <&gpa1 7 0x1>;
|
|
gpio_scl= <&gpa2 0 0x1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* USI_0_CH1_HSI2C */
|
|
hsi2c_6: hsi2c@13920000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
reg = <0x0 0x13920000 0x1000>;
|
|
interrupts = <0 460 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hs_i2c6_bus>;
|
|
clocks = <&clock 351>, <&clock 351>;
|
|
clock-names = "rate_hsi2c", "gate_hsi2c";
|
|
samsung,scl-clk-stretching;
|
|
gpio_sda= <&gpa2 1 0x1>;
|
|
gpio_scl= <&gpa2 2 0x1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* USI_1_CH0_HSI2C */
|
|
hsi2c_7: hsi2c@13930000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
reg = <0x0 0x13930000 0x1000>;
|
|
interrupts = <0 463 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hs_i2c7_bus>;
|
|
clocks = <&clock 352>, <&clock 352>;
|
|
clock-names = "rate_hsi2c", "gate_hsi2c";
|
|
samsung,scl-clk-stretching;
|
|
gpio_sda= <&gpa2 4 0x1>;
|
|
gpio_scl= <&gpa2 5 0x1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* USI_1_CH1_HSI2C */
|
|
hsi2c_8: hsi2c@13940000 {
|
|
compatible = "samsung,exynos5-hsi2c";
|
|
samsung,check-transdone-int;
|
|
reg = <0x0 0x13940000 0x1000>;
|
|
interrupts = <0 464 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hs_i2c8_bus>;
|
|
clocks = <&clock 352>, <&clock 352>;
|
|
clock-names = "rate_hsi2c", "gate_hsi2c";
|
|
samsung,scl-clk-stretching;
|
|
gpio_sda= <&gpa2 6 0x1>;
|
|
gpio_scl= <&gpa2 7 0x1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* DMA */
|
|
amba {
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
compatible = "arm,amba-bus";
|
|
interrupt-parent = <&gic>;
|
|
ranges;
|
|
|
|
pdma0: pdma0@10490000 {
|
|
compatible = "arm,pl330", "arm,primecell";
|
|
reg = <0x0 0x10490000 0x1000>;
|
|
interrupts = <0 383 0>;
|
|
clocks = <&clock 50>;
|
|
clock-names = "apb_pclk";
|
|
#dma-cells = <1>;
|
|
#dma-channels = <8>;
|
|
#dma-requests = <32>;
|
|
};
|
|
};
|
|
|
|
speedy@10510000 {
|
|
compatible = "samsung,exynos-speedy";
|
|
reg = <0x0 0x10510000 0x2000>;
|
|
interrupts = <0 372 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&speedy_bus>;
|
|
clocks = <&clock 11>;
|
|
clock-names = "gate_speedy";
|
|
status = "okay";
|
|
samsung,always-interrupt-high;
|
|
};
|
|
|
|
/* SPI_ESE */
|
|
spi_0: spi@100C0000 {
|
|
compatible = "samsung,exynos-spi";
|
|
reg = <0x0 0x100C0000 0x100>;
|
|
samsung,spi-fifosize = <256>;
|
|
interrupts = <0 434 0>;
|
|
/*
|
|
dma-mode;
|
|
dmas = <&pdma0 19
|
|
&pdma0 18>;
|
|
*/
|
|
dma-names = "tx", "rx";
|
|
swap-mode;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock 362>, <&clock 23>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi0_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* SPI_REARFROM */
|
|
spi_1: spi@13900000 {
|
|
compatible = "samsung,exynos-spi";
|
|
reg = <0x0 0x13900000 0x100>;
|
|
samsung,spi-fifosize = <64>;
|
|
interrupts = <0 433 0>;
|
|
/*
|
|
dma-mode;
|
|
dmas = <&pdma0 17
|
|
&pdma0 16>;
|
|
*/
|
|
dma-names = "tx", "rx";
|
|
swap-mode;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock 363>, <&clock 22>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi1_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* SPI USI0 */
|
|
spi_2: spi@13910000 {
|
|
compatible = "samsung,exynos-spi";
|
|
reg = <0x0 0x13910000 0x100>;
|
|
samsung,spi-fifosize = <32>;
|
|
interrupts = <0 462 0>;
|
|
/*
|
|
dma-mode;
|
|
dmas = <&pdma0 21
|
|
&pdma0 20>;
|
|
*/
|
|
dma-names = "tx", "rx";
|
|
swap-mode;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock 351>, <&clock 40>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi2_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* SPI USI1 */
|
|
spi_3: spi@13930000 {
|
|
compatible = "samsung,exynos-spi";
|
|
reg = <0x0 0x13930000 0x100>;
|
|
samsung,spi-fifosize = <32>;
|
|
interrupts = <0 466 0>;
|
|
/*
|
|
dma-mode;
|
|
dmas = <&pdma0 25
|
|
&pdma0 24>;
|
|
*/
|
|
dma-names = "tx", "rx";
|
|
swap-mode;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock 352>, <&clock 41>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi3_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
secgpio_dvs {
|
|
compatible = "samsung,exynos7570-secgpio-dvs";
|
|
status = "okay";
|
|
};
|
|
|
|
dwmmc_0: dwmmc0@13540000 {
|
|
compatible = "samsung,exynos-dw-mshc";
|
|
reg = <0x0 0x13540000 0x2000>;
|
|
interrupts = <0 245 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock 513>, <&clock 515>, <&clock 30>;
|
|
clock-names = "biu", "ciu", "ciu_gate";
|
|
status = "disabled";
|
|
};
|
|
|
|
dwmmc_2: dwmmc2@13560000 {
|
|
compatible = "samsung,exynos-dw-mshc";
|
|
reg = <0x0 0x13560000 0x2000>;
|
|
interrupts = <0 247 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&clock 514>, <&clock 516>, <&clock 31>;
|
|
clock-names = "biu", "ciu", "ciu_gate";
|
|
status = "disabled";
|
|
};
|
|
|
|
mali: mali@11400000 {
|
|
compatible = "arm,mali";
|
|
reg = <0x0 0x11400000 0x5000>;
|
|
interrupts = <0 282 0>, <0 283 0>, <0 281 0>;
|
|
interrupt-names = "JOB", "MMU", "GPU";
|
|
clocks = <&clock 203>;
|
|
clock-names = "vclk_g3d";
|
|
samsung,power-domain = <&pd_g3d>;
|
|
};
|
|
|
|
mfc_0: mfc0@12C30000 {
|
|
compatible = "samsung,mfc-v6";
|
|
#pb-id-cells = <0>;
|
|
reg = <0x0 0x12C30000 0x10000>;
|
|
interrupts = <0 354 0>;
|
|
clock-names = "aclk_mfc";
|
|
clocks = <&clock 612>;
|
|
samsung,power-domain = <&pd_mfcmscl>;
|
|
status = "ok";
|
|
ip_ver = <17>;
|
|
clock_rate = <415000000>;
|
|
min_rate = <100000>;
|
|
num_qos_steps = <1>;
|
|
mfc_qos_table {
|
|
mfc_qos_variant_0 {
|
|
thrd_mb = <0>;
|
|
freq_mfc = <0>;
|
|
freq_int = <415000>;
|
|
freq_mif = <415000>;
|
|
freq_cpu = <0>;
|
|
freq_kfc = <0>;
|
|
has_enc_table = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mipi_phy_dsim: phy_m4s4_dsi@148F100C {
|
|
/* SYSREG_DISPAUD - DISPAUD_MIPI_PHY_CON */
|
|
compatible = "samsung,mipi-phy-dsim";
|
|
reg = <0x0 0x148F100C 0x4>;
|
|
samsung,pmu-syscon = <&pmu_system_controller>;
|
|
isolation = <0x070C>;
|
|
reset = <0>;
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
mdev_0: mdev_output {
|
|
compatible = "samsung,exynos5-mdev";
|
|
};
|
|
|
|
dsim_0: dsim@14800000 {
|
|
compatible = "samsung,exynos8-mipi-dsi";
|
|
reg = <0x0 0x14800000 0x100>;
|
|
|
|
interrupts = <0 207 0>;
|
|
samsung,power-domain = <&spd_disp>;
|
|
|
|
phys = <&mipi_phy_dsim 0>;
|
|
phy-names = "dsim_dphy";
|
|
|
|
/* TBD: power domain will be added later */
|
|
|
|
clocks = <&clock 704>, /* dispaud_dsim0 */
|
|
<&clock 721>, /* dispaud_mipiphy_rxclkesc0 */
|
|
<&clock 720>; /* dispaud_mipiphy_txbyteclkhs */
|
|
clock-names = "dsim_pclk", "dphy_escclk", "dphy_byteclk";
|
|
|
|
/* number of data lanes in use */
|
|
data_lane_cnt = <4>;
|
|
};
|
|
|
|
decon_0: decon_fb@14830000 {
|
|
compatible = "samsung,exynos5-decon_driver";
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
reg = <0x0 0x14830000 0x8000>;
|
|
#pb-id-cells = <0>;
|
|
|
|
samsung,power-domain = <&spd_disp>;
|
|
|
|
/* int_0: fifo_irq, int_1: vsync_irq, int_2: frame_done_irq, 3: te_irq */
|
|
interrupts = <0 201 0>, <0 202 0>, <0 203 0>, <0 360 0>;
|
|
|
|
clocks = <&clock 703>, /* dispaud_decon */
|
|
<&clock 730>, /* decon_vclk */
|
|
<&clock 731>; /* decon_vclk_local */
|
|
clock-names = "decon_core", "vclk_user", "vclk_leaf";
|
|
|
|
ip_ver = <4>;
|
|
max_win = <3>;
|
|
n_sink_pad = <3>;
|
|
n_src_pad = <1>;
|
|
default_win = <0>;
|
|
trig_mode = <1>; /* 0: hw trigger, 1: sw trigger */
|
|
dsi_mode = <0>; /* 0: single dsi, 1: dual dsi */
|
|
#if 0
|
|
pinctrl-names = "decon_te_on", "decon_te_off";
|
|
pinctrl-0 = <&decon_te_on>;
|
|
pinctrl-1 = <&decon_te_off>;
|
|
|
|
cam-stat {
|
|
/* ISP_STATUS register */
|
|
reg = <0x0 0x10484044 0x4>;
|
|
};
|
|
#endif
|
|
};
|
|
|
|
mailbox_cp: mcu_ipc@10500000 {
|
|
compatible = "samsung,exynos-shd-ipc-mailbox";
|
|
reg = <0x0 0x10500000 0x180>;
|
|
mcu,name = "mcu_ipc_cp";
|
|
mcu,id = <0>;
|
|
interrupts = <0 369 0 >;
|
|
};
|
|
|
|
mailbox_gnss: mcu_ipc@10570000 {
|
|
compatible = "samsung,exynos-shd-ipc-mailbox";
|
|
reg = <0x0 0x10570000 0x180>;
|
|
mcu,name = "mcu_ipc_gnss";
|
|
mcu,id = <1>;
|
|
interrupts = <0 373 0 >;
|
|
};
|
|
|
|
i2s0: i2s@148A0000 {
|
|
compatible = "samsung,i2s-v5";
|
|
reg = <0x0 0x148A0000 0x100>;
|
|
interrupts = <0 69 0>;
|
|
clocks = <&clock 711>, /* dispaud_mi2s_aud */
|
|
<&clock 741>, /* d1_i2s */
|
|
<&clock 741>; /* d1_i2s */
|
|
clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
|
|
samsung,supports-secdai;
|
|
samsung,i2s-str;
|
|
status = "disabled";
|
|
i2s-sec {
|
|
clocks = <&clock 711>, /* dispaud_mi2s_aud */
|
|
<&clock 741>, /* d1_i2s */
|
|
<&clock 741>; /* d1_i2s */
|
|
clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
|
|
};
|
|
};
|
|
|
|
gnss_pdata {
|
|
compatible = "samsung,gnss_shdmem_if";
|
|
shmem,name = "KEPLER";
|
|
shmem,device_node_name = "gnss_ipc";
|
|
status = "okay";
|
|
/* ACTIVE WATCHDOG WAKEUP */
|
|
interrupts = <0 19 0>, <0 478 0>, <0 477 0>;
|
|
|
|
mbx,int_ap2gnss_bcmd = <0>;
|
|
mbx,int_ap2gnss_req_fault_info = <1>;
|
|
mbx,int_ap2gnss_ipc_msg = <2>;
|
|
mbx,int_ap2gnss_ack_wake_set = <3>;
|
|
mbx,int_ap2gnss_ack_wake_clr = <4>;
|
|
|
|
mbx,irq_gnss2ap_bcmd = <0>;
|
|
mbx,irq_gnss2ap_rsp_fault_info = <1>;
|
|
mbx,irq_gnss2ap_ipc_msg = <2>;
|
|
mbx,irq_gnss2ap_req_wake_clr = <4>;
|
|
|
|
mbx,reg_bcmd_ctrl = <0>, <1>, <2>, <3>;
|
|
|
|
reg_rx_ipc_msg = <1 5>;
|
|
reg_tx_ipc_msg = <1 4>;
|
|
reg_rx_head = <1 3>;
|
|
reg_rx_tail = <1 2>;
|
|
reg_tx_head = <1 1>;
|
|
reg_tx_tail = <1 0>;
|
|
fault_info = <1 0x100000 0x100000>;
|
|
|
|
shmem,ipc_offset = <0x180000>;
|
|
shmem,ipc_size = <0x80000>;
|
|
shmem,ipc_reg_cnt = <32>;
|
|
};
|
|
|
|
cmu_fsys: cmu_fsys@0x13730000 {
|
|
compatible = "samsung,exynos7570-cmu_fsys", "syscon";
|
|
reg = <0x0 0x13730000 0x2000>;
|
|
};
|
|
|
|
scsc_wifibt: scsc_wifibt@10580000 {
|
|
compatible = "samsung,scsc_wifibt";
|
|
/* Mailbox registers */
|
|
reg = <0x0 0x10580000 0x180>;
|
|
interrupts = <0 376 4>, <0 21 4>, <0 476 4>;
|
|
interrupt-names = "MBOX","ALIVE","WDOG";
|
|
/* PMU alive handle */
|
|
samsung,syscon-phandle = <&pmu_system_controller>;
|
|
/* USBPLL ownership */
|
|
samsung,syscon-cmu_fsys = <&cmu_fsys>;
|
|
usbpll,owner="y";
|
|
usbpll,udelay=<20>;
|
|
status = "okay";
|
|
};
|
|
|
|
iommu-domain_mfc_mscl {
|
|
compatible = "samsung,exynos-iommu-bus";
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
domain-clients = <&smfc>, <&scaler_0>, <&mfc_0>, <&fimc_is>, <&fimc_is_sensor0>, <&fimc_is_sensor1>;
|
|
ranges;
|
|
|
|
smfc: smfc@12C20000 {
|
|
compatible = "samsung,exynos8890-jpeg";
|
|
reg = <0x0 0x12C20000 0x2000>;
|
|
interrupts = <0 404 0>;
|
|
clocks = <&clock CLK_GATE_JPEG>;
|
|
clock-names = "gate";
|
|
samsung,power-domain = <&pd_mfcmscl>;
|
|
};
|
|
|
|
scaler_0: scaler@12C10000 {
|
|
compatible = "samsung,exynos5-scaler";
|
|
reg = <0x0 0x12C10000 0x1300>;
|
|
interrupts = <0 401 0>;
|
|
clocks = <&clock CLK_GATE_MSCL>;
|
|
clock-names = "gate";
|
|
samsung,power-domain = <&pd_mfcmscl>;
|
|
prefetch-buffer,disable;
|
|
};
|
|
|
|
sysmmu_mfc_mscl: sysmmu@12C80000 {
|
|
compatible = "samsung,exynos7420-sysmmu";
|
|
reg = <0x0 0x12C80000 0x3000>;
|
|
interrupts = <0 352 0>,
|
|
<0 409 0>;
|
|
clocks = <&clock CLK_VCLK_SYSMMU_MFC_MSCL>;
|
|
clock-names = "aclk";
|
|
samsung,power-domain = <&pd_mfcmscl>;
|
|
sysmmu,v7tlb_property = <AR(0x2) SYSMMU_BL4_PREFETCH_PREDICTION>,
|
|
<AR(0x6) SYSMMU_BL4_PREFETCH_PREDICTION>,
|
|
<AR(0xE) SYSMMU_BL4_PREFETCH_ASCENDING>,
|
|
<AW(0x22) SYSMMU_BL4_PREFETCH_ASCENDING>,
|
|
<AW(0x26) SYSMMU_BL4_PREFETCH_ASCENDING>,
|
|
<AW(0x2A) SYSMMU_BL4_PREFETCH_ASCENDING>;
|
|
sysmmu,secure_reg = <0x12C70000>;
|
|
sysmmu,handle_secure-irq;
|
|
master_ip_list = <&smfc>, <&scaler_0>, <&mfc_0>, <&fimc_is>;
|
|
};
|
|
|
|
sysmmu_isp: sysmmu@0x14470000 {
|
|
compatible = "samsung,exynos7420-sysmmu";
|
|
reg = <0x0 0x14470000 0x3000>;
|
|
interrupts = <0 128 0>;
|
|
qos = <15>;
|
|
clocks = <&clock CLK_VCLK_SYSMMU_ISP>;
|
|
clock-names = "aclk";
|
|
samsung,power-domain = <&pd_isp>;
|
|
sysmmu,v7tlb_property = <AW(0x0) SYSMMU_BL1_PREFETCH_PREDICTION>,
|
|
<AW(0x4) SYSMMU_BL1_PREFETCH_PREDICTION>,
|
|
<AR(0x1) SYSMMU_BL1_PREFETCH_PREDICTION>,
|
|
<AW(0x1) SYSMMU_BL1_PREFETCH_PREDICTION>,
|
|
<AW(0x5) SYSMMU_BL1_PREFETCH_PREDICTION>,
|
|
<AW(0x2) SYSMMU_BL1_PREFETCH_PREDICTION>,
|
|
<AW(0x6) SYSMMU_BL1_PREFETCH_PREDICTION>,
|
|
<AW(0xA) SYSMMU_BL1_PREFETCH_PREDICTION>,
|
|
<AW(0x3) SYSMMU_BL1_PREFETCH_PREDICTION>,
|
|
<AR(0x3) SYSMMU_BL2_NO_PREFETCH>;
|
|
master_ip_list = <&fimc_is>, <&fimc_is_sensor0>, <&fimc_is_sensor1>;
|
|
};
|
|
};
|
|
|
|
iommu-domain_disp {
|
|
compatible = "samsung,exynos-iommu-bus";
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
domain-clients = <&decon_0>;
|
|
|
|
sysmmu_disp: sysmmu@14860000 {
|
|
compatible = "samsung,exynos7420-sysmmu";
|
|
reg = <0x0 0x14860000 0x3000>;
|
|
interrupts = <0 192 0>,
|
|
<0 193 0>;
|
|
qos = <15>;
|
|
clocks = <&clock CLK_VCLK_SYSMMU_DISP_AUD>;
|
|
clock-names = "aclk";
|
|
samsung,power-domain = <&pd_dispaud>;
|
|
sysmmu,v7tlb_property = <AR(0x0) SYSMMU_BL1_NO_PREFETCH>,
|
|
<AR(0x2) SYSMMU_BL1_NO_PREFETCH>,
|
|
<AR(0x4) SYSMMU_BL1_NO_PREFETCH>,
|
|
<AR(0x5) SYSMMU_BL1_NO_PREFETCH>;
|
|
sysmmu,secure_reg = <0x14850000>;
|
|
sysmmu,handle_secure-irq;
|
|
master_ip_list = <&decon_0>;
|
|
};
|
|
};
|
|
|
|
watchdog@10170000 {
|
|
compatible = "samsung,exynos7-wdt";
|
|
reg = <0x0 0x10170000 0x100>;
|
|
interrupts = <0 100 0>;
|
|
clocks = <&clock 371>, <&clock 371>;
|
|
clock-names = "rate_watchdog", "gate_watchdog";
|
|
timeout-sec = <30>;
|
|
samsung,syscon-phandle = <&pmu_system_controller>;
|
|
};
|
|
|
|
exynos_adc: adc@10550000 {
|
|
compatible = "samsung,exynos-adc-v3";
|
|
reg = <0x0 0x10550000 0x1000>;
|
|
interrupts = <0 395 0>;
|
|
#io-channel-cells = <1>;
|
|
io-channel-ranges;
|
|
clocks = <&clock 10>;
|
|
clock-names = "gate_adcif";
|
|
};
|
|
|
|
rtc@101A0000 {
|
|
compatible = "samsung,s3c6410-rtc";
|
|
reg = <0x0 0x101A0000 0x100>;
|
|
interrupts = <0 92 0>, <0 93 0>;
|
|
clocks = <&clock 374>;
|
|
clock-names = "gate_rtc";
|
|
};
|
|
|
|
coresight@16000000 {
|
|
compatible = "exynos,coresight";
|
|
base = <0x16000000>;
|
|
sjtag-offset = <0x6000>;
|
|
|
|
cs_apollo0@400000 {
|
|
device_type = "cs";
|
|
dbg-offset = <0x410000>;
|
|
};
|
|
cs_apollo1@500000 {
|
|
device_type = "cs";
|
|
dbg-offset = <0x510000>;
|
|
};
|
|
cs_apollo2@600000 {
|
|
device_type = "cs";
|
|
dbg-offset = <0x610000>;
|
|
};
|
|
cs_apollo3@700000 {
|
|
device_type = "cs";
|
|
dbg-offset = <0x710000>;
|
|
};
|
|
};
|
|
|
|
udc: usb@13600000 {
|
|
compatible = "samsung,exynos7570-dwusb2";
|
|
reg = <0x0 0x13600000 0x10000>;
|
|
clocks = <&clock 512>;
|
|
clock-names = "usbdrd20";
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
usbdrd_dwc3: dwc3 {
|
|
compatible = "synopsys,dwc3";
|
|
reg = <0x0 0x13600000 0x10000>;
|
|
interrupts = <0 230 0>;
|
|
maximum-speed = "high-speed";
|
|
is_not_vbus_pad;
|
|
suspend_clk_freq = <67000000>;
|
|
enable_sprs_transfer;
|
|
phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
|
|
phy-names = "usb2-phy", "usb3-phy";
|
|
};
|
|
};
|
|
|
|
usbdrd_phy: usbphy@135c0000 {
|
|
compatible = "samsung,exynos7570-usbdrd-phy";
|
|
reg = <0x0 0x135c0000 0x100>;
|
|
clocks = <&clock 512>, <&clock 520>, <&clock 530>;
|
|
clock-names = "usbdrd20", "phyumux", "usb_pll";
|
|
#phy-cells = <1>;
|
|
samsung,pmu-syscon = <&pmu_system_controller>;
|
|
is_not_vbus_pad;
|
|
use_additional_tuning;
|
|
request_extrefclk;
|
|
uart_io_share_enable = <1>;
|
|
uart_io_share_offset = <0x6200>;
|
|
uart_io_share_mask = <0x1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sec_pwm: pwm@13970000 {
|
|
compatible = "samsung,s3c6400-pwm";
|
|
reg = <0x0 0x13970000 0x1000>;
|
|
samsung,pwm-outputs = <0>, <1>, <2>, <3>, <4>;
|
|
samsung,pwm-sclk-ctrl;
|
|
#pwm-cells = <3>;
|
|
clocks = <&clock 330>, <&clock 331>,
|
|
<&clock_pwm 1>, <&clock_pwm 2>,
|
|
<&clock_pwm 5>, <&clock_pwm 6>,
|
|
<&clock_pwm 7>, <&clock_pwm 8>,
|
|
<&clock_pwm 10>, <&clock_pwm 11>,
|
|
<&clock_pwm 12>, <&clock_pwm 13>;
|
|
clock-names = "gate_timers", "sclk_pwm",
|
|
"pwm-scaler0", "pwm-scaler1",
|
|
"pwm-tdiv0", "pwm-tdiv1",
|
|
"pwm-tdiv2", "pwm-tdiv3",
|
|
"pwm-tin0", "pwm-tin1",
|
|
"pwm-tin2", "pwm-tin3";
|
|
status = "ok";
|
|
};
|
|
|
|
clock_pwm: pwm-clock-controller@13970000 {
|
|
compatible = "samsung,exynos-pwm-clock";
|
|
reg = <0x0 0x13970000 0x50>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
mipi_phy_csis: phy_phy_csis@144F1040 {
|
|
compatible = "samsung,mipi-phy-csis";
|
|
reg = <0x0 0x144F1040 0x4>; /* SYSREG address for reset */
|
|
samsung,pmu-syscon = <&pmu_system_controller>;
|
|
isolation = <0x070C 0x0714>; /* PMU address offset 0x714 M0S4 */
|
|
reset = <1 0>; /* reset bit [0] */
|
|
#phy-cells = <1>;
|
|
};
|
|
|
|
fimc_is_sensor0: fimc_is_sensor0@14420000 {
|
|
/* REAR */
|
|
compatible = "samsung,exynos5-fimc-is-sensor";
|
|
#pb-id-cells = <0>;
|
|
reg = <0x0 0x14420000 0x10000>, /* MIPI-CSI0 */
|
|
<0x0 0x14410000 0x10000>; /* FIMC-BSC */
|
|
interrupts = <0 144 0>, /* MIPI-CSI0 */
|
|
<0 137 0>; /* FIMC-BSC */
|
|
samsung,power-domain = <&pd_isp>;
|
|
|
|
phys = <&mipi_phy_csis 1>;
|
|
phy-names = "csis_dphy";
|
|
clock-names =
|
|
"mif_isp_sensor0";
|
|
clocks = <&clock 43>;
|
|
};
|
|
|
|
fimc_is_sensor1: fimc_is_sensor1@14420000 {
|
|
/* FRONT */
|
|
compatible = "samsung,exynos5-fimc-is-sensor";
|
|
#pb-id-cells = <0>;
|
|
reg = <0x0 0x14420000 0x10000>, /* MIPI-CSI0 */
|
|
<0x0 0x14410000 0x10000>; /* FIMC-BSC */
|
|
interrupts = <0 144 0>, /* MIPI-CSI0 */
|
|
<0 137 0>; /* FIMC-BSC */
|
|
samsung,power-domain = <&pd_isp>;
|
|
|
|
phys = <&mipi_phy_csis 0>;
|
|
phy-names = "csis_dphy";
|
|
clock-names =
|
|
"mif_isp_sensor0";
|
|
clocks = <&clock 43>;
|
|
};
|
|
|
|
fimc_is: fimc_is@14400000 {
|
|
compatible = "samsung,exynos5-fimc-is";
|
|
#pb-id-cells = <0>;
|
|
reg = <0x0 0x14400000 0xC400>, /* FIMC-ISP */
|
|
<0x0 0x14430000 0x2000>, /* MC-Scaler */
|
|
<0x0 0x14440000 0x10000>, /* FIMC-VRA CH0 */
|
|
<0x0 0x14450000 0x10000>, /* FIMC-VRA CH1 */
|
|
<0x0 0x14480000 0xC400>, /* FIMC-ISP(setB) */
|
|
<0x0 0x12C00000 0x2000>; /* MC-Scaler M2M */
|
|
|
|
interrupts = <0 139 0>, /* FIMC-ISP0 */
|
|
<0 140 0>, /* FIMC-ISP1 */
|
|
<0 141 0>, /* FIMC-ISP2 */
|
|
<0 142 0>, /* MC-SCALER */
|
|
<0 146 0>, /* FIMC-VRA */
|
|
<0 400 0>; /* MC-SCALER M2M */
|
|
samsung,power-domain = <&pd_isp>;
|
|
|
|
clock-names =
|
|
"oscclk",
|
|
"isp_ppmu",
|
|
"isp_bts",
|
|
"isp_cam",
|
|
"isp_vra",
|
|
"umux_isp_clkphy_isp_s_rxbyteclkhs0_s4_user",
|
|
"gate_mscl",
|
|
"mif_isp_sensor0";
|
|
clocks = <&clock 1>,
|
|
<&clock 801>,
|
|
<&clock 802>,
|
|
<&clock 803>,
|
|
<&clock 804>,
|
|
<&clock 810>,
|
|
<&clock 610>,
|
|
<&clock 43>;
|
|
|
|
status = "ok";
|
|
};
|
|
|
|
fm@14840000 {
|
|
compatible = "samsung,exynos7570-fm";
|
|
reg = <0x0 0x14840000 0x2000>,
|
|
<0x0 0x11C80000 0x1000>,
|
|
<0x0 0x10580000 0x100>,
|
|
<0x0 0x148D0000 0x500>,
|
|
<0x0 0x10460000 0x3000>,
|
|
<0x0 0x13730000 0x2000>,
|
|
<0x0 0x14880000 0x100>;
|
|
interrupts = <0 195 0>;
|
|
clocks = <&clock 743>; /* fm_52M_div */
|
|
clock-names = "oscclk_fm_52m_div";
|
|
samsung,syscon-phandle = <&pmu_system_controller>;
|
|
samsung,power-domain = <&spd_fm>;
|
|
status = "okay";
|
|
};
|
|
};
|