mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 01:08:03 -04:00
332 lines
16 KiB
C
332 lines
16 KiB
C
/*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This file contains clocks of Exynos7870.
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*/
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <dt-bindings/clock/exynos7870.h>
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#include "../../soc/samsung/pwrcal/S5E7870/S5E7870-vclk.h"
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#include "composite.h"
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#if defined(CONFIG_ECT)
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#include <soc/samsung/ect_parser.h>
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#endif
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enum exynos7870_clks {
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none,
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oscclk = 1,
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/* The group of clocks in mfcmscl */
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mscl_sysmmu = 10, mfc_sysmmu, mfcmscl_ppmu, mfcmscl_bts, gate_mscl_bi, gate_mscl_poly, gate_jpeg, gate_mfc,
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/* The group of clocks in g3d */
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g3d_sysmmu = 50, g3d_ppmu, g3d_bts, gate_g3d,
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/* The group of clocks related with pwm and mct in peri */
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peri_pwm_motor = 100, peri_sclk_pwm_motor, peri_mct,
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/* The group of clocks related with i2c in peri */
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i2c_sensor1 = 110, i2c_sensor2, i2c_tsp, i2c_touchkey, i2c_fuelgauge, i2c_spkamp, i2c_nfc, i2c_muic, i2c_ifpmic,
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/* The group of clocks related with hsi2c in peri */
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hsi2c_frontcam = 130, hsi2c_maincam, hsi2c_depthcam, hsi2c_frontsensor, hsi2c_rearaf, hsi2c_rearsensor,
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/* The group of clocks related with gpio in peri */
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gpio_touch = 150, gpio_top, gpio_nfc, gpio_ese, gpio_alive,
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/* The group of clocks related with wdt in peri */
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wdt_cpucl0 = 160, wdt_cpucl1,
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/* The group of clocks related with uart in peri */
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uart_debug = 170, uart_btwififm, uart_sensor,
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/* The group of clocks related with tmu in peri */
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peri_tmu_g3d = 180, peri_tmu_cpucl1, peri_tmu_cpucl0,
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/* The group of clocks related with spi in peri */
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peri_spi_sensorhub = 190, peri_spi_voiceprocessor, peri_spi_ese, peri_spi_rearfrom, peri_spi_frontfrom,
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/* The group of clocks related with rtc in peri */
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peri_rtc_alive = 210, peri_rtc_top,
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/* The group of etc clocks in peri */
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peri_chipid = 220, peri_otp_con_top,
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/* The group of clocks in fsys */
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fsys_sysmmu = 300, fsys_ppmu, fsys_bts,
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fsys_mmc0 = 310, fsys_mmc1, fsys_mmc2, fsys_sclk_mmc0, fsys_sclk_mmc1, fsys_sclk_mmc2,
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fsys_sss = 330, fsys_rtic, fsys_pdma0, fsys_pdma1, fsys_sromc, fsys_usb20drd, fsys_usb20drd_phyclock,
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usb_pll = 350,
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/* The group of clocks in dispaud */
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dispaud_sysmmu = 400, dispaud_ppmu, dispaud_bts,
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dispaud_decon = 410, dispaud_dsim0, dispaud_mixer, dispaud_mi2s_aud, dispaud_mi2s_amp,
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dispaud_bus = 430, dispaud_decon_int_vclk, dispaud_decon_int_eclk, dispaud_mipiphy_txbyteclkhs, dispaud_mipiphy_rxclkesc0,
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decon_vclk = 450, decon_vclk_local, decon_eclk, decon_eclk_local,
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disp_pll = 460, aud_pll, d1_i2s, d1_mixer,
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/* The group of clocks in isp */
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isp_sysmmu = 500, isp_ppmu, isp_bts,
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isp_cam = 510, isp_isp, isp_vra, pxmxdx_vra, pxmxdx_cam, pxmxdx_isp,
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isp_s_rxbyteclkhs0_s4 = 520, isp_s_rxbyteclkhs0_s4s,
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isp_pll = 530,
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/* The group of clocks in mif */
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mif_adcif = 600, mif_hsi2c_mif, mmc0_sclk, mmc1_sclk, mmc2_sclk,
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ufsunipro_sclk = 610, ufsunipro_cfg_sclk, usb20drd_sclk,
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uart_sensor_sclk = 620, uart_btwififm_sclk, uart_debug_sclk,
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spi_frontfrom_sclk = 630, spi_rearfrom_sclk, spi_ese_sclk, spi_voiceprocessor_sclk, spi_sensorhub_sclk,
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isp_sensor0_sclk = 640, isp_sensor1_sclk, isp_sensor2_sclk,
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/* number of dfs driver starts from 2000 */
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dfs_mif = 2000, dfs_mif_sw, dfs_int, dfs_cam, dfs_disp,
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nr_clks,
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};
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/* fixed rate clocks generated outside the soc */
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static struct samsung_fixed_rate exynos7870_fixed_rate_ext_clks[] __initdata = {
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FRATE(oscclk, "fin_pll", NULL, CLK_IS_ROOT, 26000000),
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};
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static struct of_device_id ext_clk_match[] __initdata = {
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{ .compatible = "samsung,exynos7870-oscclk", .data = (void *)0, },
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};
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static struct init_vclk exynos7870_mfcmscl_vclks[] __initdata = {
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/* MFC & MSCL ACLK */
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VCLK(mscl_sysmmu, gate_mfcmscl_sysmmu_mscl, "gate_mfcmscl_sysmmu_mscl", 0, 0, NULL),
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VCLK(mfc_sysmmu, gate_mfcmscl_sysmmu_mfc, "gate_mfcmscl_sysmmu_mfc", 0, 0, NULL),
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VCLK(mfcmscl_ppmu, gate_mfcmscl_ppmu, "gate_mfcmscl_ppmu", 0, 0, NULL),
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VCLK(mfcmscl_bts, gate_mfcmscl_bts, "gate_mfcmscl_bts", 0, 0, NULL),
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VCLK(gate_mscl_bi, gate_mfcmscl_mscl_bi, "gate_mfcmscl_mscl_bi", 0, 0, NULL),
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VCLK(gate_mscl_poly, gate_mfcmscl_mscl_poly, "gate_mfcmscl_mscl_poly", 0, 0, NULL),
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VCLK(gate_jpeg, gate_mfcmscl_jpeg, "gate_mfcmscl_jpeg", 0, 0, NULL),
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VCLK(gate_mfc, gate_mfcmscl_mfc, "gate_mfcmscl_mfc", 0, 0, NULL),
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};
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static struct init_vclk exynos7870_g3d_vclks[] __initdata = {
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/* G3D ACLK */
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VCLK(g3d_sysmmu, gate_g3d_sysmmu, "gate_g3d_sysmmu", 0, 0, NULL),
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VCLK(g3d_ppmu, gate_g3d_ppmu, "gate_g3d_ppmu", 0, 0, NULL),
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VCLK(g3d_bts, gate_g3d_bts, "gate_g3d_bts", 0, 0, "gate_g3d_bts_alias"),
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VCLK(gate_g3d, gate_g3d_g3d, "gate_g3d_g3d", 0, 0, "vclk_g3d"),
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};
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static struct init_vclk exynos7870_peri_vclks[] __initdata = {
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/* PERI PWM ACLK & SCLK */
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VCLK(peri_pwm_motor, gate_peri_pwm_motor, "gate_peri_pwm_motor", 0, 0, NULL),
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VCLK(peri_sclk_pwm_motor, gate_peri_sclk_pwm_motor, "gate_peri_sclk_pwm_motor", 0, 0, NULL),
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/* PERI MCT ACLK */
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VCLK(peri_mct, gate_peri_mct, "gate_peri_mct", 0, 0, NULL),
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/* PERI I2C ACLK */
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VCLK(i2c_sensor1, gate_peri_i2c_sensor1, "gate_peri_i2c_sensor1", 0, 0, NULL),
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VCLK(i2c_sensor2, gate_peri_i2c_sensor2, "gate_peri_i2c_sensor2", 0, 0, NULL),
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VCLK(i2c_tsp, gate_peri_i2c_tsp, "gate_peri_i2c_tsp", 0, 0, NULL),
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VCLK(i2c_touchkey, gate_peri_i2c_touchkey, "gate_peri_i2c_touchkey", 0, 0, NULL),
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VCLK(i2c_fuelgauge, gate_peri_i2c_fuelgauge, "gate_peri_i2c_fuelgauge", 0, 0, NULL),
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VCLK(i2c_spkamp, gate_peri_i2c_spkamp, "gate_peri_i2c_spkamp", 0, 0, NULL),
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VCLK(i2c_nfc, gate_peri_i2c_nfc, "gate_peri_i2c_nfc", 0, 0, NULL),
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VCLK(i2c_muic, gate_peri_i2c_muic, "gate_peri_i2c_muic", 0, 0, NULL),
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VCLK(i2c_ifpmic, gate_peri_i2c_ifpmic, "gate_peri_i2c_ifpmic", 0, 0, NULL),
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/* PERI HSI2C ACLK */
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VCLK(hsi2c_frontcam, gate_peri_hsi2c_frontcam, "gate_peri_hsi2c_frontcam", 0, 0, NULL),
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VCLK(hsi2c_maincam, gate_peri_hsi2c_maincam, "gate_peri_hsi2c_maincam", 0, 0, NULL),
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VCLK(hsi2c_depthcam, gate_peri_hsi2c_depthcam, "gate_peri_hsi2c_depthcam", 0, 0, NULL),
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VCLK(hsi2c_frontsensor, gate_peri_hsi2c_frontsensor, "gate_peri_hsi2c_frontsensor", 0, 0, NULL),
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VCLK(hsi2c_rearaf,gate_peri_hsi2c_rearaf, "gate_peri_hsi2c_rearaf", 0, 0, NULL),
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VCLK(hsi2c_rearsensor, gate_peri_hsi2c_rearsensor, "gate_peri_hsi2c_rearsensor", 0, 0, NULL),
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/* PERI GPIO ACLK */
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VCLK(gpio_touch, gate_peri_gpio_touch, "gate_peri_gpio_touch", 0, 0, NULL),
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VCLK(gpio_top, gate_peri_gpio_top, "gate_peri_gpio_top", 0, 0, NULL),
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VCLK(gpio_nfc, gate_peri_gpio_nfc, "gate_peri_gpio_nfc", 0, 0, NULL),
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VCLK(gpio_ese, gate_peri_gpio_ese, "gate_peri_gpio_ese", 0, 0, NULL),
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VCLK(gpio_alive, gate_peri_gpio_alive, "gate_peri_gpio_alive", 0, 0, NULL),
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/* PERI WDT ACLK */
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VCLK(wdt_cpucl0, gate_peri_wdt_cpucl0, "gate_peri_wdt_cpucl0", 0, 0, NULL),
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VCLK(wdt_cpucl1, gate_peri_wdt_cpucl1, "gate_peri_wdt_cpucl1", 0, 0, NULL),
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/* PERI UART ACLK */
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VCLK(uart_debug, gate_peri_uart_debug, "gate_peri_uart_debug", 0, 0, "console-pclk0"),
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VCLK(uart_btwififm, gate_peri_uart_btwififm, "gate_peri_uart_btwififm", 0, 0, NULL),
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VCLK(uart_sensor, gate_peri_uart_sensor, "gate_peri_uart_sensor", 0, 0, NULL),
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/* PERI TMU ACLK */
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VCLK(peri_tmu_g3d, gate_peri_tmu_g3d, "gate_peri_tmu_g3d", 0, 0, NULL),
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VCLK(peri_tmu_cpucl1, gate_peri_tmu_cpucl1, "gate_peri_tmu_cpucl1", 0, 0, NULL),
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VCLK(peri_tmu_cpucl0, gate_peri_tmu_cpucl0, "gate_peri_tmu_cpucl0", 0, 0, NULL),
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/* PERI SPI ACLK */
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VCLK(peri_spi_sensorhub, gate_peri_spi_sensorhub, "gate_peri_spi_sensorhub", 0, 0, NULL),
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VCLK(peri_spi_voiceprocessor, gate_peri_spi_voiceprocessor, "gate_peri_spi_voiceprocessor", 0, 0, NULL),
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VCLK(peri_spi_ese, gate_peri_spi_ese, "gate_peri_spi_ese", 0, 0, NULL),
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VCLK(peri_spi_rearfrom, gate_peri_spi_rearfrom, "gate_peri_spi_rearfrom", 0, 0, NULL),
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VCLK(peri_spi_frontfrom, gate_peri_spi_frontfrom, "gate_peri_spi_frontfrom", 0, 0, NULL),
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/* PERI RTC ACLK */
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VCLK(peri_rtc_alive, gate_peri_rtc_alive, "gate_peri_rtc_alive", 0, 0, NULL),
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VCLK(peri_rtc_top, gate_peri_rtc_top, "gate_peri_rtc_top", 0, 0, NULL),
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/* PERI ETC ACLK */
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VCLK(peri_chipid, gate_peri_chipid, "gate_peri_chipid", 0, 0, NULL),
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VCLK(peri_otp_con_top, gate_peri_otp_con_top, "gate_peri_otp_con_top", 0, 0, NULL),
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};
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static struct init_vclk exynos7870_fsys_vclks[] __initdata = {
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/* FSYS COMMON*/
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VCLK(fsys_sysmmu, gate_fsys_sysmmu, "gate_fsys_sysmmu", 0, 0, NULL),
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VCLK(fsys_ppmu, gate_fsys_ppmu, "gate_fsys_ppmu", 0, 0, NULL),
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VCLK(fsys_bts, gate_fsys_bts, "gate_fsys_bts", 0, 0, NULL),
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VCLK(fsys_usb20drd, gate_fsys_usb20drd, "gate_fsys_usb20drd", 0, 0, NULL),
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VCLK(fsys_mmc0, gate_fsys_mmc0, "gate_fsys_mmc0", 0, 0, NULL),
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VCLK(fsys_mmc1, gate_fsys_mmc1, "gate_fsys_mmc1", 0, 0, NULL),
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VCLK(fsys_mmc2, gate_fsys_mmc2, "gate_fsys_mmc2", 0, 0, NULL),
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VCLK(fsys_sclk_mmc0, gate_fsys_sclk_mmc0, "gate_fsys_sclk_mmc0", 0, 0, NULL),
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VCLK(fsys_sclk_mmc1, gate_fsys_sclk_mmc1, "gate_fsys_sclk_mmc1", 0, 0, NULL),
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VCLK(fsys_sclk_mmc2, gate_fsys_sclk_mmc2, "gate_fsys_sclk_mmc2", 0, 0, NULL),
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VCLK(fsys_sss, gate_fsys_sss, "gate_fsys_sss", 0, 0, NULL),
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VCLK(fsys_rtic, gate_fsys_rtic, "gate_fsys_rtic", 0, 0, NULL),
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VCLK(fsys_pdma0, gate_fsys_pdma0, "gate_fsys_pdma0", 0, 0, NULL),
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VCLK(fsys_pdma1, gate_fsys_pdma1, "gate_fsys_pdma1", 0, 0, NULL),
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VCLK(fsys_sromc, gate_fsys_sromc, "gate_fsys_sromc", 0, 0, NULL),
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VCLK(fsys_usb20drd_phyclock, umux_fsys_clkphy_fsys_usb20drd_phyclock_user, "umux_fsys_clkphy_fsys_usb20drd_phyclock_user", 0, 0, NULL),
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VCLK(usb_pll, p1_usb_pll, "p1_usb_pll", 0, 0, NULL),
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};
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static struct init_vclk exynos7870_dispaud_vclks[] __initdata = {
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/* DISPAUD ACLK */
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VCLK(dispaud_sysmmu, gate_dispaud_sysmmu, "gate_dispaud_sysmmu", 0, 0, NULL),
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VCLK(dispaud_ppmu, gate_dispaud_ppmu, "gate_dispaud_ppmu", 0, 0, NULL),
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VCLK(dispaud_bts, gate_dispaud_bts, "gate_dispaud_bts", 0, 0, NULL),
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VCLK(dispaud_decon, gate_dispaud_decon, "gate_dispaud_decon", 0, 0, NULL),
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VCLK(dispaud_dsim0, gate_dispaud_dsim0, "gate_dispaud_dsim0", 0, 0, NULL),
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VCLK(dispaud_mixer, gate_dispaud_mixer, "gate_dispaud_mixer", 0, 0, NULL),
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VCLK(dispaud_mi2s_aud, gate_dispaud_mi2s_aud, "gate_dispaud_mi2s_aud", 0, 0, NULL),
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VCLK(dispaud_mi2s_amp, gate_dispaud_mi2s_amp, "gate_dispaud_mi2s_amp", 0, 0, NULL),
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/*
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VCLK(dispaud_bus, umux_dispaud_clkcmu_dispaud_bus_user, "umux_dispaud_clkcmu_dispaud_bus_user", 0, 0, NULL),
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VCLK(dispaud_decon_int_vclk, umux_dispaud_clkcmu_dispaud_decon_int_vclk_user, "umux_dispaud_clkcmu_dispaud_decon_int_vclk_user", 0, 0, NULL),
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VCLK(dispaud_decon_int_eclk, umux_dispaud_clkcmu_dispaud_decon_int_eclk_user, "umux_dispaud_clkcmu_dispaud_decon_int_eclk_user", 0, 0, NULL),
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*/
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VCLK(dispaud_mipiphy_txbyteclkhs, umux_dispaud_clkphy_dispaud_mipiphy_txbyteclkhs_user, "umux_dispaud_clkphy_dispaud_mipiphy_txbyteclkhs_user", 0, 0, NULL),
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VCLK(dispaud_mipiphy_rxclkesc0, umux_dispaud_clkphy_dispaud_mipiphy_rxclkesc0_user, "umux_dispaud_clkphy_dispaud_mipiphy_rxclkesc0_user", 0, 0, NULL),
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/* DISPAUD SCLK */
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VCLK(decon_vclk, sclk_decon_vclk, "sclk_decon_vclk", 0, 0, NULL),
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VCLK(decon_vclk_local, sclk_decon_vclk_local, "sclk_decon_vclk_local", 0, 0, NULL),
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VCLK(decon_eclk, sclk_decon_eclk, "sclk_decon_eclk", 0, 0, NULL),
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VCLK(decon_eclk_local, sclk_decon_eclk_local, "sclk_decon_eclk_local", 0, 0, NULL),
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/* DISPAUD PLL */
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VCLK(disp_pll, p1_disp_pll, "p1_disp_pll", 0, 0, NULL),
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VCLK(aud_pll, p1_aud_pll, "p1_aud_pll", 0, 0, NULL),
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VCLK(d1_i2s, d1_dispaud_mi2s, "d1_dispaud_mi2s", 0, 0, NULL),
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VCLK(d1_mixer, d1_dispaud_mixer, "d1_dispaud_mixer", 0, 0, NULL),
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};
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static struct init_vclk exynos7870_isp_vclks[] __initdata = {
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VCLK(isp_sysmmu, gate_isp_sysmmu, "gate_isp_sysmmu", 0, 0, NULL),
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VCLK(isp_ppmu, gate_isp_ppmu, "gate_isp_ppmu", 0, 0, NULL),
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VCLK(isp_bts, gate_isp_bts, "gate_isp_bts", 0, 0, NULL),
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VCLK(isp_cam, gate_isp_cam, "gate_isp_cam", 0, 0, NULL),
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VCLK(isp_isp, gate_isp_isp, "gate_isp_isp", 0, 0, NULL),
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VCLK(isp_vra, gate_isp_vra, "gate_isp_vra", 0, 0, NULL),
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VCLK(pxmxdx_vra, pxmxdx_isp_vra, "pxmxdx_isp_vra", 0, 0, NULL),
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VCLK(pxmxdx_cam, pxmxdx_isp_cam, "pxmxdx_isp_cam", 0, 0, NULL),
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VCLK(pxmxdx_isp, pxmxdx_isp_isp, "pxmxdx_isp_isp", 0, 0, NULL),
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VCLK(isp_s_rxbyteclkhs0_s4, umux_isp_clkphy_isp_s_rxbyteclkhs0_s4_user, "umux_isp_clkphy_isp_s_rxbyteclkhs0_s4_user", 0, 0, NULL),
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VCLK(isp_s_rxbyteclkhs0_s4s, umux_isp_clkphy_isp_s_rxbyteclkhs0_s4s_user, "umux_isp_clkphy_isp_s_rxbyteclkhs0_s4s_user", 0, 0, NULL),
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VCLK(isp_pll, p1_isp_pll, "p1_isp_pll", 0, 0, NULL),
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};
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static struct init_vclk exynos7870_mif_vclks[] __initdata = {
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VCLK(mif_adcif, gate_mif_adcif, "gate_mif_adcif", 0, 0, NULL),
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VCLK(mif_hsi2c_mif, gate_mif_hsi2c_mif, "gate_mif_hsi2c_mif", 0, 0, NULL),
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VCLK(mmc0_sclk, sclk_mmc0, "sclk_mmc0", 0, 0, NULL),
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VCLK(mmc1_sclk, sclk_mmc1, "sclk_mmc1", 0, 0, NULL),
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VCLK(mmc2_sclk, sclk_mmc2, "sclk_mmc2", 0, 0, NULL),
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/*
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VCLK(ufsunipro_sclk, sclk_ufsunipro, "sclk_ufsunipro", 0, 0, NULL),
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VCLK(ufsunipro_cfg_sclk, sclk_ufsunipro_cfg, "sclk_ufsunipro_cfg", 0, 0, NULL),
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*/
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VCLK(usb20drd_sclk, sclk_usb20drd, "sclk_usb20drd" , 0, 0, NULL),
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VCLK(uart_sensor_sclk, sclk_uart_sensor, "sclk_uart_sensor", 0, 0, "console-sclk0"),
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VCLK(uart_btwififm_sclk, sclk_uart_btwififm, "sclk_uart_btwififm", 0, 0, NULL),
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VCLK(uart_debug_sclk, sclk_uart_debug, "sclk_uart_debug", 0, 0, NULL),
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VCLK(spi_frontfrom_sclk, sclk_spi_frontfrom, "sclk_spi_frontfrom", 0, 0, NULL),
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VCLK(spi_rearfrom_sclk, sclk_spi_rearfrom, "sclk_spi_rearfrom", 0, 0, NULL),
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VCLK(spi_ese_sclk, sclk_spi_ese, "sclk_spi_ese", 0, 0, NULL),
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VCLK(spi_voiceprocessor_sclk, sclk_spi_voiceprocessor, "sclk_spi_voiceprocessor", 0, 0, NULL),
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VCLK(spi_sensorhub_sclk, sclk_spi_sensorhub, "sclk_spi_sensorhub", 0, 0, NULL),
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VCLK(isp_sensor0_sclk, sclk_isp_sensor0, "sclk_isp_sensor0", 0, 0, NULL),
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VCLK(isp_sensor1_sclk, sclk_isp_sensor1, "sclk_isp_sensor1", 0, 0, NULL),
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VCLK(isp_sensor2_sclk, sclk_isp_sensor2, "sclk_isp_sensor2", 0, 0, NULL),
|
|
};
|
|
|
|
static struct init_vclk exynos7870_dfs_vclks[] __initdata = {
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|
/* DFS */
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|
VCLK(dfs_mif, dvfs_mif, "dvfs_mif", 0, VCLK_DFS, NULL),
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|
VCLK(dfs_mif_sw, dvfs_mif, "dvfs_mif_sw", 0, VCLK_DFS_SWITCH, NULL),
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|
VCLK(dfs_int, dvfs_int, "dvfs_int", 0, VCLK_DFS, NULL),
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|
VCLK(dfs_cam, dvfs_cam, "dvfs_cam", 0, VCLK_DFS, NULL),
|
|
VCLK(dfs_disp, dvfs_disp, "dvfs_disp", 0, VCLK_DFS, NULL),
|
|
};
|
|
|
|
/* register exynos7870 clocks */
|
|
void __init exynos7870_clk_init(struct device_node *np)
|
|
{
|
|
struct samsung_clk_provider *ctx;
|
|
void __iomem *reg_base;
|
|
int ret;
|
|
|
|
if (np) {
|
|
reg_base = of_iomap(np, 0);
|
|
if (!reg_base)
|
|
panic("%s: failed to map registers\n", __func__);
|
|
} else {
|
|
panic("%s: unable to determine soc\n", __func__);
|
|
}
|
|
|
|
#if defined(CONFIG_ECT)
|
|
ect_parse_binary_header();
|
|
#endif
|
|
|
|
ret = cal_init();
|
|
if (ret)
|
|
pr_err("%s: unable to initialize power cal\n", __func__);
|
|
|
|
ctx = samsung_clk_init(np, reg_base, nr_clks);
|
|
if (!ctx)
|
|
panic("%s: unable to allocate context.\n", __func__);
|
|
|
|
samsung_register_of_fixed_ext(ctx, exynos7870_fixed_rate_ext_clks,
|
|
ARRAY_SIZE(exynos7870_fixed_rate_ext_clks), ext_clk_match);
|
|
|
|
/* Regist clock local IP */
|
|
samsung_register_vclk(ctx, exynos7870_mfcmscl_vclks, ARRAY_SIZE(exynos7870_mfcmscl_vclks));
|
|
samsung_register_vclk(ctx, exynos7870_g3d_vclks, ARRAY_SIZE(exynos7870_g3d_vclks));
|
|
samsung_register_vclk(ctx, exynos7870_peri_vclks, ARRAY_SIZE(exynos7870_peri_vclks));
|
|
samsung_register_vclk(ctx, exynos7870_fsys_vclks, ARRAY_SIZE(exynos7870_fsys_vclks));
|
|
samsung_register_vclk(ctx, exynos7870_dispaud_vclks, ARRAY_SIZE(exynos7870_dispaud_vclks));
|
|
samsung_register_vclk(ctx, exynos7870_isp_vclks, ARRAY_SIZE(exynos7870_isp_vclks));
|
|
samsung_register_vclk(ctx, exynos7870_mif_vclks, ARRAY_SIZE(exynos7870_mif_vclks));
|
|
samsung_register_vclk(ctx, exynos7870_dfs_vclks, ARRAY_SIZE(exynos7870_dfs_vclks));
|
|
|
|
samsung_clk_of_add_provider(np, ctx);
|
|
|
|
clk_register_fixed_factor(NULL, "pwm-clock", "gate_peri_sclk_pwm_motor", CLK_SET_RATE_PARENT, 1, 1);
|
|
|
|
pr_info("EXYNOS7870: Clock setup completed\n");
|
|
}
|
|
CLK_OF_DECLARE(exynos7870_clks, "samsung,exynos7870-clock", exynos7870_clk_init);
|