mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-07 00:38:05 -04:00
458 lines
14 KiB
C
458 lines
14 KiB
C
/*
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6* s2mpu06-irq.c - Interrupt controller support for S2MPU06
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*
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* Copyright (C) 2015 Samsung Electronics Co.Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/err.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/gpio.h>
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#include <linux/mfd/samsung/s2mpu06.h>
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#include <linux/mfd/samsung/s2mpu06-private.h>
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#include <sound/soc.h>
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#include <sound/cod9002x.h>
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static const u8 s2mpu06_mask_reg[] = {
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/* TODO: Need to check other INTMASK */
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[PMIC_INT1] = S2MPU06_PMIC_REG_INT1M,
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[PMIC_INT2] = S2MPU06_PMIC_REG_INT2M,
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[PMIC_INT3] = S2MPU06_PMIC_REG_INT3M,
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[CHG_INT1] = S2MPU06_CHG_REG_INT1M,
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[CHG_INT2] = S2MPU06_CHG_REG_INT2M,
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[CHG_INT3] = S2MPU06_CHG_REG_INT3M,
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[CHG_PMIC_INT] = S2MPU06_CHG_REG_PMIC_INTM,
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[FG_INT] = S2MPU06_FG_REG_IRQ_INTM,
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};
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static struct i2c_client *get_i2c(struct s2mpu06_dev *s2mpu06,
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enum s2mpu06_irq_source src)
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{
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switch (src) {
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case PMIC_INT1 ... PMIC_INT3:
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return s2mpu06->pmic;
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case CHG_INT1 ... CHG_PMIC_INT:
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return s2mpu06->charger;
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case FG_INT:
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return s2mpu06->fuelgauge;
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default:
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return ERR_PTR(-EINVAL);
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}
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}
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struct s2mpu06_irq_data {
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int mask;
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enum s2mpu06_irq_source group;
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};
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#define DECLARE_IRQ(idx, _group, _mask) \
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[(idx)] = { .group = (_group), .mask = (_mask) }
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static const struct s2mpu06_irq_data s2mpu06_irqs[] = {
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DECLARE_IRQ(S2MPU06_PMIC_IRQ_PWRONR_INT1, PMIC_INT1, 1 << 1),
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DECLARE_IRQ(S2MPU06_PMIC_IRQ_PWRONF_INT1, PMIC_INT1, 1 << 0),
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DECLARE_IRQ(S2MPU06_PMIC_IRQ_JIGONBF_INT1, PMIC_INT1, 1 << 2),
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DECLARE_IRQ(S2MPU06_PMIC_IRQ_JIGONBR_INT1, PMIC_INT1, 1 << 3),
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DECLARE_IRQ(S2MPU06_PMIC_IRQ_ACOKBF_INT1, PMIC_INT1, 1 << 4),
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DECLARE_IRQ(S2MPU06_PMIC_IRQ_ACOKBR_INT1, PMIC_INT1, 1 << 5),
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DECLARE_IRQ(S2MPU06_PMIC_IRQ_PWRON1S_INT1, PMIC_INT1, 1 << 6),
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DECLARE_IRQ(S2MPU06_PMIC_IRQ_MRB_INT1, PMIC_INT1, 1 << 7),
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DECLARE_IRQ(S2MPU06_PMIC_IRQ_RTC60S_INT2, PMIC_INT2, 1 << 0),
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DECLARE_IRQ(S2MPU06_PMIC_IRQ_RTCA1_INT2, PMIC_INT2, 1 << 1),
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DECLARE_IRQ(S2MPU06_PMIC_IRQ_RTCA0_INT2, PMIC_INT2, 1 << 2),
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DECLARE_IRQ(S2MPU06_PMIC_IRQ_SMPL_INT2, PMIC_INT2, 1 << 3),
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DECLARE_IRQ(S2MPU06_PMIC_IRQ_RTC1S_INT2, PMIC_INT2, 1 << 4),
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DECLARE_IRQ(S2MPU06_PMIC_IRQ_WTSR_INT2, PMIC_INT2, 1 << 5),
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DECLARE_IRQ(S2MPU06_PMIC_IRQ_WRSTB_INT2, PMIC_INT2, 1 << 7),
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DECLARE_IRQ(S2MPU06_PMIC_IRQ_120C_INT3, PMIC_INT3, 1 << 0),
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DECLARE_IRQ(S2MPU06_PMIC_IRQ_140C_INT3, PMIC_INT3, 1 << 1),
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DECLARE_IRQ(S2MPU06_PMIC_IRQ_TSD_INT3, PMIC_INT3, 1 << 2),
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DECLARE_IRQ(S2MPU06_PMIC_IRQ_120C_INT3, PMIC_INT3, 1 << 0),
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DECLARE_IRQ(S2MPU06_PMIC_IRQ_140C_INT3, PMIC_INT3, 1 << 1),
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DECLARE_IRQ(S2MPU06_PMIC_IRQ_TSD_INT3, PMIC_INT3, 1 << 2),
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DECLARE_IRQ(S2MPU06_CHG_IRQ_EOC_INT1, CHG_INT1, 1 << 1),
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DECLARE_IRQ(S2MPU06_CHG_IRQ_CINIR_INT1, CHG_INT1, 1 << 2),
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DECLARE_IRQ(S2MPU06_CHG_IRQ_BATP_INT1, CHG_INT1, 1 << 3),
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DECLARE_IRQ(S2MPU06_CHG_IRQ_BATLV_INT1, CHG_INT1, 1 << 4),
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DECLARE_IRQ(S2MPU06_CHG_IRQ_TOPOFF_INT1, CHG_INT1, 1 << 5),
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DECLARE_IRQ(S2MPU06_CHG_IRQ_CINOVP_INT1, CHG_INT1, 1 << 6),
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DECLARE_IRQ(S2MPU06_CHG_IRQ_CHGTSD_INT1, CHG_INT1, 1 << 7),
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DECLARE_IRQ(S2MPU06_CHG_IRQ_CHGVINVR_INT2, CHG_INT2, 1 << 0),
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DECLARE_IRQ(S2MPU06_CHG_IRQ_CHGTR_INT2, CHG_INT2, 1 << 1),
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DECLARE_IRQ(S2MPU06_CHG_IRQ_TMROUT_INT2, CHG_INT2, 1 << 2),
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DECLARE_IRQ(S2MPU06_CHG_IRQ_RECHG_INT2, CHG_INT2, 1 << 3),
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DECLARE_IRQ(S2MPU06_CHG_IRQ_CHGTERM_INT2, CHG_INT2, 1 << 4),
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DECLARE_IRQ(S2MPU06_CHG_IRQ_BATOVP_INT2, CHG_INT2, 1 << 5),
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DECLARE_IRQ(S2MPU06_CHG_IRQ_CHGVIN_INT2, CHG_INT2, 1 << 6),
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DECLARE_IRQ(S2MPU06_CHG_IRQ_CIN2BAT_INT2, CHG_INT2, 1 << 7),
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DECLARE_IRQ(S2MPU06_CHG_IRQ_CHGSTS_INT3, CHG_INT3, 1 << 1),
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DECLARE_IRQ(S2MPU06_CHG_IRQ_OTGILIM_INT3, CHG_INT3, 1 << 4),
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DECLARE_IRQ(S2MPU06_CHG_IRQ_BSTINLV_INT3, CHG_INT3, 1 << 5),
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DECLARE_IRQ(S2MPU06_CHG_IRQ_BSTILIM_INT3, CHG_INT3, 1 << 6),
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DECLARE_IRQ(S2MPU06_CHG_IRQ_VMIDOVP_INT3, CHG_INT3, 1 << 7),
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DECLARE_IRQ(S2MPU06_CHG_IRQ_WDT_PM, CHG_PMIC_INT, 1 << 0),
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DECLARE_IRQ(S2MPU06_CHG_IRQ_TSD_PM, CHG_PMIC_INT, 1 << 6),
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DECLARE_IRQ(S2MPU06_CHG_IRQ_VDDALV_PM, CHG_PMIC_INT, 1 << 7),
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DECLARE_IRQ(S2MPU06_FG_IRQ_VBAT_L_INT, FG_INT, 1 << 0),
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DECLARE_IRQ(S2MPU06_FG_IRQ_SOC_L_INT, FG_INT, 1 << 1),
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DECLARE_IRQ(S2MPU06_FG_IRQ_IDLE_ST_INT, FG_INT, 1 << 2),
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DECLARE_IRQ(S2MPU06_FG_IRQ_INIT_ST_INT, FG_INT, 1 << 3),
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};
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static const char * const s2mpu06_irqs_name[] = {
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/* PMIC */
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"S2MPU06_PMIC_IRQ_PWRONR_INT1",
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"S2MPU06_PMIC_IRQ_PWRONF_INT1",
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"S2MPU06_PMIC_IRQ_JIGONBF_INT1",
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"S2MPU06_PMIC_IRQ_JIGONBR_INT1",
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"S2MPU06_PMIC_IRQ_ACOKBF_INT1",
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"S2MPU06_PMIC_IRQ_ACOKBR_INT1",
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"S2MPU06_PMIC_IRQ_PWRON1S_INT1",
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"S2MPU06_PMIC_IRQ_MRB_INT1",
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"S2MPU06_PMIC_IRQ_RTC60S_INT2",
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"S2MPU06_PMIC_IRQ_RTCA1_INT2",
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"S2MPU06_PMIC_IRQ_RTCA0_INT2",
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"S2MPU06_PMIC_IRQ_SMPL_INT2",
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"S2MPU06_PMIC_IRQ_RTC1S_INT2",
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"S2MPU06_PMIC_IRQ_WTSR_INT2",
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"S2MPU06_PMIC_IRQ_WRSTB_INT2",
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"S2MPU06_PMIC_IRQ_120C_INT3",
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"S2MPU06_PMIC_IRQ_140C_INT3",
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"S2MPU06_PMIC_IRQ_TSD_INT3",
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/* Charger */
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"S2MPU06_CHG_IRQ_EOC_INT1",
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"S2MPU06_CHG_IRQ_CINIR_INT1",
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"S2MPU06_CHG_IRQ_BATP_INT1",
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"S2MPU06_CHG_IRQ_BATLV_INT1",
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"S2MPU06_CHG_IRQ_TOPOFF_INT1",
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"S2MPU06_CHG_IRQ_CINOVP_INT1",
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"S2MPU06_CHG_IRQ_CHGTSD_INT1",
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"S2MPU06_CHG_IRQ_CHGVINVR_INT2",
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"S2MPU06_CHG_IRQ_CHGTR_INT2",
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"S2MPU06_CHG_IRQ_TMROUT_INT2",
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"S2MPU06_CHG_IRQ_RECHG_INT2",
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"S2MPU06_CHG_IRQ_CHGTERM_INT2",
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"S2MPU06_CHG_IRQ_BATOVP_INT2",
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"S2MPU06_CHG_IRQ_CHGVIN_INT2",
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"S2MPU06_CHG_IRQ_CIN2BAT_INT2",
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"S2MPU06_CHG_IRQ_CHGSTS_INT3",
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"S2MPU06_CHG_IRQ_OTGILIM_INT3",
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"S2MPU06_CHG_IRQ_BSTINLV_INT3",
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"S2MPU06_CHG_IRQ_BSTILIM_INT3",
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"S2MPU06_CHG_IRQ_VMIDOVP_INT3",
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"S2MPU06_CHG_IRQ_WDT_PM",
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"S2MPU06_CHG_IRQ_TSD_PM",
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"S2MPU06_CHG_IRQ_VDDALV_PM",
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/* Fuelgauge */
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"S2MPU06_FG_IRQ_VBAT_L_INT",
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"S2MPU06_FG_IRQ_SOC_L_INT",
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"S2MPU06_FG_IRQ_IDLE_ST_INT",
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"S2MPU06_FG_IRQ_INIT_ST_INT",
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"S2MPU06_IRQ_NR"
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};
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static void s2mpu06_irq_lock(struct irq_data *data)
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{
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struct s2mpu06_dev *s2mpu06 = irq_get_chip_data(data->irq);
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mutex_lock(&s2mpu06->irqlock);
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}
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static void s2mpu06_irq_sync_unlock(struct irq_data *data)
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{
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struct s2mpu06_dev *s2mpu06 = irq_get_chip_data(data->irq);
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int i;
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for (i = 0; i < S2MPU06_IRQ_GROUP_NR; i++) {
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u8 mask_reg = s2mpu06_mask_reg[i];
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struct i2c_client *i2c = get_i2c(s2mpu06, i);
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if (mask_reg == S2MPU06_REG_INVALID ||
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IS_ERR_OR_NULL(i2c))
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continue;
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s2mpu06->irq_masks_cache[i] = s2mpu06->irq_masks_cur[i];
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s2mpu06_write_reg(i2c, s2mpu06_mask_reg[i],
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s2mpu06->irq_masks_cur[i]);
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}
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mutex_unlock(&s2mpu06->irqlock);
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}
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static const inline struct s2mpu06_irq_data *
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irq_to_s2mpu06_irq(struct s2mpu06_dev *s2mpu06, int irq)
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{
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return &s2mpu06_irqs[irq - s2mpu06->irq_base];
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}
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static void s2mpu06_irq_mask(struct irq_data *data)
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{
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struct s2mpu06_dev *s2mpu06 = irq_get_chip_data(data->irq);
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const struct s2mpu06_irq_data *irq_data =
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irq_to_s2mpu06_irq(s2mpu06, data->irq);
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if (irq_data->group >= S2MPU06_IRQ_GROUP_NR)
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return;
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s2mpu06->irq_masks_cur[irq_data->group] |= irq_data->mask;
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}
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static void s2mpu06_irq_unmask(struct irq_data *data)
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{
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struct s2mpu06_dev *s2mpu06 = irq_get_chip_data(data->irq);
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const struct s2mpu06_irq_data *irq_data =
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irq_to_s2mpu06_irq(s2mpu06, data->irq);
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if (irq_data->group >= S2MPU06_IRQ_GROUP_NR)
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return;
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s2mpu06->irq_masks_cur[irq_data->group] &= ~irq_data->mask;
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}
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static struct irq_chip s2mpu06_irq_chip = {
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.name = MFD_DEV_NAME,
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.irq_bus_lock = s2mpu06_irq_lock,
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.irq_bus_sync_unlock = s2mpu06_irq_sync_unlock,
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.irq_mask = s2mpu06_irq_mask,
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.irq_unmask = s2mpu06_irq_unmask,
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};
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static irqreturn_t s2mpu06_irq_thread(int irq, void *data)
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{
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struct s2mpu06_dev *s2mpu06 = data;
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u8 irq_reg[S2MPU06_IRQ_GROUP_NR] = {0};
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u8 irq_src;
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u8 irq1_codec, irq2_codec, irq3_codec, status1;
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int i, ret;
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pr_debug("%s: irq gpio pre-state(0x%02x)\n", __func__,
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gpio_get_value(s2mpu06->irq_gpio));
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ret = s2mpu06_read_reg(s2mpu06->i2c,
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S2MPU06_PMIC_REG_INTSRC, &irq_src);
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if (ret) {
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pr_err("%s:%s Failed to read interrupt source: %d\n",
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MFD_DEV_NAME, __func__, ret);
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return IRQ_NONE;
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}
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pr_info("%s: interrupt source(0x%02x)\n", __func__, irq_src);
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if (irq_src & S2MPU06_IRQSRC_PMIC) {
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/* PMIC_INT */
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ret = s2mpu06_bulk_read(s2mpu06->pmic, S2MPU06_PMIC_REG_INT1,
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S2MPU06_NUM_IRQ_PMIC_REGS, &irq_reg[PMIC_INT1]);
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if (ret) {
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pr_err("%s:%s Failed to read pmic interrupt: %d\n",
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MFD_DEV_NAME, __func__, ret);
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return IRQ_NONE;
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}
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pr_info("%s: pmic interrupt(0x%02x, 0x%02x, 0x%02x)\n",
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__func__, irq_reg[PMIC_INT1], irq_reg[PMIC_INT2],
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irq_reg[PMIC_INT3]);
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pr_info("%s: pmic interrupt mask(0x%02x, 0x%02x, 0x%02x)\n",
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__func__, s2mpu06->irq_masks_cur[PMIC_INT1],
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s2mpu06->irq_masks_cur[PMIC_INT2],
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s2mpu06->irq_masks_cur[PMIC_INT3]);
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}
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if(irq_src & S2MPU06_IRQSRC_CODEC) {
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if(s2mpu06->codec){
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pr_err("%s codec interrupt occur\n", __func__);
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ret = s2mpu06_read_codec_reg(s2mpu06->codec, 0x1, &irq1_codec);
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ret = s2mpu06_read_codec_reg(s2mpu06->codec, 0x2, &irq2_codec);
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ret = s2mpu06_read_codec_reg(s2mpu06->codec, 0x3, &irq3_codec);
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ret = s2mpu06_read_codec_reg(s2mpu06->codec, 0x7, &status1);
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cod9002x_call_notifier(irq1_codec, irq2_codec, irq3_codec, status1);
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}
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}
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if (irq_src & S2MPU06_IRQSRC_CHG) {
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/* CHG_INT */
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ret = s2mpu06_bulk_read(s2mpu06->charger, S2MPU06_CHG_REG_INT1,
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S2MPU06_NUM_IRQ_CHG_REGS, &irq_reg[CHG_INT1]);
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if (ret) {
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pr_err("%s:%s Failed to read charger interrupt: %d\n",
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MFD_DEV_NAME, __func__, ret);
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return IRQ_NONE;
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}
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pr_info("%s: charger interrupt(0x%02x, 0x%02x, 0x%02x, 0x%02x)\n",
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__func__, irq_reg[CHG_INT1], irq_reg[CHG_INT2], irq_reg[CHG_INT3],
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irq_reg[CHG_PMIC_INT]);
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pr_info("%s: charger interrupt mask(0x%02x, 0x%02x, 0x%02x, 0x%02x)\n",
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__func__, s2mpu06->irq_masks_cur[CHG_INT1],
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s2mpu06->irq_masks_cur[CHG_INT2], s2mpu06->irq_masks_cur[CHG_INT3],
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s2mpu06->irq_masks_cur[CHG_PMIC_INT]);
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}
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if (irq_src & S2MPU06_IRQSRC_FG) {
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/* FG_INT */
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ret = s2mpu06_read_reg(s2mpu06->fuelgauge, S2MPU06_FG_REG_IRQ_INT,
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&irq_reg[FG_INT]);
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if (ret) {
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pr_err("%s:%s Failed to read charger interrupt: %d\n",
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MFD_DEV_NAME, __func__, ret);
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return IRQ_NONE;
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}
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pr_info("%s: fuelgauge interrupt(0x%02x)\n", __func__,
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irq_reg[FG_INT]);
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pr_info("%s: fuelgauge interrupt mask(0x%02x)\n", __func__,
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s2mpu06->irq_masks_cur[FG_INT]);
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}
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/* Apply masking */
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for (i = 0; i < S2MPU06_IRQ_GROUP_NR; i++)
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irq_reg[i] &= ~s2mpu06->irq_masks_cur[i];
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/* Report */
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for (i = 0; i < S2MPU06_IRQ_NR; i++) {
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if (irq_reg[s2mpu06_irqs[i].group] & s2mpu06_irqs[i].mask) {
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pr_info("%s: interrupt caused by %s\n", __func__, s2mpu06_irqs_name[i]);
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handle_nested_irq(s2mpu06->irq_base + i);
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}
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}
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return IRQ_HANDLED;
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}
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int s2mpu06_irq_init(struct s2mpu06_dev *s2mpu06)
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{
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int i;
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int ret;
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u8 i2c_data;
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int cur_irq;
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if (!s2mpu06->irq_gpio) {
|
|
dev_warn(s2mpu06->dev, "No interrupt specified.\n");
|
|
s2mpu06->irq_base = 0;
|
|
return 0;
|
|
}
|
|
|
|
if (!s2mpu06->irq_base) {
|
|
dev_err(s2mpu06->dev, "No interrupt base specified.\n");
|
|
return 0;
|
|
}
|
|
|
|
mutex_init(&s2mpu06->irqlock);
|
|
|
|
s2mpu06->irq = gpio_to_irq(s2mpu06->irq_gpio);
|
|
pr_info("%s:%s irq=%d, irq->gpio=%d\n", MFD_DEV_NAME, __func__,
|
|
s2mpu06->irq, s2mpu06->irq_gpio);
|
|
|
|
ret = gpio_request(s2mpu06->irq_gpio, "if_pmic_irq");
|
|
if (ret) {
|
|
dev_err(s2mpu06->dev, "%s: failed requesting gpio %d\n",
|
|
__func__, s2mpu06->irq_gpio);
|
|
return ret;
|
|
}
|
|
gpio_direction_input(s2mpu06->irq_gpio);
|
|
gpio_free(s2mpu06->irq_gpio);
|
|
|
|
/* Mask individual interrupt sources */
|
|
for (i = 0; i < S2MPU06_IRQ_GROUP_NR; i++) {
|
|
struct i2c_client *i2c;
|
|
|
|
s2mpu06->irq_masks_cur[i] = 0xff;
|
|
s2mpu06->irq_masks_cache[i] = 0xff;
|
|
|
|
i2c = get_i2c(s2mpu06, i);
|
|
|
|
if (IS_ERR_OR_NULL(i2c))
|
|
continue;
|
|
if (s2mpu06_mask_reg[i] == S2MPU06_REG_INVALID)
|
|
continue;
|
|
|
|
s2mpu06_write_reg(i2c, s2mpu06_mask_reg[i], 0xff);
|
|
}
|
|
|
|
/* Register with genirq */
|
|
for (i = 0; i < S2MPU06_IRQ_NR; i++) {
|
|
cur_irq = i + s2mpu06->irq_base;
|
|
irq_set_chip_data(cur_irq, s2mpu06);
|
|
irq_set_chip_and_handler(cur_irq, &s2mpu06_irq_chip,
|
|
handle_level_irq);
|
|
irq_set_nested_thread(cur_irq, 1);
|
|
#ifdef CONFIG_ARM
|
|
set_irq_flags(cur_irq, IRQF_VALID);
|
|
#else
|
|
irq_set_noprobe(cur_irq);
|
|
#endif
|
|
}
|
|
|
|
s2mpu06_write_reg(s2mpu06->i2c, S2MPU06_PMIC_REG_INTSRC_MASK, 0xff);
|
|
/* Unmask s2mpu06 interrupt */
|
|
ret = s2mpu06_read_reg(s2mpu06->i2c, S2MPU06_PMIC_REG_INTSRC_MASK,
|
|
&i2c_data);
|
|
if (ret) {
|
|
pr_err("%s:%s fail to read intsrc mask reg\n",
|
|
MFD_DEV_NAME, __func__);
|
|
return ret;
|
|
}
|
|
|
|
if (s2mpu06->pmic_rev)
|
|
i2c_data &= ~(S2MPU06_IRQSRC_PMIC); /* Unmask pmic interrupt */
|
|
i2c_data &= ~(S2MPU06_IRQSRC_CHG); /* Unmask charger interrupt */
|
|
i2c_data &= ~(S2MPU06_IRQSRC_FG); /* Unmask fuelgauge interrupt */
|
|
|
|
if(s2mpu06->codec)
|
|
i2c_data &= ~(S2MPU06_IRQSRC_CODEC);
|
|
|
|
s2mpu06_write_reg(s2mpu06->i2c, S2MPU06_PMIC_REG_INTSRC_MASK,
|
|
i2c_data);
|
|
|
|
pr_info("%s:%s s2mpu06_PMIC_REG_INTSRC_MASK=0x%02x\n",
|
|
MFD_DEV_NAME, __func__, i2c_data);
|
|
|
|
ret = request_threaded_irq(s2mpu06->irq, NULL, s2mpu06_irq_thread,
|
|
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
|
|
"s2mpu06-irq", s2mpu06);
|
|
|
|
if (ret) {
|
|
dev_err(s2mpu06->dev, "Failed to request IRQ %d: %d\n",
|
|
s2mpu06->irq, ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
void s2mpu06_irq_exit(struct s2mpu06_dev *s2mpu06)
|
|
{
|
|
if (s2mpu06->irq)
|
|
free_irq(s2mpu06->irq, s2mpu06);
|
|
}
|