mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
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145 lines
3.2 KiB
C
145 lines
3.2 KiB
C
/****************************************************************************
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*
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* Copyright (c) 2014 - 2016 Samsung Electronics Co., Ltd. All rights reserved
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*
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****************************************************************************/
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/**
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* mx140 Infrastructure Configuration Structure.
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*
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* Used to pass configuration data from AP to R4 infrastructure
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* on Maxwell Subsystem startup.
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*
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* Notes:
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*
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* - All multi-octet integers shall be stored LittleEndian.
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*
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* - All location fields ("*_loc") are 32 bit octet offsets w.r.t. the R4
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* address map. They can therefore refer to DRAM memory or Mailbox registers.
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*
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* - "typedefs" are avoided to allow inclusion in linux source code.
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*/
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#ifndef MXCONF_H__
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#define MXCONF_H__
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/* Uses */
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/* Definitions */
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/**
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* Config structure magic number.
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*
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* The AP writes this value and the R4 checks it to trap endian mismatches.
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*/
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#define MXCONF_MAGIC 0x79828486
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/**
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* Config structure version
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*
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* The AP writes these values and the R4 checks them to trap config structure
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* mismatches.
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*/
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#define MXCONF_VERSION_MAJOR 0
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#define MXCONF_VERSION_MINOR 1
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/* Macros */
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#define GCC_PACKED __attribute__((packed))
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/* Types */
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/**
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* Maxwell Circular Packet Buffer Configuration.
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*/
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GCC_PACKED struct mxcbufconf {
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scsc_mifram_ref buffer_loc; /**< Location of allocated buffer in DRAM */
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uint32_t num_packets; /**< Total number of packets that can be stored in the buffer */
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uint32_t packet_size; /**< Size of each individual packet within the buffer */
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scsc_mifram_ref read_index_loc; /**< Location of 32bit read index in DRAM or Mailbox */
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scsc_mifram_ref write_index_loc; /**< Location of 32bit write index */
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};
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/**
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* Maxwell Management Simplex Stream Configuration
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*
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* A circular buffer plus a pair of R/W signaling bits.
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*/
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GCC_PACKED struct mxstreamconf {
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/** Circular Packet Buffer configuration */
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struct mxcbufconf buf_conf;
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/** Allocated MIF Interrupt Read Bit Index */
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uint8_t read_bit_idx;
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/** Allocated MIF Interrupt Write Bit Index */
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uint8_t write_bit_idx;
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};
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/**
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* Maxwell Management Transport Configuration
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*
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* A pair of simplex streams.
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*/
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GCC_PACKED struct mxtransconf {
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struct mxstreamconf to_ap_stream_conf;
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struct mxstreamconf from_ap_stream_conf;
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};
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/**
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* Maxwell Infrastructure Configuration Version
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*/
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GCC_PACKED struct mxconfversion {
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uint16_t major;
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uint16_t minor;
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};
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/**
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* Mxlog Event Buffer Configuration.
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*
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* A circular buffer. Size must be a multiple of 2.
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*/
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GCC_PACKED struct mxlogconf
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{
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struct mxstreamconf stream_conf;
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};
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/**
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* Maxwell Infrastructure Configuration
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*/
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GCC_PACKED struct mxconf {
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/**
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* Config Magic Number
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*
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* Always 1st field in config.
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*/
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uint32_t magic;
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/**
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* Config Version.
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*
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* Always second field in config.
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*/
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struct mxconfversion version;
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/**
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* MX Management Message Transport Configuration.
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*/
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struct mxtransconf mx_trans_conf;
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/**
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* MX Management GDB Message Transport Configuration.
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*/
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/* Cortex-R4 channel */
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struct mxtransconf mx_trans_conf_gdb_r4;
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/* Cortex-M4 channel */
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struct mxtransconf mx_trans_conf_gdb_m4;
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/**
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* Mxlog Event Buffer Configuration.
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*/
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struct mxlogconf mxlogconf;
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};
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#endif /* MXCONF_H__ */
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