mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 17:18:05 -04:00
141 lines
4 KiB
C
141 lines
4 KiB
C
/****************************************************************************
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*
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* Copyright (c) 2014 - 2016 Samsung Electronics Co., Ltd. All rights reserved
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*
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****************************************************************************/
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#ifndef __PCIE_MIF_H
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#define __PCIE_MIF_H
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#include <linux/pci.h>
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#include "scsc_mif_abs.h"
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#ifdef CONDOR
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#define FPGA_OFFSET 0xb8000000
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#else
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#define FPGA_OFFSET 0x80000000
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#endif
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#define SCSC_PCIE_MAGIC_VAL 0xdeadbeef
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#define SCSC_PCIE_GRST_OFFSET 0x48
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/* BAR0 Registers */
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#define SCSC_PCIE_NEWMSG 0x0
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#define SCSC_PCIE_SIGNATURE 0x4
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#define SCSC_PCIE_OFFSET 0x8
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#define SCSC_PCIE_RUNEN 0xC
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#define SCSC_PCIE_DEBUG 0x10
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#define SCSC_PCIE_AXIWCNT 0x14
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#define SCSC_PCIE_AXIRCNT 0x18
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#define SCSC_PCIE_AXIWADDR 0x1C
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#define SCSC_PCIE_AXIRADDR 0x20
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#define SCSC_PCIE_TBD 0x24
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#define SCSC_PCIE_AXICTRL 0x28
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#define SCSC_PCIE_AXIDATA 0x2C
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#define SCSC_PCIE_AXIRDBP 0x30
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#define SCSC_PCIE_IFAXIWCNT 0x34
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#define SCSC_PCIE_IFAXIRCNT 0x38
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#define SCSC_PCIE_IFAXIWADDR 0x3C
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#define SCSC_PCIE_IFAXIRADDR 0x40
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#define SCSC_PCIE_IFAXICTRL 0x44
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#define SCSC_PCIE_GRST 0x48
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#define SCSC_PCIE_AMBA2TRANSAXIWCNT 0x4C
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#define SCSC_PCIE_AMBA2TRANSAXIRCNT 0x50
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#define SCSC_PCIE_AMBA2TRANSAXIWADDR 0x54
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#define SCSC_PCIE_AMBA2TRANSAXIRADDR 0x58
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#define SCSC_PCIE_AMBA2TRANSAXICTR 0x5C
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#define SCSC_PCIE_TRANS2PCIEREADALIGNAXIWCNT 0x60
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#define SCSC_PCIE_TRANS2PCIEREADALIGNAXIRCNT 0x64
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#define SCSC_PCIE_TRANS2PCIEREADALIGNAXIWADDR 0x68
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#define SCSC_PCIE_TRANS2PCIEREADALIGNAXIRADDR 0x6C
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#define SCSC_PCIE_TRANS2PCIEREADALIGNAXICTRL 0x70
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#define SCSC_PCIE_READROUNDTRIPMIN 0x74
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#define SCSC_PCIE_READROUNDTRIPMAX 0x78
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#define SCSC_PCIE_READROUNDTRIPLAST 0x7C
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#define SCSC_PCIE_CPTAW0 0x80
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#define SCSC_PCIE_CPTAW1 0x84
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#define SCSC_PCIE_CPTAR0 0x88
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#define SCSC_PCIE_CPTAR1 0x8C
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#define SCSC_PCIE_CPTB0 0x90
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#define SCSC_PCIE_CPTW0 0x94
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#define SCSC_PCIE_CPTW1 0x98
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#define SCSC_PCIE_CPTW2 0x9C
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#define SCSC_PCIE_CPTR0 0xA0
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#define SCSC_PCIE_CPTR1 0xA4
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#define SCSC_PCIE_CPTR2 0xA8
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#define SCSC_PCIE_CPTRES 0xAC
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#define SCSC_PCIE_CPTAWDELAY 0xB0
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#define SCSC_PCIE_CPTARDELAY 0xB4
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#define SCSC_PCIE_CPTSRTADDR 0xB8
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#define SCSC_PCIE_CPTENDADDR 0xBC
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#define SCSC_PCIE_CPTSZLTHID 0xC0
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#define SCSC_PCIE_CPTPHSEL 0xC4
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#define SCSC_PCIE_CPTRUN 0xC8
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#define SCSC_PCIE_FPGAVER 0xCC
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struct scsc_bar0_reg {
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u32 NEWMSG;
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u32 SIGNATURE;
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u32 OFFSET;
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u32 RUNEN;
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u32 DEBUG;
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u32 AXIWCNT;
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u32 AXIRCNT;
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u32 AXIWADDR;
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u32 AXIRADDR;
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u32 TBD;
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u32 AXICTRL;
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u32 AXIDATA;
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u32 AXIRDBP;
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u32 IFAXIWCNT;
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u32 IFAXIRCNT;
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u32 IFAXIWADDR;
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u32 IFAXIRADDR;
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u32 IFAXICTRL;
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u32 GRST;
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u32 AMBA2TRANSAXIWCNT;
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u32 AMBA2TRANSAXIRCNT;
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u32 AMBA2TRANSAXIWADDR;
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u32 AMBA2TRANSAXIRADDR;
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u32 AMBA2TRANSAXICTR;
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u32 TRANS2PCIEREADALIGNAXIWCNT;
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u32 TRANS2PCIEREADALIGNAXIRCNT;
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u32 TRANS2PCIEREADALIGNAXIWADDR;
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u32 TRANS2PCIEREADALIGNAXIRADDR;
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u32 TRANS2PCIEREADALIGNAXICTRL;
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u32 READROUNDTRIPMIN;
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u32 READROUNDTRIPMAX;
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u32 READROUNDTRIPLAST;
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u32 CPTAW0;
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u32 CPTAW1;
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u32 CPTAR0;
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u32 CPTAR1;
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u32 CPTB0;
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u32 CPTW0;
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u32 CPTW1;
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u32 CPTW2;
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u32 CPTR0;
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u32 CPTR1;
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u32 CPTR2;
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u32 CPTRES;
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u32 CPTAWDELAY;
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u32 CPTARDELAY;
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u32 CPTSRTADDR;
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u32 CPTENDADDR;
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u32 CPTSZLTHID;
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u32 CPTPHSEL;
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u32 CPTRUN;
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u32 FPGAVER;
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};
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struct scsc_mif_abs *pcie_mif_create(struct pci_dev *pdev, const struct pci_device_id *id);
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void pcie_mif_destroy_pcie(struct pci_dev *pdev, struct scsc_mif_abs *interface);
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struct pci_dev *pcie_mif_get_pci_dev(struct scsc_mif_abs *interface);
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struct device *pcie_mif_get_dev(struct scsc_mif_abs *interface);
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struct pcie_mif;
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void pcie_mif_get_bar0(struct pcie_mif *pcie, struct scsc_bar0_reg *bar0);
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int pcie_mif_set_bar0_register(struct pcie_mif *pcie, unsigned int value, unsigned int offset);
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#endif
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