mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-07 08:48:05 -04:00
917 lines
26 KiB
C
917 lines
26 KiB
C
/*
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* Synopsys Designware PCIe host controller driver
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Author: Jingoo Han <jg1.han@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/hardirq.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/msi.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/pci.h>
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#include <linux/pci_regs.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include "pcie-designware.h"
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#include "pci-exynos.h"
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/* Synopsis specific PCIE configuration registers */
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#define PM_CAP_ID_OFFSET 0x40
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#define EXP_CAP_ID_OFFSET 0x70
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#define PCI_EXP_LNKCAP_MLW_X1 (0x1 << 4)
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#define PCI_EXP_LNKCAP_L1EL_64USEC (0x7 << 15)
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#define PCI_EXP_LNKCTL2_TLS 0xf
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#define PCI_EXP_LNKCTL2_TLS_2_5GB 0x1
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#define PCIE_LINK_L1SS_CONTROL 0x158
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#define PORT_LINK_TCOMMON_32US (0x20 << 8)
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#define PCIE_LINK_L1SS_CONTROL2 0x15C
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#define PORT_LINK_L1SS_ENABLE (0xf << 0)
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#define PORT_LINK_TPOWERON_130US (0x69 << 0)
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#define PORT_LINK_TPOWERON_3100US (0xfa << 0)
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#define PCIE_LINK_L1SS_OFF 0xb44
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#define PORT_LINK_L1SS_T_PCLKACK (0x3 << 6)
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#define PORT_LINK_L1SS_T_L1_2 (0x4 << 2)
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#define PORT_LINK_L1SS_T_POWER_OFF (0x2 << 0)
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#define PCIE_ACK_F_ASPM_CONTROL 0x70C
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#define PCIE_PORT_LINK_CONTROL 0x710
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#define PORT_LINK_MODE_MASK (0x3f << 16)
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#define PORT_LINK_MODE_1_LANES (0x1 << 16)
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#define PORT_LINK_MODE_2_LANES (0x3 << 16)
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#define PORT_LINK_MODE_4_LANES (0x7 << 16)
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#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
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#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
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#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
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#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
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#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
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#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
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#define PCIE_MSI_ADDR_LO 0x820
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#define PCIE_MSI_ADDR_HI 0x824
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#define PCIE_MSI_INTR0_ENABLE 0x828
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#define PCIE_MSI_INTR0_MASK 0x82C
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#define PCIE_MSI_INTR0_STATUS 0x830
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#define PCIE_MISC_CONTROL 0x8BC
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#define DBI_RO_WR_EN 0x1
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#define PCIE_ATU_VIEWPORT 0x900
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#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
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#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
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#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
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#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
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#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
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#define PCIE_ATU_CR1 0x904
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#define PCIE_ATU_TYPE_MEM (0x0 << 0)
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#define PCIE_ATU_TYPE_IO (0x2 << 0)
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#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
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#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
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#define PCIE_ATU_CR2 0x908
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#define PCIE_ATU_ENABLE (0x1 << 31)
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#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
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#define PCIE_ATU_LOWER_BASE 0x90C
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#define PCIE_ATU_UPPER_BASE 0x910
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#define PCIE_ATU_LIMIT 0x914
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#define PCIE_ATU_LOWER_TARGET 0x918
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#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
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#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
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#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
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#define PCIE_ATU_UPPER_TARGET 0x91C
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#define PCIE_AUX_CLK_FREQ_OFF 0xB40
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#define PCIE_AUX_CLK_FREQ_24MHZ 0x18
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#define PCIE_AUX_CLK_FREQ_26MHZ 0x1A
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#define PCIE_L1_SUBSTATES_OFF 0xB44
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static struct pci_ops dw_pcie_ops;
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static unsigned long global_io_offset;
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int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
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{
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*val = readl(addr);
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if (size == 1)
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*val = (*val >> (8 * (where & 3))) & 0xff;
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else if (size == 2)
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*val = (*val >> (8 * (where & 3))) & 0xffff;
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else if (size != 4)
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return PCIBIOS_BAD_REGISTER_NUMBER;
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return PCIBIOS_SUCCESSFUL;
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}
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int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)
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{
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if (size == 4)
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writel(val, addr);
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else if (size == 2)
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writew(val, addr + (where & 2));
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else if (size == 1)
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writeb(val, addr + (where & 3));
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else
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return PCIBIOS_BAD_REGISTER_NUMBER;
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return PCIBIOS_SUCCESSFUL;
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}
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static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
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u32 *val)
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{
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int ret;
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if (pp->ops->rd_own_conf)
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ret = pp->ops->rd_own_conf(pp, where, size, val);
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else
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ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
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size, val);
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return ret;
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}
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static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
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u32 val)
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{
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int ret;
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if (pp->ops->wr_own_conf)
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ret = pp->ops->wr_own_conf(pp, where, size, val);
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else
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ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,
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size, val);
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return ret;
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}
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static struct irq_chip dw_msi_irq_chip = {
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.name = "PCI-MSI",
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.irq_enable = unmask_msi_irq,
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.irq_disable = mask_msi_irq,
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.irq_mask = mask_msi_irq,
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.irq_unmask = unmask_msi_irq,
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};
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/* MSI int handler */
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irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
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{
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unsigned long val;
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unsigned long flags;
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int i, pos, irq;
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irqreturn_t ret = IRQ_NONE;
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for (i = 0; i < MAX_MSI_CTRLS; i++) {
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spin_lock_irqsave(&pp->conf_lock, flags);
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dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
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(u32 *)&val);
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spin_unlock_irqrestore(&pp->conf_lock, flags);
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if (val) {
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ret = IRQ_HANDLED;
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pos = 0;
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while ((pos = find_next_bit(&val, 32, pos)) != 32) {
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irq = irq_find_mapping(pp->irq_domain,
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i * 32 + pos);
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spin_lock_irqsave(&pp->conf_lock, flags);
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dw_pcie_wr_own_conf(pp,
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PCIE_MSI_INTR0_STATUS + i * 12,
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4, 1 << pos);
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spin_unlock_irqrestore(&pp->conf_lock, flags);
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generic_handle_irq(irq);
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pos++;
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}
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}
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}
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return ret;
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}
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void dw_pcie_msi_init(struct pcie_port *pp)
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{
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unsigned long flags;
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pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
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/* program the msi_data */
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spin_lock_irqsave(&pp->conf_lock, flags);
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dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
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virt_to_phys((void *)pp->msi_data));
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dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
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spin_unlock_irqrestore(&pp->conf_lock, flags);
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}
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static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
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{
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unsigned int res, bit, val;
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unsigned long flags;
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res = (irq / 32) * 12;
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bit = irq % 32;
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spin_lock_irqsave(&pp->conf_lock, flags);
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dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
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val &= ~(1 << bit);
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dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
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spin_unlock_irqrestore(&pp->conf_lock, flags);
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}
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static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
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unsigned int nvec, unsigned int pos)
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{
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unsigned int i;
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for (i = 0; i < nvec; i++) {
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irq_set_msi_desc_off(irq_base, i, NULL);
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/* Disable corresponding interrupt on MSI controller */
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if (pp->ops->msi_clear_irq)
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pp->ops->msi_clear_irq(pp, pos + i);
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else
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dw_pcie_msi_clear_irq(pp, pos + i);
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}
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bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec));
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}
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static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
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{
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unsigned int res, bit, val;
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unsigned long flags;
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res = (irq / 32) * 12;
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bit = irq % 32;
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spin_lock_irqsave(&pp->conf_lock, flags);
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dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
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val |= 1 << bit;
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dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
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spin_unlock_irqrestore(&pp->conf_lock, flags);
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}
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static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
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{
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int irq, pos0, i;
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struct pcie_port *pp = desc->dev->bus->sysdata;
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pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
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order_base_2(no_irqs));
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if (pos0 < 0)
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goto no_valid_irq;
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irq = irq_find_mapping(pp->irq_domain, pos0);
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if (!irq)
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goto no_valid_irq;
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/*
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* irq_create_mapping (called from dw_pcie_host_init) pre-allocates
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* descs so there is no need to allocate descs here. We can therefore
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* assume that if irq_find_mapping above returns non-zero, then the
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* descs are also successfully allocated.
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*/
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for (i = 0; i < no_irqs; i++) {
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if (irq_set_msi_desc_off(irq, i, desc) != 0) {
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clear_irq_range(pp, irq, i, pos0);
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goto no_valid_irq;
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}
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/*Enable corresponding interrupt in MSI interrupt controller */
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if (pp->ops->msi_set_irq)
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pp->ops->msi_set_irq(pp, pos0 + i);
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else
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dw_pcie_msi_set_irq(pp, pos0 + i);
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}
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*pos = pos0;
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return irq;
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no_valid_irq:
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*pos = pos0;
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return -ENOSPC;
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}
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static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
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struct msi_desc *desc)
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{
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int irq, pos;
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struct msi_msg msg;
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struct pcie_port *pp = pdev->bus->sysdata;
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if (desc->msi_attrib.is_msix)
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return -EINVAL;
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irq = assign_irq(1, desc, &pos);
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if (irq < 0)
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return irq;
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if (pp->ops->get_msi_addr)
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msg.address_lo = pp->ops->get_msi_addr(pp);
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else
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msg.address_lo = virt_to_phys((void *)pp->msi_data);
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msg.address_hi = 0x0;
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if (pp->ops->get_msi_data)
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msg.data = pp->ops->get_msi_data(pp, pos);
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else
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msg.data = pos;
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#ifdef CONFIG_PCI_MSI
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write_msi_msg(irq, &msg);
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#endif
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return 0;
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}
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static void dw_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
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{
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struct irq_data *data = irq_get_irq_data(irq);
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struct msi_desc *msi = irq_data_get_msi(data);
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struct pcie_port *pp = msi->dev->bus->sysdata;
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clear_irq_range(pp, irq, 1, data->hwirq);
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}
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static struct msi_chip dw_pcie_msi_chip = {
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.setup_irq = dw_msi_setup_irq,
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.teardown_irq = dw_msi_teardown_irq,
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};
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int dw_pcie_link_up(struct pcie_port *pp)
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{
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if (pp == NULL)
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return 0;
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if (pp->ops == NULL)
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return 0;
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if (pp->ops->link_up)
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return pp->ops->link_up(pp);
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else
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return 0;
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}
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void dw_pcie_config_l1ss(struct pcie_port *pp)
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{
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u32 val;
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void __iomem *ep_dbi_base = pp->va_cfg0_base;
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u32 exp_cap_off = EXP_CAP_ID_OFFSET;
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/* Enable L1SS on Root Complex */
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val = readl(ep_dbi_base + 0xbc);
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val &= ~0x3;
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val |= 0x142;
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writel(val, ep_dbi_base + 0xBC);
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val = readl(ep_dbi_base + 0x248);
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writel(val | 0xa0f, ep_dbi_base + 0x248);
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writel(PORT_LINK_TPOWERON_130US, ep_dbi_base + 0x24C);
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writel(0x10031003, ep_dbi_base + 0x1B4);
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val = readl(ep_dbi_base + 0xD4);
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writel(val | (1 << 10), ep_dbi_base + 0xD4);
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dw_pcie_rd_own_conf(pp, PCIE_LINK_L1SS_CONTROL, 4, &val);
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val |= PORT_LINK_TCOMMON_32US | PORT_LINK_L1SS_ENABLE;
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dw_pcie_wr_own_conf(pp, PCIE_LINK_L1SS_CONTROL, 4, val);
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dw_pcie_wr_own_conf(pp, PCIE_LINK_L1SS_CONTROL2, 4, PORT_LINK_TPOWERON_130US);
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val = PORT_LINK_L1SS_T_PCLKACK | PORT_LINK_L1SS_T_L1_2 |
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PORT_LINK_L1SS_T_POWER_OFF;
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dw_pcie_wr_own_conf(pp, PCIE_LINK_L1SS_OFF, 4, val);
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dw_pcie_rd_own_conf(pp, exp_cap_off + PCI_EXP_LNKCTL, 4, &val);
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val &= ~PCI_EXP_LNKCTL_ASPMC;
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val |= PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKCTL_ASPM_L1;
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dw_pcie_wr_own_conf(pp, exp_cap_off + PCI_EXP_LNKCTL, 4, val);
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dw_pcie_wr_own_conf(pp, exp_cap_off + PCI_EXP_DEVCTL2, 4, PCI_EXP_DEVCTL2_LTR_EN);
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}
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static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
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irq_set_chip_data(irq, domain->host_data);
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set_irq_flags(irq, IRQF_VALID);
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return 0;
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}
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static const struct irq_domain_ops msi_domain_ops = {
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.map = dw_pcie_msi_map,
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};
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int dw_pcie_host_init(struct pcie_port *pp)
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{
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struct device_node *np = pp->dev->of_node;
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struct platform_device *pdev = to_platform_device(pp->dev);
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struct of_pci_range range;
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struct of_pci_range_parser parser;
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struct resource *cfg_res;
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u32 na, ns;
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const __be32 *addrp;
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int i, index, ret;
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/* Find the address cell size and the number of cells in order to get
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* the untranslated address.
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*/
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of_property_read_u32(np, "#address-cells", &na);
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ns = of_n_size_cells(np);
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cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
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if (cfg_res) {
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pp->cfg0_size = resource_size(cfg_res)/2;
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pp->cfg1_size = resource_size(cfg_res)/2;
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pp->cfg0_base = cfg_res->start;
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pp->cfg1_base = cfg_res->start + pp->cfg0_size;
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/* Find the untranslated configuration space address */
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index = of_property_match_string(np, "reg-names", "config");
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addrp = of_get_address(np, index, NULL, NULL);
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pp->cfg0_mod_base = of_read_number(addrp, of_n_addr_cells(np));
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pp->cfg1_mod_base = pp->cfg0_mod_base + pp->cfg0_size;
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} else {
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dev_err(pp->dev, "missing *config* reg space\n");
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}
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if (of_pci_range_parser_init(&parser, np)) {
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dev_err(pp->dev, "missing ranges property\n");
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return -EINVAL;
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}
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/* Get the I/O and memory ranges from DT */
|
|
for_each_of_pci_range(&parser, &range) {
|
|
unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
|
|
if (restype == IORESOURCE_IO) {
|
|
of_pci_range_to_resource(&range, np, &pp->io);
|
|
pp->io.name = "I/O";
|
|
pp->io.start = max_t(resource_size_t,
|
|
PCIBIOS_MIN_IO,
|
|
range.pci_addr + global_io_offset);
|
|
pp->io.end = min_t(resource_size_t,
|
|
IO_SPACE_LIMIT,
|
|
range.pci_addr + range.size
|
|
+ global_io_offset - 1);
|
|
pp->io_size = resource_size(&pp->io);
|
|
pp->io_bus_addr = range.pci_addr;
|
|
pp->io_base = range.cpu_addr;
|
|
|
|
/* Find the untranslated IO space address */
|
|
pp->io_mod_base = of_read_number(parser.range -
|
|
parser.np + na,
|
|
of_n_addr_cells(np));
|
|
}
|
|
if (restype == IORESOURCE_MEM) {
|
|
of_pci_range_to_resource(&range, np, &pp->mem);
|
|
pp->mem.name = "MEM";
|
|
pp->mem_size = resource_size(&pp->mem);
|
|
pp->mem_bus_addr = range.pci_addr;
|
|
|
|
/* Find the untranslated MEM space address */
|
|
pp->mem_mod_base = of_read_number(parser.range -
|
|
parser.np + na,
|
|
of_n_addr_cells(np));
|
|
}
|
|
if (restype == 0) {
|
|
of_pci_range_to_resource(&range, np, &pp->cfg);
|
|
pp->cfg0_size = resource_size(&pp->cfg)/2;
|
|
pp->cfg1_size = resource_size(&pp->cfg)/2;
|
|
pp->cfg0_base = pp->cfg.start;
|
|
pp->cfg1_base = pp->cfg.start + pp->cfg0_size;
|
|
|
|
/* Find the untranslated configuration space address */
|
|
pp->cfg0_mod_base = of_read_number(parser.range -
|
|
parser.np + na, ns);
|
|
pp->cfg1_mod_base = pp->cfg0_mod_base +
|
|
pp->cfg0_size;
|
|
}
|
|
}
|
|
|
|
ret = of_pci_parse_bus_range(np, &pp->busn);
|
|
if (ret < 0) {
|
|
pp->busn.name = np->name;
|
|
pp->busn.start = 0;
|
|
pp->busn.end = 0xff;
|
|
pp->busn.flags = IORESOURCE_BUS;
|
|
dev_dbg(pp->dev, "failed to parse bus-range property: %d, using default %pR\n",
|
|
ret, &pp->busn);
|
|
}
|
|
|
|
if (!pp->dbi_base) {
|
|
pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
|
|
resource_size(&pp->cfg));
|
|
if (!pp->dbi_base) {
|
|
dev_err(pp->dev, "error with ioremap\n");
|
|
return -ENOMEM;
|
|
}
|
|
}
|
|
|
|
pp->mem_base = pp->mem.start;
|
|
|
|
if (!pp->va_cfg0_base) {
|
|
pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
|
|
pp->cfg0_size);
|
|
if (!pp->va_cfg0_base) {
|
|
dev_err(pp->dev, "error with ioremap in function\n");
|
|
return -ENOMEM;
|
|
}
|
|
}
|
|
|
|
if (!pp->va_cfg1_base) {
|
|
pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
|
|
pp->cfg1_size);
|
|
if (!pp->va_cfg1_base) {
|
|
dev_err(pp->dev, "error with ioremap\n");
|
|
return -ENOMEM;
|
|
}
|
|
}
|
|
|
|
if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
|
|
dev_err(pp->dev, "Failed to parse the number of lanes\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
|
if (!pp->ops->msi_host_init) {
|
|
pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
|
|
MAX_MSI_IRQS, &msi_domain_ops,
|
|
&dw_pcie_msi_chip);
|
|
if (!pp->irq_domain) {
|
|
dev_err(pp->dev, "irq domain init failed\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
for (i = 0; i < MAX_MSI_IRQS; i++)
|
|
irq_create_mapping(pp->irq_domain, i);
|
|
} else {
|
|
ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int dw_pcie_scan(struct pcie_port *pp)
|
|
{
|
|
struct pci_bus *bus;
|
|
LIST_HEAD(res);
|
|
struct device_node *np = pp->dev->of_node;
|
|
u32 val;
|
|
int ret;
|
|
|
|
dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
|
|
|
|
/* program correct class for RC */
|
|
dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
|
|
|
|
dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
|
|
val |= PORT_LOGIC_SPEED_CHANGE;
|
|
dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
|
|
|
|
#ifdef CONFIG_ARM
|
|
/*
|
|
* FIXME: we should really be able to use
|
|
* of_pci_get_host_bridge_resources on arm32 as well,
|
|
* but the conversion needs some more testing
|
|
*/
|
|
if (global_io_offset < SZ_1M && pp->io_size > 0) {
|
|
pci_ioremap_io(global_io_offset, pp->io_base);
|
|
global_io_offset += SZ_64K;
|
|
pci_add_resource_offset(&res, &pp->io,
|
|
global_io_offset - pp->io_bus_addr);
|
|
}
|
|
pci_add_resource_offset(&res, &pp->mem,
|
|
pp->mem.start - pp->mem_bus_addr);
|
|
pci_add_resource(&res, &pp->busn);
|
|
#else
|
|
ret = of_pci_get_host_bridge_resources(np, 0, 0xff, &res, &pp->io_base);
|
|
if (ret)
|
|
return ret;
|
|
#endif
|
|
|
|
bus = pci_create_root_bus(pp->dev, pp->root_bus_nr, &dw_pcie_ops,
|
|
pp, &res);
|
|
if (!bus)
|
|
return -ENOMEM;
|
|
|
|
#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
|
|
bus->msi = container_of(&pp->irq_domain, struct msi_controller, domain);
|
|
#else
|
|
bus->msi = &dw_pcie_msi_chip;
|
|
#endif
|
|
|
|
pci_scan_child_bus(bus);
|
|
if (pp->ops->scan_bus)
|
|
pp->ops->scan_bus(pp);
|
|
|
|
#ifdef CONFIG_ARM
|
|
/* support old dtbs that incorrectly describe IRQs */
|
|
pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
|
|
#endif
|
|
|
|
pci_assign_unassigned_bus_resources(bus);
|
|
pci_bus_add_devices(bus);
|
|
|
|
dw_pcie_config_l1ss(pp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
|
|
{
|
|
/* Program viewport 0 : OUTBOUND : CFG0 */
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_VIEWPORT, 4,
|
|
PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0);
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_LOWER_BASE, 4, pp->cfg0_mod_base);
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_UPPER_BASE, 4, (pp->cfg0_mod_base >> 32));
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_LIMIT, 4, pp->cfg0_mod_base + pp->cfg0_size - 1);
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_LOWER_TARGET, 4, busdev);
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_UPPER_TARGET, 4, 0);
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_CR1, 4, PCIE_ATU_TYPE_CFG0);
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_CR2, 4, PCIE_ATU_ENABLE);
|
|
}
|
|
|
|
static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
|
|
{
|
|
/* Program viewport 1 : OUTBOUND : CFG1 */
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_VIEWPORT, 4,
|
|
PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX2);
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_CR1, 4, PCIE_ATU_TYPE_CFG1);
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_LOWER_BASE, 4, pp->cfg1_mod_base);
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_UPPER_BASE, 4, (pp->cfg1_mod_base >> 32));
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_LIMIT, 4, pp->cfg1_mod_base + pp->cfg1_size - 1);
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_LOWER_TARGET, 4, busdev);
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_UPPER_TARGET, 4, 0);
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_CR2, 4, PCIE_ATU_ENABLE);
|
|
}
|
|
|
|
void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
|
|
{
|
|
/* Program viewport 0 : OUTBOUND : MEM */
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_VIEWPORT, 4,
|
|
PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1);
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_CR1, 4, PCIE_ATU_TYPE_MEM);
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_LOWER_BASE, 4, pp->mem_mod_base);
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_UPPER_BASE, 4, (pp->mem_mod_base >> 32));
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_LIMIT, 4, pp->mem_mod_base + pp->mem_size - 1);
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_LOWER_TARGET, 4, pp->mem_bus_addr);
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_UPPER_TARGET, 4, upper_32_bits(pp->mem_bus_addr));
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_CR2, 4, PCIE_ATU_ENABLE);
|
|
}
|
|
|
|
static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
|
|
{
|
|
/* Program viewport 1 : OUTBOUND : IO */
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_VIEWPORT, 4,
|
|
PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX2);
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_CR1, 4, PCIE_ATU_TYPE_IO);
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_LOWER_BASE, 4, pp->io_mod_base);
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_UPPER_BASE, 4, (pp->io_mod_base >> 32));
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_LIMIT, 4, pp->io_mod_base + pp->io_size - 1);
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_LOWER_TARGET, 4, pp->io_bus_addr);
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_UPPER_TARGET, 4, upper_32_bits(pp->io_bus_addr));
|
|
dw_pcie_wr_own_conf(pp, PCIE_ATU_CR2, 4, PCIE_ATU_ENABLE);
|
|
}
|
|
|
|
static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
|
|
u32 devfn, int where, int size, u32 *val)
|
|
{
|
|
int ret = PCIBIOS_SUCCESSFUL;
|
|
u32 address, busdev;
|
|
|
|
busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
|
|
PCIE_ATU_FUNC(PCI_FUNC(devfn));
|
|
address = where & ~0x3;
|
|
|
|
if (bus->parent->number == pp->root_bus_nr) {
|
|
dw_pcie_prog_viewport_cfg0(pp, busdev);
|
|
ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
|
|
val);
|
|
dw_pcie_prog_viewport_mem_outbound(pp);
|
|
} else {
|
|
dw_pcie_prog_viewport_cfg1(pp, busdev);
|
|
ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
|
|
val);
|
|
dw_pcie_prog_viewport_io_outbound(pp);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
|
|
u32 devfn, int where, int size, u32 val)
|
|
{
|
|
int ret = PCIBIOS_SUCCESSFUL;
|
|
u32 address, busdev;
|
|
|
|
busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
|
|
PCIE_ATU_FUNC(PCI_FUNC(devfn));
|
|
address = where & ~0x3;
|
|
|
|
if (bus->parent->number == pp->root_bus_nr) {
|
|
dw_pcie_prog_viewport_cfg0(pp, busdev);
|
|
ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
|
|
val);
|
|
dw_pcie_prog_viewport_mem_outbound(pp);
|
|
} else {
|
|
dw_pcie_prog_viewport_cfg1(pp, busdev);
|
|
ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
|
|
val);
|
|
dw_pcie_prog_viewport_io_outbound(pp);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dw_pcie_valid_config(struct pcie_port *pp,
|
|
struct pci_bus *bus, int dev)
|
|
{
|
|
struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
|
|
|
|
if (exynos_pcie->state != STATE_LINK_UP)
|
|
return 0;
|
|
|
|
/* If there is no link, then there is no device */
|
|
if (bus->number != pp->root_bus_nr) {
|
|
if (!dw_pcie_link_up(pp))
|
|
return 0;
|
|
}
|
|
|
|
/* access only one slot on each root port */
|
|
if (bus->number == pp->root_bus_nr && dev > 0)
|
|
return 0;
|
|
|
|
/*
|
|
* do not read more than one device on the bus directly attached
|
|
* to RC's (Virtual Bridge's) DS side.
|
|
*/
|
|
if (bus->primary == pp->root_bus_nr && dev > 0)
|
|
return 0;
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
|
|
int size, u32 *val)
|
|
{
|
|
struct pcie_port *pp = bus->sysdata;
|
|
unsigned long flags;
|
|
int ret;
|
|
|
|
spin_lock_irqsave(&pp->conf_lock, flags);
|
|
if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
|
|
spin_unlock_irqrestore(&pp->conf_lock, flags);
|
|
*val = 0xffffffff;
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
}
|
|
|
|
if (bus->number != pp->root_bus_nr)
|
|
if (pp->ops->rd_other_conf)
|
|
ret = pp->ops->rd_other_conf(pp, bus, devfn,
|
|
where, size, val);
|
|
else
|
|
ret = dw_pcie_rd_other_conf(pp, bus, devfn,
|
|
where, size, val);
|
|
else
|
|
ret = dw_pcie_rd_own_conf(pp, where, size, val);
|
|
spin_unlock_irqrestore(&pp->conf_lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
|
|
int where, int size, u32 val)
|
|
{
|
|
struct pcie_port *pp = bus->sysdata;
|
|
unsigned long flags;
|
|
int ret;
|
|
|
|
spin_lock_irqsave(&pp->conf_lock, flags);
|
|
if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
|
|
spin_unlock_irqrestore(&pp->conf_lock, flags);
|
|
return PCIBIOS_DEVICE_NOT_FOUND;
|
|
}
|
|
|
|
if (bus->number != pp->root_bus_nr)
|
|
if (pp->ops->wr_other_conf)
|
|
ret = pp->ops->wr_other_conf(pp, bus, devfn,
|
|
where, size, val);
|
|
else
|
|
ret = dw_pcie_wr_other_conf(pp, bus, devfn,
|
|
where, size, val);
|
|
else
|
|
ret = dw_pcie_wr_own_conf(pp, where, size, val);
|
|
spin_unlock_irqrestore(&pp->conf_lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct pci_ops dw_pcie_ops = {
|
|
.read = dw_pcie_rd_conf,
|
|
.write = dw_pcie_wr_conf,
|
|
};
|
|
|
|
void dw_pcie_setup_rc(struct pcie_port *pp)
|
|
{
|
|
struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
|
|
u32 val;
|
|
u32 membase;
|
|
u32 memlimit;
|
|
u32 exp_cap_off = EXP_CAP_ID_OFFSET;
|
|
u32 pm_cap_off = PM_CAP_ID_OFFSET;
|
|
|
|
/* enable writing to DBI read-only registers */
|
|
dw_pcie_wr_own_conf(pp, PCIE_MISC_CONTROL, 4, DBI_RO_WR_EN);
|
|
|
|
/* change vendor ID and device ID for PCIe */
|
|
dw_pcie_wr_own_conf(pp, PCI_VENDOR_ID, 2, PCI_VENDOR_ID_SAMSUNG);
|
|
dw_pcie_wr_own_conf(pp, PCI_DEVICE_ID, 2,
|
|
PCI_DEVICE_ID_EXYNOS + exynos_pcie->ch_num);
|
|
|
|
/* set the number of lanes */
|
|
dw_pcie_rd_own_conf(pp, PCIE_PORT_LINK_CONTROL, 4, &val);
|
|
val &= ~PORT_LINK_MODE_MASK;
|
|
switch (pp->lanes) {
|
|
case 1:
|
|
val |= PORT_LINK_MODE_1_LANES;
|
|
break;
|
|
case 2:
|
|
val |= PORT_LINK_MODE_2_LANES;
|
|
break;
|
|
case 4:
|
|
val |= PORT_LINK_MODE_4_LANES;
|
|
break;
|
|
}
|
|
dw_pcie_wr_own_conf(pp, PCIE_PORT_LINK_CONTROL, 4, val);
|
|
|
|
/* set link width speed control register */
|
|
dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
|
|
val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
|
|
switch (pp->lanes) {
|
|
case 1:
|
|
val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
|
|
break;
|
|
case 2:
|
|
val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
|
|
break;
|
|
case 4:
|
|
val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
|
|
break;
|
|
}
|
|
dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
|
|
|
|
/* set max link width & speed : Gen2, Lane1 */
|
|
dw_pcie_rd_own_conf(pp, exp_cap_off + PCI_EXP_LNKCAP, 4, &val);
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val &= ~(PCI_EXP_LNKCAP_L1EL|PCI_EXP_LNKCAP_MLW|PCI_EXP_LNKCAP_SLS);
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val |= PCI_EXP_LNKCAP_L1EL_64USEC|PCI_EXP_LNKCAP_MLW_X1|PCI_EXP_LNKCAP_SLS_5_0GB;
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dw_pcie_wr_own_conf(pp, exp_cap_off + PCI_EXP_LNKCAP, 4, val);
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|
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/* set auxiliary clock frequency: 26MHz */
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dw_pcie_wr_own_conf(pp, PCIE_AUX_CLK_FREQ_OFF, 4, PCIE_AUX_CLK_FREQ_26MHZ);
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|
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/* set duration of L1.2 & L1.2.Entry */
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dw_pcie_wr_own_conf(pp, PCIE_L1_SUBSTATES_OFF, 4, 0xD2);
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|
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/* clear power management control and status register */
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dw_pcie_wr_own_conf(pp, pm_cap_off + PCI_PM_CTRL, 4, 0x0);
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|
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/* setup RC BARs */
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dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0x00000004);
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dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_1, 4, 0x00000000);
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|
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/* setup bus numbers */
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dw_pcie_rd_own_conf(pp, PCI_PRIMARY_BUS, 4, &val);
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val &= 0xff000000;
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val |= 0x00010100;
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dw_pcie_wr_own_conf(pp, PCI_PRIMARY_BUS, 4, val);
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|
|
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/* setup memory base, memory limit */
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membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
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memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000;
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val = memlimit | membase;
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dw_pcie_wr_own_conf(pp, PCI_MEMORY_BASE, 4, val);
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|
|
|
/* setup command register */
|
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dw_pcie_rd_own_conf(pp, PCI_COMMAND, 4, &val);
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val &= 0xffff0000;
|
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val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
|
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PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
|
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dw_pcie_wr_own_conf(pp, PCI_COMMAND, 4, val);
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|
|
|
/* initiate link retraining */
|
|
dw_pcie_rd_own_conf(pp, exp_cap_off + PCI_EXP_LNKCTL, 4, &val);
|
|
val |= PCI_EXP_LNKCTL_RL;
|
|
dw_pcie_wr_own_conf(pp, exp_cap_off + PCI_EXP_LNKCTL, 4, val);
|
|
|
|
/* set target speed to GEN1 only */
|
|
dw_pcie_rd_own_conf(pp, exp_cap_off + PCI_EXP_LNKCTL2, 4, &val);
|
|
val &= ~PCI_EXP_LNKCTL2_TLS;
|
|
val |= PCI_EXP_LNKCTL2_TLS_2_5GB;
|
|
dw_pcie_wr_own_conf(pp, exp_cap_off + PCI_EXP_LNKCTL2, 4, val);
|
|
}
|
|
|
|
MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
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|
MODULE_DESCRIPTION("Designware PCIe host controller driver");
|
|
MODULE_LICENSE("GPL v2");
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