mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 01:08:03 -04:00
247 lines
7.1 KiB
C
247 lines
7.1 KiB
C
/*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* Exynos - Support SoC specific Reboot
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* Author: Hosung Kim <hosung0.kim@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/reboot.h>
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#include <linux/soc/samsung/exynos-soc.h>
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extern void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
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static void __iomem *exynos_pmu_base = NULL;
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static const char * const mngs_cores[] = {
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"arm,mongoose",
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NULL,
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};
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static bool is_mngs_cpu(struct device_node *cn)
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{
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const char * const *lc;
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for (lc = mngs_cores; *lc; lc++)
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if (of_device_is_compatible(cn, *lc))
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return true;
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return false;
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}
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int soc_has_mongoose(void)
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{
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struct device_node *cn = NULL;
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u32 mngs_cpu_cnt = 0;
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/* find arm,mongoose compatable in device tree */
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while ((cn = of_find_node_by_type(cn, "cpu"))) {
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if (is_mngs_cpu(cn))
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mngs_cpu_cnt++;
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}
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return mngs_cpu_cnt;
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}
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/* defines for MNGS reset */
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#define PEND_MNGS (1 << 1)
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#define PEND_APOLLO (1 << 0)
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#define DEFAULT_VAL_CPU_RESET_DISABLE (0xFFFFFFFC)
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#define RESET_DISABLE_GPR_CPUPORESET (1 << 15)
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#define RESET_DISABLE_WDT_CPUPORESET (1 << 12)
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#define RESET_DISABLE_CORERESET (1 << 9)
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#define RESET_DISABLE_CPUPORESET (1 << 8)
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#define RESET_DISABLE_WDT_PRESET_DBG (1 << 25)
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#define RESET_DISABLE_PRESET_DBG (1 << 18)
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#define DFD_EDPCSR_DUMP_EN (1 << 0)
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#define RESET_DISABLE_L2RESET (1 << 16)
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#define RESET_DISABLE_WDT_L2RESET (1 << 31)
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#define EXYNOS_PMU_CPU_RESET_DISABLE_FROM_SOFTRESET (0x041C)
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#define EXYNOS_PMU_CPU_RESET_DISABLE_FROM_WDTRESET (0x0414)
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#define EXYNOS_PMU_ATLAS_CPU0_RESET (0x200C)
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#define EXYNOS_PMU_ATLAS_DBG_RESET (0x244C)
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#define EXYNOS_PMU_ATLAS_NONCPU_RESET (0x240C)
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#define EXYNOS_PMU_SWRESET (0x0400)
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#define EXYNOS_PMU_RESET_SEQUENCER_CONFIGURATION (0x0500)
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#define EXYNOS_PMU_PS_HOLD_CONTROL (0x330C)
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static void mngs_reset_control(int en)
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{
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u32 reg_val, val;
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u32 mngs_cpu_cnt = soc_has_mongoose();
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if (mngs_cpu_cnt == 0 || !exynos_pmu_base)
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return;
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if (en) {
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/* reset disable for MNGS */
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pr_err("%s: mngs cpu reset disable\n", __func__);
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reg_val = readl(exynos_pmu_base + EXYNOS_PMU_CPU_RESET_DISABLE_FROM_SOFTRESET);
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if (reg_val & (PEND_MNGS | PEND_APOLLO)) {
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reg_val &= ~(PEND_MNGS | PEND_APOLLO);
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writel(reg_val, exynos_pmu_base + EXYNOS_PMU_CPU_RESET_DISABLE_FROM_SOFTRESET);
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}
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reg_val = readl(exynos_pmu_base + EXYNOS_PMU_CPU_RESET_DISABLE_FROM_WDTRESET);
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if (reg_val != DEFAULT_VAL_CPU_RESET_DISABLE) {
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reg_val &= ~(PEND_MNGS | PEND_APOLLO);
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writel(reg_val, exynos_pmu_base + EXYNOS_PMU_CPU_RESET_DISABLE_FROM_WDTRESET);
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}
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for (val = 0; val < mngs_cpu_cnt; val++) {
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reg_val = readl(exynos_pmu_base + EXYNOS_PMU_ATLAS_CPU0_RESET + (val * 0x80));
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#ifdef CONFIG_SOC_EXYNOS8890_EVT1
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reg_val |= (RESET_DISABLE_WDT_CPUPORESET
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| RESET_DISABLE_CORERESET | RESET_DISABLE_CPUPORESET);
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#else
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reg_val |= (RESET_DISABLE_CORERESET | RESET_DISABLE_CPUPORESET);
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#endif
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writel(reg_val, exynos_pmu_base + EXYNOS_PMU_ATLAS_CPU0_RESET + (val * 0x80));
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}
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reg_val = readl(exynos_pmu_base + EXYNOS_PMU_ATLAS_DBG_RESET);
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#ifdef CONFIG_SOC_EXYNOS8890_EVT1
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reg_val |= (RESET_DISABLE_WDT_PRESET_DBG | RESET_DISABLE_PRESET_DBG);
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#else
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reg_val |= (RESET_DISABLE_PRESET_DBG);
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#endif
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writel(reg_val, exynos_pmu_base + EXYNOS_PMU_ATLAS_DBG_RESET);
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reg_val = readl(exynos_pmu_base + EXYNOS_PMU_ATLAS_NONCPU_RESET);
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#ifdef CONFIG_SOC_EXYNOS8890_EVT1
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reg_val |= (RESET_DISABLE_L2RESET | RESET_DISABLE_WDT_L2RESET);
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#else
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reg_val |= (RESET_DISABLE_L2RESET);
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#endif
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writel(reg_val, exynos_pmu_base + EXYNOS_PMU_ATLAS_NONCPU_RESET);
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} else {
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/* reset enable for MNGS */
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pr_err("%s: mngs cpu reset enable before s/w reset\n", __func__);
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for (val = 0; val < mngs_cpu_cnt; val++) {
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reg_val = readl(exynos_pmu_base + EXYNOS_PMU_ATLAS_CPU0_RESET + (val * 0x80));
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#ifdef CONFIG_SOC_EXYNOS8890_EVT1
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reg_val &= ~(RESET_DISABLE_WDT_CPUPORESET
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| RESET_DISABLE_CORERESET | RESET_DISABLE_CPUPORESET);
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#else
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reg_val &= ~(RESET_DISABLE_CORERESET | RESET_DISABLE_CPUPORESET);
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#endif
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writel(reg_val, exynos_pmu_base + EXYNOS_PMU_ATLAS_CPU0_RESET + (val * 0x80));
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}
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reg_val = readl(exynos_pmu_base + EXYNOS_PMU_ATLAS_DBG_RESET);
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#ifdef CONFIG_SOC_EXYNOS8890_EVT1
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reg_val &= ~(RESET_DISABLE_WDT_PRESET_DBG | RESET_DISABLE_PRESET_DBG);
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#else
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reg_val &= ~(RESET_DISABLE_PRESET_DBG);
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#endif
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writel(reg_val, exynos_pmu_base + EXYNOS_PMU_ATLAS_DBG_RESET);
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reg_val = readl(exynos_pmu_base + EXYNOS_PMU_ATLAS_NONCPU_RESET);
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#ifdef CONFIG_SOC_EXYNOS8890_EVT1
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reg_val &= ~(RESET_DISABLE_L2RESET);
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#endif
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writel(reg_val, exynos_pmu_base + EXYNOS_PMU_ATLAS_NONCPU_RESET);
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}
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}
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#define INFORM_NONE 0x0
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#define INFORM_RAMDUMP 0xd
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#define INFORM_RECOVERY 0xf
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#if !defined(CONFIG_SEC_REBOOT)
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#ifdef CONFIG_OF
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static void exynos_power_off(void)
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{
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pr_emerg("%s: Set PS_HOLD Low.\n", __func__);
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writel(readl(exynos_pmu_base + EXYNOS_PMU_PS_HOLD_CONTROL) & 0xFFFFFEFF,
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exynos_pmu_base + EXYNOS_PMU_PS_HOLD_CONTROL);
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}
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#else
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static void exynos_power_off(void)
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{
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pr_info("Exynos power off does not support.\n");
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}
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#endif
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#endif
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static void exynos_reboot(enum reboot_mode mode, const char *cmd)
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{
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u32 restart_inform, soc_id;
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if (!exynos_pmu_base)
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return;
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restart_inform = INFORM_NONE;
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if (cmd) {
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if (!strcmp((char *)cmd, "recovery"))
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restart_inform = INFORM_RECOVERY;
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else if(!strcmp((char *)cmd, "ramdump"))
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restart_inform = INFORM_RAMDUMP;
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}
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/* Check by each SoC */
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soc_id = exynos_soc_info.product_id & EXYNOS_SOC_MASK;
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switch(soc_id) {
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case EXYNOS8890_SOC_ID:
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/* Check reset_sequencer_configuration register */
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if (readl(exynos_pmu_base + EXYNOS_PMU_RESET_SEQUENCER_CONFIGURATION) & DFD_EDPCSR_DUMP_EN)
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mngs_reset_control(0);
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break;
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default:
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break;
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}
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/* Do S/W Reset */
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__raw_writel(0x1, exynos_pmu_base + EXYNOS_PMU_SWRESET);
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}
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static int __init exynos_reboot_setup(struct device_node *np)
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{
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int err = 0;
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u32 id;
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if (!of_property_read_u32(np, "pmu_base", &id)) {
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exynos_pmu_base = ioremap(id, SZ_16K);
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if (!exynos_pmu_base) {
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pr_err("%s: failed to map to exynos-pmu-base address 0x%x\n",
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__func__, id);
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err = -ENOMEM;
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}
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}
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of_node_put(np);
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return err;
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}
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static const struct of_device_id reboot_of_match[] __initconst = {
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{ .compatible = "exynos,reboot", .data = exynos_reboot_setup},
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{},
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};
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typedef int (*reboot_initcall_t)(const struct device_node *);
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static int __init exynos_reboot_init(void)
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{
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struct device_node *np;
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const struct of_device_id *matched_np;
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reboot_initcall_t init_fn;
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np = of_find_matching_node_and_match(NULL, reboot_of_match, &matched_np);
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if (!np)
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return -ENODEV;
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arm_pm_restart = exynos_reboot;
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#if !defined(CONFIG_SEC_REBOOT)
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pm_power_off = exynos_power_off;
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#endif
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init_fn = (reboot_initcall_t)matched_np->data;
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return init_fn(np);
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}
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subsys_initcall(exynos_reboot_init);
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