mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-30 15:48:52 +01:00
1059 lines
88 KiB
C
1059 lines
88 KiB
C
#include "../pwrcal.h"
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#include "../pwrcal-clk.h"
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#include "../pwrcal-env.h"
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#include "../pwrcal-rae.h"
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#include "../pwrcal-pmu.h"
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#include "S5E7570-cmusfr.h"
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#include "S5E7570-pmusfr.h"
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#include "S5E7570-cmu.h"
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struct pwrcal_clk *fixed_rate_type_list[NUM_OF_FIXED_RATE_TYPE];
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struct pwrcal_clk *fixed_factor_type_list[NUM_OF_FIXED_FACTOR_TYPE];
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struct pwrcal_clk *pll_type_list[NUM_OF_PLL_TYPE];
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struct pwrcal_clk *mux_type_list[NUM_OF_MUX_TYPE];
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struct pwrcal_clk *div_type_list[NUM_OF_DIV_TYPE];
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struct pwrcal_clk *gate_type_list[NUM_OF_GATE_TYPE];
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#define ADD_CLK_TO_LIST(to, x) to[clk_##x.clk.id & 0xFFF] = &(clk_##x.clk)
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#define PLL_RATE_MPS(_rate, _m, _p, _s) \
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{ \
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.rate = (_rate), \
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.mdiv = (_m), \
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.pdiv = (_p), \
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.sdiv = (_s), \
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}
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#define PLL_RATE_MPSK(_rate, _m, _p, _s, _k) \
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{ \
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.rate = (_rate), \
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.mdiv = (_m), \
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.pdiv = (_p), \
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.sdiv = (_s), \
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.kdiv = (_k), \
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}
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extern struct pwrcal_pll_ops pll141xx_ops;
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extern struct pwrcal_pll_ops pll1431x_ops;
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extern struct pwrcal_pll_ops wpll_usbpll_ops;
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CLK_PLL(14170, CPUCL0_PLL, 0, CPUCL0_PLL_LOCK, CPUCL0_PLL_CON0, NULL, CPUCL0_MUX_CPUCL0_PLL, &pll141xx_ops);
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CLK_PLL(14170, SHARED0_PLL, 0, SHARED0_PLL_LOCK, SHARED0_PLL_CON0, NULL, MIF_MUX_SHARED0_PLL, &pll141xx_ops);
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CLK_PLL(14170, SHARED1_PLL, 0, SHARED1_PLL_LOCK, SHARED1_PLL_CON0, NULL, MIF_MUX_SHARED1_PLL, &pll141xx_ops);
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CLK_PLL(14170, SHARED2_PLL, 0, SHARED2_PLL_LOCK, SHARED2_PLL_CON0, NULL, MIF_MUX_SHARED2_PLL, &pll141xx_ops);
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CLK_PLL(14310, AUD_PLL, 0, AUD_PLL_LOCK, AUD_PLL_CON0, NULL, DISPAUD_MUX_AUD_PLL, &pll1431x_ops);
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CLK_PLL(0, WPLL_USB_PLL, 0, USBPLL_CON0, USBPLL_CON1, NULL, 0, &wpll_usbpll_ops);
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FIXEDRATE(OSCCLK, 26 * MHZ, 0);
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FIXEDRATE(OSCCLK_FM_52M, 26 * MHZ, 0);
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FIXEDRATE(CLK_MIF_DDRPHY0, 1 * MHZ, 0);
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FIXEDRATE(TCXO, 26 * MHZ, 0);
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FIXEDRATE(WIFI2AP_USBPLL_CLK, 20 * MHZ, 0);
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FIXEDRATE(CLKPHY_FSYS_USB20DRD_PHYCLOCK, 60 * MHZ, 0);
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FIXEDRATE(CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS, 188 * MHZ, 0);
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FIXEDRATE(CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0, 188 * MHZ, 0);
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FIXEDRATE(CLKIO_DISPAUD_MIXER_BCLK_CP, 24576 * KHZ, 0);
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FIXEDRATE(CLKPHY_ISP_S_RXBYTECLKHS0_S4, 188 * MHZ, 0);
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FIXEDFACTOR(MIF_FF_SHARED0_PLL_DIV2, MIF_MUX_SHARED0_PLL, 2, 0);
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FIXEDFACTOR(MIF_FF_SHARED1_PLL_DIV2, MIF_MUX_SHARED1_PLL, 2, 0);
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FIXEDFACTOR(MIF_FF_SHARED2_PLL_DIV2, MIF_MUX_SHARED2_PLL, 2, 0);
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static struct pwrcal_clk *apm_mux_clkcmu_apm_user_p[] = {CLK(OSCCLK), CLK(MIF_GATE_CLKCMU_APM)};
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static struct pwrcal_clk *cpucl0_mux_cpucl0_pll_p[] = {CLK(OSCCLK), CLK(CPUCL0_PLL)};
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static struct pwrcal_clk *cpucl0_mux_clkcmu_cpucl0_switch_user_p[] = {CLK(OSCCLK), CLK(MIF_GATE_CLKCMU_CPUCL0_SWITCH)};
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static struct pwrcal_clk *cpucl0_mux_clk_cpucl0_p[] = {CLK(CPUCL0_MUX_CPUCL0_PLL), CLK(CPUCL0_MUX_CLKCMU_CPUCL0_SWITCH_USER)};
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static struct pwrcal_clk *dispaud_mux_aud_pll_p[] = {CLK(OSCCLK), CLK(AUD_PLL)};
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static struct pwrcal_clk *dispaud_mux_clkcmu_dispaud_bus_user_p[] = {CLK(OSCCLK), CLK(MIF_GATE_CLKCMU_DISPAUD_BUS)};
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static struct pwrcal_clk *dispaud_mux_clkcmu_dispaud_decon_int_vclk_user_p[] = {CLK(OSCCLK), CLK(MIF_GATE_CLKCMU_DISPAUD_DECON_INT_VCLK)};
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static struct pwrcal_clk *dispaud_mux_clkcmu_dispaud_decon_int_eclk_user_p[] = {CLK(OSCCLK), CLK(MIF_GATE_CLKCMU_DISPAUD_DECON_INT_VCLK)};
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static struct pwrcal_clk *dispaud_mux_clkphy_dispaud_mipiphy_txbyteclkhs_user_p[] = {CLK(OSCCLK), CLK(CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS)};
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static struct pwrcal_clk *dispaud_mux_clkphy_dispaud_mipiphy_rxclkesc0_user_p[] = {CLK(OSCCLK), CLK(CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0)};
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static struct pwrcal_clk *fsys_mux_clkphy_fsys_usb20drd_phyclock_user_p[] = {CLK(OSCCLK), CLK(CLKPHY_FSYS_USB20DRD_PHYCLOCK)};
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static struct pwrcal_clk *g3d_mux_clkcmu_g3d_user_p[] = {CLK(OSCCLK), CLK(MIF_GATE_CLKCMU_G3D)};
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static struct pwrcal_clk *isp_mux_clkcmu_isp_vra_user_p[] = {CLK(OSCCLK), CLK(MIF_GATE_CLKCMU_ISP_VRA)};
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static struct pwrcal_clk *isp_mux_clkcmu_isp_cam_user_p[] = {CLK(OSCCLK), CLK(MIF_GATE_CLKCMU_ISP_CAM)};
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static struct pwrcal_clk *isp_mux_clkphy_isp_s_rxbyteclkhs0_s4_user_p[] = {CLK(OSCCLK), CLK(CLKPHY_ISP_S_RXBYTECLKHS0_S4)};
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static struct pwrcal_clk *mfcmscl_mux_clkcmu_mfcmscl_mscl_user_p[] = {CLK(OSCCLK), CLK(MIF_GATE_CLKCMU_MFCMSCL_MSCL)};
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static struct pwrcal_clk *mfcmscl_mux_clkcmu_mfcmscl_mfc_user_p[] = {CLK(OSCCLK), CLK(MIF_GATE_CLKCMU_MFCMSCL_MFC)};
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static struct pwrcal_clk *mif_mux_shared0_pll_p[] = {CLK(OSCCLK), CLK(SHARED0_PLL)};
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static struct pwrcal_clk *mif_mux_shared1_pll_p[] = {CLK(OSCCLK), CLK(SHARED1_PLL)};
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static struct pwrcal_clk *mif_mux_shared2_pll_p[] = {CLK(OSCCLK), CLK(SHARED2_PLL)};
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static struct pwrcal_clk *mif_mux_clk_mif_phy_clk_p[] = {CLK(MIF_MUX_SHARED0_PLL), CLK(MIF_MUX_SHARED1_PLL), CLK(MIF_MUX_SHARED2_PLL), CLK(MIF_MUX_SHARED2_PLL)};
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static struct pwrcal_clk *mif_mux_clk_mif_phy_clk_a_p[] = {CLK(MIF_MUX_SHARED0_PLL), CLK(MIF_MUX_SHARED1_PLL)};
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static struct pwrcal_clk *mif_mux_clk_mif_phy_clk_b_p[] = {CLK(MIF_MUX_CLK_MIF_PHY_CLK_A), CLK(MIF_MUX_SHARED2_PLL)};
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static struct pwrcal_clk *mif_mux_clk_mif_busd_p[] = {CLK(MIF_MUX_SHARED0_PLL), CLK(MIF_FF_SHARED1_PLL_DIV2), CLK(MIF_FF_SHARED2_PLL_DIV2)};
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static struct pwrcal_clk *mif_mux_clkcmu_g3d_p[] = {CLK(MIF_MUX_SHARED0_PLL), CLK(MIF_MUX_SHARED1_PLL), CLK(MIF_MUX_SHARED2_PLL)};
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static struct pwrcal_clk *mif_mux_clkcmu_isp_vra_p[] = {CLK(MIF_MUX_SHARED0_PLL), CLK(MIF_MUX_SHARED1_PLL)};
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static struct pwrcal_clk *mif_mux_clkcmu_isp_cam_p[] = {CLK(MIF_FF_SHARED0_PLL_DIV2), CLK(MIF_MUX_SHARED1_PLL)};
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static struct pwrcal_clk *mif_mux_clkcmu_dispaud_bus_p[] = {CLK(MIF_FF_SHARED0_PLL_DIV2), CLK(MIF_FF_SHARED1_PLL_DIV2)};
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static struct pwrcal_clk *mif_mux_clkcmu_dispaud_decon_int_vclk_p[] = {CLK(MIF_MUX_SHARED0_PLL), CLK(MIF_MUX_SHARED1_PLL), CLK(MIF_MUX_SHARED2_PLL)};
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static struct pwrcal_clk *mif_mux_clkcmu_mfcmscl_mscl_p[] = {CLK(MIF_FF_SHARED0_PLL_DIV2), CLK(MIF_MUX_SHARED2_PLL)};
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static struct pwrcal_clk *mif_mux_clkcmu_mfcmscl_mfc_p[] = {CLK(MIF_FF_SHARED0_PLL_DIV2), CLK(MIF_MUX_SHARED2_PLL)};
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static struct pwrcal_clk *mif_mux_clkcmu_fsys_bus_p[] = {CLK(MIF_FF_SHARED0_PLL_DIV2), CLK(MIF_FF_SHARED1_PLL_DIV2)};
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static struct pwrcal_clk *mif_mux_clkcmu_fsys_mmc0_p[] = {CLK(MIF_FF_SHARED0_PLL_DIV2), CLK(MIF_FF_SHARED2_PLL_DIV2)};
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static struct pwrcal_clk *mif_mux_clkcmu_fsys_mmc2_p[] = {CLK(MIF_FF_SHARED0_PLL_DIV2), CLK(MIF_FF_SHARED2_PLL_DIV2)};
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static struct pwrcal_clk *mif_mux_clkcmu_fsys_usb20drd_refclk_p[] = {CLK(MIF_FF_SHARED0_PLL_DIV2), CLK(MIF_FF_SHARED1_PLL_DIV2)};
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static struct pwrcal_clk *mif_mux_clkcmu_peri_bus_p[] = {CLK(MIF_FF_SHARED0_PLL_DIV2), CLK(MIF_FF_SHARED1_PLL_DIV2)};
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static struct pwrcal_clk *mif_mux_clkcmu_peri_uart_debug_p[] = {CLK(MIF_FF_SHARED0_PLL_DIV2), CLK(MIF_FF_SHARED1_PLL_DIV2)};
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static struct pwrcal_clk *mif_mux_clkcmu_peri_uart_sensor_p[] = {CLK(MIF_FF_SHARED0_PLL_DIV2), CLK(MIF_FF_SHARED1_PLL_DIV2)};
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static struct pwrcal_clk *mif_mux_clkcmu_peri_spi_rearfrom_p[] = {CLK(MIF_FF_SHARED0_PLL_DIV2), CLK(OSCCLK)};
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static struct pwrcal_clk *mif_mux_clkcmu_peri_spi_ese_p[] = {CLK(MIF_FF_SHARED0_PLL_DIV2), CLK(OSCCLK)};
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static struct pwrcal_clk *mif_mux_clkcmu_peri_usi_0_p[] = {CLK(MIF_FF_SHARED0_PLL_DIV2), CLK(MIF_FF_SHARED1_PLL_DIV2), CLK(OSCCLK)};
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static struct pwrcal_clk *mif_mux_clkcmu_peri_usi_1_p[] = {CLK(MIF_FF_SHARED0_PLL_DIV2), CLK(MIF_FF_SHARED1_PLL_DIV2), CLK(OSCCLK)};
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static struct pwrcal_clk *mif_mux_clkcmu_apm_p[] = {CLK(MIF_FF_SHARED0_PLL_DIV2), CLK(MIF_FF_SHARED1_PLL_DIV2)};
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static struct pwrcal_clk *mif_mux_clkcmu_isp_sensor0_p[] = {CLK(MIF_FF_SHARED0_PLL_DIV2), CLK(OSCCLK)};
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CLK_MUX(APM_MUX_CLKCMU_APM_USER, apm_mux_clkcmu_apm_user_p, CLK_CON_MUX_CLKCMU_APM_USER, 12, 1, CLK_STAT_MUX_CLKCMU_APM_USER, 12, 2, CLK_CON_MUX_CLKCMU_APM_USER, 21, 0);
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CLK_MUX(CPUCL0_MUX_CPUCL0_PLL, cpucl0_mux_cpucl0_pll_p, CLK_CON_MUX_CPUCL0_PLL, 12, 1, CLK_STAT_MUX_CPUCL0_PLL, 12, 2, CLK_CON_MUX_CPUCL0_PLL, 21, 0);
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CLK_MUX(CPUCL0_MUX_CLKCMU_CPUCL0_SWITCH_USER, cpucl0_mux_clkcmu_cpucl0_switch_user_p, CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH_USER, 12, 1, CLK_STAT_MUX_CLKCMU_CPUCL0_SWITCH_USER, 12, 2, CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH_USER, 21, 0);
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CLK_MUX(CPUCL0_MUX_CLK_CPUCL0, cpucl0_mux_clk_cpucl0_p, CLK_CON_MUX_CLK_CPUCL0, 12, 1, CLK_STAT_MUX_CLK_CPUCL0, 12, 2, CLK_CON_MUX_CLK_CPUCL0, 21, 0);
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CLK_MUX(DISPAUD_MUX_AUD_PLL, dispaud_mux_aud_pll_p, CLK_CON_MUX_AUD_PLL, 12, 1, CLK_STAT_MUX_AUD_PLL, 12, 2, CLK_CON_MUX_AUD_PLL, 21, 0);
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CLK_MUX(DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER, dispaud_mux_clkcmu_dispaud_bus_user_p, CLK_CON_MUX_CLKCMU_DISPAUD_BUS_USER, 12, 1, CLK_STAT_MUX_CLKCMU_DISPAUD_BUS_USER, 12, 2, CLK_CON_MUX_CLKCMU_DISPAUD_BUS_USER, 21, 0);
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CLK_MUX(DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER, dispaud_mux_clkcmu_dispaud_decon_int_vclk_user_p, CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER, 12, 1, CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER, 12, 2, CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER, 21, 0);
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CLK_MUX(DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER, dispaud_mux_clkcmu_dispaud_decon_int_eclk_user_p, CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER, 12, 1, CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER, 12, 2, CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER, 21, 0);
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CLK_MUX(DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER, dispaud_mux_clkphy_dispaud_mipiphy_txbyteclkhs_user_p, CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER, 12, 1, CLK_STAT_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER, 12, 2, CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER, 21, 0);
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CLK_MUX(DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER, dispaud_mux_clkphy_dispaud_mipiphy_rxclkesc0_user_p, CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER, 12, 1, CLK_STAT_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER, 12, 2, CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER, 21, 0);
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CLK_MUX(FSYS_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER, fsys_mux_clkphy_fsys_usb20drd_phyclock_user_p, CLK_CON_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER, 12, 1, CLK_STAT_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER, 12, 2, CLK_CON_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER, 21, 0);
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CLK_MUX(G3D_MUX_CLKCMU_G3D_USER, g3d_mux_clkcmu_g3d_user_p, CLK_CON_MUX_CLKCMU_G3D_USER, 12, 1, CLK_STAT_MUX_CLKCMU_G3D_USER, 12, 2, CLK_CON_MUX_CLKCMU_G3D_USER, 21, 0);
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CLK_MUX(ISP_MUX_CLKCMU_ISP_VRA_USER, isp_mux_clkcmu_isp_vra_user_p, CLK_CON_MUX_CLKCMU_ISP_VRA_USER, 12, 1, CLK_STAT_MUX_CLKCMU_ISP_VRA_USER, 12, 2, CLK_CON_MUX_CLKCMU_ISP_VRA_USER, 21, 0);
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CLK_MUX(ISP_MUX_CLKCMU_ISP_CAM_USER, isp_mux_clkcmu_isp_cam_user_p, CLK_CON_MUX_CLKCMU_ISP_CAM_USER, 12, 1, CLK_STAT_MUX_CLKCMU_ISP_CAM_USER, 12, 2, CLK_CON_MUX_CLKCMU_ISP_CAM_USER, 21, 0);
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CLK_MUX(ISP_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER, isp_mux_clkphy_isp_s_rxbyteclkhs0_s4_user_p, CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER, 12, 1, CLK_STAT_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER, 12, 2, CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER, 21, 0);
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CLK_MUX(MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER, mfcmscl_mux_clkcmu_mfcmscl_mscl_user_p, CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL_USER, 12, 1, CLK_STAT_MUX_CLKCMU_MFCMSCL_MSCL_USER, 12, 2, CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL_USER, 21, 0);
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CLK_MUX(MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER, mfcmscl_mux_clkcmu_mfcmscl_mfc_user_p, CLK_CON_MUX_CLKCMU_MFCMSCL_MFC_USER, 12, 1, CLK_STAT_MUX_CLKCMU_MFCMSCL_MFC_USER, 12, 2, CLK_CON_MUX_CLKCMU_MFCMSCL_MFC_USER, 21, 0);
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CLK_MUX(MIF_MUX_SHARED0_PLL, mif_mux_shared0_pll_p, CLK_CON_MUX_SHARED0_PLL, 12, 1, CLK_STAT_MUX_SHARED0_PLL, 12, 2, CLK_CON_MUX_SHARED0_PLL, 21, 0);
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CLK_MUX(MIF_MUX_SHARED1_PLL, mif_mux_shared1_pll_p, CLK_CON_MUX_SHARED1_PLL, 12, 1, CLK_STAT_MUX_SHARED1_PLL, 12, 2, CLK_CON_MUX_SHARED1_PLL, 21, 0);
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CLK_MUX(MIF_MUX_SHARED2_PLL, mif_mux_shared2_pll_p, CLK_CON_MUX_SHARED2_PLL, 12, 1, CLK_STAT_MUX_SHARED2_PLL, 12, 2, CLK_CON_MUX_SHARED2_PLL, 21, 0);
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struct pwrcal_mux clk_MIF_MUX_CLK_MIF_PHY_CLK __attribute__((unused, aligned(8), section(".clk_mux."))) = {
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.clk.id = MIF_MUX_CLK_MIF_PHY_CLK,
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.clk.name = "MIF_MUX_CLK_MIF_PHY_CLK", /* (const char *) */
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.clk.offset = DREX_FREQ_CTRL0,
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.clk.shift = 4,
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.clk.width = 2,
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.clk.status = CLK_STAT_MUX_CLK_MIF_PHY_CLK_B,
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.clk.s_shift = 21,
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.clk.s_width = 2,
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.clk.enable = CLK_CON_MUX_CLK_MIF_PHY_CLK_B,
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.clk.e_shift = 21,
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.parents = mif_mux_clk_mif_phy_clk_p,
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.num_parents = 0xFF,
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.gate = &(clk_0.clk),
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};
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CLK_MUX(MIF_MUX_CLK_MIF_PHY_CLK_A, mif_mux_clk_mif_phy_clk_a_p, CLK_CON_MUX_CLK_MIF_PHY_CLK_A, 12, 1, CLK_STAT_MUX_CLK_MIF_PHY_CLK_A, 12, 2, CLK_CON_MUX_CLK_MIF_PHY_CLK_A, 21, 0);
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CLK_MUX(MIF_MUX_CLK_MIF_PHY_CLK_B, mif_mux_clk_mif_phy_clk_b_p, CLK_CON_MUX_CLK_MIF_PHY_CLK_B, 12, 1, CLK_STAT_MUX_CLK_MIF_PHY_CLK_B, 12, 2, CLK_CON_MUX_CLK_MIF_PHY_CLK_B, 21, 0);
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CLK_MUX(MIF_MUX_CLK_MIF_BUSD, mif_mux_clk_mif_busd_p, CLK_CON_MUX_CLK_MIF_BUSD, 12, 2, CLK_STAT_MUX_CLK_MIF_BUSD, 12, 4, CLK_CON_MUX_CLK_MIF_BUSD, 21, 0);
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CLK_MUX(MIF_MUX_CLKCMU_G3D, mif_mux_clkcmu_g3d_p, CLK_CON_MUX_CLKCMU_G3D, 12, 2, CLK_STAT_MUX_CLKCMU_G3D, 12, 4, CLK_CON_MUX_CLKCMU_G3D, 21, 0);
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CLK_MUX(MIF_MUX_CLKCMU_ISP_VRA, mif_mux_clkcmu_isp_vra_p, CLK_CON_MUX_CLKCMU_ISP_VRA, 12, 1, CLK_STAT_MUX_CLKCMU_ISP_VRA, 12, 2, CLK_CON_MUX_CLKCMU_ISP_VRA, 21, MIF_MUXGATE_CLKCMU_ISP_VRA);
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CLK_MUX(MIF_MUX_CLKCMU_ISP_CAM, mif_mux_clkcmu_isp_cam_p, CLK_CON_MUX_CLKCMU_ISP_CAM, 12, 1, CLK_STAT_MUX_CLKCMU_ISP_CAM, 12, 2, CLK_CON_MUX_CLKCMU_ISP_CAM, 21, MIF_MUXGATE_CLKCMU_ISP_CAM);
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CLK_MUX(MIF_MUX_CLKCMU_DISPAUD_BUS, mif_mux_clkcmu_dispaud_bus_p, CLK_CON_MUX_CLKCMU_DISPAUD_BUS, 12, 1, CLK_STAT_MUX_CLKCMU_DISPAUD_BUS, 12, 2, CLK_CON_MUX_CLKCMU_DISPAUD_BUS, 21, MIF_MUXGATE_CLKCMU_DISPAUD_BUS);
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CLK_MUX(MIF_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK, mif_mux_clkcmu_dispaud_decon_int_vclk_p, CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK, 12, 2, CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK, 12, 4, CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK, 21, MIF_MUXGATE_CLKCMU_DISPAUD_DECON_INT_VCLK);
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CLK_MUX(MIF_MUX_CLKCMU_MFCMSCL_MSCL, mif_mux_clkcmu_mfcmscl_mscl_p, CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL, 12, 1, CLK_STAT_MUX_CLKCMU_MFCMSCL_MSCL, 12, 2, CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL, 21, MIF_MUXGATE_CLKCMU_MFCMSCL_MSCL);
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CLK_MUX(MIF_MUX_CLKCMU_MFCMSCL_MFC, mif_mux_clkcmu_mfcmscl_mfc_p, CLK_CON_MUX_CLKCMU_MFCMSCL_MFC, 12, 1, CLK_STAT_MUX_CLKCMU_MFCMSCL_MFC, 12, 2, CLK_CON_MUX_CLKCMU_MFCMSCL_MFC, 21, MIF_MUXGATE_CLKCMU_MFCMSCL_MFC);
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CLK_MUX(MIF_MUX_CLKCMU_FSYS_BUS, mif_mux_clkcmu_fsys_bus_p, CLK_CON_MUX_CLKCMU_FSYS_BUS, 12, 1, CLK_STAT_MUX_CLKCMU_FSYS_BUS, 12, 2, CLK_CON_MUX_CLKCMU_FSYS_BUS, 21, MIF_MUXGATE_CLKCMU_FSYS_BUS);
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CLK_MUX(MIF_MUX_CLKCMU_FSYS_MMC0, mif_mux_clkcmu_fsys_mmc0_p, CLK_CON_MUX_CLKCMU_FSYS_MMC0, 12, 1, CLK_STAT_MUX_CLKCMU_FSYS_MMC0, 12, 2, CLK_CON_MUX_CLKCMU_FSYS_MMC0, 21, MIF_MUXGATE_CLKCMU_FSYS_MMC0);
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CLK_MUX(MIF_MUX_CLKCMU_FSYS_MMC2, mif_mux_clkcmu_fsys_mmc2_p, CLK_CON_MUX_CLKCMU_FSYS_MMC2, 12, 1, CLK_STAT_MUX_CLKCMU_FSYS_MMC2, 12, 2, CLK_CON_MUX_CLKCMU_FSYS_MMC2, 21, MIF_MUXGATE_CLKCMU_FSYS_MMC2);
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CLK_MUX(MIF_MUX_CLKCMU_FSYS_USB20DRD_REFCLK, mif_mux_clkcmu_fsys_usb20drd_refclk_p, CLK_CON_MUX_CLKCMU_FSYS_USB20DRD_REFCLK, 12, 1, CLK_STAT_MUX_CLKCMU_FSYS_USB20DRD_REFCLK, 12, 2, CLK_CON_MUX_CLKCMU_FSYS_USB20DRD_REFCLK, 21, MIF_MUXGATE_CLKCMU_FSYS_USB20DRD_REFCLK);
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CLK_MUX(MIF_MUX_CLKCMU_PERI_BUS, mif_mux_clkcmu_peri_bus_p, CLK_CON_MUX_CLKCMU_PERI_BUS, 12, 1, CLK_STAT_MUX_CLKCMU_PERI_BUS, 12, 2, CLK_CON_MUX_CLKCMU_PERI_BUS, 21, MIF_MUXGATE_CLKCMU_PERI_BUS);
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CLK_MUX(MIF_MUX_CLKCMU_PERI_UART_DEBUG, mif_mux_clkcmu_peri_uart_debug_p, CLK_CON_MUX_CLKCMU_PERI_UART_DEBUG, 12, 1, CLK_STAT_MUX_CLKCMU_PERI_UART_DEBUG, 12, 2, CLK_CON_MUX_CLKCMU_PERI_UART_DEBUG, 21, MIF_MUXGATE_CLKCMU_PERI_UART_DEBUG);
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CLK_MUX(MIF_MUX_CLKCMU_PERI_UART_SENSOR, mif_mux_clkcmu_peri_uart_sensor_p, CLK_CON_MUX_CLKCMU_PERI_UART_SENSOR, 12, 1, CLK_STAT_MUX_CLKCMU_PERI_UART_SENSOR, 12, 2, CLK_CON_MUX_CLKCMU_PERI_UART_SENSOR, 21, MIF_MUXGATE_CLKCMU_PERI_UART_SENSOR);
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CLK_MUX(MIF_MUX_CLKCMU_PERI_SPI_REARFROM, mif_mux_clkcmu_peri_spi_rearfrom_p, CLK_CON_MUX_CLKCMU_PERI_SPI_REARFROM, 12, 1, CLK_STAT_MUX_CLKCMU_PERI_SPI_REARFROM, 12, 2, CLK_CON_MUX_CLKCMU_PERI_SPI_REARFROM, 21, MIF_MUXGATE_CLKCMU_PERI_SPI_REARFROM);
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CLK_MUX(MIF_MUX_CLKCMU_PERI_SPI_ESE, mif_mux_clkcmu_peri_spi_ese_p, CLK_CON_MUX_CLKCMU_PERI_SPI_ESE, 12, 1, CLK_STAT_MUX_CLKCMU_PERI_SPI_ESE, 12, 2, CLK_CON_MUX_CLKCMU_PERI_SPI_ESE, 21, MIF_MUXGATE_CLKCMU_PERI_SPI_ESE);
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CLK_MUX(MIF_MUX_CLKCMU_PERI_USI_0, mif_mux_clkcmu_peri_usi_0_p, CLK_CON_MUX_CLKCMU_PERI_USI_0, 12, 2, CLK_STAT_MUX_CLKCMU_PERI_USI_0, 12, 4, CLK_CON_MUX_CLKCMU_PERI_USI_0, 21, MIF_MUXGATE_CLKCMU_PERI_USI_0);
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CLK_MUX(MIF_MUX_CLKCMU_PERI_USI_1, mif_mux_clkcmu_peri_usi_1_p, CLK_CON_MUX_CLKCMU_PERI_USI_1, 12, 2, CLK_STAT_MUX_CLKCMU_PERI_USI_1, 12, 4, CLK_CON_MUX_CLKCMU_PERI_USI_1, 21, MIF_MUXGATE_CLKCMU_PERI_USI_1);
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CLK_MUX(MIF_MUX_CLKCMU_APM, mif_mux_clkcmu_apm_p, CLK_CON_MUX_CLKCMU_APM, 12, 1, CLK_STAT_MUX_CLKCMU_APM, 12, 2, CLK_CON_MUX_CLKCMU_APM, 21, MIF_MUXGATE_CLKCMU_APM);
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CLK_MUX(MIF_MUX_CLKCMU_ISP_SENSOR0, mif_mux_clkcmu_isp_sensor0_p, CLK_CON_MUX_CLKCMU_ISP_SENSOR0, 12, 1, CLK_STAT_MUX_CLKCMU_ISP_SENSOR0, 12, 2, CLK_CON_MUX_CLKCMU_ISP_SENSOR0, 21, MIF_MUXGATE_CLKCMU_ISP_SENSOR0);
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CLK_DIV(CPUCL0_DIV_CLK_CPUCL0_1, CPUCL0_MUX_CLK_CPUCL0, CLK_CON_DIV_CLK_CPUCL0_1, 0, 3, CLK_CON_DIV_CLK_CPUCL0_1, 25, 1, 0);
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CLK_DIV(CPUCL0_DIV_CLK_CPUCL0_2, CPUCL0_DIV_CLK_CPUCL0_1, CLK_CON_DIV_CLK_CPUCL0_2, 0, 3, CLK_CON_DIV_CLK_CPUCL0_2, 25, 1, 0);
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CLK_DIV(CPUCL0_DIV_CLK_CPUCL0_ACLK, CPUCL0_DIV_CLK_CPUCL0_2, CLK_CON_DIV_CLK_CPUCL0_ACLK, 0, 3, CLK_CON_DIV_CLK_CPUCL0_ACLK, 25, 1, 0);
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CLK_DIV(CPUCL0_DIV_CLK_CPUCL0_PCLK, CPUCL0_DIV_CLK_CPUCL0_2, CLK_CON_DIV_CLK_CPUCL0_PCLK, 0, 3, CLK_CON_DIV_CLK_CPUCL0_PCLK, 25, 1, 0);
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CLK_DIV(CPUCL0_DIV_CLK_CPUCL0_ATCLK, CPUCL0_DIV_CLK_CPUCL0_2, CLK_CON_DIV_CLK_CPUCL0_ATCLK, 0, 3, CLK_CON_DIV_CLK_CPUCL0_ATCLK, 25, 1, 0);
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CLK_DIV(CPUCL0_DIV_CLK_CPUCL0_PCLKDBG, CPUCL0_DIV_CLK_CPUCL0_2, CLK_CON_DIV_CLK_CPUCL0_PCLKDBG, 0, 3, CLK_CON_DIV_CLK_CPUCL0_PCLKDBG, 25, 1, 0);
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CLK_DIV(CPUCL0_DIV_CLK_CPUCL0_CNTCLK, CPUCL0_DIV_CLK_CPUCL0_2, CLK_CON_DIV_CLK_CPUCL0_CNTCLK, 0, 3, CLK_CON_DIV_CLK_CPUCL0_CNTCLK, 25, 1, 0);
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CLK_DIV(CPUCL0_DIV_CLK_CPUCL0_RUN_MONITOR, CPUCL0_DIV_CLK_CPUCL0_2, CLK_CON_DIV_CLK_CPUCL0_RUN_MONITOR, 0, 3, CLK_CON_DIV_CLK_CPUCL0_RUN_MONITOR, 25, 1, 0);
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CLK_DIV(CPUCL0_DIV_CLK_CPUCL0_HPM, CPUCL0_MUX_CLK_CPUCL0, CLK_CON_DIV_CLK_CPUCL0_HPM, 0, 3, CLK_CON_DIV_CLK_CPUCL0_HPM, 25, 1, 0);
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CLK_DIV(CPUCL0_DIV_CLK_CPUCL0_PLL, CPUCL0_MUX_CLK_CPUCL0, CLK_CON_DIV_CLK_CPUCL0_PLL, 0, 3, CLK_CON_DIV_CLK_CPUCL0_PLL, 25, 1, 0);
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CLK_DIV(DISPAUD_DIV_CLK_DISPAUD_APB, DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER , CLK_CON_DIV_CLK_DISPAUD_APB, 0, 2, CLK_CON_DIV_CLK_DISPAUD_APB, 25, 1, 0);
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CLK_DIV(DISPAUD_DIV_CLK_DISPAUD_DECON_INT_VCLK, DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER, CLK_CON_DIV_CLK_DISPAUD_DECON_INT_VCLK, 0, 3, CLK_CON_DIV_CLK_DISPAUD_DECON_INT_VCLK, 25, 1, 0);
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CLK_DIV(DISPAUD_DIV_CLK_DISPAUD_DECON_INT_ECLK, DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER, CLK_CON_DIV_CLK_DISPAUD_DECON_INT_ECLK, 0, 3, CLK_CON_DIV_CLK_DISPAUD_DECON_INT_ECLK, 25, 1, 0);
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CLK_DIV(DISPAUD_DIV_CLK_DISPAUD_MI2S, DISPAUD_MUX_AUD_PLL, CLK_CON_DIV_CLK_DISPAUD_MI2S, 0, 4, CLK_CON_DIV_CLK_DISPAUD_MI2S, 25, 1, 0);
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CLK_DIV(DISPAUD_DIV_CLK_DISPAUD_MIXER, DISPAUD_MUX_AUD_PLL, CLK_CON_DIV_CLK_DISPAUD_MIXER, 0, 4, CLK_CON_DIV_CLK_DISPAUD_MIXER, 25, 1, 0);
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CLK_DIV(DISPAUD_DIV_CLK_DISPAUD_OSCCLK_FM_52M_DIV, OSCCLK_FM_52M, CLK_CON_DIV_CLK_DISPAUD_OSCCLK_FM_52M_DIV, 0, 11, CLK_CON_DIV_CLK_DISPAUD_OSCCLK_FM_52M_DIV, 25, 1, 0);
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CLK_DIV(G3D_DIV_CLK_G3D_BUS, G3D_MUX_CLKCMU_G3D_USER, CLK_CON_DIV_CLK_G3D_BUS, 0, 3, CLK_CON_DIV_CLK_G3D_BUS, 25, 1, 0);
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CLK_DIV(G3D_DIV_CLK_G3D_APB, G3D_DIV_CLK_G3D_BUS, CLK_CON_DIV_CLK_G3D_APB, 0, 3, CLK_CON_DIV_CLK_G3D_APB, 25, 1, 0);
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CLK_DIV(ISP_DIV_CLK_ISP_CAM_HALF, ISP_MUX_CLKCMU_ISP_CAM_USER, CLK_CON_DIV_CLK_ISP_CAM_HALF, 0, 2, CLK_CON_DIV_CLK_ISP_CAM_HALF, 25, 1, 0);
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CLK_DIV(MFCMSCL_DIV_CLK_MFCMSCL_APB, MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER, CLK_CON_DIV_CLK_MFCMSCL_APB, 0, 2, CLK_CON_DIV_CLK_MFCMSCL_APB, 25, 1, 0);
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CLK_DIV(MIF_DIV_CLK_MIF_PHY_CLK2X, MIF_MUX_CLK_MIF_PHY_CLK_B, CLK_CON_DIV_CLK_MIF_PHY_CLK2X, 0, 4, CLK_CON_DIV_CLK_MIF_PHY_CLK2X, 25, 1, 0);
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CLK_DIV(MIF_DIV_CLK_MIF_PHY_CLKM, MIF_MUX_CLK_MIF_PHY_CLK_B, CLK_CON_DIV_CLK_MIF_PHY_CLKM, 0, 4, CLK_CON_DIV_CLK_MIF_PHY_CLKM, 25, 1, 0);
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CLK_DIV(MIF_DIV_CLKCMU_CP_SHARED0_PLL, MIF_MUX_SHARED0_PLL, CLK_CON_DIV_CLKCMU_CP_SHARED0_PLL, 0, 4, CLK_CON_DIV_CLKCMU_CP_SHARED0_PLL, 25, 1, 0);
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CLK_DIV(MIF_DIV_CLKCMU_CP_SHARED1_PLL, MIF_MUX_SHARED1_PLL, CLK_CON_DIV_CLKCMU_CP_SHARED1_PLL, 0, 4, CLK_CON_DIV_CLKCMU_CP_SHARED1_PLL, 25, 1, 0);
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CLK_DIV(MIF_DIV_CLKCMU_CP_SHARED2_PLL, MIF_MUX_SHARED2_PLL, CLK_CON_DIV_CLKCMU_CP_SHARED2_PLL, 0, 4, CLK_CON_DIV_CLKCMU_CP_SHARED2_PLL, 25, 1, 0);
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CLK_DIV(MIF_DIV_CLK_MIF_BUSD, MIF_MUX_CLK_MIF_BUSD, CLK_CON_DIV_CLK_MIF_BUSD, 0, 4, CLK_CON_DIV_CLK_MIF_BUSD, 25, 1, 0);
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CLK_DIV(MIF_DIV_CLK_MIF_APB, MIF_DIV_CLK_MIF_BUSD, CLK_CON_DIV_CLK_MIF_APB, 0, 2, CLK_CON_DIV_CLK_MIF_APB, 25, 1, 0);
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CLK_DIV(MIF_DIV_CLKCMU_CPUCL0_SWITCH, MIF_FF_SHARED0_PLL_DIV2, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 2, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 25, 1, 0);
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CLK_DIV(MIF_DIV_CLKCMU_G3D, MIF_MUX_CLKCMU_G3D, CLK_CON_DIV_CLKCMU_G3D, 0, 4, CLK_CON_DIV_CLKCMU_G3D, 25, 1, 0);
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CLK_DIV(MIF_DIV_CLKCMU_ISP_VRA, MIF_MUX_CLKCMU_ISP_VRA, CLK_CON_DIV_CLKCMU_ISP_VRA, 0, 4, CLK_CON_DIV_CLKCMU_ISP_VRA, 25, 1, MIF_MUXGATE_CLKCMU_ISP_VRA);
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CLK_DIV(MIF_DIV_CLKCMU_ISP_CAM, MIF_MUX_CLKCMU_ISP_CAM, CLK_CON_DIV_CLKCMU_ISP_CAM, 0, 4, CLK_CON_DIV_CLKCMU_ISP_CAM, 25, 1, MIF_MUXGATE_CLKCMU_ISP_CAM);
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CLK_DIV(MIF_DIV_CLKCMU_DISPAUD_BUS, MIF_MUX_CLKCMU_DISPAUD_BUS, CLK_CON_DIV_CLKCMU_DISPAUD_BUS, 0, 4, CLK_CON_DIV_CLKCMU_DISPAUD_BUS, 25, 1, MIF_MUXGATE_CLKCMU_DISPAUD_BUS);
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CLK_DIV(MIF_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK, MIF_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK, CLK_CON_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK, 0, 4, CLK_CON_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK, 25, 1, MIF_MUXGATE_CLKCMU_DISPAUD_DECON_INT_VCLK);
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CLK_DIV(MIF_DIV_CLKCMU_MFCMSCL_MSCL, MIF_MUX_CLKCMU_MFCMSCL_MSCL, CLK_CON_DIV_CLKCMU_MFCMSCL_MSCL, 0, 4, CLK_CON_DIV_CLKCMU_MFCMSCL_MSCL, 25, 1, MIF_MUXGATE_CLKCMU_MFCMSCL_MSCL);
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CLK_DIV(MIF_DIV_CLKCMU_MFCMSCL_MFC, MIF_MUX_CLKCMU_MFCMSCL_MFC, CLK_CON_DIV_CLKCMU_MFCMSCL_MFC, 0, 4, CLK_CON_DIV_CLKCMU_MFCMSCL_MFC, 25, 1, MIF_MUXGATE_CLKCMU_MFCMSCL_MFC);
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CLK_DIV(MIF_DIV_CLKCMU_FSYS_BUS, MIF_MUX_CLKCMU_FSYS_BUS, CLK_CON_DIV_CLKCMU_FSYS_BUS, 0, 4, CLK_CON_DIV_CLKCMU_FSYS_BUS, 25, 1, MIF_MUXGATE_CLKCMU_FSYS_BUS);
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CLK_DIV(MIF_DIV_CLKCMU_FSYS_MMC0, MIF_MUX_CLKCMU_FSYS_MMC0, CLK_CON_DIV_CLKCMU_FSYS_MMC0, 0, 10, CLK_CON_DIV_CLKCMU_FSYS_MMC0, 25, 1, MIF_MUXGATE_CLKCMU_FSYS_MMC0);
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CLK_DIV(MIF_DIV_CLKCMU_FSYS_MMC2, MIF_MUX_CLKCMU_FSYS_MMC2, CLK_CON_DIV_CLKCMU_FSYS_MMC2, 0, 10, CLK_CON_DIV_CLKCMU_FSYS_MMC2, 25, 1, MIF_MUXGATE_CLKCMU_FSYS_MMC2);
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CLK_DIV(MIF_DIV_CLKCMU_FSYS_USB20DRD_REFCLK, MIF_MUX_CLKCMU_FSYS_USB20DRD_REFCLK, CLK_CON_DIV_CLKCMU_FSYS_USB20DRD_REFCLK, 0, 4, CLK_CON_DIV_CLKCMU_FSYS_USB20DRD_REFCLK, 25, 1, MIF_MUXGATE_CLKCMU_FSYS_MMC2);
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CLK_DIV(MIF_DIV_CLKCMU_PERI_BUS, MIF_MUX_CLKCMU_PERI_BUS, CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4, CLK_CON_DIV_CLKCMU_PERI_BUS, 25, 1, MIF_MUXGATE_CLKCMU_PERI_BUS);
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CLK_DIV(MIF_DIV_CLKCMU_PERI_UART_DEBUG, MIF_MUX_CLKCMU_PERI_UART_DEBUG, CLK_CON_DIV_CLKCMU_PERI_UART_DEBUG, 0, 4, CLK_CON_DIV_CLKCMU_PERI_UART_DEBUG, 25, 1, MIF_MUXGATE_CLKCMU_PERI_UART_DEBUG);
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CLK_DIV(MIF_DIV_CLKCMU_PERI_UART_SENSOR, MIF_MUX_CLKCMU_PERI_UART_SENSOR, CLK_CON_DIV_CLKCMU_PERI_UART_SENSOR, 0, 4, CLK_CON_DIV_CLKCMU_PERI_UART_SENSOR, 25, 1, MIF_MUXGATE_CLKCMU_PERI_UART_SENSOR);
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CLK_DIV(MIF_DIV_CLKCMU_PERI_SPI_REARFROM, MIF_MUX_CLKCMU_PERI_SPI_REARFROM, CLK_CON_DIV_CLKCMU_PERI_SPI_REARFROM, 0, 6, CLK_CON_DIV_CLKCMU_PERI_SPI_REARFROM, 25, 1, MIF_MUXGATE_CLKCMU_PERI_SPI_REARFROM);
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CLK_DIV(MIF_DIV_CLKCMU_PERI_SPI_ESE, MIF_MUX_CLKCMU_PERI_SPI_ESE, CLK_CON_DIV_CLKCMU_PERI_SPI_ESE, 0, 6, CLK_CON_DIV_CLKCMU_PERI_SPI_ESE, 25, 1, MIF_MUXGATE_CLKCMU_PERI_SPI_ESE);
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CLK_DIV(MIF_DIV_CLKCMU_PERI_USI_0, MIF_MUX_CLKCMU_PERI_USI_0, CLK_CON_DIV_CLKCMU_PERI_USI_0, 0, 6, CLK_CON_DIV_CLKCMU_PERI_USI_0, 25, 1, MIF_MUXGATE_CLKCMU_PERI_USI_0);
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CLK_DIV(MIF_DIV_CLKCMU_PERI_USI_1, MIF_MUX_CLKCMU_PERI_USI_1, CLK_CON_DIV_CLKCMU_PERI_USI_1, 0, 6, CLK_CON_DIV_CLKCMU_PERI_USI_1, 25, 1, MIF_MUXGATE_CLKCMU_PERI_USI_1);
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CLK_DIV(MIF_DIV_CLKCMU_APM, MIF_MUX_CLKCMU_APM, CLK_CON_DIV_CLKCMU_APM, 0, 4, CLK_CON_DIV_CLKCMU_APM, 25, 1, MIF_MUXGATE_CLKCMU_APM);
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CLK_DIV(MIF_DIV_CLKCMU_ISP_SENSOR0, MIF_MUX_CLKCMU_ISP_SENSOR0, CLK_CON_DIV_CLKCMU_ISP_SENSOR0, 0, 6, CLK_CON_DIV_CLKCMU_ISP_SENSOR0, 25, 1, MIF_MUXGATE_CLKCMU_ISP_SENSOR0);
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CLK_DIV(MIF_DIV_CLKCMU_GNSS_EXTPLL_SCAN, /* NOT DESCRIPTED ON DIAGRAM, SO OSCCLK */OSCCLK, CLK_CON_DIV_CLKCMU_GNSS_EXTPLL_SCAN, 0, 1, CLK_CON_DIV_CLKCMU_GNSS_EXTPLL_SCAN, 25, 1, 0);
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CLK_DIV(PERI_DIV_CLK_PERI_USI_0_SPI, MIF_GATE_CLKCMU_PERI_USI_0, CLK_CON_DIV_CLK_PERI_USI_0_SPI, 0, 2, CLK_CON_DIV_CLK_PERI_USI_0_SPI, 25, 1, 0);
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CLK_DIV(PERI_DIV_CLK_PERI_USI_1_SPI, MIF_GATE_CLKCMU_PERI_USI_1, CLK_CON_DIV_CLK_PERI_USI_1_SPI, 0, 2, CLK_CON_DIV_CLK_PERI_USI_1_SPI, 25, 1, 0);
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CLK_GATE(APM_GATE_CLK_APM_UID_APM_IPCLKPORT_ACLK_SYS, APM_MUX_CLKCMU_APM_USER, CLK_ENABLE_CLKCMU_APM_USER, 3);
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CLK_GATE(APM_GATE_CLK_APM_UID_APM_IPCLKPORT_ACLK_CPU, APM_MUX_CLKCMU_APM_USER, CLK_ENABLE_CLKCMU_APM_USER, 2);
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CLK_GATE(APM_GATE_CLK_APM_UID_ASYNCS_APM_IPCLKPORT_I_CLK, APM_MUX_CLKCMU_APM_USER, CLK_ENABLE_CLKCMU_APM_USER, 1);
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CLK_GATE(APM_GATE_CLK_APM_UID_ASYNCM_APM_IPCLKPORT_I_CLK, APM_MUX_CLKCMU_APM_USER, CLK_ENABLE_CLKCMU_APM_USER, 0);
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CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_CLK, OSCCLK, CLK_ENABLE_CLK_CPUCL0_OSCCLK, 1);
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CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_I_CLK__PMU_CPUCL0, OSCCLK, CLK_ENABLE_CLK_CPUCL0_OSCCLK, 0);
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CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_D_CPUCL0_IPCLKPORT_I_CLK, CPUCL0_DIV_CLK_CPUCL0_ACLK, CLK_ENABLE_CLK_CPUCL0_ACLK, 0);
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CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, CPUCL0_DIV_CLK_CPUCL0_PCLK, CLK_ENABLE_CLK_CPUCL0_PCLK, 5);
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CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_PCLK, CPUCL0_DIV_CLK_CPUCL0_PCLK, CLK_ENABLE_CLK_CPUCL0_PCLK, 4);
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CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_I_PCLK, CPUCL0_DIV_CLK_CPUCL0_PCLK, CLK_ENABLE_CLK_CPUCL0_PCLK, 3);
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CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK, CPUCL0_DIV_CLK_CPUCL0_PCLK, CLK_ENABLE_CLK_CPUCL0_PCLK, 2);
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CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_BUSP1_CPUCL0_IPCLKPORT_ACLK, CPUCL0_DIV_CLK_CPUCL0_PCLK, CLK_ENABLE_CLK_CPUCL0_PCLK, 1);
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CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCM_P_CPUCL0_IPCLKPORT_I_CLK, CPUCL0_DIV_CLK_CPUCL0_PCLK, CLK_ENABLE_CLK_CPUCL0_PCLK, 0);
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CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_ATCLK, CPUCL0_DIV_CLK_CPUCL0_ATCLK, CLK_ENABLE_CLK_CPUCL0_ATCLK, 0);
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CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_SECJTAG_IPCLKPORT_i_clk, CPUCL0_DIV_CLK_CPUCL0_PCLKDBG, CLK_ENABLE_CLK_CPUCL0_PCLKDBG, 6);
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CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLKDBG, CPUCL0_DIV_CLK_CPUCL0_PCLKDBG, CLK_ENABLE_CLK_CPUCL0_PCLKDBG, 5);
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CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_DBG_MUX_CPUCL0_IPCLKPORT_I_CLK, CPUCL0_DIV_CLK_CPUCL0_PCLKDBG, CLK_ENABLE_CLK_CPUCL0_PCLKDBG, 4);
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CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG, CPUCL0_DIV_CLK_CPUCL0_PCLKDBG, CLK_ENABLE_CLK_CPUCL0_PCLKDBG, 3);
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CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_CSSYS_DBG_IPCLKPORT_PCLKS, CPUCL0_DIV_CLK_CPUCL0_PCLKDBG, CLK_ENABLE_CLK_CPUCL0_PCLKDBG, 2);
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CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_T_CSSYS_DBG_IPCLKPORT_ACLK, CPUCL0_DIV_CLK_CPUCL0_PCLKDBG, CLK_ENABLE_CLK_CPUCL0_PCLKDBG, 1);
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CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCM_P_CSSYS_DBG_IPCLKPORT_PCLKM, CPUCL0_DIV_CLK_CPUCL0_PCLKDBG, CLK_ENABLE_CLK_CPUCL0_PCLKDBG, 0);
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CLK_GATE(CPUCL0_GATE_CLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_I_HPM_TARGETCLK_C, CPUCL0_DIV_CLK_CPUCL0_HPM, CLK_ENABLE_CLK_CPUCL0_HPM, 0);
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CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_OSCCLK, OSCCLK, CLK_ENABLE_CLK_DISPAUD_OSCCLK, 0);
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CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_PPMU, DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER, CLK_ENABLE_CLK_DISPAUD_BUS, 3);
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CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_DISP, DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER, CLK_ENABLE_CLK_DISPAUD_BUS, 2);
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CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_VPP, DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER, CLK_ENABLE_CLK_DISPAUD_BUS, 1);
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CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS, DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER, CLK_ENABLE_CLK_DISPAUD_BUS, 0);
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CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_FM, DISPAUD_DIV_CLK_DISPAUD_APB, CLK_ENABLE_CLK_DISPAUD_APB, 4);
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CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD_AMP, DISPAUD_DIV_CLK_DISPAUD_APB, CLK_ENABLE_CLK_DISPAUD_APB, 3);
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CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD, DISPAUD_DIV_CLK_DISPAUD_APB, CLK_ENABLE_CLK_DISPAUD_APB, 2);
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CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_DISP, DISPAUD_DIV_CLK_DISPAUD_APB, CLK_ENABLE_CLK_DISPAUD_APB, 1);
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CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB, DISPAUD_DIV_CLK_DISPAUD_APB, CLK_ENABLE_CLK_DISPAUD_APB, 0);
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CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_APB_SECURE_SMMU_DISP, DISPAUD_DIV_CLK_DISPAUD_APB, CLK_ENABLE_CLK_DISPAUD_APB_SECURE_SMMU_DISP, 0);
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CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_VCLK, DISPAUD_DIV_CLK_DISPAUD_DECON_INT_VCLK, CLK_ENABLE_CLK_DISPAUD_DECON_INT_VCLK, 0);
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CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_DSIM0_IPCLKPORT_I_TXBYTECLKHS, DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER, CLK_ENABLE_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS, 0);
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CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_DSIM0_IPCLKPORT_I_RXCLKESC0, DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER, CLK_ENABLE_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0, 0);
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CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AMP_IPCLKPORT_I2SCODCLKI, DISPAUD_DIV_CLK_DISPAUD_MI2S, CLK_ENABLE_CLK_DISPAUD_MI2S, 1);
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CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AUD_IPCLKPORT_I2SCODCLKI, DISPAUD_DIV_CLK_DISPAUD_MI2S, CLK_ENABLE_CLK_DISPAUD_MI2S, 0);
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CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_MIXER_AUD_IPCLKPORT_SYSCLK, DISPAUD_DIV_CLK_DISPAUD_MIXER, CLK_ENABLE_CLK_DISPAUD_MIXER, 0);
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CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_CP2AUD_BCK, CLKIO_DISPAUD_MIXER_BCLK_CP, CLK_ENABLE_CLKIO_DISPAUD_MIXER_BCLK_CP, 0);
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CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_OSCCLK_FM_52M, OSCCLK_FM_52M, CLK_ENABLE_CLK_OSCCLK_FM_52M, 0);
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CLK_GATE(DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_OSCCLK_FM_52M_DIV, DISPAUD_DIV_CLK_DISPAUD_OSCCLK_FM_52M_DIV, CLK_ENABLE_CLK_OSCCLK_FM_52M_DIV, 0);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_CLK, /* CLK_FSYS_*/OSCCLK, CLK_ENABLE_CLK_FSYS_OSCCLK, 1);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_PMU_FSYS_IPCLKPORT_I_CLK__PMU_FSYS, /* CLK_FSYS_*/OSCCLK, CLK_ENABLE_CLK_FSYS_OSCCLK, 0);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_BUSD1_FSYS_IPCLKPORT_ACLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 24);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_BUSD0_FSYS_IPCLKPORT_ACLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 23);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HCLK_USB20_CTRL, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 21);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_HSDRD, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 20);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 19);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 18);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 17);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_PMU_FSYS_IPCLKPORT_I_PCLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 16);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_ASYNCS_D_FSYS_IPCLKPORT_I_CLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 15);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_ASYNCM_P_FSYS_IPCLKPORT_I_CLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 14);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 13);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 10);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 8);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_BR_BUSP1_FSYS_IPCLKPORT_aclk, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 5);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_BUSP5_FSYS_IPCLKPORT_HCLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 3);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_BUSP3_FSYS_IPCLKPORT_HCLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 2);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_BUSP2_FSYS_IPCLKPORT_HCLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 1);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_BUSP1_FSYS_IPCLKPORT_HCLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_BUS, 0);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_RTIC_IPCLKPORT_i_PCLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_SECURE_RTIC, 1);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_RTIC_IPCLKPORT_i_ACLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_SECURE_RTIC, 0);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_SSS_IPCLKPORT_i_PCLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_SECURE_SSS, 1);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_SSS_IPCLKPORT_i_ACLK, MIF_GATE_CLKCMU_FSYS_BUS, CLK_ENABLE_CLK_FSYS_SECURE_SSS, 0);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN, MIF_GATE_CLKCMU_FSYS_MMC0/*MMC_EMBD*/, CLK_ENABLE_CLK_FSYS_MMC_EMBD, 0);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN, MIF_GATE_CLKCMU_FSYS_MMC2/*MMC_CARD*/, CLK_ENABLE_CLK_FSYS_MMC_CARD, 0);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_ref_clk, MIF_GATE_CLKCMU_FSYS_USB20DRD_REFCLK, CLK_ENABLE_CLK_FSYS_USB20DRD_REFCLK, 0);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_PHYCLOCK, FSYS_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER, CLK_ENABLE_CLKPHY_FSYS_USB20DRD_PHYCLOCK, 0);
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CLK_GATE(FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_USB20_CLKCORE_0, WPLL_USB_PLL/*WIFI2AP_USBPLL_CLK*/, CLK_ENABLE_CLK_FSYS_USB20PHY_CLKCORE, 0);
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CLK_GATE(G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_CLK, /*CLK_G3D_*/OSCCLK, CLK_ENABLE_CLK_G3D_OSCCLK, 1);
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CLK_GATE(G3D_GATE_CLK_G3D_UID_PMU_G3D_IPCLKPORT_I_CLK__PMU_G3D, /*CLK_G3D_*/OSCCLK, CLK_ENABLE_CLK_G3D_OSCCLK, 0);
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CLK_GATE(G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_ACLK, G3D_DIV_CLK_G3D_BUS, CLK_ENABLE_CLK_G3D_BUS, 8);
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CLK_GATE(G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_ACLK, G3D_DIV_CLK_G3D_BUS, CLK_ENABLE_CLK_G3D_BUS, 7);
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CLK_GATE(G3D_GATE_CLK_G3D_UID_G3D_IPCLKPORT_CLK, G3D_DIV_CLK_G3D_BUS, CLK_ENABLE_CLK_G3D_BUS, 6);
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CLK_GATE(G3D_GATE_CLK_G3D_UID_REGSLICE_D1_G3D_IPCLKPORT_aclk, G3D_DIV_CLK_G3D_BUS, CLK_ENABLE_CLK_G3D_BUS, 5);
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CLK_GATE(G3D_GATE_CLK_G3D_UID_REGSLICE_D0_G3D_IPCLKPORT_aclk, G3D_DIV_CLK_G3D_BUS, CLK_ENABLE_CLK_G3D_BUS, 4);
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CLK_GATE(G3D_GATE_CLK_G3D_UID_IXIU_D_G3D_IPCLKPORT_ACLK, G3D_DIV_CLK_G3D_BUS, CLK_ENABLE_CLK_G3D_BUS, 3);
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CLK_GATE(G3D_GATE_CLK_G3D_UID_ASYNCS_D1_G3D_IPCLKPORT_I_CLK, G3D_DIV_CLK_G3D_BUS, CLK_ENABLE_CLK_G3D_BUS, 2);
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CLK_GATE(G3D_GATE_CLK_G3D_UID_ASYNCS_D0_G3D_IPCLKPORT_I_CLK, G3D_DIV_CLK_G3D_BUS, CLK_ENABLE_CLK_G3D_BUS, 1);
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CLK_GATE(G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKM, G3D_DIV_CLK_G3D_BUS, CLK_ENABLE_CLK_G3D_BUS, 0);
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CLK_GATE(G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, G3D_DIV_CLK_G3D_APB, CLK_ENABLE_CLK_G3D_APB, 6);
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CLK_GATE(G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_PCLK, G3D_DIV_CLK_G3D_APB, CLK_ENABLE_CLK_G3D_APB, 5);
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CLK_GATE(G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_PCLK, G3D_DIV_CLK_G3D_APB, CLK_ENABLE_CLK_G3D_APB, 4);
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CLK_GATE(G3D_GATE_CLK_G3D_UID_PMU_G3D_IPCLKPORT_I_PCLK, G3D_DIV_CLK_G3D_APB, CLK_ENABLE_CLK_G3D_APB, 3);
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CLK_GATE(G3D_GATE_CLK_G3D_UID_BUSP_G3D_IPCLKPORT_ACLK, G3D_DIV_CLK_G3D_APB, CLK_ENABLE_CLK_G3D_APB, 2);
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CLK_GATE(G3D_GATE_CLK_G3D_UID_ASYNCM_P_G3D_IPCLKPORT_I_CLK, G3D_DIV_CLK_G3D_APB, CLK_ENABLE_CLK_G3D_APB, 1);
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CLK_GATE(G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKS, G3D_DIV_CLK_G3D_APB, CLK_ENABLE_CLK_G3D_APB, 0);
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CLK_GATE(G3D_GATE_CLK_G3D_UID_CFW_G3D_IPCLKPORT_ACLK, G3D_DIV_CLK_G3D_BUS, CLK_ENABLE_CLK_G3D_BUS_SECURE_CFW_G3D, 0);
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CLK_GATE(G3D_GATE_CLK_G3D_UID_CFW_G3D_IPCLKPORT_PCLK, G3D_DIV_CLK_G3D_APB, CLK_ENABLE_CLK_G3D_APB_SECURE_CFW_G3D, 0);
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CLK_GATE(ISP_GATE_CLK_ISP_UID_CLK_ISP_OSCCLK, /*CLK_ISP_*/OSCCLK, CLK_ENABLE_CLK_ISP_OSCCLK, 0);
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CLK_GATE(ISP_GATE_CLK_ISP_UID_CLK_ISP_VRA, ISP_MUX_CLKCMU_ISP_VRA_USER, CLK_ENABLE_CLK_ISP_VRA, 0);
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CLK_GATE(ISP_GATE_CLK_ISP_UID_CLK_ISP_CAM, ISP_MUX_CLKCMU_ISP_CAM_USER, CLK_ENABLE_CLK_ISP_CAM, 0);
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CLK_GATE(ISP_GATE_CLK_ISP_UID_CLKPHY_ISP_S_RXBYTECLKHS0_S4, ISP_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER, CLK_ENABLE_CLKPHY_ISP_S_RXBYTECLKHS0_S4, 0);
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CLK_GATE(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLK_MFCMSCL_OSCCLK, /*CLK_MFCMSCL_*/OSCCLK, CLK_ENABLE_CLK_MFCMSCL_OSCCLK, 0);
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CLK_GATE(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_BI, MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER, CLK_ENABLE_CLK_MFCMSCL_MSCL, 0);
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CLK_GATE(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_D, MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER, CLK_ENABLE_CLK_MFCMSCL_MFC, 3);
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CLK_GATE(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_JPEG, MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER, CLK_ENABLE_CLK_MFCMSCL_MFC, 2);
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CLK_GATE(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_POLY, MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER, CLK_ENABLE_CLK_MFCMSCL_MFC, 1);
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CLK_GATE(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_MFC, MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER, CLK_ENABLE_CLK_MFCMSCL_MFC, 0);
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CLK_GATE(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLK_MFCMSCL_APB, MFCMSCL_DIV_CLK_MFCMSCL_APB, CLK_ENABLE_CLK_MFCMSCL_APB, 0);
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CLK_GATE(MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_APB_SMMU_MSCL, MFCMSCL_DIV_CLK_MFCMSCL_APB/*_SMMU_MSCL*/, CLK_ENABLE_CLK_MFCMSCL_APB_SMMU_MSCL, 0);
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CLK_GATE(MIF_GATE_CLK_MIF_UID_OTP_DESERIAL_MIF_IPCLKPORT_I_CLK, /*CLK_MIF_*/OSCCLK, CLK_ENABLE_CLK_MIF_OSCCLK, 4);
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CLK_GATE(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_RCLK, /*CLK_MIF_*/OSCCLK, CLK_ENABLE_CLK_MIF_OSCCLK, 3);
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CLK_GATE(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_I_OSC_SYS, /*CLK_MIF_*/OSCCLK, CLK_ENABLE_CLK_MIF_OSCCLK, 2);
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CLK_GATE(MIF_GATE_CLK_MIF_UID_SYSREG_MIF_IPCLKPORT_CLK, /*CLK_MIF_*/OSCCLK, CLK_ENABLE_CLK_MIF_OSCCLK, 1);
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CLK_GATE(MIF_GATE_CLK_MIF_UID_PMU_MIF_IPCLKPORT_I_CLK__PMU_MIF_JV, /*CLK_MIF_*/OSCCLK, CLK_ENABLE_CLK_MIF_OSCCLK, 0);
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CLK_GATE(MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_clk, MIF_DIV_CLK_MIF_PHY_CLK2X, CLK_ENABLE_CLK_MIF_PHY_CLK2X, 0);
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CLK_GATE(MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_clkm, MIF_DIV_CLK_MIF_PHY_CLKM, CLK_ENABLE_CLK_MIF_PHY_CLKM, 0);
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CLK_GATE(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_APB_ACLK, CLK_MIF_DDRPHY0/*FROM DDRPHY*/, CLK_ENABLE_CLK_MIF_DDRPHY0, 14);
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CLK_GATE(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_SECURE_APB_ACLK, CLK_MIF_DDRPHY0, CLK_ENABLE_CLK_MIF_DDRPHY0, 13);
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CLK_GATE(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PEREV_CLK, CLK_MIF_DDRPHY0, CLK_ENABLE_CLK_MIF_DDRPHY0, 12);
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CLK_GATE(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_MEMIF_WR_CLK, CLK_MIF_DDRPHY0, CLK_ENABLE_CLK_MIF_DDRPHY0, 11);
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CLK_GATE(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_MEMIF_RD_CLK, CLK_MIF_DDRPHY0, CLK_ENABLE_CLK_MIF_DDRPHY0, 10);
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CLK_GATE(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_MEMIF_CLK, CLK_MIF_DDRPHY0, CLK_ENABLE_CLK_MIF_DDRPHY0, 9);
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CLK_GATE(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_SCH_SLICE1_CLK, CLK_MIF_DDRPHY0, CLK_ENABLE_CLK_MIF_DDRPHY0, 8);
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CLK_GATE(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_SCH_SLICE0_CLK, CLK_MIF_DDRPHY0, CLK_ENABLE_CLK_MIF_DDRPHY0, 7);
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CLK_GATE(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_SCH_CLK, CLK_MIF_DDRPHY0, CLK_ENABLE_CLK_MIF_DDRPHY0, 6);
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CLK_GATE(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_VCF_WR_CLK, CLK_MIF_DDRPHY0, CLK_ENABLE_CLK_MIF_DDRPHY0, 5);
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CLK_GATE(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_VCF_RD_CLK, CLK_MIF_DDRPHY0, CLK_ENABLE_CLK_MIF_DDRPHY0, 4);
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CLK_GATE(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_VCF_CLK, CLK_MIF_DDRPHY0, CLK_ENABLE_CLK_MIF_DDRPHY0, 3);
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CLK_GATE(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_ACLK, CLK_MIF_DDRPHY0, CLK_ENABLE_CLK_MIF_DDRPHY0, 2);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_PPMU_CPU_IPCLKPORT_ACLK, CLK_MIF_DDRPHY0, CLK_ENABLE_CLK_MIF_DDRPHY0, 1);
|
|
CLK_GATE(MIF_GATE_CLK_MIF_UID_QE_DMC0_CPU_IPCLKPORT_ACLK, CLK_MIF_DDRPHY0, CLK_ENABLE_CLK_MIF_DDRPHY0, 0);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNCM_CPUCL0_IPCLKPORT_ACLK, MIF_DIV_CLK_MIF_BUSD, CLK_ENABLE_CLK_MIF_BUSD, 8);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNCM_DBG_IPCLKPORT_ACLK, MIF_DIV_CLK_MIF_BUSD, CLK_ENABLE_CLK_MIF_BUSD, 6);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_PDMA_MIF_IPCLKPORT_ACLK_PDMA0, MIF_DIV_CLK_MIF_BUSD, CLK_ENABLE_CLK_MIF_BUSD, 5);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_CLEANY_WLBT_IPCLKPORT_ACLK, MIF_DIV_CLK_MIF_BUSD, CLK_ENABLE_CLK_MIF_BUSD, 3);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_CLEANY_GNSS_IPCLKPORT_ACLK, MIF_DIV_CLK_MIF_BUSD, CLK_ENABLE_CLK_MIF_BUSD, 2);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_CLEANY_CEL_IPCLKPORT_ACLK, MIF_DIV_CLK_MIF_BUSD, CLK_ENABLE_CLK_MIF_BUSD, 1);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_CPU0_MO_MON_IPCLKPORT_I_ACLK, MIF_DIV_CLK_MIF_BUSD, CLK_ENABLE_CLK_MIF_BUSD, 0);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_PPMU_CPU_IPCLKPORT_PCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 29);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_SPEEDY_BATCHER_WRAPPER_IPCLKPORT_PCLK_BATCHER_SPEEDY, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 28);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_SPEEDY_BATCHER_WRAPPER_IPCLKPORT_PCLK_BATCHER_CP, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 27);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_SPEEDY_BATCHER_WRAPPER_IPCLKPORT_PCLK_BATCHER_AP, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 26);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_SPEEDY_MIF_IPCLKPORT_PCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 25);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_MAILBOX_WLBT_IPCLKPORT_CLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 24);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_MAILBOX_GNSS_IPCLKPORT_CLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 23);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_MAILBOX_CEL_IPCLKPORT_CLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 22);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_ASYNCAPB_MIF_CSSYS_IPCLKPORT_PCLKS, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 21);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_SYNC_INTC_SOC_IPCLKPORT_CLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 20);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_INTC_SOC_IPCLKPORT_CLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 19);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_AXI2APB_MIF_TREX_IPCLKPORT_ACLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 18);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_AXI2AHB_MIF_P_IPCLKPORT_HCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 17);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_AHB2APB_MIF2_IPCLKPORT_HCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 16);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_AHB2APB_MIF1_IPCLKPORT_HCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 15);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_AHB2APB_MIF0_IPCLKPORT_HCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 14);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_AHB_BRIDGE_MIF_IPCLKPORT_HCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 13);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_QE_DMC0_CPU_IPCLKPORT_PCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 12);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_DDRDMC0_APB_IPCLKPORT_PCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 11);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_PF, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 10);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 9);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_PCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 6);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 5);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 4);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_GPIO_MIF_IPCLKPORT_PCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 2);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 1);
|
|
CLK_GATE(MIF_GATE_CLK_MIF_UID_PMU_MIF_IPCLKPORT_I_PCLK, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB, 0);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_PF_SECURE, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB_SECURE_DMC0, 1);
|
|
CLK_GATE(MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_SECURE, MIF_DIV_CLK_MIF_APB, CLK_ENABLE_CLK_MIF_APB_SECURE_DMC0, 0);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_MAILBOX_SECURE_IPCLKPORT_CLK, MIF_DIV_CLK_MIF_APB/*_SECURE_MAILBOX_SECURE*/, CLK_ENABLE_CLK_MIF_APB_SECURE_MAILBOX_SECURE, 0);
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|
CLK_GATE(MIF_GATE_CLKCMU_CP_SHARED0_PLL, MIF_DIV_CLKCMU_CP_SHARED0_PLL, CLK_ENABLE_CLKCMU_CP_SHARED0_PLL, 0);
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|
CLK_GATE(MIF_GATE_CLKCMU_CP_SHARED1_PLL, MIF_DIV_CLKCMU_CP_SHARED1_PLL, CLK_ENABLE_CLKCMU_CP_SHARED1_PLL, 0);
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|
CLK_GATE(MIF_GATE_CLKCMU_CP_SHARED2_PLL, MIF_DIV_CLKCMU_CP_SHARED2_PLL, CLK_ENABLE_CLKCMU_CP_SHARED2_PLL, 0);
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|
CLK_GATE(MIF_GATE_CLKCMU_CPUCL0_SWITCH, MIF_DIV_CLKCMU_CPUCL0_SWITCH, CLK_ENABLE_CLKCMU_CPUCL0_SWITCH, 0);
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|
CLK_GATE(MIF_GATE_CLKCMU_G3D, MIF_DIV_CLKCMU_G3D, CLK_ENABLE_CLKCMU_G3D, 0);
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|
CLK_GATE(MIF_GATE_CLKCMU_ISP_VRA, MIF_DIV_CLKCMU_ISP_VRA, CLK_ENABLE_CLKCMU_ISP_VRA, 0);
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|
CLK_GATE(MIF_GATE_CLKCMU_ISP_CAM, MIF_DIV_CLKCMU_ISP_CAM, CLK_ENABLE_CLKCMU_ISP_CAM, 0);
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|
CLK_GATE(MIF_GATE_CLKCMU_DISPAUD_BUS, MIF_DIV_CLKCMU_DISPAUD_BUS, CLK_ENABLE_CLKCMU_DISPAUD_BUS, 0);
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|
CLK_GATE(MIF_GATE_CLKCMU_DISPAUD_DECON_INT_VCLK, MIF_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK, CLK_ENABLE_CLKCMU_DISPAUD_DECON_INT_VCLK, 0);
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|
CLK_GATE(MIF_GATE_CLKCMU_MFCMSCL_MFC, MIF_DIV_CLKCMU_MFCMSCL_MFC, CLK_ENABLE_CLKCMU_MFCMSCL_MFC, 0);
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|
CLK_GATE(MIF_GATE_CLKCMU_MFCMSCL_MSCL, MIF_DIV_CLKCMU_MFCMSCL_MSCL, CLK_ENABLE_CLKCMU_MFCMSCL_MSCL, 0);
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|
CLK_GATE(MIF_GATE_CLKCMU_FSYS_BUS, MIF_DIV_CLKCMU_FSYS_BUS, CLK_ENABLE_CLKCMU_FSYS_BUS, 0);
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|
CLK_GATE(MIF_GATE_CLKCMU_FSYS_MMC0, MIF_DIV_CLKCMU_FSYS_MMC0, CLK_ENABLE_CLKCMU_FSYS_MMC0, 0);
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|
CLK_GATE(MIF_GATE_CLKCMU_FSYS_MMC2, MIF_DIV_CLKCMU_FSYS_MMC2, CLK_ENABLE_CLKCMU_FSYS_MMC2, 0);
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|
CLK_GATE(MIF_GATE_CLKCMU_FSYS_USB20DRD_REFCLK, MIF_DIV_CLKCMU_FSYS_USB20DRD_REFCLK, CLK_ENABLE_CLKCMU_FSYS_USB20DRD_REFCLK, 0);
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|
CLK_GATE(MIF_GATE_CLKCMU_PERI_BUS, MIF_DIV_CLKCMU_PERI_BUS, CLK_ENABLE_CLKCMU_PERI_BUS, 0);
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|
CLK_GATE(MIF_GATE_CLKCMU_PERI_UART_DEBUG, MIF_DIV_CLKCMU_PERI_UART_DEBUG, CLK_ENABLE_CLKCMU_PERI_UART_DEBUG, 0);
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|
CLK_GATE(MIF_GATE_CLKCMU_PERI_UART_SENSOR, MIF_DIV_CLKCMU_PERI_UART_SENSOR, CLK_ENABLE_CLKCMU_PERI_UART_SENSOR, 0);
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|
CLK_GATE(MIF_GATE_CLKCMU_PERI_SPI_REARFROM, MIF_DIV_CLKCMU_PERI_SPI_REARFROM, CLK_ENABLE_CLKCMU_PERI_SPI_REARFROM, 0);
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|
CLK_GATE(MIF_GATE_CLKCMU_PERI_SPI_ESE, MIF_DIV_CLKCMU_PERI_SPI_ESE, CLK_ENABLE_CLKCMU_PERI_SPI_ESE, 0);
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|
CLK_GATE(MIF_GATE_CLKCMU_PERI_USI_0, MIF_DIV_CLKCMU_PERI_USI_0, CLK_ENABLE_CLKCMU_PERI_USI_0, 0);
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|
CLK_GATE(MIF_GATE_CLKCMU_PERI_USI_1, MIF_DIV_CLKCMU_PERI_USI_1, CLK_ENABLE_CLKCMU_PERI_USI_1, 0);
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|
CLK_GATE(MIF_GATE_CLKCMU_APM, MIF_DIV_CLKCMU_APM, CLK_ENABLE_CLKCMU_APM, 0);
|
|
CLK_GATE(MIF_GATE_CLKCMU_ISP_SENSOR0, MIF_DIV_CLKCMU_ISP_SENSOR0, CLK_ENABLE_CLKCMU_ISP_SENSOR0, 0);
|
|
CLK_GATE(MIF_GATE_CLKCMU_GNSS_TEST_EXTPLL_SCAN_CLK, MIF_DIV_CLKCMU_GNSS_EXTPLL_SCAN, CLK_ENABLE_CLKCMU_GNSS_EXTPLL_SCAN, 0);
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|
CLK_GATE(MIF_GATE_CLK_MIF_UID_SPEEDY_MIF_IPCLKPORT_CLK, /*CLK_MIF_*/TCXO, CLK_ENABLE_CLK_MIF_TCXO, 0);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_TMU_CPUCL0_IPCLKPORT_I_CLK, /*CLK_PERI_*/OSCCLK, CLK_ENABLE_CLK_PERI_OSCCLK, 4);
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|
CLK_GATE(PERI_GATE_CLK_PERI_UID_SYSREG_PERI_IPCLKPORT_CLK, /*CLK_PERI_*/OSCCLK, CLK_ENABLE_CLK_PERI_OSCCLK, 3);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_OSCCLK, /*CLK_PERI_*/OSCCLK, CLK_ENABLE_CLK_PERI_OSCCLK, 2);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_PMU_PERI_IPCLKPORT_I_CLK__PMU_PERI, /*CLK_PERI_*/OSCCLK, CLK_ENABLE_CLK_PERI_OSCCLK, 0);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_CHIPID_IPCLKPORT_CLK, /*CLK_PERI_*/OSCCLK/*_SECURE_CHIPID*/, CLK_ENABLE_CLK_PERI_OSCCLK_SECURE_CHIPID, 0);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_PCLK_S0, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 29);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_PMU_PERI_IPCLKPORT_I_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 27);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_MCT_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 26);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_I2C_SENSOR2_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 25);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_I2C_SENSOR1_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 24);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_I2C_TSP_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 23);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_I2C_FUELGAUGE_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 21);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_I2C_NFC_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 19);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_I2C_MUIC_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 18);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_HSI2C_FRONTCAM_IPCLKPORT_iPCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 16);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_HSI2C_MAINCAM_IPCLKPORT_iPCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 15);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_HSI2C_FRONTSENSOR_IPCLKPORT_iPCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 13);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_HSI2C_REARAF_IPCLKPORT_iPCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 12);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_HSI2C_REARSENSOR_IPCLKPORT_iPCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 11);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_GPIO_TOUCH_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 10);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_GPIO_TOP_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 9);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_GPIO_NFC_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 8);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_GPIO_ESE_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 7);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_BUSP1_PERIS1_IPCLKPORT_HCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 6);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 5);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_BUSP1_PERIC1_IPCLKPORT_HCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 4);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_BUSP1_PERIC0_IPCLKPORT_HCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 3);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_BUSP_BR_PERIC_IPCLKPORT_HCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 2);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_aclk, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 1);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_ASYNCM_PERI_IPCLKPORT_I_CLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS0, 0);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_USI_1_IPCLKPORT_i_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 16);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_USI_0_IPCLKPORT_i_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 15);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_WDT_CPUCL0_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 13);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 12);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 10);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 9);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 6);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 5);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_SFRIF_TMU_CPUCL0_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 1);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_SFRIF_GPIO_ALIVE_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS, CLK_ENABLE_CLK_PERI_BUS1, 0);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_TZPC10_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS/*_SECURE_TZPC*/, CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC, 10);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_TZPC9_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS/*_SECURE_TZPC*/, CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC, 9);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_TZPC8_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS/*_SECURE_TZPC*/, CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC, 8);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_TZPC7_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS/*_SECURE_TZPC*/, CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC, 7);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_TZPC6_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS/*_SECURE_TZPC*/, CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC, 6);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_TZPC5_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS/*_SECURE_TZPC*/, CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC, 5);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_TZPC4_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS/*_SECURE_TZPC*/, CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC, 4);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_TZPC3_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS/*_SECURE_TZPC*/, CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC, 3);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_TZPC2_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS/*_SECURE_TZPC*/, CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC, 2);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_TZPC1_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS/*_SECURE_TZPC*/, CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC, 1);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_TZPC0_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS/*_SECURE_TZPC*/, CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC, 0);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_SFRIF_CHIPID_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS/*_SECURE_CHIPID*/, CLK_ENABLE_CLK_PERI_BUS_SECURE_CHIPID, 0);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS/*_SECURE_OTP_CON_TOP*/, CLK_ENABLE_CLK_PERI_BUS_SECURE_OTP_CON_TOP, 0);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_SFRIF_RTC_ALIVE_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS/*_SECURE_RTC_ALIVE*/, CLK_ENABLE_CLK_PERI_BUS_SECURE_RTC_ALIVE, 0);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_SFRIF_RTC_TOP_IPCLKPORT_PCLK, MIF_GATE_CLKCMU_PERI_BUS/*_SECURE_RTC_TOP*/, CLK_ENABLE_CLK_PERI_BUS_SECURE_RTC_TOP, 0);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_EXT_UCLK, MIF_GATE_CLKCMU_PERI_UART_DEBUG, CLK_ENABLE_CLK_PERI_UART_DEBUG, 0);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_EXT_UCLK, MIF_GATE_CLKCMU_PERI_UART_SENSOR, CLK_ENABLE_CLK_PERI_UART_SENSOR, 0);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_SPI_EXT_CLK, MIF_GATE_CLKCMU_PERI_SPI_REARFROM, CLK_ENABLE_CLK_PERI_SPI_REARFROM, 0);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_SPI_EXT_CLK, MIF_GATE_CLKCMU_PERI_SPI_ESE, CLK_ENABLE_CLK_PERI_SPI_ESE, 0);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_USI_0_IPCLKPORT_i_SCLK_UART, MIF_GATE_CLKCMU_PERI_USI_0, CLK_ENABLE_CLK_PERI_USI_0, 0);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_USI_1_IPCLKPORT_i_SCLK_UART, MIF_GATE_CLKCMU_PERI_USI_1, CLK_ENABLE_CLK_PERI_USI_1, 0);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_USI_0_IPCLKPORT_i_SCLK_SPI, PERI_DIV_CLK_PERI_USI_0_SPI, CLK_ENABLE_CLK_PERI_USI_0_SPI, 0);
|
|
CLK_GATE(PERI_GATE_CLK_PERI_UID_USI_1_IPCLKPORT_i_SCLK_SPI, PERI_DIV_CLK_PERI_USI_1_SPI, CLK_ENABLE_CLK_PERI_USI_1_SPI, 0);
|
|
|
|
CLK_GATE(MIF_MUXGATE_CLKCMU_ISP_VRA, 0, CLK_CON_MUX_CLKCMU_ISP_VRA, 21);
|
|
CLK_GATE(MIF_MUXGATE_CLKCMU_ISP_CAM, 0, CLK_CON_MUX_CLKCMU_ISP_CAM, 21);
|
|
CLK_GATE(MIF_MUXGATE_CLKCMU_DISPAUD_BUS, 0, CLK_CON_MUX_CLKCMU_DISPAUD_BUS, 21);
|
|
CLK_GATE(MIF_MUXGATE_CLKCMU_DISPAUD_DECON_INT_VCLK, 0, CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK, 21);
|
|
CLK_GATE(MIF_MUXGATE_CLKCMU_MFCMSCL_MSCL, 0, CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL, 21);
|
|
CLK_GATE(MIF_MUXGATE_CLKCMU_MFCMSCL_MFC, 0, CLK_CON_MUX_CLKCMU_MFCMSCL_MFC, 21);
|
|
CLK_GATE(MIF_MUXGATE_CLKCMU_FSYS_BUS, 0, CLK_CON_MUX_CLKCMU_FSYS_BUS, 21);
|
|
CLK_GATE(MIF_MUXGATE_CLKCMU_FSYS_MMC0, 0, CLK_CON_MUX_CLKCMU_FSYS_MMC0, 21);
|
|
CLK_GATE(MIF_MUXGATE_CLKCMU_FSYS_MMC2, 0, CLK_CON_MUX_CLKCMU_FSYS_MMC2, 21);
|
|
CLK_GATE(MIF_MUXGATE_CLKCMU_FSYS_USB20DRD_REFCLK, 0, CLK_CON_MUX_CLKCMU_FSYS_USB20DRD_REFCLK, 21);
|
|
CLK_GATE(MIF_MUXGATE_CLKCMU_PERI_BUS, 0, CLK_CON_MUX_CLKCMU_PERI_BUS, 21);
|
|
CLK_GATE(MIF_MUXGATE_CLKCMU_PERI_UART_DEBUG, 0, CLK_CON_MUX_CLKCMU_PERI_UART_DEBUG, 21);
|
|
CLK_GATE(MIF_MUXGATE_CLKCMU_PERI_UART_SENSOR, 0, CLK_CON_MUX_CLKCMU_PERI_UART_SENSOR, 21);
|
|
CLK_GATE(MIF_MUXGATE_CLKCMU_PERI_SPI_REARFROM, 0, CLK_CON_MUX_CLKCMU_PERI_SPI_REARFROM, 21);
|
|
CLK_GATE(MIF_MUXGATE_CLKCMU_PERI_SPI_ESE, 0, CLK_CON_MUX_CLKCMU_PERI_SPI_ESE, 21);
|
|
CLK_GATE(MIF_MUXGATE_CLKCMU_PERI_USI_0, 0, CLK_CON_MUX_CLKCMU_PERI_USI_0, 21);
|
|
CLK_GATE(MIF_MUXGATE_CLKCMU_PERI_USI_1, 0, CLK_CON_MUX_CLKCMU_PERI_USI_1, 21);
|
|
CLK_GATE(MIF_MUXGATE_CLKCMU_APM, 0, CLK_CON_MUX_CLKCMU_APM, 21);
|
|
CLK_GATE(MIF_MUXGATE_CLKCMU_ISP_SENSOR0, 0, CLK_CON_MUX_CLKCMU_ISP_SENSOR0, 21);
|
|
|
|
CLK_GATE(PMU_DEBUG_CLKOUT_SEL08, OSCCLK, PMU_DEBUG, 8);
|
|
CLK_GATE(PMU_DEBUG_CLKOUT_SEL09, OSCCLK, PMU_DEBUG, 9);
|
|
CLK_GATE(PMU_DEBUG_CLKOUT_SEL10, OSCCLK, PMU_DEBUG, 10);
|
|
CLK_GATE(PMU_DEBUG_CLKOUT_SEL11, OSCCLK, PMU_DEBUG, 11);
|
|
CLK_GATE(PMU_DEBUG_CLKOUT_SEL12, OSCCLK, PMU_DEBUG, 12);
|
|
CLK_GATE(PMU_DEBUG_CLKOUT_DISABLE, OSCCLK, PMU_DEBUG, 0);
|
|
|
|
int _pwrcal_is_private_mux_set_src(struct pwrcal_clk *clk)
|
|
{
|
|
if (clk->id == MIF_MUX_CLK_MIF_PHY_CLK)
|
|
return 1;
|
|
return 0;
|
|
}
|
|
|
|
int _pwrcal_private_mux_set_src(struct pwrcal_clk *clk, unsigned int src)
|
|
{
|
|
struct pwrcal_clk *mout_clk_mif_phy_clk_submux[2] = {CLK(MIF_MUX_CLK_MIF_PHY_CLK_A), CLK(MIF_MUX_CLK_MIF_PHY_CLK_B)};
|
|
struct pwrcal_clk *dout_clk_mif_phy_clk_subdiv[2] = {CLK(MIF_DIV_CLK_MIF_PHY_CLK2X), CLK(MIF_DIV_CLK_MIF_PHY_CLKM)};
|
|
struct pwrcal_clk **submux, **subdiv;
|
|
struct pwrcal_mux *mux = to_mux(clk);
|
|
int timeout;
|
|
unsigned int mux_stat, div_stat_val;
|
|
unsigned int drex_freq = 0;
|
|
int i;
|
|
unsigned char value[4] = {0, };
|
|
|
|
switch (clk->id) {
|
|
case MIF_MUX_CLK_MIF_PHY_CLK:
|
|
submux = mout_clk_mif_phy_clk_submux;
|
|
subdiv = dout_clk_mif_phy_clk_subdiv;
|
|
break;
|
|
default:
|
|
return -1;
|
|
}
|
|
|
|
if (src >= (unsigned int)(mux->num_parents))
|
|
return -1;
|
|
|
|
value[0] = (unsigned char)((src & (0x1 << 7)) >> 7);
|
|
value[1] = (unsigned char)((src & (0x1 << 6)) >> 6);
|
|
value[2] = (unsigned char)((src & (0x7 << 3)) >> 3);
|
|
value[3] = (unsigned char)((src & (0x7 << 0)) >> 0);
|
|
|
|
drex_freq |= (value[0] & 0x1) << 4; // MIF_MUX_CLK_MIF_PHY_CLK_A
|
|
drex_freq |= (value[1] & 0x1) << 5; // MIF_MUX_CLK_MIF_PHY_CLK_B
|
|
drex_freq |= (value[2] & 0x7) << 16; // MIF_DIV_CLK_MIF_PHY_CLK2X
|
|
drex_freq |= (value[3] & 0x7) << 20; // MIF_DIV_CLK_MIF_PHY_CLKM
|
|
|
|
pwrcal_setf(clk->offset, 0, 0x00FF0030, drex_freq);
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
for (timeout = 0;; timeout++) {
|
|
mux_stat = pwrcal_getf(submux[i]->status,
|
|
submux[i]->s_shift,
|
|
TO_MASK(submux[i]->s_width));
|
|
if (mux_stat == (1 << value[i]))
|
|
break;
|
|
|
|
if (timeout > CLK_WAIT_CNT)
|
|
goto timeout_error;
|
|
cpu_relax();
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
for (timeout = 0;; timeout++) {
|
|
div_stat_val = pwrcal_getf(subdiv[i]->status,
|
|
subdiv[i]->s_shift,
|
|
TO_MASK(subdiv[i]->s_width));
|
|
if (0 == div_stat_val)
|
|
break;
|
|
|
|
if (timeout > CLK_WAIT_CNT)
|
|
goto timeout_error;
|
|
cpu_relax();
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
timeout_error:
|
|
pr_err("stat(=%d) check time out, \'%s\', src_num(=%d)",
|
|
mux_stat, clk->name, src);
|
|
return -1;
|
|
}
|
|
|
|
static int strcmp_unalign_address(const char *src1, const char *src2)
|
|
{
|
|
for (; *src1 == *src2; src1++, src2++)
|
|
if (*src1 == '\0')
|
|
return 0;
|
|
|
|
return ((*(unsigned char *)src1 < *(unsigned char *)src2) ? -1 : 1);
|
|
}
|
|
|
|
static struct pwrcal_clk *clk_get_with_list(char *clk_name, struct pwrcal_clk **clk_list, int clk_count)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < clk_count; ++i) {
|
|
if (strcmp_unalign_address(clk_list[i]->name, clk_name) == 0)
|
|
return clk_list[i];
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
struct pwrcal_clk *clk_find(char *clk_name)
|
|
{
|
|
struct pwrcal_clk *ret_cal = NULL;
|
|
|
|
if (strstr(clk_name, "PLL"))
|
|
ret_cal = clk_get_with_list(clk_name, pll_type_list, NUM_OF_PLL_TYPE);
|
|
|
|
if (strstr(clk_name, "DIV"))
|
|
ret_cal = clk_get_with_list(clk_name, div_type_list, NUM_OF_DIV_TYPE);
|
|
|
|
if (strstr(clk_name, "MUX"))
|
|
ret_cal = clk_get_with_list(clk_name, mux_type_list, NUM_OF_MUX_TYPE);
|
|
|
|
if (strstr(clk_name, "GATE"))
|
|
ret_cal = clk_get_with_list(clk_name, gate_type_list, NUM_OF_GATE_TYPE);
|
|
|
|
return ret_cal;
|
|
}
|
|
|
|
void clk_pll_set_rate_table(struct pwrcal_pll *pll)
|
|
{
|
|
int i;
|
|
void *pll_block;
|
|
struct pwrcal_pll_rate_table *pll_rate_table;
|
|
struct ect_pll *pll_unit;
|
|
struct ect_pll_frequency *pll_frequency;
|
|
|
|
if (pll == NULL)
|
|
return;
|
|
|
|
pll_block = ect_get_block(BLOCK_PLL);
|
|
if (pll_block == NULL)
|
|
return;
|
|
|
|
pll_unit = ect_pll_get_pll(pll_block, (char *)pll->clk.name);
|
|
if (pll_unit == NULL)
|
|
return;
|
|
|
|
pll_rate_table = kzalloc(sizeof(struct pwrcal_pll_rate_table) * pll_unit->num_of_frequency, GFP_KERNEL);
|
|
if (pll_rate_table == NULL)
|
|
return;
|
|
|
|
for (i = 0; i < pll_unit->num_of_frequency; ++i) {
|
|
pll_frequency = &pll_unit->frequency_list[i];
|
|
|
|
pll_rate_table[i].rate = pll_frequency->frequency;
|
|
pll_rate_table[i].pdiv = pll_frequency->p;
|
|
pll_rate_table[i].mdiv = pll_frequency->m;
|
|
pll_rate_table[i].sdiv = pll_frequency->s;
|
|
pll_rate_table[i].kdiv = pll_frequency->k;
|
|
}
|
|
|
|
pll->rate_table = pll_rate_table;
|
|
pll->rate_count = pll_unit->num_of_frequency;
|
|
}
|
|
|
|
void clk_init(void)
|
|
{
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, OSCCLK);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, OSCCLK_FM_52M);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, CLK_MIF_DDRPHY0);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, WIFI2AP_USBPLL_CLK);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, CLKPHY_FSYS_USB20DRD_PHYCLOCK);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, CLKIO_DISPAUD_MIXER_BCLK_CP);
|
|
ADD_CLK_TO_LIST(fixed_rate_type_list, CLKPHY_ISP_S_RXBYTECLKHS0_S4);
|
|
|
|
ADD_CLK_TO_LIST(fixed_factor_type_list, MIF_FF_SHARED0_PLL_DIV2);
|
|
ADD_CLK_TO_LIST(fixed_factor_type_list, MIF_FF_SHARED1_PLL_DIV2);
|
|
ADD_CLK_TO_LIST(fixed_factor_type_list, MIF_FF_SHARED2_PLL_DIV2);
|
|
|
|
ADD_CLK_TO_LIST(pll_type_list, CPUCL0_PLL);
|
|
ADD_CLK_TO_LIST(pll_type_list, SHARED0_PLL);
|
|
ADD_CLK_TO_LIST(pll_type_list, SHARED1_PLL);
|
|
ADD_CLK_TO_LIST(pll_type_list, SHARED2_PLL);
|
|
ADD_CLK_TO_LIST(pll_type_list, AUD_PLL);
|
|
ADD_CLK_TO_LIST(pll_type_list, WPLL_USB_PLL);
|
|
|
|
ADD_CLK_TO_LIST(mux_type_list, CPUCL0_MUX_CPUCL0_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, CPUCL0_MUX_CLK_CPUCL0);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISPAUD_MUX_AUD_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_SHARED0_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_SHARED1_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_SHARED2_PLL);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLK_MIF_PHY_CLK);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLK_MIF_PHY_CLK_A);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLK_MIF_PHY_CLK_B);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLK_MIF_BUSD);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_G3D);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_ISP_VRA);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_ISP_CAM);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_DISPAUD_BUS);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_MFCMSCL_MSCL);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_MFCMSCL_MFC);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_FSYS_BUS);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_FSYS_MMC0);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_FSYS_MMC2);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_FSYS_USB20DRD_REFCLK);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_PERI_BUS);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_PERI_UART_DEBUG);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_PERI_UART_SENSOR);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_PERI_SPI_REARFROM);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_PERI_SPI_ESE);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_PERI_USI_0);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_PERI_USI_1);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_APM);
|
|
ADD_CLK_TO_LIST(mux_type_list, MIF_MUX_CLKCMU_ISP_SENSOR0);
|
|
|
|
ADD_CLK_TO_LIST(mux_type_list, APM_MUX_CLKCMU_APM_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, CPUCL0_MUX_CLKCMU_CPUCL0_SWITCH_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISPAUD_MUX_CLKCMU_DISPAUD_BUS_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISPAUD_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, DISPAUD_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, FSYS_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, G3D_MUX_CLKCMU_G3D_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, ISP_MUX_CLKCMU_ISP_VRA_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, ISP_MUX_CLKCMU_ISP_CAM_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, ISP_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, MFCMSCL_MUX_CLKCMU_MFCMSCL_MSCL_USER);
|
|
ADD_CLK_TO_LIST(mux_type_list, MFCMSCL_MUX_CLKCMU_MFCMSCL_MFC_USER);
|
|
|
|
ADD_CLK_TO_LIST(div_type_list, CPUCL0_DIV_CLK_CPUCL0_1);
|
|
ADD_CLK_TO_LIST(div_type_list, CPUCL0_DIV_CLK_CPUCL0_2);
|
|
ADD_CLK_TO_LIST(div_type_list, CPUCL0_DIV_CLK_CPUCL0_ACLK);
|
|
ADD_CLK_TO_LIST(div_type_list, CPUCL0_DIV_CLK_CPUCL0_PCLK);
|
|
ADD_CLK_TO_LIST(div_type_list, CPUCL0_DIV_CLK_CPUCL0_ATCLK);
|
|
ADD_CLK_TO_LIST(div_type_list, CPUCL0_DIV_CLK_CPUCL0_PCLKDBG);
|
|
ADD_CLK_TO_LIST(div_type_list, CPUCL0_DIV_CLK_CPUCL0_CNTCLK);
|
|
ADD_CLK_TO_LIST(div_type_list, CPUCL0_DIV_CLK_CPUCL0_RUN_MONITOR);
|
|
ADD_CLK_TO_LIST(div_type_list, CPUCL0_DIV_CLK_CPUCL0_HPM);
|
|
ADD_CLK_TO_LIST(div_type_list, CPUCL0_DIV_CLK_CPUCL0_PLL);
|
|
ADD_CLK_TO_LIST(div_type_list, DISPAUD_DIV_CLK_DISPAUD_APB);
|
|
ADD_CLK_TO_LIST(div_type_list, DISPAUD_DIV_CLK_DISPAUD_DECON_INT_VCLK);
|
|
ADD_CLK_TO_LIST(div_type_list, DISPAUD_DIV_CLK_DISPAUD_DECON_INT_ECLK);
|
|
ADD_CLK_TO_LIST(div_type_list, DISPAUD_DIV_CLK_DISPAUD_MI2S);
|
|
ADD_CLK_TO_LIST(div_type_list, DISPAUD_DIV_CLK_DISPAUD_MIXER);
|
|
ADD_CLK_TO_LIST(div_type_list, DISPAUD_DIV_CLK_DISPAUD_OSCCLK_FM_52M_DIV);
|
|
ADD_CLK_TO_LIST(div_type_list, G3D_DIV_CLK_G3D_BUS);
|
|
ADD_CLK_TO_LIST(div_type_list, G3D_DIV_CLK_G3D_APB);
|
|
ADD_CLK_TO_LIST(div_type_list, ISP_DIV_CLK_ISP_CAM_HALF);
|
|
ADD_CLK_TO_LIST(div_type_list, MFCMSCL_DIV_CLK_MFCMSCL_APB);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLK_MIF_PHY_CLK2X);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLK_MIF_PHY_CLKM);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_CP_SHARED0_PLL);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_CP_SHARED1_PLL);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_CP_SHARED2_PLL);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLK_MIF_BUSD);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLK_MIF_APB);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_CPUCL0_SWITCH);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_G3D);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_ISP_VRA);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_ISP_CAM);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_DISPAUD_BUS);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_MFCMSCL_MSCL);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_MFCMSCL_MFC);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_FSYS_BUS);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_FSYS_MMC0);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_FSYS_MMC2);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_FSYS_USB20DRD_REFCLK);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_PERI_BUS);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_PERI_UART_DEBUG);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_PERI_UART_SENSOR);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_PERI_SPI_REARFROM);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_PERI_SPI_ESE);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_PERI_USI_0);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_PERI_USI_1);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_APM);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_ISP_SENSOR0);
|
|
ADD_CLK_TO_LIST(div_type_list, MIF_DIV_CLKCMU_GNSS_EXTPLL_SCAN);
|
|
ADD_CLK_TO_LIST(div_type_list, PERI_DIV_CLK_PERI_USI_0_SPI);
|
|
ADD_CLK_TO_LIST(div_type_list, PERI_DIV_CLK_PERI_USI_1_SPI);
|
|
|
|
ADD_CLK_TO_LIST(gate_type_list, APM_GATE_CLK_APM_UID_APM_IPCLKPORT_ACLK_SYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, APM_GATE_CLK_APM_UID_APM_IPCLKPORT_ACLK_CPU);
|
|
ADD_CLK_TO_LIST(gate_type_list, APM_GATE_CLK_APM_UID_ASYNCS_APM_IPCLKPORT_I_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, APM_GATE_CLK_APM_UID_ASYNCM_APM_IPCLKPORT_I_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_I_CLK__PMU_CPUCL0);
|
|
ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_D_CPUCL0_IPCLKPORT_I_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_I_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_BUSP1_CPUCL0_IPCLKPORT_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCM_P_CPUCL0_IPCLKPORT_I_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_ATCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_SECJTAG_IPCLKPORT_i_clk);
|
|
ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_DUMP_PC_CPUCL0_IPCLKPORT_I_PCLKDBG);
|
|
ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_DBG_MUX_CPUCL0_IPCLKPORT_I_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_CSSYS_DBG_IPCLKPORT_PCLKDBG);
|
|
ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_CSSYS_DBG_IPCLKPORT_PCLKS);
|
|
ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCS_T_CSSYS_DBG_IPCLKPORT_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_ASYNCM_P_CSSYS_DBG_IPCLKPORT_PCLKM);
|
|
ADD_CLK_TO_LIST(gate_type_list, CPUCL0_GATE_CLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_I_HPM_TARGETCLK_C);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_OSCCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_PPMU);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_DISP);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS_VPP);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_BUS);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_FM);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD_AMP);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_AUD);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB_DISP);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_APB);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CLKCMU_DISPAUD_APB_SECURE_SMMU_DISP);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_DECON_IPCLKPORT_I_VCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_DSIM0_IPCLKPORT_I_TXBYTECLKHS);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_DSIM0_IPCLKPORT_I_RXCLKESC0);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AMP_IPCLKPORT_I2SCODCLKI);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_MI2S_AUD_IPCLKPORT_I2SCODCLKI);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_MIXER_AUD_IPCLKPORT_SYSCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CON_DISPAUD_IPCLKPORT_I_CP2AUD_BCK);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_OSCCLK_FM_52M);
|
|
ADD_CLK_TO_LIST(gate_type_list, DISPAUD_GATE_CLK_DISPAUD_UID_CLK_DISPAUD_OSCCLK_FM_52M_DIV);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_PMU_FSYS_IPCLKPORT_I_CLK__PMU_FSYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_BUSD1_FSYS_IPCLKPORT_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_BUSD0_FSYS_IPCLKPORT_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HCLK_USB20_CTRL);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_ACLK_HSDRD);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_SYSREG_FSYS_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_PPMU_FSYS_IPCLKPORT_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_PMU_FSYS_IPCLKPORT_I_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_ASYNCS_D_FSYS_IPCLKPORT_I_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_ASYNCM_P_FSYS_IPCLKPORT_I_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_GPIO_FSYS_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_MMC_CARD_IPCLKPORT_I_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_MMC_EMBD_IPCLKPORT_I_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_BR_BUSP1_FSYS_IPCLKPORT_aclk);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_BUSP5_FSYS_IPCLKPORT_HCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_BUSP3_FSYS_IPCLKPORT_HCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_BUSP2_FSYS_IPCLKPORT_HCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_BUSP1_FSYS_IPCLKPORT_HCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_RTIC_IPCLKPORT_i_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_RTIC_IPCLKPORT_i_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_SSS_IPCLKPORT_i_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_SSS_IPCLKPORT_i_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_MMC_EMBD_IPCLKPORT_SDCLKIN);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_MMC_CARD_IPCLKPORT_SDCLKIN);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_ref_clk);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_HSDRD_PHYCLOCK);
|
|
ADD_CLK_TO_LIST(gate_type_list, FSYS_GATE_CLK_FSYS_UID_USB20DRD_IPCLKPORT_USB20_CLKCORE_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_PMU_G3D_IPCLKPORT_I_CLK__PMU_G3D);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_G3D_IPCLKPORT_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_REGSLICE_D1_G3D_IPCLKPORT_aclk);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_REGSLICE_D0_G3D_IPCLKPORT_aclk);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_IXIU_D_G3D_IPCLKPORT_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_ASYNCS_D1_G3D_IPCLKPORT_I_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_ASYNCS_D0_G3D_IPCLKPORT_I_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKM);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_QE_G3D_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_PPMU_G3D_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_PMU_G3D_IPCLKPORT_I_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_BUSP_G3D_IPCLKPORT_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_ASYNCM_P_G3D_IPCLKPORT_I_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_ASYNC_G3D_P_IPCLKPORT_PCLKS);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_CFW_G3D_IPCLKPORT_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, G3D_GATE_CLK_G3D_UID_CFW_G3D_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP_GATE_CLK_ISP_UID_CLK_ISP_OSCCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP_GATE_CLK_ISP_UID_CLK_ISP_VRA);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP_GATE_CLK_ISP_UID_CLK_ISP_CAM);
|
|
ADD_CLK_TO_LIST(gate_type_list, ISP_GATE_CLK_ISP_UID_CLKPHY_ISP_S_RXBYTECLKHS0_S4);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFCMSCL_GATE_CLK_MFCMSCL_UID_CLK_MFCMSCL_OSCCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MSCL_BI);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_D);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_JPEG);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_POLY);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_MFC_MFC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFCMSCL_GATE_CLK_MFCMSCL_UID_CLK_MFCMSCL_APB);
|
|
ADD_CLK_TO_LIST(gate_type_list, MFCMSCL_GATE_CLK_MFCMSCL_UID_CLKCMU_MFCMSCL_APB_SMMU_MSCL);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_OTP_DESERIAL_MIF_IPCLKPORT_I_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_RCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_I_OSC_SYS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_SYSREG_MIF_IPCLKPORT_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_PMU_MIF_IPCLKPORT_I_CLK__PMU_MIF_JV);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_clk);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_clkm);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_APB_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_SECURE_APB_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PEREV_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_MEMIF_WR_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_MEMIF_RD_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_MEMIF_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_SCH_SLICE1_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_SCH_SLICE0_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_SCH_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_VCF_WR_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_VCF_RD_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_VCF_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_PPMU_CPU_IPCLKPORT_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_QE_DMC0_CPU_IPCLKPORT_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNCM_CPUCL0_IPCLKPORT_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNCM_DBG_IPCLKPORT_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_PDMA_MIF_IPCLKPORT_ACLK_PDMA0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_CLEANY_WLBT_IPCLKPORT_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_CLEANY_GNSS_IPCLKPORT_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_CLEANY_CEL_IPCLKPORT_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_CPU0_MO_MON_IPCLKPORT_I_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_PPMU_CPU_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_SPEEDY_BATCHER_WRAPPER_IPCLKPORT_PCLK_BATCHER_SPEEDY);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_SPEEDY_BATCHER_WRAPPER_IPCLKPORT_PCLK_BATCHER_CP);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_SPEEDY_BATCHER_WRAPPER_IPCLKPORT_PCLK_BATCHER_AP);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_SPEEDY_MIF_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_MAILBOX_WLBT_IPCLKPORT_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_MAILBOX_GNSS_IPCLKPORT_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_MAILBOX_CEL_IPCLKPORT_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_ASYNCAPB_MIF_CSSYS_IPCLKPORT_PCLKS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_SYNC_INTC_SOC_IPCLKPORT_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_INTC_SOC_IPCLKPORT_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_AXI2APB_MIF_TREX_IPCLKPORT_ACLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_AXI2AHB_MIF_P_IPCLKPORT_HCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_AHB2APB_MIF2_IPCLKPORT_HCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_AHB2APB_MIF1_IPCLKPORT_HCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_AHB2APB_MIF0_IPCLKPORT_HCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_AHB_BRIDGE_MIF_IPCLKPORT_HCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_QE_DMC0_CPU_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DDRDMC0_APB_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_PF);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DDR_PHY0_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_WRAP_ADC_IF_IPCLKPORT_PCLK_S0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_GPIO_MIF_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_PMU_MIF_IPCLKPORT_I_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_PF_SECURE);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_DMC0_IPCLKPORT_PCLK_SECURE);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_MAILBOX_SECURE_IPCLKPORT_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_CP_SHARED0_PLL);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_CP_SHARED1_PLL);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_CP_SHARED2_PLL);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_CPUCL0_SWITCH);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_G3D);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_ISP_VRA);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_ISP_CAM);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_DISPAUD_BUS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_DISPAUD_DECON_INT_VCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_MFCMSCL_MFC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_MFCMSCL_MSCL);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_FSYS_BUS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_FSYS_MMC0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_FSYS_MMC2);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_FSYS_USB20DRD_REFCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_PERI_BUS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_PERI_UART_DEBUG);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_PERI_UART_SENSOR);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_PERI_SPI_REARFROM);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_PERI_SPI_ESE);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_PERI_USI_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_PERI_USI_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_APM);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_ISP_SENSOR0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLKCMU_GNSS_TEST_EXTPLL_SCAN_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_GATE_CLK_MIF_UID_SPEEDY_MIF_IPCLKPORT_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TMU_CPUCL0_IPCLKPORT_I_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SYSREG_PERI_IPCLKPORT_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_OSCCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_PMU_PERI_IPCLKPORT_I_CLK__PMU_PERI);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_CHIPID_IPCLKPORT_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_PWM_MOTOR_IPCLKPORT_i_PCLK_S0);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_PMU_PERI_IPCLKPORT_I_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_MCT_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_I2C_SENSOR2_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_I2C_SENSOR1_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_I2C_TSP_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_I2C_FUELGAUGE_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_I2C_NFC_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_I2C_MUIC_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_HSI2C_FRONTCAM_IPCLKPORT_iPCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_HSI2C_MAINCAM_IPCLKPORT_iPCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_HSI2C_FRONTSENSOR_IPCLKPORT_iPCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_HSI2C_REARAF_IPCLKPORT_iPCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_HSI2C_REARSENSOR_IPCLKPORT_iPCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_GPIO_TOUCH_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_GPIO_TOP_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_GPIO_NFC_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_GPIO_ESE_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_BUSP1_PERIS1_IPCLKPORT_HCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_BUSP1_PERIS0_IPCLKPORT_HCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_BUSP1_PERIC1_IPCLKPORT_HCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_BUSP1_PERIC0_IPCLKPORT_HCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_BUSP_BR_PERIC_IPCLKPORT_HCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_AXI2AHB_MSD32_PERI_IPCLKPORT_aclk);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_ASYNCM_PERI_IPCLKPORT_I_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_USI_1_IPCLKPORT_i_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_USI_0_IPCLKPORT_i_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_WDT_CPUCL0_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SYSREG_PERI_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SFRIF_TMU_CPUCL0_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SFRIF_GPIO_ALIVE_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TZPC10_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TZPC9_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TZPC8_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TZPC7_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TZPC6_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TZPC5_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TZPC4_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TZPC3_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TZPC2_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TZPC1_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_TZPC0_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SFRIF_CHIPID_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_OTP_CON_TOP_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SFRIF_RTC_ALIVE_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SFRIF_RTC_TOP_IPCLKPORT_PCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_UART_DEBUG_IPCLKPORT_EXT_UCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_UART_SENSOR_IPCLKPORT_EXT_UCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SPI_REARFROM_IPCLKPORT_SPI_EXT_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_SPI_ESE_IPCLKPORT_SPI_EXT_CLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_USI_0_IPCLKPORT_i_SCLK_UART);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_USI_1_IPCLKPORT_i_SCLK_UART);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_USI_0_IPCLKPORT_i_SCLK_SPI);
|
|
ADD_CLK_TO_LIST(gate_type_list, PERI_GATE_CLK_PERI_UID_USI_1_IPCLKPORT_i_SCLK_SPI);
|
|
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_ISP_VRA);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_ISP_CAM);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_DISPAUD_BUS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_DISPAUD_DECON_INT_VCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_MFCMSCL_MSCL);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_MFCMSCL_MFC);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_FSYS_BUS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_FSYS_MMC0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_FSYS_MMC2);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_FSYS_USB20DRD_REFCLK);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_PERI_BUS);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_PERI_UART_DEBUG);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_PERI_UART_SENSOR);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_PERI_SPI_REARFROM);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_PERI_SPI_ESE);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_PERI_USI_0);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_PERI_USI_1);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_APM);
|
|
ADD_CLK_TO_LIST(gate_type_list, MIF_MUXGATE_CLKCMU_ISP_SENSOR0);
|
|
|
|
ADD_CLK_TO_LIST(gate_type_list, PMU_DEBUG_CLKOUT_SEL08);
|
|
ADD_CLK_TO_LIST(gate_type_list, PMU_DEBUG_CLKOUT_SEL09);
|
|
ADD_CLK_TO_LIST(gate_type_list, PMU_DEBUG_CLKOUT_SEL10);
|
|
ADD_CLK_TO_LIST(gate_type_list, PMU_DEBUG_CLKOUT_SEL11);
|
|
ADD_CLK_TO_LIST(gate_type_list, PMU_DEBUG_CLKOUT_SEL12);
|
|
ADD_CLK_TO_LIST(gate_type_list, PMU_DEBUG_CLKOUT_DISABLE);
|
|
|
|
clk_pll_set_rate_table(&clk_CPUCL0_PLL);
|
|
clk_pll_set_rate_table(&clk_SHARED0_PLL);
|
|
clk_pll_set_rate_table(&clk_SHARED1_PLL);
|
|
clk_pll_set_rate_table(&clk_SHARED2_PLL);
|
|
clk_pll_set_rate_table(&clk_AUD_PLL);
|
|
}
|