mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-09 01:28:05 -04:00
229 lines
5.5 KiB
C
229 lines
5.5 KiB
C
/*
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* s2mps15.h
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef __LINUX_MFD_S2MPS15_H
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#define __LINUX_MFD_S2MPS15_H
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/* S2MPS15 Revision Number */
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enum s2mps15_revision_number {
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S2MPS15_REV_0 = 0x00,
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S2MPS15_REV_1 = 0x01,
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};
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/* S2MPS15 registers */
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enum S2MPS15_reg {
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S2MPS15_REG_ID,
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S2MPS15_REG_INT1,
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S2MPS15_REG_INT2,
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S2MPS15_REG_INT3,
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S2MPS15_REG_INT1M,
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S2MPS15_REG_INT2M,
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S2MPS15_REG_INT3M,
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S2MPS15_REG_ST1,
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S2MPS15_REG_ST2,
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S2MPS15_REG_PWRONSRC,
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S2MPS15_REG_OFFSRC,
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S2MPS15_REG_BU_CHG,
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S2MPS15_REG_RTC_BUF,
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S2MPS15_REG_CTRL1,
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S2MPS15_REG_CTRL2,
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S2MPS15_REG_ETC_TEST,
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S2MPS15_REG_OTP_ADRL,
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S2MPS15_REG_OTP_ADRH,
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S2MPS15_REG_OTP_DATA,
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S2MPS15_REG_MON1SEL,
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S2MPS15_REG_MON2SEL,
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S2MPS15_REG_CTRL3,
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S2MPS15_REG_ETC_OTP,
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S2MPS15_REG_UVLO_OTP,
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S2MPS15_REG_LEE,
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S2MPS15_REG_B1CTRL1,
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S2MPS15_REG_B1CTRL2,
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S2MPS15_REG_B2CTRL1,
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S2MPS15_REG_B2CTRL2,
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S2MPS15_REG_B3CTRL1,
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S2MPS15_REG_B3CTRL2,
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S2MPS15_REG_B4CTRL1,
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S2MPS15_REG_B4CTRL2,
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S2MPS15_REG_B5CTRL1,
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S2MPS15_REG_B5CTRL2,
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S2MPS15_REG_B6CTRL1,
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S2MPS15_REG_B6CTRL2,
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S2MPS15_REG_B7CTRL1,
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S2MPS15_REG_B7CTRL2,
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S2MPS15_REG_B8CTRL1,
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S2MPS15_REG_B8CTRL2,
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S2MPS15_REG_B9CTRL1,
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S2MPS15_REG_B9CTRL2,
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S2MPS15_REG_B10CTRL1,
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S2MPS15_REG_B10CTRL2,
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S2MPS15_REG_BB1CTRL1,
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S2MPS15_REG_BB1CTRL2,
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S2MPS15_REG_BUCK_RAMP1,
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S2MPS15_REG_LDO_DVS1,
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S2MPS15_REG_LDO_DVS2,
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S2MPS15_REG_LDO_DVS3,
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S2MPS15_REG_LDO_DVS4,
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S2MPS15_REG_L1CTRL,
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S2MPS15_REG_L2CTRL,
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S2MPS15_REG_L3CTRL,
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S2MPS15_REG_L4CTRL,
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S2MPS15_REG_L5CTRL,
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S2MPS15_REG_L6CTRL,
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S2MPS15_REG_L7CTRL,
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S2MPS15_REG_L8CTRL,
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S2MPS15_REG_L9CTRL,
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S2MPS15_REG_L10CTRL,
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S2MPS15_REG_L11CTRL,
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S2MPS15_REG_L12CTRL,
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S2MPS15_REG_L13CTRL,
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S2MPS15_REG_L14CTRL,
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S2MPS15_REG_L15CTRL,
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S2MPS15_REG_L16CTRL,
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S2MPS15_REG_L17CTRL,
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S2MPS15_REG_L18CTRL,
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S2MPS15_REG_L19CTRL,
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S2MPS15_REG_L20CTRL,
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S2MPS15_REG_L21CTRL,
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S2MPS15_REG_L22CTRL,
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S2MPS15_REG_L23CTRL,
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S2MPS15_REG_L24CTRL,
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S2MPS15_REG_L25CTRL,
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S2MPS15_REG_L26CTRL,
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S2MPS15_REG_L27CTRL,
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S2MPS15_REG_LDO_DSCH1,
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S2MPS15_REG_LDO_DSCH2,
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S2MPS15_REG_LDO_DSCH3,
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S2MPS15_REG_LDO_DSCH4,
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S2MPS15_REG_L26CTRL_REV1 = 0x4C,
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S2MPS15_REG_L25CTRL_REV1 = 0x4D,
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S2MPS15_REG_LDO_RSVD3 = 0x52,
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S2MPS15_REG_B6CTRL3 = 0x57,
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S2MPS15_REG_ADC_CTRL1 = 0x5B,
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S2MPS15_REG_ADC_CTRL2 = 0x5C,
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S2MPS15_REG_ADC_DATA = 0x5D,
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};
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/* S2MPS15 regulator ids */
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enum S2MPS15_regulators {
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S2MPS15_LDO1,
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S2MPS15_LDO2,
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S2MPS15_LDO3,
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S2MPS15_LDO4,
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S2MPS15_LDO5,
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S2MPS15_LDO6,
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S2MPS15_LDO7,
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S2MPS15_LDO8,
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S2MPS15_LDO9,
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S2MPS15_LDO10,
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S2MPS15_LDO11,
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S2MPS15_LDO12,
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S2MPS15_LDO13,
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S2MPS15_LDO14,
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S2MPS15_LDO15,
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S2MPS15_LDO16,
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S2MPS15_LDO17,
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S2MPS15_LDO18,
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S2MPS15_LDO19,
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S2MPS15_LDO20,
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S2MPS15_LDO21,
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S2MPS15_LDO22,
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S2MPS15_LDO23,
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S2MPS15_LDO24,
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S2MPS15_LDO25,
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S2MPS15_LDO26,
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S2MPS15_LDO27,
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S2MPS15_BUCK1,
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S2MPS15_BUCK2,
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S2MPS15_BUCK3,
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S2MPS15_BUCK4,
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S2MPS15_BUCK5,
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S2MPS15_BUCK6,
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S2MPS15_BUCK7,
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S2MPS15_BUCK8,
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S2MPS15_BUCK9,
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S2MPS15_BUCK10,
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S2MPS15_BB1,
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S2MPS15_AP_EN32KHZ,
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S2MPS15_CP_EN32KHZ,
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S2MPS15_BT_EN32KHZ,
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S2MPS15_REG_MAX,
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};
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#define S2MPS15_BUCK_MIN1 400000
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#define S2MPS15_BUCK_MIN1_REV1 300000
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#define S2MPS15_BUCK_MIN2 600000
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#define S2MPS15_BUCK_MIN3 2600000
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#define S2MPS15_LDO_MIN1 400000
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#define S2MPS15_LDO_MIN1_REV1 300000
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#define S2MPS15_LDO_MIN2 500000
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#define S2MPS15_LDO_MIN3 700000
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#define S2MPS15_LDO_MIN4 1800000
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#define S2MPS15_BUCK_STEP1 6250
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#define S2MPS15_BUCK_STEP2 12500
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#define S2MPS15_LDO_STEP1 12500
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#define S2MPS15_LDO_STEP2 25000
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#define S2MPS15_LDO_VSEL_MASK 0x3F
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#define S2MPS15_BUCK_VSEL_MASK 0xFF
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#define S2MPS15_ENABLE_MASK (0x03 << S2MPS15_ENABLE_SHIFT)
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#define S2MPS15_SW_ENABLE_MASK 0x03
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#define S2MPS15_RAMP_DELAY 12000
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#define S2MPS15_ENABLE_TIME_LDO 115
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#define S2MPS15_ENABLE_TIME_BUCK1 65
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#define S2MPS15_ENABLE_TIME_BUCK2 65
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#define S2MPS15_ENABLE_TIME_BUCK3 65
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#define S2MPS15_ENABLE_TIME_BUCK4 65
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#define S2MPS15_ENABLE_TIME_BUCK5 65
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#define S2MPS15_ENABLE_TIME_BUCK6 65
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#define S2MPS15_ENABLE_TIME_BUCK7 75
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#define S2MPS15_ENABLE_TIME_BUCK8 90
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#define S2MPS15_ENABLE_TIME_BUCK9 115
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#define S2MPS15_ENABLE_TIME_BUCK10 75
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#define S2MPS15_ENABLE_TIME_BB 171
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#define S2MPS15_ENABLE_TIME_LDO_REV1 128
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#define S2MPS15_ENABLE_TIME_BUCK1_REV1 95
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#define S2MPS15_ENABLE_TIME_BUCK2_REV1 95
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#define S2MPS15_ENABLE_TIME_BUCK3_REV1 95
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#define S2MPS15_ENABLE_TIME_BUCK4_REV1 95
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#define S2MPS15_ENABLE_TIME_BUCK5_REV1 95
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#define S2MPS15_ENABLE_TIME_BUCK6_REV1 128
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#define S2MPS15_ENABLE_TIME_BUCK7_REV1 95
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#define S2MPS15_ENABLE_TIME_BUCK8_REV1 106
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#define S2MPS15_ENABLE_TIME_BUCK9_REV1 150
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#define S2MPS15_ENABLE_TIME_BUCK10_REV1 95
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#define S2MPS15_ENABLE_TIME_BB_REV1 217
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#define S2MPS15_ENABLE_SHIFT 0x06
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#define S2MPS15_LDO_N_VOLTAGES (S2MPS15_LDO_VSEL_MASK + 1)
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#define S2MPS15_BUCK_N_VOLTAGES (S2MPS15_BUCK_VSEL_MASK + 1)
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#define S2MPS15_PMIC_EN_SHIFT 6
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#define S2MPS15_REGULATOR_MAX (S2MPS15_REG_MAX)
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#define S2MPS15_MAX_ADC_CHANNEL 4
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#define S2MPS15_BUCK_MAX 11
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#define S2MPS15_LDO_START 0x21
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#define S2MPS15_LDO_END 0x3b
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#define S2MPS15_BUCK_START 0x1
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#define S2MPS15_BUCK_END 0xb
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#define S2MPS15_ADC_SMP_NUM_MAX 0x3
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#define S2MPS15_ADC_DIV_RATIO_MAX 0xf
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#define S2MPS15_ADCEN_MASK 0x80
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#define S2MPS15_SMP_NUM_MASK 0x30
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#define S2MPS15_SMP_NUM_SHIFT 4
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#define S2MPS15_DIV_RATIO_MASK 0x0F
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#endif /* __LINUX_MFD_S2MPS15_H */
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