mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 01:08:03 -04:00
106 lines
3 KiB
C
106 lines
3 KiB
C
/*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* EXYNOS - PMU(Power Management Unit) support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __EXYNOS_PMU_CP_H
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#define __EXYNOS_PMU_CP_H __FILE__
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/* BLK_ALIVE: CP related SFRs */
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#define EXYNOS_PMU_CP_CTRL_NS 0x0030
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#define EXYNOS_PMU_CP_CTRL_S 0x0034
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#define EXYNOS_PMU_CP_STAT 0x0038
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#define EXYNOS_PMU_CP_DEBUG 0x003C
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#define EXYNOS_PMU_CP2AP_MEM_CONFIG 0x0050
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#define EXYNOS_PMU_CP2AP_MIF_ACCESS_WIN0 0x0054
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#define EXYNOS_PMU_CP2AP_MIF_ACCESS_WIN1 0x0058
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#define EXYNOS_PMU_CP2AP_MIF_ACCESS_WIN2 0x005C
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#define EXYNOS_PMU_CP2AP_MIF_ACCESS_WIN3 0x0060
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#define EXYNOS_PMU_CP2AP_MIF_CONFIG1 0x0064
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#define EXYNOS_PMU_CP_BOOT_TEST_RST_CONFIG 0x0068
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#define EXYNOS_PMU_CP2AP_PERI_ACCESS_WIN 0x006C
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#define EXYNOS_PMU_MODAPIF_CONFIG 0x0070
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#define EXYNOS_PMU_CP_CLK_CTRL 0x0074
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#define EXYNOS_PMU_CP_QOS 0x0078
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#define EXYNOS_PMU_CP2AP_MIF_CONFIG2 0x007C
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#define EXYNOS_PMU_CP2AP_ADDR_RNG 0x0084
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#define EXYNOS_PMU_CENTRAL_SEQ_CP_CONFIGURATION 0x0280
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#define EXYNOS_PMU_RESET_AHEAD_CP_SYS_PWR_REG 0x1170
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#define EXYNOS_PMU_CLEANY_BUS_SYS_PWR_REG 0x11CC
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#define EXYNOS_PMU_LOGIC_RESET_CP_SYS_PWR_REG 0x11D0
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#define EXYNOS_PMU_TCXO_GATE_SYS_PWR_REG 0x11D4
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#define EXYNOS_PMU_RESET_ASB_CP_SYS_PWR_REG 0x11D8
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#if defined(CONFIG_SOC_EXYNOS7870) || defined(CONFIG_SOC_EXYNOS7570)
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#define PMU_USBDEV_PHY_CONTROL 0x0704
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#define USBDEV_PHY_ENABLE BIT(1)
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/* UART IO SHARE CTRL */
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#define EXYNOS_PMU_UART_IO_SHARE_CTRL 0x6200
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#define SEL_CP_UART_DBG BIT(8)
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#define SEL_UART_DBG_GPIO BIT(4)
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#define FUNC_ISO_EN BIT(0)
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#endif
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/* CP PMU */
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/* For EXYNOS_PMU_CP_CTRL Register */
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#define CP_PWRON BIT(1)
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#define CP_RESET_SET BIT(2)
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#define CP_START BIT(3)
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#define CP_ACTIVE_REQ_EN BIT(5)
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#define CP_ACTIVE_REQ_CLR BIT(6)
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#define CP_RESET_REQ_EN BIT(7)
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#define CP_RESET_REQ_CLR BIT(8)
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#define MASK_CP_PWRDN_DONE BIT(9)
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#define RTC_OUT_EN BIT(10)
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#define MASK_SLEEP_START_REQ BIT(12)
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#define SET_SW_SLEEP_START_REQ BIT(13)
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#define CLEANY_BYPASS_END BIT(16)
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#define SMC_ID 0x82000700
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#define READ_CTRL 0x3
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#define WRITE_CTRL 0x4
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#ifdef CONFIG_SOC_EXYNOS7870
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/* UART IO SHARE CTRL */
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#define EXYNOS_PMU_UART_IO_SHARE_CTRL 0x6200
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#define SEL_CP_UART_DBG BIT(8)
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#define SEL_UART_DBG_GPIO BIT(4)
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#define FUNC_ISO_EN BIT(0)
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#endif
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enum cp_mode {
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CP_POWER_ON,
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CP_RESET,
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CP_POWER_OFF,
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NUM_CP_MODE,
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};
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enum reset_mode {
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CP_HW_RESET,
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CP_SW_RESET,
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};
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enum cp_control {
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CP_CTRL_S,
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CP_CTRL_NS,
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};
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extern int exynos_cp_reset(void);
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extern int exynos_cp_release(void);
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extern int exynos_cp_init(void);
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extern int exynos_cp_active_clear(void);
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extern int exynos_clear_cp_reset(void);
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extern int exynos_get_cp_power_status(void);
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extern int exynos_set_cp_power_onoff(enum cp_mode mode);
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extern void exynos_sys_powerdown_conf_cp(void);
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extern int exynos_pmu_cp_init(void);
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#endif /* __EXYNOS_PMU_CP_H */
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