mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-07 08:48:05 -04:00
118 lines
3.3 KiB
C
118 lines
3.3 KiB
C
/* sound/soc/samsung/lpass.h
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*
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* ALSA SoC Audio Layer - Samsung Audio Subsystem driver
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*
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* Copyright (c) 2013 Samsung Electronics Co. Ltd.
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* Yeongman Seo <yman.seo@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __SND_SOC_SAMSUNG_LPASS_H
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#define __SND_SOC_SAMSUNG_LPASS_H
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#include <linux/pm_qos.h>
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/* SFR */
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#define LPASS_VERSION (0x00)
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#define LPASS_CA5_SW_RESET (0x04)
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#define LPASS_CORE_SW_RESET (0x08)
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#define LPASS_MIF_POWER (0x10)
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#define LPASS_CA5_BOOTADDR (0x20)
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#define LPASS_CA5_DBG (0x30)
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#define LPASS_SW_INTR_CA5 (0x40)
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#define LPASS_INTR_CA5_STATUS (0x44)
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#define LPASS_INTR_CA5_MASK (0x48)
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#define LPASS_SW_INTR_CPU (0x50)
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#define LPASS_INTR_CPU_STATUS (0x54)
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#define LPASS_INTR_CPU_MASK (0x58)
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/* SW_RESET */
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#define LPASS_SW_RESET_CA5 (1 << 0)
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#define LPASS_SW_RESET_SB (1 << 11)
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#define LPASS_SW_RESET_UART (1 << 10)
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#ifndef CONFIG_SOC_EXYNOS8890
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#define LPASS_SW_RESET_PCM (1 << 9)
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#define LPASS_SW_RESET_I2S (1 << 8)
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#else
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#define LPASS_SW_RESET_PCM (1 << 8)
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#define LPASS_SW_RESET_I2S (1 << 7)
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#endif
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#define LPASS_SW_RESET_TIMER (1 << 2)
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#define LPASS_SW_RESET_MEM (1 << 1)
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#define LPASS_SW_RESET_DMA (1 << 0)
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/* Interrupt mask */
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#define LPASS_INTR_APM (1 << 9)
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#define LPASS_INTR_MIF (1 << 8)
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#define LPASS_INTR_TIMER (1 << 7)
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#define LPASS_INTR_DMA (1 << 6)
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#define LPASS_INTR_GPIO (1 << 5)
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#define LPASS_INTR_I2S (1 << 4)
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#define LPASS_INTR_PCM (1 << 3)
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#define LPASS_INTR_SB (1 << 2)
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#define LPASS_INTR_UART (1 << 1)
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#define LPASS_INTR_SFR (1 << 0)
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struct lpass_info {
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spinlock_t lock;
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bool valid;
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bool enabled;
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int ver;
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struct platform_device *pdev;
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void __iomem *regs;
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void __iomem *regs_s;
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void __iomem *mem;
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int mem_size;
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void __iomem *sysmmu;
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struct iommu_domain *domain;
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struct proc_dir_entry *proc_file;
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struct clk *clk_dmac;
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struct clk *clk_sramc;
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struct clk *clk_intr;
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struct clk *clk_timer;
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struct regmap *pmureg;
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atomic_t dma_use_cnt;
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atomic_t use_cnt;
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atomic_t stream_cnt;
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bool display_on;
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bool uhqa_on;
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bool i2s_master_mode;
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struct pm_qos_request aud_cluster1_qos;
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struct pm_qos_request aud_cluster0_qos;
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struct pm_qos_request aud_mif_qos;
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struct pm_qos_request aud_int_qos;
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int cpu_qos;
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int kfc_qos;
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int mif_qos;
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int int_qos;
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};
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extern void __iomem *lpass_get_regs(void);
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extern void __iomem *lpass_get_regs_s(void);
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extern void __iomem *lpass_get_mem(void);
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extern struct clk *lpass_get_i2s_opclk(int clk_id);
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extern void lpass_reg_dump(void);
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extern void __iomem *lpass_cmu_save[];
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extern int lpass_get_clk(struct device *dev, struct lpass_info *lpass);
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extern void lpass_put_clk(struct lpass_info *lpass);
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extern int lpass_set_clk_heirachy(struct device *dev);
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extern void lpass_set_mux_pll(void);
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extern void lpass_set_mux_osc(void);
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extern void lpass_enable_pll(bool on);
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extern void lpass_retention_pad_reg(void);
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extern void lpass_release_pad_reg(void);
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extern void lpass_reset_clk_default(void);
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extern void lpass_init_clk_gate(void);
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extern void update_cp_available(bool);
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extern bool lpass_i2s_master_mode(void);
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#ifdef CONFIG_SND_SAMSUNG_SEIREN_OFFLOAD
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extern void lpass_set_cpu_lock(int level);
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#endif
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#endif /* __SND_SOC_SAMSUNG_LPASS_H */
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