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https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
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276 lines
7.7 KiB
Text
276 lines
7.7 KiB
Text
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* Marvell MBus
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Required properties:
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- compatible: Should be set to one of the following:
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marvell,armada370-mbus
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marvell,armadaxp-mbus
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marvell,armada370-mbus
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marvell,armadaxp-mbus
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marvell,kirkwood-mbus
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marvell,dove-mbus
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marvell,orion5x-88f5281-mbus
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marvell,orion5x-88f5182-mbus
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marvell,orion5x-88f5181-mbus
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marvell,orion5x-88f6183-mbus
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marvell,mv78xx0-mbus
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- address-cells: Must be '2'. The first cell for the MBus ID encoding,
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the second cell for the address offset within the window.
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- size-cells: Must be '1'.
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- ranges: Must be set up to provide a proper translation for each child.
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See the examples below.
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- controller: Contains a single phandle referring to the MBus controller
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node. This allows to specify the node that contains the
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registers that control the MBus, which is typically contained
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within the internal register window (see below).
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Optional properties:
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- pcie-mem-aperture: This optional property contains the aperture for
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the memory region of the PCIe driver.
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If it's defined, it must encode the base address and
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size for the address decoding windows allocated for
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the PCIe memory region.
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- pcie-io-aperture: Just as explained for the above property, this
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optional property contains the aperture for the
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I/O region of the PCIe driver.
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* Marvell MBus controller
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Required properties:
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- compatible: Should be set to "marvell,mbus-controller".
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- reg: Device's register space.
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Two entries are expected (see the examples below):
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the first one controls the devices decoding window and
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the second one controls the SDRAM decoding window.
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Example:
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soc {
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compatible = "marvell,armada370-mbus", "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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controller = <&mbusc>;
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pcie-mem-aperture = <0xe0000000 0x8000000>;
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pcie-io-aperture = <0xe8000000 0x100000>;
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internal-regs {
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compatible = "simple-bus";
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mbusc: mbus-controller@20000 {
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compatible = "marvell,mbus-controller";
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reg = <0x20000 0x100>, <0x20180 0x20>;
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};
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/* more children ...*/
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};
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};
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** MBus address decoding window specification
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The MBus children address space is comprised of two cells: the first one for
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the window ID and the second one for the offset within the window.
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In order to allow to describe valid and non-valid window entries, the
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following encoding is used:
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0xSIAA0000 0x00oooooo
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Where:
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S = 0x0 for a MBus valid window
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S = 0xf for a non-valid window (see below)
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If S = 0x0, then:
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I = 4-bit window target ID
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AA = windpw attribute
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If S = 0xf, then:
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I = don't care
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AA = 1 for internal register
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Following the above encoding, for each ranges entry for a MBus valid window
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(S = 0x0), an address decoding window is allocated. On the other side,
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entries for translation that do not correspond to valid windows (S = 0xf)
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are skipped.
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soc {
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compatible = "marvell,armada370-mbus", "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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controller = <&mbusc>;
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ranges = <0xf0010000 0 0 0xd0000000 0x100000
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0x01e00000 0 0 0xfff00000 0x100000>;
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bootrom {
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compatible = "marvell,bootrom";
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reg = <0x01e00000 0 0x100000>;
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};
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/* other children */
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...
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internal-regs {
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compatible = "simple-bus";
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ranges = <0 0xf0010000 0 0x100000>;
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mbusc: mbus-controller@20000 {
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compatible = "marvell,mbus-controller";
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reg = <0x20000 0x100>, <0x20180 0x20>;
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};
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/* more children ...*/
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};
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};
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In the shown example, the translation entry in the 'ranges' property is what
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makes the MBus driver create a static decoding window for the corresponding
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given child device. Note that the binding does not require child nodes to be
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present. Of course, child nodes are needed to probe the devices.
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Since each window is identified by its target ID and attribute ID there's
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a special macro that can be use to simplify the translation entries:
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#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
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Using this macro, the above example would be:
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soc {
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compatible = "marvell,armada370-mbus", "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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controller = <&mbusc>;
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ranges = < MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
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MBUS_ID(0x01, 0xe0) 0 0 0xfff00000 0x100000>;
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bootrom {
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compatible = "marvell,bootrom";
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reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
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};
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/* other children */
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...
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internal-regs {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
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mbusc: mbus-controller@20000 {
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compatible = "marvell,mbus-controller";
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reg = <0x20000 0x100>, <0x20180 0x20>;
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};
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/* other children */
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...
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};
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};
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** About the window base address
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Remember the MBus controller allows a great deal of flexibility for choosing
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the decoding window base address. When planning the device tree layout it's
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possible to choose any address as the base address, provided of course there's
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a region large enough available, and with the required alignment.
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Yet in other words: there's nothing preventing us from setting a base address
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of 0xf0000000, or 0xd0000000 for the NOR device shown above, if such region is
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unused.
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** Window allocation policy
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The mbus-node ranges property defines a set of mbus windows that are expected
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to be set by the operating system and that are guaranteed to be free of overlaps
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with one another or with the system memory ranges.
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Each entry in the property refers to exactly one window. If the operating system
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chooses to use a different set of mbus windows, it must ensure that any address
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translations performed from downstream devices are adapted accordingly.
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The operating system may insert additional mbus windows that do not conflict
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with the ones listed in the ranges, e.g. for mapping PCIe devices.
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As a special case, the internal register window must be set up by the boot
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loader at the address listed in the ranges property, since access to that region
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is needed to set up the other windows.
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** Example
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See the example below, where a more complete device tree is shown:
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soc {
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compatible = "marvell,armadaxp-mbus", "simple-bus";
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controller = <&mbusc>;
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ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000 /* internal-regs */
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MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
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MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
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bootrom {
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compatible = "marvell,bootrom";
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reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
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};
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devbus-bootcs {
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status = "okay";
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ranges = <0 MBUS_ID(0x01, 0x2f) 0 0x8000000>;
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/* NOR */
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nor {
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compatible = "cfi-flash";
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reg = <0 0x8000000>;
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bank-width = <2>;
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};
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};
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pcie-controller {
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compatible = "marvell,armada-xp-pcie";
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status = "okay";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges =
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<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
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0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
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0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
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0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
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0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
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0x82000800 0 0xe0000000 MBUS_ID(0x04, 0xe8) 0xe0000000 0 0x08000000 /* Port 0.0 MEM */
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0x81000800 0 0 MBUS_ID(0x04, 0xe0) 0xe8000000 0 0x00100000 /* Port 0.0 IO */>;
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pcie@1,0 {
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/* Port 0, Lane 0 */
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status = "okay";
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};
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};
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internal-regs {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
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mbusc: mbus-controller@20000 {
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reg = <0x20000 0x100>, <0x20180 0x20>;
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};
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interrupt-controller@20000 {
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reg = <0x20a00 0x2d0>, <0x21070 0x58>;
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};
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};
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};
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