mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-07 08:48:05 -04:00
480 lines
14 KiB
C
480 lines
14 KiB
C
/*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Data structure definition for Exynos IOMMU driver
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _EXYNOS_IOMMU_H_
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#define _EXYNOS_IOMMU_H_
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/list.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/genalloc.h>
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#include <linux/iommu.h>
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#include <linux/irq.h>
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#include <linux/clk.h>
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#include <linux/exynos_iovmm.h>
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#include "exynos-iommu-log.h"
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#define TRACE_LOG(...) do { } while (0) /* trace_printk */
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#define TRACE_LOG_DEV(dev, fmt, args...) \
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TRACE_LOG("%s: " fmt, dev_name(dev), ##args)
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#define MODULE_NAME "exynos-sysmmu"
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#define IOVA_START 0x10000000
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#define IOVM_SIZE (SZ_2G + SZ_1G + SZ_256M) /* last 4K is for error values */
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#define IOVM_NUM_PAGES(vmsize) (vmsize / PAGE_SIZE)
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#define IOVM_BITMAP_SIZE(vmsize) \
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((IOVM_NUM_PAGES(vmsize) + BITS_PER_BYTE) / BITS_PER_BYTE)
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#define SPSECT_ORDER 24
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#define DSECT_ORDER 21
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#define SECT_ORDER 20
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#define LPAGE_ORDER 16
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#define SPAGE_ORDER 12
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#define SPSECT_SIZE (1 << SPSECT_ORDER)
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#define DSECT_SIZE (1 << DSECT_ORDER)
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#define SECT_SIZE (1 << SECT_ORDER)
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#define LPAGE_SIZE (1 << LPAGE_ORDER)
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#define SPAGE_SIZE (1 << SPAGE_ORDER)
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#define SPSECT_MASK ~(SPSECT_SIZE - 1)
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#define DSECT_MASK ~(DSECT_SIZE - 1)
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#define SECT_MASK ~(SECT_SIZE - 1)
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#define LPAGE_MASK ~(LPAGE_SIZE - 1)
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#define SPAGE_MASK ~(SPAGE_SIZE - 1)
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#define SPSECT_ENT_MASK ~((SPSECT_SIZE >> PG_ENT_SHIFT) - 1)
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#define DSECT_ENT_MASK ~((DSECT_SIZE >> PG_ENT_SHIFT) - 1)
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#define SECT_ENT_MASK ~((SECT_SIZE >> PG_ENT_SHIFT) - 1)
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#define LPAGE_ENT_MASK ~((LPAGE_SIZE >> PG_ENT_SHIFT) - 1)
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#define SPAGE_ENT_MASK ~((SPAGE_SIZE >> PG_ENT_SHIFT) - 1)
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#define SECT_PER_SPSECT (SPSECT_SIZE / SECT_SIZE)
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#define SECT_PER_DSECT (DSECT_SIZE / SECT_SIZE)
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#define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
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#define PGBASE_TO_PHYS(pgent) ((phys_addr_t)(pgent) << PG_ENT_SHIFT)
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#define MAX_NUM_PBUF 6
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#define MAX_NUM_PLANE 6
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#define NUM_LV1ENTRIES 4096
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#define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE)
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#define lv1ent_offset(iova) ((iova) >> SECT_ORDER)
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#define lv2ent_offset(iova) ((iova & ~SECT_MASK) >> SPAGE_ORDER)
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typedef u32 sysmmu_pte_t;
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#define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t))
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#define ENT_TO_PHYS(ent) (phys_addr_t)(*(ent))
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#define spsection_phys(sent) PGBASE_TO_PHYS(ENT_TO_PHYS(sent) & SPSECT_ENT_MASK)
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#define spsection_offs(iova) ((iova) & (SPSECT_SIZE - 1))
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#define section_phys(sent) PGBASE_TO_PHYS(ENT_TO_PHYS(sent) & SECT_ENT_MASK)
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#define section_offs(iova) ((iova) & (SECT_SIZE - 1))
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#define lpage_phys(pent) PGBASE_TO_PHYS(ENT_TO_PHYS(pent) & LPAGE_ENT_MASK)
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#define lpage_offs(iova) ((iova) & (LPAGE_SIZE - 1))
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#define spage_phys(pent) PGBASE_TO_PHYS(ENT_TO_PHYS(pent) & SPAGE_ENT_MASK)
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#define spage_offs(iova) ((iova) & (SPAGE_SIZE - 1))
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#define lv2table_base(sent) ((phys_addr_t)(*(sent) & ~0x3F) << PG_ENT_SHIFT)
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#define SYSMMU_BLOCK_POLLING_COUNT 4096
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#define REG_MMU_CTRL 0x000
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#define REG_MMU_CFG 0x004
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#define REG_MMU_STATUS 0x008
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#define REG_MMU_VERSION 0x034
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#define CTRL_ENABLE 0x5
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#define CTRL_BLOCK 0x7
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#define CTRL_DISABLE 0x0
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#define CTRL_BLOCK_DISABLE 0x3
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#define CFG_ACGEN (1 << 24) /* System MMU 3.3+ */
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#define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ */
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#define CFG_SHAREABLE (1 << 12) /* System MMU 3.0+ */
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#define CFG_QOS_OVRRIDE (1 << 11) /* System MMU 3.3+ */
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#define CFG_QOS(n) (((n) & 0xF) << 7)
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/*
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* Metadata attached to the owner of a group of System MMUs that belong
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* to the same owner device.
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*/
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struct exynos_iommu_owner {
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struct list_head client; /* entry of exynos_iommu_domain.clients */
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struct device *dev;
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struct exynos_iommu_owner *next; /* linked list of Owners */
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void *vmm_data; /* IO virtual memory manager's data */
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spinlock_t lock; /* Lock to preserve consistency of System MMU */
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struct list_head mmu_list; /* head of sysmmu_list_data.node */
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struct notifier_block nb;
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iommu_fault_handler_t fault_handler;
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void *token;
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};
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struct exynos_vm_region {
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struct list_head node;
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u32 start;
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u32 size;
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u32 section_off;
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u32 dummy_size;
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};
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struct exynos_iovmm {
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struct iommu_domain *domain; /* iommu domain for this iovmm */
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size_t iovm_size[MAX_NUM_PLANE]; /* iovm bitmap size per plane */
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u32 iova_start[MAX_NUM_PLANE]; /* iovm start address per plane */
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unsigned long *vm_map[MAX_NUM_PLANE]; /* iovm biatmap per plane */
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struct list_head regions_list; /* list of exynos_vm_region */
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spinlock_t vmlist_lock; /* lock for updating regions_list */
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spinlock_t bitmap_lock; /* lock for manipulating bitmaps */
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struct device *dev; /* peripheral device that has this iovmm */
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size_t allocated_size[MAX_NUM_PLANE];
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int num_areas[MAX_NUM_PLANE];
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int inplanes;
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int onplanes;
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unsigned int num_map;
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unsigned int num_unmap;
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const char *domain_name;
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#ifdef CONFIG_EXYNOS_IOMMU_EVENT_LOG
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struct exynos_iommu_event_log log;
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#endif
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};
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void exynos_sysmmu_tlb_invalidate(struct iommu_domain *domain, dma_addr_t start,
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size_t size);
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#define SYSMMU_FAULT_WRITE (1 << SYSMMU_FAULTS_NUM)
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enum sysmmu_property {
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SYSMMU_PROP_RESERVED,
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SYSMMU_PROP_READ,
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SYSMMU_PROP_WRITE,
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SYSMMU_PROP_READWRITE = SYSMMU_PROP_READ | SYSMMU_PROP_WRITE,
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SYSMMU_PROP_RW_MASK = SYSMMU_PROP_READWRITE,
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SYSMMU_PROP_NONBLOCK_TLBINV = 0x10,
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SYSMMU_PROP_STOP_BLOCK = 0x20,
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SYSMMU_PROP_DISABLE_ACG = 0x40,
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SYSMMU_PROP_WINDOW_SHIFT = 16,
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SYSMMU_PROP_WINDOW_MASK = 0x1F << SYSMMU_PROP_WINDOW_SHIFT,
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};
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enum sysmmu_clock_ids {
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SYSMMU_ACLK,
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SYSMMU_PCLK,
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SYSMMU_CLK_NUM,
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};
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/*
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* Metadata attached to each System MMU devices.
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*/
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struct sysmmu_drvdata {
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struct list_head node; /* entry of exynos_iommu_owner.mmu_list */
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struct list_head pb_grp_list; /* list of pb groups */
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struct sysmmu_drvdata *next; /* linked list of System MMU */
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struct device *sysmmu; /* System MMU's device descriptor */
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struct device *master; /* Client device that needs System MMU */
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void __iomem *sfrbase;
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struct clk *clocks[SYSMMU_CLK_NUM];
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int activations;
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struct iommu_domain *domain; /* domain given to iommu_attach_device() */
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phys_addr_t pgtable;
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spinlock_t lock;
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struct sysmmu_prefbuf pbufs[MAX_NUM_PBUF];
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short qos;
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int runtime_active;
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enum sysmmu_property prop; /* mach/sysmmu.h */
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#ifdef CONFIG_EXYNOS_IOMMU_EVENT_LOG
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struct exynos_iommu_event_log log;
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#endif
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struct atomic_notifier_head fault_notifiers;
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unsigned char event_cnt;
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struct _tlbprops {
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u32 axid;
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u32 attr;
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} *tlbprops;
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u32 props_num;
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u32 hw_ver;
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u32 securebase;
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bool is_suspended;
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};
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struct exynos_iommu_domain {
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struct list_head clients; /* list of sysmmu_drvdata.node */
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sysmmu_pte_t *pgtable; /* lv1 page table, 16KB */
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atomic_t *lv2entcnt; /* free lv2 entry counter for each section */
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spinlock_t lock; /* lock for this structure */
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spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
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#ifdef CONFIG_EXYNOS_IOMMU_EVENT_LOG
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struct exynos_iommu_event_log log;
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#endif
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};
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struct pb_info {
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struct list_head node;
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int ar_id_num;
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int aw_id_num;
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int grp_num;
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int ar_axi_id[MAX_NUM_PBUF];
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int aw_axi_id[MAX_NUM_PBUF];
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struct device *master;
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enum sysmmu_property prop;
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};
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int sysmmu_set_ppc_event(struct sysmmu_drvdata *drvdata, int event);
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void dump_sysmmu_ppc_cnt(struct sysmmu_drvdata *drvdata);
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extern const char *ppc_event_name[];
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#define REG_PPC_EVENT_SEL(x) (0x600 + 0x4 * (x))
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#define REG_PPC_PMNC 0x620
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#define REG_PPC_CNTENS 0x624
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#define REG_PPC_CNTENC 0x628
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#define REG_PPC_INTENS 0x62C
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#define REG_PPC_INTENC 0x630
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#define REG_PPC_FLAG 0x634
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#define REG_PPC_CCNT 0x640
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#define REG_PPC_PMCNT(x) (0x644 + 0x4 * (x))
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#define SYSMMU_OF_COMPAT_STRING "samsung,exynos5430-sysmmu"
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#define DEFAULT_QOS_VALUE -1 /* Inherited from master */
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#define PG_ENT_SHIFT 4 /* 36bit PA, 32bit VA */
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#define lv1ent_fault(sent) ((*(sent) & 7) == 0)
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#define lv1ent_page(sent) ((*(sent) & 7) == 1)
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#define FLPD_FLAG_MASK 7
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#define SLPD_FLAG_MASK 3
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#define SPSECT_FLAG 6
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#define DSECT_FLAG 4
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#define SECT_FLAG 2
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#define SLPD_FLAG 1
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#define LPAGE_FLAG 1
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#define SPAGE_FLAG 2
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#define lv1ent_section(sent) ((*(sent) & FLPD_FLAG_MASK) == SECT_FLAG)
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#define lv1ent_dsection(sent) ((*(sent) & FLPD_FLAG_MASK) == DSECT_FLAG)
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#define lv1ent_spsection(sent) ((*(sent) & FLPD_FLAG_MASK) == SPSECT_FLAG)
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#define lv2ent_fault(pent) ((*(pent) & SLPD_FLAG_MASK) == 0 || \
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(PGBASE_TO_PHYS(*(pent) & SPAGE_ENT_MASK) == fault_page))
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#define lv2ent_small(pent) ((*(pent) & SLPD_FLAG_MASK) == SPAGE_FLAG)
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#define lv2ent_large(pent) ((*(pent) & SLPD_FLAG_MASK) == LPAGE_FLAG)
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#define dsection_phys(sent) PGBASE_TO_PHYS(*(sent) & DSECT_ENT_MASK)
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#define dsection_offs(iova) ((iova) & (DSECT_SIZE - 1))
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#define mk_lv1ent_spsect(pa) ((sysmmu_pte_t) ((pa) >> PG_ENT_SHIFT) | 6)
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#define mk_lv1ent_dsect(pa) ((sysmmu_pte_t) ((pa) >> PG_ENT_SHIFT) | 4)
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#define mk_lv1ent_sect(pa) ((sysmmu_pte_t) ((pa) >> PG_ENT_SHIFT) | 2)
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#define mk_lv1ent_page(pa) ((sysmmu_pte_t) ((pa) >> PG_ENT_SHIFT) | 1)
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#define mk_lv2ent_lpage(pa) ((sysmmu_pte_t) ((pa) >> PG_ENT_SHIFT) | 1)
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#define mk_lv2ent_spage(pa) ((sysmmu_pte_t) ((pa) >> PG_ENT_SHIFT) | 2)
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#define set_lv1ent_shareable(sent) (*(sent) |= (1 << 6))
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#define set_lv2ent_shareable(pent) (*(pent) |= (1 << 4))
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#define mk_lv2ent_pfnmap(pent) (*(pent) |= (1 << 5)) /* unused field */
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#define lv2ent_pfnmap(pent) ((*(pent) & (1 << 5)) == (1 << 5))
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#define PGSIZE_BITMAP (DSECT_SIZE | SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE)
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void __sysmmu_show_status(struct sysmmu_drvdata *drvdata);
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static inline void __sysmmu_clk_enable(struct sysmmu_drvdata *data)
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{
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if (!IS_ERR(data->clocks[SYSMMU_ACLK]))
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clk_enable(data->clocks[SYSMMU_ACLK]);
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if (!IS_ERR(data->clocks[SYSMMU_PCLK]))
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clk_enable(data->clocks[SYSMMU_PCLK]);
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}
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static inline void __sysmmu_clk_disable(struct sysmmu_drvdata *data)
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{
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if (!IS_ERR(data->clocks[SYSMMU_ACLK]))
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clk_disable(data->clocks[SYSMMU_ACLK]);
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if (!IS_ERR(data->clocks[SYSMMU_PCLK]))
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clk_disable(data->clocks[SYSMMU_PCLK]);
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}
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static inline bool get_sysmmu_runtime_active(struct sysmmu_drvdata *data)
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{
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return ++data->runtime_active == 1;
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}
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static inline bool put_sysmmu_runtime_active(struct sysmmu_drvdata *data)
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{
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BUG_ON(data->runtime_active < 1);
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return --data->runtime_active == 0;
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}
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static inline bool is_sysmmu_runtime_active(struct sysmmu_drvdata *data)
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{
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return data->runtime_active > 0;
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}
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static inline bool set_sysmmu_active(struct sysmmu_drvdata *data)
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{
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/* return true if the System MMU was not active previously
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and it needs to be initialized */
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return ++data->activations == 1;
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}
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static inline bool set_sysmmu_inactive(struct sysmmu_drvdata *data)
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{
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/* return true if the System MMU is needed to be disabled */
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BUG_ON(data->activations < 1);
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return --data->activations == 0;
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}
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static inline bool is_sysmmu_active(struct sysmmu_drvdata *data)
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{
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return !data->is_suspended && data->activations > 0;
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}
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static inline bool is_sysmmu_really_enabled(struct sysmmu_drvdata *data)
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{
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return is_sysmmu_active(data) && data->runtime_active;
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}
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#define MMU_MAJ_VER(val) ((val) >> 11)
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#define MMU_MIN_VER(val) ((val >> 4) & 0x7F)
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#define MMU_REV_VER(val) ((val) & 0xF)
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#define MMU_RAW_VER(reg) (((reg) >> 17) & 0x7FFF) /* upper 15 bits */
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#define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 11) | \
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(((min) & 0x7F) << 4))
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static inline unsigned int __raw_sysmmu_version(void __iomem *sfrbase)
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{
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return MMU_RAW_VER(__raw_readl(sfrbase + REG_MMU_VERSION));
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}
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static inline void __raw_sysmmu_disable(void __iomem *sfrbase, int disable)
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{
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__raw_writel(0, sfrbase + REG_MMU_CFG);
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__raw_writel(disable, sfrbase + REG_MMU_CTRL);
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BUG_ON(__raw_readl(sfrbase + REG_MMU_CTRL) != disable);
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}
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static inline void __raw_sysmmu_enable(void __iomem *sfrbase)
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{
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__raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL);
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}
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#define sysmmu_unblock __raw_sysmmu_enable
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void dump_sysmmu_tlb_pb(void __iomem *sfrbase);
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static inline bool sysmmu_block(void __iomem *sfrbase)
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{
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int i = SYSMMU_BLOCK_POLLING_COUNT;
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__raw_writel(CTRL_BLOCK, sfrbase + REG_MMU_CTRL);
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while ((i > 0) && !(__raw_readl(sfrbase + REG_MMU_STATUS) & 1))
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--i;
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if (!(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) {
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dump_sysmmu_tlb_pb(sfrbase);
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panic("Failed to block System MMU!");
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sysmmu_unblock(sfrbase);
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return false;
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}
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return true;
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}
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void __sysmmu_init_config(struct sysmmu_drvdata *drvdata);
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void __sysmmu_set_ptbase(void __iomem *sfrbase, phys_addr_t pfn_pgtable);
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extern sysmmu_pte_t *zero_lv2_table;
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static inline sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, unsigned long iova)
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{
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return (sysmmu_pte_t *)(phys_to_virt(lv2table_base(sent))) +
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lv2ent_offset(iova);
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}
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static inline sysmmu_pte_t *section_entry(
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sysmmu_pte_t *pgtable, unsigned long iova)
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{
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return (sysmmu_pte_t *)(pgtable + lv1ent_offset(iova));
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}
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irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id);
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void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase, dma_addr_t iova);
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void __sysmmu_tlb_invalidate(struct sysmmu_drvdata *drvdata,
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dma_addr_t iova, size_t size);
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int exynos_iommu_map_userptr(struct iommu_domain *dom, unsigned long addr,
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dma_addr_t iova, size_t size, int prot);
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void exynos_iommu_unmap_userptr(struct iommu_domain *dom,
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dma_addr_t iova, size_t size);
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void dump_sysmmu_tlb_pb(void __iomem *sfrbase);
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#if defined(CONFIG_EXYNOS_IOVMM)
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static inline struct exynos_iovmm *exynos_get_iovmm(struct device *dev)
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{
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if (!dev->archdata.iommu) {
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dev_err(dev, "%s: System MMU is not configured\n", __func__);
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return NULL;
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}
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return ((struct exynos_iommu_owner *)dev->archdata.iommu)->vmm_data;
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}
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struct exynos_vm_region *find_iovm_region(struct exynos_iovmm *vmm,
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dma_addr_t iova);
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static inline int find_iovmm_plane(struct exynos_iovmm *vmm, dma_addr_t iova)
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{
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int i;
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for (i = 0; i < (vmm->inplanes + vmm->onplanes); i++)
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if ((iova >= vmm->iova_start[i]) &&
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(iova < (vmm->iova_start[i] + vmm->iovm_size[i])))
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return i;
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return -1;
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}
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struct exynos_iovmm *exynos_create_single_iovmm(const char *name);
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int exynos_sysmmu_add_fault_notifier(struct device *dev,
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iommu_fault_handler_t handler, void *token);
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#else
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static inline struct exynos_iovmm *exynos_get_iovmm(struct device *dev)
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{
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return NULL;
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}
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struct exynos_vm_region *find_iovm_region(struct exynos_iovmm *vmm,
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dma_addr_t iova)
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{
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return NULL;
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}
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static inline int find_iovmm_plane(struct exynos_iovmm *vmm, dma_addr_t iova)
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{
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return -1;
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}
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static inline struct exynos_iovmm *exynos_create_single_iovmm(const char *name)
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{
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return NULL;
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}
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#endif /* CONFIG_EXYNOS_IOVMM */
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#endif /* _EXYNOS_IOMMU_H_ */
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