mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-11-01 08:38:52 +01:00
484 lines
32 KiB
C
484 lines
32 KiB
C
/*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd. All rights reserved.
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* http://www.samsung.com
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*
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* Chip Abstraction Layer for local/system power down support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __EXYNOS7870_CMUSFR_H__
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#define __EXYNOS7870_CMUSFR_H__
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#include "S5E7870-sfrbase.h"
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#define MEM_PLL_LOCK ((void *)(CMU_MIF_BASE + 0x0000))
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#define MEDIA_PLL_LOCK ((void *)(CMU_MIF_BASE + 0x0020))
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#define BUS_PLL_LOCK ((void *)(CMU_MIF_BASE + 0x0040))
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#define MEM_PLL_CON0 ((void *)(CMU_MIF_BASE + 0x0100))
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#define MEM_PLL_CON1 ((void *)(CMU_MIF_BASE + 0x0104))
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#define MEDIA_PLL_CON0 ((void *)(CMU_MIF_BASE + 0x0120))
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#define MEDIA_PLL_CON1 ((void *)(CMU_MIF_BASE + 0x0124))
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#define BUS_PLL_CON0 ((void *)(CMU_MIF_BASE + 0x0140))
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#define BUS_PLL_CON1 ((void *)(CMU_MIF_BASE + 0x0144))
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#define CLK_CON_MUX_MEM_PLL ((void *)(CMU_MIF_BASE + 0x0200))
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#define CLK_CON_MUX_MEDIA_PLL ((void *)(CMU_MIF_BASE + 0x0204))
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#define CLK_CON_MUX_BUS_PLL ((void *)(CMU_MIF_BASE + 0x0208))
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#define CLK_CON_MUX_CLK_MIF_PHY_CLK2X ((void *)(CMU_MIF_BASE + 0x0210))
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#define CLK_CON_MUX_CLK_MIF_PHY_SWITCH ((void *)(CMU_MIF_BASE + 0x0214))
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#define CLK_CON_MUX_CLK_MIF_BUSD ((void *)(CMU_MIF_BASE + 0x0220))
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#define CLK_CON_MUX_CLK_MIF_CCI ((void *)(CMU_MIF_BASE + 0x0228))
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#define CLK_CON_MUX_CLKCMU_ISP_VRA ((void *)(CMU_MIF_BASE + 0x0264))
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#define CLK_CON_MUX_CLKCMU_ISP_CAM ((void *)(CMU_MIF_BASE + 0x0268))
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#define CLK_CON_MUX_CLKCMU_ISP_ISP ((void *)(CMU_MIF_BASE + 0x026C))
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#define CLK_CON_MUX_CLKCMU_DISPAUD_BUS ((void *)(CMU_MIF_BASE + 0x0270))
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#define CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK ((void *)(CMU_MIF_BASE + 0x0274))
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#define CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK ((void *)(CMU_MIF_BASE + 0x0278))
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#define CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL ((void *)(CMU_MIF_BASE + 0x027C))
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#define CLK_CON_MUX_CLKCMU_MFCMSCL_MFC ((void *)(CMU_MIF_BASE + 0x0280))
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#define CLK_CON_MUX_CLKCMU_FSYS_BUS ((void *)(CMU_MIF_BASE + 0x0284))
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#define CLK_CON_MUX_CLKCMU_FSYS_MMC0 ((void *)(CMU_MIF_BASE + 0x0288))
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#define CLK_CON_MUX_CLKCMU_FSYS_MMC1 ((void *)(CMU_MIF_BASE + 0x028C))
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#define CLK_CON_MUX_CLKCMU_FSYS_MMC2 ((void *)(CMU_MIF_BASE + 0x0290))
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#define CLK_CON_MUX_CLKCMU_FSYS_UFSUNIPRO ((void *)(CMU_MIF_BASE + 0x0294))
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#define CLK_CON_MUX_CLKCMU_FSYS_UFSUNIPRO_CFG ((void *)(CMU_MIF_BASE + 0x0298))
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#define CLK_CON_MUX_CLKCMU_FSYS_USB20DRD_REFCLK ((void *)(CMU_MIF_BASE + 0x029C))
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#define CLK_CON_MUX_CLKCMU_PERI_BUS ((void *)(CMU_MIF_BASE + 0x02A0))
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#define CLK_CON_MUX_CLKCMU_PERI_UART_BTWIFIFM ((void *)(CMU_MIF_BASE + 0x02A4))
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#define CLK_CON_MUX_CLKCMU_PERI_UART_DEBUG ((void *)(CMU_MIF_BASE + 0x02A8))
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#define CLK_CON_MUX_CLKCMU_PERI_UART_SENSOR ((void *)(CMU_MIF_BASE + 0x02AC))
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#define CLK_CON_MUX_CLKCMU_PERI_SPI_FRONTFROM ((void *)(CMU_MIF_BASE + 0x02B0))
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#define CLK_CON_MUX_CLKCMU_PERI_SPI_REARFROM ((void *)(CMU_MIF_BASE + 0x02B4))
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#define CLK_CON_MUX_CLKCMU_PERI_SPI_ESE ((void *)(CMU_MIF_BASE + 0x02B8))
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#define CLK_CON_MUX_CLKCMU_PERI_SPI_VOICEPROCESSOR ((void *)(CMU_MIF_BASE + 0x02BC))
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#define CLK_CON_MUX_CLKCMU_PERI_SPI_SENSORHUB ((void *)(CMU_MIF_BASE + 0x02C0))
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#define CLK_CON_MUX_CLKCMU_ISP_SENSOR0 ((void *)(CMU_MIF_BASE + 0x02C4))
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#define CLK_CON_MUX_CLKCMU_ISP_SENSOR1 ((void *)(CMU_MIF_BASE + 0x02C8))
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#define CLK_CON_MUX_CLKCMU_ISP_SENSOR2 ((void *)(CMU_MIF_BASE + 0x02CC))
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#define CLK_CON_DIV_CLK_MIF_PHY_CLKM ((void *)(CMU_MIF_BASE + 0x0414))
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#define CLK_CON_DIV_CLK_MIF_BUSD ((void *)(CMU_MIF_BASE + 0x0420))
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#define CLK_CON_DIV_CLK_MIF_APB ((void *)(CMU_MIF_BASE + 0x0424))
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#define CLK_CON_DIV_CLK_MIF_CCI ((void *)(CMU_MIF_BASE + 0x0428))
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#define CLK_CON_DIV_CLK_MIF_BUSP ((void *)(CMU_MIF_BASE + 0x042C))
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#define CLK_CON_DIV_CLK_MIF_HSI2C ((void *)(CMU_MIF_BASE + 0x0430))
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#define CLK_CON_DIV_CLKCMU_CP_MEDIA_PLL ((void *)(CMU_MIF_BASE + 0x0450))
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#define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH ((void *)(CMU_MIF_BASE + 0x0458))
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#define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH ((void *)(CMU_MIF_BASE + 0x045C))
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#define CLK_CON_DIV_CLKCMU_G3D_SWITCH ((void *)(CMU_MIF_BASE + 0x0460))
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#define CLK_CON_DIV_CLKCMU_ISP_VRA ((void *)(CMU_MIF_BASE + 0x0464))
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#define CLK_CON_DIV_CLKCMU_ISP_CAM ((void *)(CMU_MIF_BASE + 0x0468))
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#define CLK_CON_DIV_CLKCMU_ISP_ISP ((void *)(CMU_MIF_BASE + 0x046C))
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#define CLK_CON_DIV_CLKCMU_DISPAUD_BUS ((void *)(CMU_MIF_BASE + 0x0470))
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#define CLK_CON_DIV_CLKCMU_DISPAUD_DECON_INT_VCLK ((void *)(CMU_MIF_BASE + 0x0474))
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#define CLK_CON_DIV_CLKCMU_DISPAUD_DECON_INT_ECLK ((void *)(CMU_MIF_BASE + 0x0478))
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#define CLK_CON_DIV_CLKCMU_MFCMSCL_MSCL ((void *)(CMU_MIF_BASE + 0x047C))
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#define CLK_CON_DIV_CLKCMU_MFCMSCL_MFC ((void *)(CMU_MIF_BASE + 0x0480))
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#define CLK_CON_DIV_CLKCMU_FSYS_BUS ((void *)(CMU_MIF_BASE + 0x0484))
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#define CLK_CON_DIV_CLKCMU_FSYS_MMC0 ((void *)(CMU_MIF_BASE + 0x0488))
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#define CLK_CON_DIV_CLKCMU_FSYS_MMC1 ((void *)(CMU_MIF_BASE + 0x048C))
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#define CLK_CON_DIV_CLKCMU_FSYS_MMC2 ((void *)(CMU_MIF_BASE + 0x0490))
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#define CLK_CON_DIV_CLKCMU_FSYS_UFSUNIPRO ((void *)(CMU_MIF_BASE + 0x0494))
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#define CLK_CON_DIV_CLKCMU_FSYS_UFSUNIPRO_CFG ((void *)(CMU_MIF_BASE + 0x0498))
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#define CLK_CON_DIV_CLKCMU_FSYS_USB20DRD_REFCLK ((void *)(CMU_MIF_BASE + 0x049C))
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#define CLK_CON_DIV_CLKCMU_PERI_BUS ((void *)(CMU_MIF_BASE + 0x04A0))
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#define CLK_CON_DIV_CLKCMU_PERI_UART_BTWIFIFM ((void *)(CMU_MIF_BASE + 0x04A4))
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#define CLK_CON_DIV_CLKCMU_PERI_UART_DEBUG ((void *)(CMU_MIF_BASE + 0x04A8))
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#define CLK_CON_DIV_CLKCMU_PERI_UART_SENSOR ((void *)(CMU_MIF_BASE + 0x04AC))
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#define CLK_CON_DIV_CLKCMU_PERI_SPI_FRONTFROM ((void *)(CMU_MIF_BASE + 0x04B0))
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#define CLK_CON_DIV_CLKCMU_PERI_SPI_REARFROM ((void *)(CMU_MIF_BASE + 0x04B4))
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#define CLK_CON_DIV_CLKCMU_PERI_SPI_ESE ((void *)(CMU_MIF_BASE + 0x04B8))
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#define CLK_CON_DIV_CLKCMU_PERI_SPI_VOICEPROCESSOR ((void *)(CMU_MIF_BASE + 0x04BC))
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#define CLK_CON_DIV_CLKCMU_PERI_SPI_SENSORHUB ((void *)(CMU_MIF_BASE + 0x04C0))
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#define CLK_CON_DIV_CLKCMU_ISP_SENSOR0 ((void *)(CMU_MIF_BASE + 0x04C4))
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#define CLK_CON_DIV_CLKCMU_ISP_SENSOR1 ((void *)(CMU_MIF_BASE + 0x04C8))
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#define CLK_CON_DIV_CLKCMU_ISP_SENSOR2 ((void *)(CMU_MIF_BASE + 0x04CC))
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#define CLK_STAT_MUX_MEM_PLL ((void *)(CMU_MIF_BASE + 0x0600))
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#define CLK_STAT_MUX_MEDIA_PLL ((void *)(CMU_MIF_BASE + 0x0604))
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#define CLK_STAT_MUX_BUS_PLL ((void *)(CMU_MIF_BASE + 0x0608))
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#define CLK_STAT_MUX_CLK_MIF_PHY_CLK2X ((void *)(CMU_MIF_BASE + 0x0610))
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#define CLK_STAT_MUX_CLK_MIF_PHY_SWITCH ((void *)(CMU_MIF_BASE + 0x0614))
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#define CLK_STAT_MUX_CLK_MIF_BUSD ((void *)(CMU_MIF_BASE + 0x0620))
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#define CLK_STAT_MUX_CLK_MIF_CCI ((void *)(CMU_MIF_BASE + 0x0628))
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#define CLK_STAT_MUX_CLKCMU_ISP_VRA ((void *)(CMU_MIF_BASE + 0x0664))
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#define CLK_STAT_MUX_CLKCMU_ISP_CAM ((void *)(CMU_MIF_BASE + 0x0668))
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#define CLK_STAT_MUX_CLKCMU_ISP_ISP ((void *)(CMU_MIF_BASE + 0x066C))
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#define CLK_STAT_MUX_CLKCMU_DISPAUD_BUS ((void *)(CMU_MIF_BASE + 0x0670))
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#define CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK ((void *)(CMU_MIF_BASE + 0x0674))
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#define CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK ((void *)(CMU_MIF_BASE + 0x0678))
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#define CLK_STAT_MUX_CLKCMU_MFCMSCL_MSCL ((void *)(CMU_MIF_BASE + 0x067C))
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#define CLK_STAT_MUX_CLKCMU_MFCMSCL_MFC ((void *)(CMU_MIF_BASE + 0x0680))
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#define CLK_STAT_MUX_CLKCMU_FSYS_BUS ((void *)(CMU_MIF_BASE + 0x0684))
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#define CLK_STAT_MUX_CLKCMU_FSYS_MMC0 ((void *)(CMU_MIF_BASE + 0x0688))
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#define CLK_STAT_MUX_CLKCMU_FSYS_MMC1 ((void *)(CMU_MIF_BASE + 0x068C))
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#define CLK_STAT_MUX_CLKCMU_FSYS_MMC2 ((void *)(CMU_MIF_BASE + 0x0690))
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#define CLK_STAT_MUX_CLKCMU_FSYS_UFSUNIPRO ((void *)(CMU_MIF_BASE + 0x0694))
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#define CLK_STAT_MUX_CLKCMU_FSYS_UFSUNIPRO_CFG ((void *)(CMU_MIF_BASE + 0x0698))
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#define CLK_STAT_MUX_CLKCMU_FSYS_USB20DRD_REFCLK ((void *)(CMU_MIF_BASE + 0x069C))
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#define CLK_STAT_MUX_CLKCMU_PERI_BUS ((void *)(CMU_MIF_BASE + 0x06A0))
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#define CLK_STAT_MUX_CLKCMU_PERI_UART_BTWIFIFM ((void *)(CMU_MIF_BASE + 0x06A4))
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#define CLK_STAT_MUX_CLKCMU_PERI_UART_DEBUG ((void *)(CMU_MIF_BASE + 0x06A8))
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#define CLK_STAT_MUX_CLKCMU_PERI_UART_SENSOR ((void *)(CMU_MIF_BASE + 0x06AC))
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#define CLK_STAT_MUX_CLKCMU_PERI_SPI_FRONTFROM ((void *)(CMU_MIF_BASE + 0x06B0))
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#define CLK_STAT_MUX_CLKCMU_PERI_SPI_REARFROM ((void *)(CMU_MIF_BASE + 0x06B4))
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#define CLK_STAT_MUX_CLKCMU_PERI_SPI_ESE ((void *)(CMU_MIF_BASE + 0x06B8))
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#define CLK_STAT_MUX_CLKCMU_PERI_SPI_VOICEPROCESSOR ((void *)(CMU_MIF_BASE + 0x06BC))
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#define CLK_STAT_MUX_CLKCMU_PERI_SPI_SENSORHUB ((void *)(CMU_MIF_BASE + 0x06C0))
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#define CLK_STAT_MUX_CLKCMU_ISP_SENSOR0 ((void *)(CMU_MIF_BASE + 0x06C4))
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#define CLK_STAT_MUX_CLKCMU_ISP_SENSOR1 ((void *)(CMU_MIF_BASE + 0x06C8))
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#define CLK_STAT_MUX_CLKCMU_ISP_SENSOR2 ((void *)(CMU_MIF_BASE + 0x06CC))
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#define CLK_ENABLE_CLK_MIF_OSCCLK ((void *)(CMU_MIF_BASE + 0x080C))
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#define CLK_ENABLE_CLK_MIF_PHY_CLK2X ((void *)(CMU_MIF_BASE + 0x0810))
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#define CLK_ENABLE_CLK_MIF_PHY_CLKM ((void *)(CMU_MIF_BASE + 0x0814))
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#define CLK_ENABLE_CLK_MIF_DDRPHY0 ((void *)(CMU_MIF_BASE + 0x0818))
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#define CLK_ENABLE_CLK_MIF_BUSD ((void *)(CMU_MIF_BASE + 0x0820))
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#define CLK_ENABLE_CLK_MIF_APB0 ((void *)(CMU_MIF_BASE + 0x0824))
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#define CLK_ENABLE_CLK_MIF_APB1 ((void *)(CMU_MIF_BASE + 0x0828))
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#define CLK_ENABLE_CLK_MIF_APB_SECURE_DMC0 ((void *)(CMU_MIF_BASE + 0x082C))
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#define CLK_ENABLE_CLK_MIF_APB_SECURE_MODAPIF ((void *)(CMU_MIF_BASE + 0x0830))
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#define CLK_ENABLE_CLK_MIF_CCI ((void *)(CMU_MIF_BASE + 0x0834))
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#define CLK_ENABLE_CLK_MIF_BUSP ((void *)(CMU_MIF_BASE + 0x0838))
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#define CLK_ENABLE_CLK_MIF_BUSP_SECURE_INTMEM ((void *)(CMU_MIF_BASE + 0x083C))
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#define CLK_ENABLE_CLK_MIF_HSI2C ((void *)(CMU_MIF_BASE + 0x0840))
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#define CLK_ENABLE_CLKCMU_CP_MEDIA_PLL ((void *)(CMU_MIF_BASE + 0x0850))
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#define CLK_ENABLE_CLKCMU_CPUCL0_SWITCH ((void *)(CMU_MIF_BASE + 0x0858))
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#define CLK_ENABLE_CLKCMU_CPUCL1_SWITCH ((void *)(CMU_MIF_BASE + 0x085C))
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#define CLK_ENABLE_CLKCMU_G3D_SWITCH ((void *)(CMU_MIF_BASE + 0x0860))
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#define CLK_ENABLE_CLKCMU_ISP_VRA ((void *)(CMU_MIF_BASE + 0x0864))
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#define CLK_ENABLE_CLKCMU_ISP_CAM ((void *)(CMU_MIF_BASE + 0x0868))
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#define CLK_ENABLE_CLKCMU_ISP_ISP ((void *)(CMU_MIF_BASE + 0x086C))
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#define CLK_ENABLE_CLKCMU_DISPAUD_BUS ((void *)(CMU_MIF_BASE + 0x0870))
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#define CLK_ENABLE_CLKCMU_DISPAUD_DECON_INT_VCLK ((void *)(CMU_MIF_BASE + 0x0874))
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#define CLK_ENABLE_CLKCMU_DISPAUD_DECON_INT_ECLK ((void *)(CMU_MIF_BASE + 0x0878))
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#define CLK_ENABLE_CLKCMU_MFCMSCL_MSCL ((void *)(CMU_MIF_BASE + 0x087C))
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#define CLK_ENABLE_CLKCMU_MFCMSCL_MFC ((void *)(CMU_MIF_BASE + 0x0880))
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#define CLK_ENABLE_CLKCMU_FSYS_BUS ((void *)(CMU_MIF_BASE + 0x0884))
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#define CLK_ENABLE_CLKCMU_FSYS_MMC0 ((void *)(CMU_MIF_BASE + 0x0888))
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#define CLK_ENABLE_CLKCMU_FSYS_MMC1 ((void *)(CMU_MIF_BASE + 0x088C))
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#define CLK_ENABLE_CLKCMU_FSYS_MMC2 ((void *)(CMU_MIF_BASE + 0x0890))
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#define CLK_ENABLE_CLKCMU_FSYS_UFSUNIPRO ((void *)(CMU_MIF_BASE + 0x0894))
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#define CLK_ENABLE_CLKCMU_FSYS_UFSUNIPRO_CFG ((void *)(CMU_MIF_BASE + 0x0898))
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#define CLK_ENABLE_CLKCMU_FSYS_USB20DRD_REFCLK ((void *)(CMU_MIF_BASE + 0x089C))
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#define CLK_ENABLE_CLKCMU_PERI_BUS ((void *)(CMU_MIF_BASE + 0x08A0))
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#define CLK_ENABLE_CLKCMU_PERI_UART_BTWIFIFM ((void *)(CMU_MIF_BASE + 0x08A4))
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#define CLK_ENABLE_CLKCMU_PERI_UART_DEBUG ((void *)(CMU_MIF_BASE + 0x08A8))
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#define CLK_ENABLE_CLKCMU_PERI_UART_SENSOR ((void *)(CMU_MIF_BASE + 0x08AC))
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#define CLK_ENABLE_CLKCMU_PERI_SPI_FRONTFROM ((void *)(CMU_MIF_BASE + 0x08B0))
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#define CLK_ENABLE_CLKCMU_PERI_SPI_REARFROM ((void *)(CMU_MIF_BASE + 0x08B4))
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#define CLK_ENABLE_CLKCMU_PERI_SPI_ESE ((void *)(CMU_MIF_BASE + 0x08B8))
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#define CLK_ENABLE_CLKCMU_PERI_SPI_VOICEPROCESSOR ((void *)(CMU_MIF_BASE + 0x08BC))
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#define CLK_ENABLE_CLKCMU_PERI_SPI_SENSORHUB ((void *)(CMU_MIF_BASE + 0x08C0))
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#define CLK_ENABLE_CLKCMU_ISP_SENSOR0 ((void *)(CMU_MIF_BASE + 0x08C4))
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#define CLK_ENABLE_CLKCMU_ISP_SENSOR1 ((void *)(CMU_MIF_BASE + 0x08C8))
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#define CLK_ENABLE_CLKCMU_ISP_SENSOR2 ((void *)(CMU_MIF_BASE + 0x08CC))
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#define SECURE_ENABLE_CLKCMU_FSYS_BUS ((void *)(CMU_MIF_BASE + 0x08D0))
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#define CLKOUT_CMU_MIF ((void *)(CMU_MIF_BASE + 0x0D00))
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#define CLKOUT_CMU_MIF_DIV_STAT ((void *)(CMU_MIF_BASE + 0x0D04))
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#define CMU_MIF_SPARE0 ((void *)(CMU_MIF_BASE + 0x0D08))
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#define CMU_MIF_SPARE1 ((void *)(CMU_MIF_BASE + 0x0D0C))
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#define CLK_ENABLE_PDN_MIF ((void *)(CMU_MIF_BASE + 0x0E00))
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#define MIF_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_MIF_BASE + 0x0F00))
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#define MIF_ROOTCLKEN ((void *)(CMU_MIF_BASE + 0x0F04))
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#define MIF_ROOTCLKEN_ON_GATE ((void *)(CMU_MIF_BASE + 0x0F10))
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#define DREX_FREQ_CTRL1 ((void *)(CMU_MIF_BASE + 0x1004))
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#define PAUSE ((void *)(CMU_MIF_BASE + 0x1008))
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#define DDRPHY_LOCK_CTRL ((void *)(CMU_MIF_BASE + 0x100C))
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#define ACG_ENABLE ((void *)(CMU_MIF_BASE + 0x1010))
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#define CP_CTRL_HSI2C_ENABLE ((void *)(CMU_MIF_BASE + 0x1014))
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#define CP_CTRL_ADCIF_ENABLE ((void *)(CMU_MIF_BASE + 0x1018))
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#define FAKE_PAUSE ((void *)(CMU_MIF_BASE + 0x1020))
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#define CG_CTRL_VAL_CLK_MIF_BUSD ((void *)(CMU_MIF_BASE + 0x1800))
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#define CG_CTRL_VAL_CLK_MIF_APB ((void *)(CMU_MIF_BASE + 0x1804))
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#define CG_CTRL_VAL_CLK_MIF_CCI ((void *)(CMU_MIF_BASE + 0x1808))
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#define CG_CTRL_MAN_CLK_MIF_BUSD ((void *)(CMU_MIF_BASE + 0x1900))
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#define CG_CTRL_MAN_CLK_MIF_APB ((void *)(CMU_MIF_BASE + 0x1904))
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#define CG_CTRL_MAN_CLK_MIF_CCI ((void *)(CMU_MIF_BASE + 0x1908))
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#define CG_CTRL_STAT_CLK_MIF_BUSD ((void *)(CMU_MIF_BASE + 0x1A00))
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#define CG_CTRL_STAT_CLK_MIF_APB ((void *)(CMU_MIF_BASE + 0x1A04))
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#define CG_CTRL_STAT_CLK_MIF_CCI ((void *)(CMU_MIF_BASE + 0x1A08))
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#define QCH_CTRL_UID_MIF_D_CCI ((void *)(CMU_MIF_BASE + 0x2000))
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#define QCH_CTRL_UID_MIF_D_NRT ((void *)(CMU_MIF_BASE + 0x2004))
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#define QCH_CTRL_UID_MIF_D_RT ((void *)(CMU_MIF_BASE + 0x2008))
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#define QCH_CTRL_UID_ASYNCM_LH_G3D0_MIF_D_NRT ((void *)(CMU_MIF_BASE + 0x200C))
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#define QCH_CTRL_UID_ASYNCM_LH_MFCMSCL0_MIF_D_NRT ((void *)(CMU_MIF_BASE + 0x2010))
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#define QCH_CTRL_UID_ASYNCM_LH_FSYS_MIF_D_NRT ((void *)(CMU_MIF_BASE + 0x2014))
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#define QCH_CTRL_UID_ASYNCM_LH_ISP_MIF_D_NRT ((void *)(CMU_MIF_BASE + 0x2018))
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#define QCH_CTRL_UID_ASYNCM_LH_ISP_MIF_D_RT ((void *)(CMU_MIF_BASE + 0x201C))
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#define QCH_CTRL_UID_ASYNCM_LH_DISPAUD_MIF_D_RT ((void *)(CMU_MIF_BASE + 0x2020))
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#define CPUCL0_PLL_LOCK ((void *)(CMU_CPUCL0_BASE + 0x0000))
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#define CPUCL0_PLL_CON0 ((void *)(CMU_CPUCL0_BASE + 0x0100))
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#define CPUCL0_PLL_CON1 ((void *)(CMU_CPUCL0_BASE + 0x0104))
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#define CLK_CON_MUX_CPUCL0_PLL ((void *)(CMU_CPUCL0_BASE + 0x0200))
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#define CLK_CON_MUX_CLKCMU_CPUCL0_SWITCH_USER ((void *)(CMU_CPUCL0_BASE + 0x0204))
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#define CLK_CON_MUX_CLK_CPUCL0 ((void *)(CMU_CPUCL0_BASE + 0x0208))
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#define CLK_CON_DIV_CLK_CPUCL0_1 ((void *)(CMU_CPUCL0_BASE + 0x0400))
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#define CLK_CON_DIV_CLK_CPUCL0_2 ((void *)(CMU_CPUCL0_BASE + 0x0404))
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#define CLK_CON_DIV_CLK_CPUCL0_ACLK ((void *)(CMU_CPUCL0_BASE + 0x0408))
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#define CLK_CON_DIV_CLK_CPUCL0_PCLK ((void *)(CMU_CPUCL0_BASE + 0x040C))
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#define CLK_CON_DIV_CLK_CPUCL0_ATCLK ((void *)(CMU_CPUCL0_BASE + 0x0410))
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#define CLK_CON_DIV_CLK_CPUCL0_PCLKDBG ((void *)(CMU_CPUCL0_BASE + 0x0414))
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#define CLK_CON_DIV_CLK_CPUCL0_CNTCLK ((void *)(CMU_CPUCL0_BASE + 0x0418))
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#define CLK_CON_DIV_CLK_CPUCL0_RUN_MONITOR ((void *)(CMU_CPUCL0_BASE + 0x041C))
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#define CLK_CON_DIV_CLK_CPUCL0_HPM ((void *)(CMU_CPUCL0_BASE + 0x0420))
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#define CLK_CON_DIV_CLK_CPUCL0_PLL ((void *)(CMU_CPUCL0_BASE + 0x0424))
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#define CLK_STAT_MUX_CPUCL0_PLL ((void *)(CMU_CPUCL0_BASE + 0x0600))
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#define CLK_STAT_MUX_CLKCMU_CPUCL0_SWITCH_USER ((void *)(CMU_CPUCL0_BASE + 0x0604))
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#define CLK_STAT_MUX_CLK_CPUCL0 ((void *)(CMU_CPUCL0_BASE + 0x0608))
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#define CLK_ENABLE_CLK_CPUCL0_OSCCLK ((void *)(CMU_CPUCL0_BASE + 0x0800))
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#define CLK_ENABLE_CLK_CPUCL0_ACLK ((void *)(CMU_CPUCL0_BASE + 0x0808))
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#define CLK_ENABLE_CLK_CPUCL0_PCLK ((void *)(CMU_CPUCL0_BASE + 0x080C))
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#define CLK_ENABLE_CLK_CPUCL0_ATCLK ((void *)(CMU_CPUCL0_BASE + 0x0810))
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#define CLK_ENABLE_CLK_CPUCL0_PCLKDBG ((void *)(CMU_CPUCL0_BASE + 0x0814))
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#define CLK_ENABLE_CLK_CPUCL0_HPM ((void *)(CMU_CPUCL0_BASE + 0x0820))
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#define CLKOUT_CMU_CPUCL0 ((void *)(CMU_CPUCL0_BASE + 0x0D00))
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#define CLKOUT_CMU_CPUCL0_DIV_STAT ((void *)(CMU_CPUCL0_BASE + 0x0D04))
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#define CMU_CPUCL0_SPARE0 ((void *)(CMU_CPUCL0_BASE + 0x0D08))
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#define CMU_CPUCL0_SPARE1 ((void *)(CMU_CPUCL0_BASE + 0x0D0C))
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#define CLK_ENABLE_PDN_CPUCL0 ((void *)(CMU_CPUCL0_BASE + 0x0E00))
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#define CPUCL0_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_CPUCL0_BASE + 0x0F00))
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#define CPUCL0_ARMCLK_STOPCTRL ((void *)(CMU_CPUCL0_BASE + 0x1000))
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#define CPUCL0_PWR_CTRL ((void *)(CMU_CPUCL0_BASE + 0x1020))
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#define CPUCL0_PWR_CTRL2 ((void *)(CMU_CPUCL0_BASE + 0x1024))
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#define CPUCL0_PWR_CTRL3 ((void *)(CMU_CPUCL0_BASE + 0x1028))
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#define CPUCL0_INTR_SPREAD_ENABLE ((void *)(CMU_CPUCL0_BASE + 0x1080))
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#define CPUCL0_INTR_SPREAD_USE_STANDBYWFI ((void *)(CMU_CPUCL0_BASE + 0x1084))
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#define CPUCL0_INTR_SPREAD_BLOCKING_DURATION ((void *)(CMU_CPUCL0_BASE + 0x1088))
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#define CPUCL1_PLL_LOCK ((void *)(CMU_CPUCL1_BASE + 0x0000))
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#define CPUCL1_PLL_CON0 ((void *)(CMU_CPUCL1_BASE + 0x0100))
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#define CPUCL1_PLL_CON1 ((void *)(CMU_CPUCL1_BASE + 0x0104))
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#define CLK_CON_MUX_CPUCL1_PLL ((void *)(CMU_CPUCL1_BASE + 0x0200))
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#define CLK_CON_MUX_CLKCMU_CPUCL1_SWITCH_USER ((void *)(CMU_CPUCL1_BASE + 0x0204))
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#define CLK_CON_MUX_CLK_CPUCL1 ((void *)(CMU_CPUCL1_BASE + 0x0208))
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#define CLK_CON_DIV_CLK_CPUCL1_1 ((void *)(CMU_CPUCL1_BASE + 0x0400))
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#define CLK_CON_DIV_CLK_CPUCL1_2 ((void *)(CMU_CPUCL1_BASE + 0x0404))
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#define CLK_CON_DIV_CLK_CPUCL1_ACLK ((void *)(CMU_CPUCL1_BASE + 0x0408))
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#define CLK_CON_DIV_CLK_CPUCL1_PCLK ((void *)(CMU_CPUCL1_BASE + 0x040C))
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#define CLK_CON_DIV_CLK_CPUCL1_ATCLK ((void *)(CMU_CPUCL1_BASE + 0x0410))
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#define CLK_CON_DIV_CLK_CPUCL1_PCLKDBG ((void *)(CMU_CPUCL1_BASE + 0x0414))
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#define CLK_CON_DIV_CLK_CPUCL1_CNTCLK ((void *)(CMU_CPUCL1_BASE + 0x0418))
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#define CLK_CON_DIV_CLK_CPUCL1_RUN_MONITOR ((void *)(CMU_CPUCL1_BASE + 0x041C))
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#define CLK_CON_DIV_CLK_CPUCL1_HPM ((void *)(CMU_CPUCL1_BASE + 0x0420))
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#define CLK_CON_DIV_CLK_CPUCL1_PLL ((void *)(CMU_CPUCL1_BASE + 0x0424))
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#define CLK_STAT_MUX_CPUCL1_PLL ((void *)(CMU_CPUCL1_BASE + 0x0600))
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#define CLK_STAT_MUX_CLKCMU_CPUCL1_SWITCH_USER ((void *)(CMU_CPUCL1_BASE + 0x0604))
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#define CLK_STAT_MUX_CLK_CPUCL1 ((void *)(CMU_CPUCL1_BASE + 0x0608))
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#define CLK_ENABLE_CLK_CPUCL1_OSCCLK ((void *)(CMU_CPUCL1_BASE + 0x0800))
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#define CLK_ENABLE_CLK_CPUCL1_ACLK ((void *)(CMU_CPUCL1_BASE + 0x0808))
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#define CLK_ENABLE_CLK_CPUCL1_PCLK ((void *)(CMU_CPUCL1_BASE + 0x080C))
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#define CLK_ENABLE_CLK_CPUCL1_PCLKDBG ((void *)(CMU_CPUCL1_BASE + 0x0814))
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#define CLK_ENABLE_CLK_CPUCL1_HPM ((void *)(CMU_CPUCL1_BASE + 0x0820))
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#define CLKOUT_CMU_CPUCL1 ((void *)(CMU_CPUCL1_BASE + 0x0D00))
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#define CLKOUT_CMU_CPUCL1_DIV_STAT ((void *)(CMU_CPUCL1_BASE + 0x0D04))
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#define CMU_CPUCL1_SPARE0 ((void *)(CMU_CPUCL1_BASE + 0x0D08))
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#define CMU_CPUCL1_SPARE1 ((void *)(CMU_CPUCL1_BASE + 0x0D0C))
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#define CLK_ENABLE_PDN_CPUCL1 ((void *)(CMU_CPUCL1_BASE + 0x0E00))
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#define CPUCL1_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_CPUCL1_BASE + 0x0F00))
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#define CPUCL1_ARMCLK_STOPCTRL ((void *)(CMU_CPUCL1_BASE + 0x1000))
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#define CPUCL1_PWR_CTRL ((void *)(CMU_CPUCL1_BASE + 0x1020))
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#define CPUCL1_PWR_CTRL2 ((void *)(CMU_CPUCL1_BASE + 0x1024))
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#define CPUCL1_PWR_CTRL3 ((void *)(CMU_CPUCL1_BASE + 0x1028))
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#define CPUCL1_INTR_SPREAD_ENABLE ((void *)(CMU_CPUCL1_BASE + 0x1080))
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#define CPUCL1_INTR_SPREAD_USE_STANDBYWFI ((void *)(CMU_CPUCL1_BASE + 0x1084))
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#define CPUCL1_INTR_SPREAD_BLOCKING_DURATION ((void *)(CMU_CPUCL1_BASE + 0x1088))
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#define G3D_PLL_LOCK ((void *)(CMU_G3D_BASE + 0x0000))
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#define G3D_PLL_CON0 ((void *)(CMU_G3D_BASE + 0x0100))
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#define G3D_PLL_CON1 ((void *)(CMU_G3D_BASE + 0x0104))
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#define CLK_CON_MUX_G3D_PLL ((void *)(CMU_G3D_BASE + 0x0200))
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#define CLK_CON_MUX_CLKCMU_G3D_SWITCH_USER ((void *)(CMU_G3D_BASE + 0x0204))
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#define CLK_CON_MUX_CLK_G3D ((void *)(CMU_G3D_BASE + 0x0208))
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#define CLK_CON_DIV_CLK_G3D_BUS ((void *)(CMU_G3D_BASE + 0x0400))
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#define CLK_CON_DIV_CLK_G3D_APB ((void *)(CMU_G3D_BASE + 0x0404))
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#define CLK_STAT_MUX_G3D_PLL ((void *)(CMU_G3D_BASE + 0x0600))
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#define CLK_STAT_MUX_CLKCMU_G3D_SWITCH_USER ((void *)(CMU_G3D_BASE + 0x0604))
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#define CLK_STAT_MUX_CLK_G3D ((void *)(CMU_G3D_BASE + 0x0608))
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#define CLK_ENABLE_CLK_G3D_OSCCLK ((void *)(CMU_G3D_BASE + 0x0800))
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#define CLK_ENABLE_CLK_G3D_BUS ((void *)(CMU_G3D_BASE + 0x0804))
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#define CLK_ENABLE_CLK_G3D_APB ((void *)(CMU_G3D_BASE + 0x0808))
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#define CLK_ENABLE_CLK_G3D_BUS_SECURE_CFW_G3D ((void *)(CMU_G3D_BASE + 0x0810))
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#define CLK_ENABLE_CLK_G3D_APB_SECURE_CFW_G3D ((void *)(CMU_G3D_BASE + 0x0814))
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#define CLKOUT_CMU_G3D ((void *)(CMU_G3D_BASE + 0x0D00))
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#define CLKOUT_CMU_G3D_DIV_STAT ((void *)(CMU_G3D_BASE + 0x0D04))
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#define CMU_G3D_SPARE0 ((void *)(CMU_G3D_BASE + 0x0D08))
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#define CMU_G3D_SPARE1 ((void *)(CMU_G3D_BASE + 0x0D0C))
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#define CLK_ENABLE_PDN_G3D ((void *)(CMU_G3D_BASE + 0x0E00))
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#define G3D_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_G3D_BASE + 0x0F00))
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#define CLK_STOPCTRL ((void *)(CMU_G3D_BASE + 0x1000))
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#define CLK_ENABLE_CLK_PERI_OSCCLK ((void *)(CMU_PERI_BASE + 0x0800))
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#define CLK_ENABLE_CLK_PERI_OSCCLK_SECURE_CHIPID ((void *)(CMU_PERI_BASE + 0x0804))
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#define CLK_ENABLE_CLK_PERI_BUS0 ((void *)(CMU_PERI_BASE + 0x0810))
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#define CLK_ENABLE_CLK_PERI_BUS1 ((void *)(CMU_PERI_BASE + 0x0814))
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#define CLK_ENABLE_CLK_PERI_BUS_SECURE_TZPC ((void *)(CMU_PERI_BASE + 0x0818))
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#define CLK_ENABLE_CLK_PERI_BUS_SECURE_CHIPID ((void *)(CMU_PERI_BASE + 0x081C))
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#define CLK_ENABLE_CLK_PERI_BUS_SECURE_OTP_CON_TOP ((void *)(CMU_PERI_BASE + 0x0820))
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#define CLK_ENABLE_CLK_PERI_BUS_SECURE_RTC_ALIVE ((void *)(CMU_PERI_BASE + 0x0824))
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#define CLK_ENABLE_CLK_PERI_BUS_SECURE_RTC_TOP ((void *)(CMU_PERI_BASE + 0x0828))
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#define CLK_ENABLE_CLK_PERI_UART_BTWIFIFM ((void *)(CMU_PERI_BASE + 0x0830))
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#define CLK_ENABLE_CLK_PERI_UART_DEBUG ((void *)(CMU_PERI_BASE + 0x0834))
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#define CLK_ENABLE_CLK_PERI_UART_SENSOR ((void *)(CMU_PERI_BASE + 0x0838))
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#define CLK_ENABLE_CLK_PERI_SPI_FRONTFROM ((void *)(CMU_PERI_BASE + 0x083C))
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#define CLK_ENABLE_CLK_PERI_SPI_REARFROM ((void *)(CMU_PERI_BASE + 0x0840))
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#define CLK_ENABLE_CLK_PERI_SPI_ESE ((void *)(CMU_PERI_BASE + 0x0844))
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#define CLK_ENABLE_CLK_PERI_SPI_VOICEPROCESSOR ((void *)(CMU_PERI_BASE + 0x0848))
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#define CLK_ENABLE_CLK_PERI_SPI_SENSORHUB ((void *)(CMU_PERI_BASE + 0x084C))
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#define CLKOUT_CMU_PERI ((void *)(CMU_PERI_BASE + 0x0D00))
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#define CLKOUT_CMU_PERI_DIV_STAT ((void *)(CMU_PERI_BASE + 0x0D04))
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#define CMU_PERI_SPARE0 ((void *)(CMU_PERI_BASE + 0x0D08))
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#define CMU_PERI_SPARE1 ((void *)(CMU_PERI_BASE + 0x0D0C))
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#define CLK_ENABLE_PDN_PERI ((void *)(CMU_PERI_BASE + 0x0E00))
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#define USB_PLL_LOCK ((void *)(CMU_FSYS_BASE + 0x0000))
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#define USB_PLL_CON0 ((void *)(CMU_FSYS_BASE + 0x0100))
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#define USB_PLL_CON1 ((void *)(CMU_FSYS_BASE + 0x0104))
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#define CLK_CON_MUX_USB_PLL ((void *)(CMU_FSYS_BASE + 0x0200))
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#define CLK_CON_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER ((void *)(CMU_FSYS_BASE + 0x0230))
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#define CLK_CON_MUX_CLKPHY_FSYS_UFS_TX0_SYMBOL_USER ((void *)(CMU_FSYS_BASE + 0x0234))
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#define CLK_CON_MUX_CLKPHY_FSYS_UFS_RX0_SYMBOL_USER ((void *)(CMU_FSYS_BASE + 0x0238))
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#define CLK_STAT_MUX_USB_PLL ((void *)(CMU_FSYS_BASE + 0x0600))
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#define CLK_STAT_MUX_CLKPHY_FSYS_USB20DRD_PHYCLOCK_USER ((void *)(CMU_FSYS_BASE + 0x0630))
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#define CLK_STAT_MUX_CLKPHY_FSYS_UFS_TX0_SYMBOL_USER ((void *)(CMU_FSYS_BASE + 0x0634))
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#define CLK_STAT_MUX_CLKPHY_FSYS_UFS_RX0_SYMBOL_USER ((void *)(CMU_FSYS_BASE + 0x0638))
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#define CLK_ENABLE_CLK_FSYS_OSCCLK ((void *)(CMU_FSYS_BASE + 0x0800))
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#define CLK_ENABLE_CLK_FSYS_BUS ((void *)(CMU_FSYS_BASE + 0x0804))
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#define CLK_ENABLE_CLK_FSYS_SECURE_RTIC ((void *)(CMU_FSYS_BASE + 0x0808))
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#define CLK_ENABLE_CLK_FSYS_SECURE_SSS ((void *)(CMU_FSYS_BASE + 0x080C))
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#define CLK_ENABLE_CLK_FSYS_SECURE_PDMA1 ((void *)(CMU_FSYS_BASE + 0x0810))
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#define CLK_ENABLE_CLK_FSYS_MMC0 ((void *)(CMU_FSYS_BASE + 0x0814))
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#define CLK_ENABLE_CLK_FSYS_MMC1 ((void *)(CMU_FSYS_BASE + 0x0818))
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#define CLK_ENABLE_CLK_FSYS_MMC2 ((void *)(CMU_FSYS_BASE + 0x081C))
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#define CLK_ENABLE_CLK_FSYS_UFSUNIPRO ((void *)(CMU_FSYS_BASE + 0x0820))
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#define CLK_ENABLE_CLK_FSYS_UFSUNIPRO_CFG ((void *)(CMU_FSYS_BASE + 0x0824))
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#define CLK_ENABLE_CLK_FSYS_USB20DRD_REFCLK ((void *)(CMU_FSYS_BASE + 0x0828))
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#define CLK_ENABLE_CLKPHY_FSYS_USB20DRD_PHYCLOCK ((void *)(CMU_FSYS_BASE + 0x0830))
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#define CLK_ENABLE_CLKPHY_FSYS_UFS_TX0_SYMBOL ((void *)(CMU_FSYS_BASE + 0x0834))
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#define CLK_ENABLE_CLKPHY_FSYS_UFS_RX0_SYMBOL ((void *)(CMU_FSYS_BASE + 0x0838))
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#define SECURE_ENABLE_BUSD0_FSYS ((void *)(CMU_FSYS_BASE + 0x08D0))
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#define CLKOUT_CMU_FSYS ((void *)(CMU_FSYS_BASE + 0x0D00))
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#define CLKOUT_CMU_FSYS_DIV_STAT ((void *)(CMU_FSYS_BASE + 0x0D04))
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#define CMU_FSYS_SPARE0 ((void *)(CMU_FSYS_BASE + 0x0D08))
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#define CMU_FSYS_SPARE1 ((void *)(CMU_FSYS_BASE + 0x0D0C))
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#define CLK_ENABLE_PDN_FSYS ((void *)(CMU_FSYS_BASE + 0x0E00))
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#define FSYS_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_FSYS_BASE + 0x0F00))
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#define CLK_CON_MUX_CLKCMU_MFCMSCL_MSCL_USER ((void *)(CMU_MFCMSCL_BASE + 0x0200))
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#define CLK_CON_MUX_CLKCMU_MFCMSCL_MFC_USER ((void *)(CMU_MFCMSCL_BASE + 0x0204))
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#define CLK_CON_DIV_CLK_MFCMSCL_APB ((void *)(CMU_MFCMSCL_BASE + 0x0400))
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#define CLK_STAT_MUX_CLKCMU_MFCMSCL_MSCL_USER ((void *)(CMU_MFCMSCL_BASE + 0x0600))
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#define CLK_STAT_MUX_CLKCMU_MFCMSCL_MFC_USER ((void *)(CMU_MFCMSCL_BASE + 0x0604))
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#define CLK_ENABLE_CLK_MFCMSCL_OSCCLK ((void *)(CMU_MFCMSCL_BASE + 0x0800))
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#define CLK_ENABLE_CLK_MFCMSCL_MSCL ((void *)(CMU_MFCMSCL_BASE + 0x0804))
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#define CLK_ENABLE_CLK_MFCMSCL_MFC ((void *)(CMU_MFCMSCL_BASE + 0x0808))
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#define CLK_ENABLE_CLK_MFCMSCL_APB ((void *)(CMU_MFCMSCL_BASE + 0x080C))
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#define CLK_ENABLE_CLK_MFCMSCL_SECURE_CFW_MSCL ((void *)(CMU_MFCMSCL_BASE + 0x0810))
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#define CLKOUT_CMU_MFCMSCL ((void *)(CMU_MFCMSCL_BASE + 0x0D00))
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#define CLKOUT_CMU_MFCMSCL_DIV_STAT ((void *)(CMU_MFCMSCL_BASE + 0x0D04))
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#define CMU_MFCMSCL_SPARE0 ((void *)(CMU_MFCMSCL_BASE + 0x0D08))
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#define CMU_MFCMSCL_SPARE1 ((void *)(CMU_MFCMSCL_BASE + 0x0D0C))
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#define CLK_ENABLE_PDN_MFCMSCL ((void *)(CMU_MFCMSCL_BASE + 0x0E00))
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#define MFCMSCL_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_MFCMSCL_BASE + 0x0F00))
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#define DISP_PLL_LOCK ((void *)(CMU_DISPAUD_BASE + 0x0000))
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#define AUD_PLL_LOCK ((void *)(CMU_DISPAUD_BASE + 0x00C0))
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#define DISP_PLL_CON0 ((void *)(CMU_DISPAUD_BASE + 0x0100))
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#define DISP_PLL_CON1 ((void *)(CMU_DISPAUD_BASE + 0x0104))
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#define AUD_PLL_CON0 ((void *)(CMU_DISPAUD_BASE + 0x01C0))
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#define AUD_PLL_CON1 ((void *)(CMU_DISPAUD_BASE + 0x01C4))
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#define AUD_PLL_CON2 ((void *)(CMU_DISPAUD_BASE + 0x01C8))
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#define CLK_CON_MUX_DISP_PLL ((void *)(CMU_DISPAUD_BASE + 0x0200))
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#define CLK_CON_MUX_AUD_PLL ((void *)(CMU_DISPAUD_BASE + 0x0204))
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#define CLK_CON_MUX_CLKCMU_DISPAUD_BUS_USER ((void *)(CMU_DISPAUD_BASE + 0x0210))
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#define CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER ((void *)(CMU_DISPAUD_BASE + 0x0214))
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#define CLK_CON_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER ((void *)(CMU_DISPAUD_BASE + 0x0218))
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#define CLK_CON_MUX_CLK_DISPAUD_DECON_INT_VCLK ((void *)(CMU_DISPAUD_BASE + 0x021C))
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#define CLK_CON_MUX_CLK_DISPAUD_DECON_INT_ECLK ((void *)(CMU_DISPAUD_BASE + 0x0220))
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#define CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER ((void *)(CMU_DISPAUD_BASE + 0x0224))
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#define CLK_CON_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER ((void *)(CMU_DISPAUD_BASE + 0x0228))
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#define CLK_CON_MUX_CLK_DISPAUD_MI2S ((void *)(CMU_DISPAUD_BASE + 0x022C))
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#define CLK_CON_DIV_CLK_DISPAUD_APB ((void *)(CMU_DISPAUD_BASE + 0x0400))
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#define CLK_CON_DIV_CLK_DISPAUD_DECON_INT_VCLK ((void *)(CMU_DISPAUD_BASE + 0x0404))
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#define CLK_CON_DIV_CLK_DISPAUD_DECON_INT_ECLK ((void *)(CMU_DISPAUD_BASE + 0x0408))
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#define CLK_CON_DIV_CLK_DISPAUD_MI2S ((void *)(CMU_DISPAUD_BASE + 0x040C))
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#define CLK_CON_DIV_CLK_DISPAUD_MIXER ((void *)(CMU_DISPAUD_BASE + 0x0410))
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#define CLK_STAT_MUX_DISP_PLL ((void *)(CMU_DISPAUD_BASE + 0x0600))
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#define CLK_STAT_MUX_AUD_PLL ((void *)(CMU_DISPAUD_BASE + 0x0604))
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#define CLK_STAT_MUX_CLKCMU_DISPAUD_BUS_USER ((void *)(CMU_DISPAUD_BASE + 0x0610))
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#define CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_VCLK_USER ((void *)(CMU_DISPAUD_BASE + 0x0614))
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#define CLK_STAT_MUX_CLKCMU_DISPAUD_DECON_INT_ECLK_USER ((void *)(CMU_DISPAUD_BASE + 0x0618))
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#define CLK_STAT_MUX_CLK_DISPAUD_DECON_INT_VCLK ((void *)(CMU_DISPAUD_BASE + 0x061C))
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#define CLK_STAT_MUX_CLK_DISPAUD_DECON_INT_ECLK ((void *)(CMU_DISPAUD_BASE + 0x0620))
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#define CLK_STAT_MUX_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS_USER ((void *)(CMU_DISPAUD_BASE + 0x0624))
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#define CLK_STAT_MUX_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0_USER ((void *)(CMU_DISPAUD_BASE + 0x0628))
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#define CLK_ENABLE_CLK_DISPAUD_OSCCLK ((void *)(CMU_DISPAUD_BASE + 0x0800))
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#define CLK_ENABLE_CLK_DISPAUD_BUS ((void *)(CMU_DISPAUD_BASE + 0x0810))
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#define CLK_ENABLE_CLK_DISPAUD_APB ((void *)(CMU_DISPAUD_BASE + 0x0814))
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#define CLK_ENABLE_CLK_DISPAUD_SECURE_CFW_DISP ((void *)(CMU_DISPAUD_BASE + 0x0818))
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#define CLK_ENABLE_CLK_DISPAUD_DECON_INT_VCLK ((void *)(CMU_DISPAUD_BASE + 0x081C))
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#define CLK_ENABLE_CLK_DISPAUD_DECON_INT_ECLK ((void *)(CMU_DISPAUD_BASE + 0x0820))
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#define CLK_ENABLE_CLKPHY_DISPAUD_MIPIPHY_TXBYTECLKHS ((void *)(CMU_DISPAUD_BASE + 0x0824))
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#define CLK_ENABLE_CLKPHY_DISPAUD_MIPIPHY_RXCLKESC0 ((void *)(CMU_DISPAUD_BASE + 0x0828))
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#define CLK_ENABLE_CLK_DISPAUD_MI2S ((void *)(CMU_DISPAUD_BASE + 0x082C))
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#define CLK_ENABLE_CLK_DISPAUD_MIXER ((void *)(CMU_DISPAUD_BASE + 0x0830))
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#define CLK_ENABLE_CLKIO_DISPAUD_MIXER_SCLK_AP ((void *)(CMU_DISPAUD_BASE + 0x0834))
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#define CLK_ENABLE_CLKIO_DISPAUD_MIXER_BCLK_BT ((void *)(CMU_DISPAUD_BASE + 0x0838))
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#define CLK_ENABLE_CLKIO_DISPAUD_MIXER_BCLK_CP ((void *)(CMU_DISPAUD_BASE + 0x083C))
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#define CLK_ENABLE_CLKIO_DISPAUD_MIXER_BCLK_FM ((void *)(CMU_DISPAUD_BASE + 0x0840))
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#define CLKOUT_CMU_DISPAUD ((void *)(CMU_DISPAUD_BASE + 0x0D00))
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#define CLKOUT_CMU_DISPAUD_DIV_STAT ((void *)(CMU_DISPAUD_BASE + 0x0D04))
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#define CMU_DISPAUD_SPARE0 ((void *)(CMU_DISPAUD_BASE + 0x0D08))
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#define CMU_DISPAUD_SPARE1 ((void *)(CMU_DISPAUD_BASE + 0x0D0C))
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#define CLK_ENABLE_PDN_DISPAUD ((void *)(CMU_DISPAUD_BASE + 0x0E00))
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#define DISPAUD_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_DISPAUD_BASE + 0x0F00))
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#define ISP_PLL_LOCK ((void *)(CMU_ISP_BASE + 0x0000))
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#define ISP_PLL_CON0 ((void *)(CMU_ISP_BASE + 0x0100))
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#define ISP_PLL_CON1 ((void *)(CMU_ISP_BASE + 0x0104))
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#define CLK_CON_MUX_ISP_PLL ((void *)(CMU_ISP_BASE + 0x0200))
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#define CLK_CON_MUX_CLKCMU_ISP_VRA_USER ((void *)(CMU_ISP_BASE + 0x0210))
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#define CLK_CON_MUX_CLKCMU_ISP_CAM_USER ((void *)(CMU_ISP_BASE + 0x0214))
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#define CLK_CON_MUX_CLKCMU_ISP_ISP_USER ((void *)(CMU_ISP_BASE + 0x0218))
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#define CLK_CON_MUX_CLK_ISP_VRA ((void *)(CMU_ISP_BASE + 0x0220))
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#define CLK_CON_MUX_CLK_ISP_CAM ((void *)(CMU_ISP_BASE + 0x0224))
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#define CLK_CON_MUX_CLK_ISP_ISP ((void *)(CMU_ISP_BASE + 0x0228))
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#define CLK_CON_MUX_CLK_ISP_ISPD ((void *)(CMU_ISP_BASE + 0x022C))
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#define CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER ((void *)(CMU_ISP_BASE + 0x0230))
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#define CLK_CON_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER ((void *)(CMU_ISP_BASE + 0x0234))
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#define CLK_CON_DIV_CLK_ISP_APB ((void *)(CMU_ISP_BASE + 0x0400))
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#define CLK_CON_DIV_CLK_ISP_CAM_HALF ((void *)(CMU_ISP_BASE + 0x0404))
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#define CLK_STAT_MUX_ISP_PLL ((void *)(CMU_ISP_BASE + 0x0600))
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#define CLK_STAT_MUX_CLKCMU_ISP_VRA_USER ((void *)(CMU_ISP_BASE + 0x0610))
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#define CLK_STAT_MUX_CLKCMU_ISP_CAM_USER ((void *)(CMU_ISP_BASE + 0x0614))
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#define CLK_STAT_MUX_CLKCMU_ISP_ISP_USER ((void *)(CMU_ISP_BASE + 0x0618))
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#define CLK_STAT_MUX_CLK_ISP_VRA ((void *)(CMU_ISP_BASE + 0x0620))
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#define CLK_STAT_MUX_CLK_ISP_ISP ((void *)(CMU_ISP_BASE + 0x0624))
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#define CLK_STAT_MUX_CLK_ISP_CAM ((void *)(CMU_ISP_BASE + 0x0628))
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#define CLK_STAT_MUX_CLK_ISP_ISPD ((void *)(CMU_ISP_BASE + 0x062C))
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#define CLK_STAT_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4_USER ((void *)(CMU_ISP_BASE + 0x0630))
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#define CLK_STAT_MUX_CLKPHY_ISP_S_RXBYTECLKHS0_S4S_USER ((void *)(CMU_ISP_BASE + 0x0634))
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#define CLK_ENABLE_CLK_ISP_OSCCLK ((void *)(CMU_ISP_BASE + 0x0800))
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#define CLK_ENABLE_CLK_ISP_VRA ((void *)(CMU_ISP_BASE + 0x0810))
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#define CLK_ENABLE_CLK_ISP_APB ((void *)(CMU_ISP_BASE + 0x0814))
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#define CLK_ENABLE_CLK_ISP_ISPD ((void *)(CMU_ISP_BASE + 0x0818))
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#define CLK_ENABLE_CLK_ISP_CAM ((void *)(CMU_ISP_BASE + 0x081C))
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#define CLK_ENABLE_CLK_ISP_CAM_HALF ((void *)(CMU_ISP_BASE + 0x0820))
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#define CLK_ENABLE_CLK_ISP_ISP ((void *)(CMU_ISP_BASE + 0x0824))
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#define CLK_ENABLE_CLKPHY_ISP_S_RXBYTECLKHS0_S4 ((void *)(CMU_ISP_BASE + 0x0828))
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#define CLK_ENABLE_CLKPHY_ISP_S_RXBYTECLKHS0_S4S ((void *)(CMU_ISP_BASE + 0x082C))
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#define CLKOUT_CMU_ISP ((void *)(CMU_ISP_BASE + 0x0D00))
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#define CLKOUT_CMU_ISP_DIV_STAT ((void *)(CMU_ISP_BASE + 0x0D04))
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#define CMU_ISP_SPARE0 ((void *)(CMU_ISP_BASE + 0x0D08))
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#define CMU_ISP_SPARE1 ((void *)(CMU_ISP_BASE + 0x0D0C))
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#define CLK_ENABLE_PDN_ISP ((void *)(CMU_ISP_BASE + 0x0E00))
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#define ISP_SFR_IGNORE_REQ_SYSCLK ((void *)(CMU_ISP_BASE + 0x0F00))
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#define CPUCL0_EMA_CON ((void *)(SYSREG_CPUCL0_BASE + 0x0330))
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#define CPUCL1_EMA_CON ((void *)(SYSREG_CPUCL1_BASE + 0x0330))
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#define G3D_EMA_RA1_HS_CON ((void *)(SYSREG_G3D_BASE + 0x0304))
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#define G3D_EMA_RF1_HS_CON ((void *)(SYSREG_G3D_BASE + 0x0314))
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#define G3D_EMA_RF2_HS_CON ((void *)(SYSREG_G3D_BASE + 0x031C))
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#endif
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