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android_kernel_samsung_on5x.../include/linux/muic/max77804-muic.h
awab228 f6dfaef42e Fixed MTP to work with TWRP
2018-06-19 23:16:04 +02:00

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/*
* max77804-muic.h - MUIC for the Maxim 77804
*
* Copyright (C) 2011 Samsung Electrnoics
* Seoyoung Jeong <seo0.jeong@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* This driver is based on max14577-muic.h
*
*/
#ifndef __MAX77804_MUIC_H__
#define __MAX77804_MUIC_H__
#define MUIC_DEV_NAME "muic-max77804"
/* max77804 muic register read/write related information defines. */
/* MAX77804 REGISTER ENABLE or DISABLE bit */
enum max77804_reg_bit_control {
MAX77804_DISABLE_BIT = 0,
MAX77804_ENABLE_BIT,
};
/* MAX77804 STATUS1 register */
#define STATUS1_ADC_SHIFT 0
#define STATUS1_ADCLOW_SHIFT 5
#define STATUS1_ADCERR_SHIFT 6
#define STATUS1_ADC1K_SHIFT 7
#define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
#define STATUS1_ADCLOW_MASK (0x1 << STATUS1_ADCLOW_SHIFT)
#define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
#define STATUS1_ADC1K_MASK (0x1 << STATUS1_ADC1K_SHIFT)
/* MAX77804 STATUS2 register */
#define STATUS2_CHGTYP_SHIFT 0
#define STATUS2_CHGDETRUN_SHIFT 3
#define STATUS2_DXOVP_SHIFT 5
#define STATUS2_VBVOLT_SHIFT 6
#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
#define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
#define STATUS2_DXOVP_MASK (0x1 << STATUS2_DXOVP_SHIFT)
#define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
/* MAX77804 CDETCTRL1 register */
#define CHGDETEN_SHIFT 0
#define CHGTYPM_SHIFT 1
#define DCHKTM_SHIFT 4
#define CHGDETEN_MASK (0x1 << CHGDETEN_SHIFT)
#define CHGTYPM_MASK (0x1 << CHGTYPM_SHIFT)
#define DCHKTM_MASK (0x1 << DCHKTM_SHIFT)
/* MAX77804 CONTROL1 register */
#define COMN1SW_SHIFT 0
#define COMP2SW_SHIFT 3
#define MICEN_SHIFT 6
#define IDBEN_SHIFT 7
#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
#define MICEN_MASK (0x1 << MICEN_SHIFT)
#define IDBEN_MASK (0x1 << IDBEN_SHIFT)
#define CLEAR_IDBEN_MICEN_MASK (COMN1SW_MASK | COMP2SW_MASK)
/* MAX77804 CONTROL2 register */
#define CTRL2_ADCLOWPWR_SHIFT 0
#define CTRL2_CPEN_SHIFT 2
#define CTRL2_ACCDET_SHIFT 5
#define CTRL2_ADCLOWPWR_MASK (0x1 << CTRL2_ADCLOWPWR_SHIFT)
#define CTRL2_CPEN_MASK (0x1 << CTRL2_CPEN_SHIFT)
#define CTRL2_ACCDET_MASK (0x1 << CTRL2_ACCDET_SHIFT)
#define CTRL2_CPEn1_LOWPWD0 ((MAX77804_ENABLE_BIT << CTRL2_CPEN_SHIFT) | \
(MAX77804_DISABLE_BIT << CTRL2_ADCLOWPWR_SHIFT))
#define CTRl2_CPEN0_LOWPWD1 ((MAX77804_DISABLE_BIT << CTRL2_CPEN_SHIFT) | \
(MAX77804_ENABLE_BIT << CTRL2_ADCLOWPWR_SHIFT))
/* MAX77804 CONTROL3 register */
#define CTRL3_JIGSET_SHIFT 0
#define CTRL3_BTLDSET_SHIFT 2
#define CTRL3_ADCDBSET_SHIFT 4
#define CTRL3_JIGSET_MASK (0x3 << CTRL3_JIGSET_SHIFT)
#define CTRL3_BTLDSET_MASK (0x3 << CTRL3_BTLDSET_SHIFT)
#define CTRL3_ADCDBSET_MASK (0x3 << CTRL3_ADCDBSET_SHIFT)
/* MAX77804 MUIC support for device tree */
struct of_max77804_muic_support {
bool notifier;
bool otg_dongle;
};
typedef enum {
VB_LOW = 0x00,
VB_HIGH = (0x1 << STATUS2_VBVOLT_SHIFT),
VB_DONTCARE = 0xff,
} vbvolt_t;
typedef enum {
CHGDETRUN_FALSE = 0x00,
CHGDETRUN_TRUE = (0x1 << STATUS2_CHGDETRUN_SHIFT),
CHGDETRUN_DONTCARE = 0xff,
} chgdetrun_t;
/* MAX77804 MUIC Output of USB Charger Detection */
typedef enum {
/* No Valid voltage at VB (Vvb < Vvbdet) */
CHGTYP_NO_VOLTAGE = 0x00,
/* Unknown (D+/D- does not present a valid USB charger signature) */
CHGTYP_USB = 0x01,
/* Charging Downstream Port */
CHGTYP_CDP = 0x02,
/* Dedicated Charger (D+/D- shorted) */
CHGTYP_DEDICATED_CHARGER = 0x03,
/* Special 500mA charger, max current 500mA */
CHGTYP_500MA = 0x04,
/* Special 1A charger, max current 1A */
CHGTYP_1A = 0x05,
/* Reserved for Future Use */
CHGTYP_RFU = 0x06,
/* Any charger type */
CHGTYP_ANY = 0xfd,
/* Don't care charger type */
CHGTYP_DONTCARE = 0xfe,
#if 0
/* Dead Battery Charging, max current 100mA */
CHGTYP_DB_100MA_CHARGER = 0x07,
CHGTYP_MAX,
CHGTYP_INIT,
CHGTYP_MIN = CHGTYP_NO_VOLTAGE
#endif
} chgtyp_t;
/* muic register value for COMN1, COMN2 in CTRL1 reg */
/*
* MAX77804 CONTROL1 register
* ID Bypass [7] / Mic En [6] / D+ [5:3] / D- [2:0]
* 0: ID Bypass Open / 1: IDB connect to UID
* 0: Mic En Open / 1: Mic connect to VB
* 000: Open / 001: USB / 010: Audio / 011: UART
*/
enum max77804_reg_ctrl1_val {
MAX77804_MUIC_CTRL1_ID_OPEN = 0x0,
MAX77804_MUIC_CTRL1_ID_BYPASS = 0x1,
MAX77804_MUIC_CTRL1_MIC_OPEN = 0x0,
MAX77804_MUIC_CTRL1_MIC_VB = 0x1,
MAX77804_MUIC_CTRL1_COM_OPEN = 0x00,
MAX77804_MUIC_CTRL1_COM_USB = 0x01,
MAX77804_MUIC_CTRL1_COM_AUDIO = 0x02,
MAX77804_MUIC_CTRL1_COM_UART = 0x03,
MAX77804_MUIC_CTRL1_COM_USB_CP = 0x04,
MAX77804_MUIC_CTRL1_COM_UART_CP = 0x05,
};
typedef enum {
CTRL1_OPEN = (MAX77804_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77804_MUIC_CTRL1_MIC_OPEN << MICEN_SHIFT) | \
(MAX77804_MUIC_CTRL1_COM_OPEN << COMP2SW_SHIFT) | \
(MAX77804_MUIC_CTRL1_COM_OPEN << COMN1SW_SHIFT),
CTRL1_USB = (MAX77804_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77804_MUIC_CTRL1_MIC_OPEN << MICEN_SHIFT) | \
(MAX77804_MUIC_CTRL1_COM_USB << COMP2SW_SHIFT) | \
(MAX77804_MUIC_CTRL1_COM_USB << COMN1SW_SHIFT),
CTRL1_AUDIO = (MAX77804_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77804_MUIC_CTRL1_MIC_OPEN << MICEN_SHIFT) | \
(MAX77804_MUIC_CTRL1_COM_AUDIO << COMP2SW_SHIFT) | \
(MAX77804_MUIC_CTRL1_COM_AUDIO << COMN1SW_SHIFT),
CTRL1_UART = (MAX77804_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77804_MUIC_CTRL1_MIC_OPEN << MICEN_SHIFT) | \
(MAX77804_MUIC_CTRL1_COM_UART << COMP2SW_SHIFT) | \
(MAX77804_MUIC_CTRL1_COM_UART << COMN1SW_SHIFT),
CTRL1_USB_CP = (MAX77804_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77804_MUIC_CTRL1_MIC_OPEN << MICEN_SHIFT) | \
(MAX77804_MUIC_CTRL1_COM_USB_CP << COMP2SW_SHIFT) | \
(MAX77804_MUIC_CTRL1_COM_USB_CP << COMN1SW_SHIFT),
CTRL1_UART_CP = (MAX77804_MUIC_CTRL1_ID_OPEN << IDBEN_SHIFT) | \
(MAX77804_MUIC_CTRL1_MIC_OPEN << MICEN_SHIFT) | \
(MAX77804_MUIC_CTRL1_COM_UART_CP << COMP2SW_SHIFT) | \
(MAX77804_MUIC_CTRL1_COM_UART_CP << COMN1SW_SHIFT),
} max77804_reg_ctrl1_t;
enum max77804_muic_reg_init_value {
/* CTRL3 ADCDbSet register. Manual Ctrl of ADC debounc Time: 25ms */
REG_CONTROL3_VALUE = (0x20),
};
extern struct device *switch_device;
#endif /* __MAX77804_MUIC_H__ */
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