mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-10-31 16:18:51 +01:00
341 lines
11 KiB
C
341 lines
11 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000 Toshiba Corporation
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*/
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#ifndef __ASM_TXX9_TX3927_H
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#define __ASM_TXX9_TX3927_H
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#define TX3927_REG_BASE 0xfffe0000UL
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#define TX3927_REG_SIZE 0x00010000
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#define TX3927_SDRAMC_REG (TX3927_REG_BASE + 0x8000)
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#define TX3927_ROMC_REG (TX3927_REG_BASE + 0x9000)
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#define TX3927_DMA_REG (TX3927_REG_BASE + 0xb000)
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#define TX3927_IRC_REG (TX3927_REG_BASE + 0xc000)
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#define TX3927_PCIC_REG (TX3927_REG_BASE + 0xd000)
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#define TX3927_CCFG_REG (TX3927_REG_BASE + 0xe000)
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#define TX3927_NR_TMR 3
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#define TX3927_TMR_REG(ch) (TX3927_REG_BASE + 0xf000 + (ch) * 0x100)
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#define TX3927_NR_SIO 2
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#define TX3927_SIO_REG(ch) (TX3927_REG_BASE + 0xf300 + (ch) * 0x100)
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#define TX3927_PIO_REG (TX3927_REG_BASE + 0xf500)
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struct tx3927_sdramc_reg {
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volatile unsigned long cr[8];
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volatile unsigned long tr[3];
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volatile unsigned long cmd;
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volatile unsigned long smrs[2];
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};
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struct tx3927_romc_reg {
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volatile unsigned long cr[8];
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};
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struct tx3927_dma_reg {
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struct tx3927_dma_ch_reg {
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volatile unsigned long cha;
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volatile unsigned long sar;
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volatile unsigned long dar;
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volatile unsigned long cntr;
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volatile unsigned long sair;
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volatile unsigned long dair;
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volatile unsigned long ccr;
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volatile unsigned long csr;
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} ch[4];
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volatile unsigned long dbr[8];
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volatile unsigned long tdhr;
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volatile unsigned long mcr;
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volatile unsigned long unused0;
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};
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#include <asm/byteorder.h>
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#ifdef __BIG_ENDIAN
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#define endian_def_s2(e1, e2) \
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volatile unsigned short e1, e2
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#define endian_def_sb2(e1, e2, e3) \
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volatile unsigned short e1;volatile unsigned char e2, e3
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#define endian_def_b2s(e1, e2, e3) \
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volatile unsigned char e1, e2;volatile unsigned short e3
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#define endian_def_b4(e1, e2, e3, e4) \
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volatile unsigned char e1, e2, e3, e4
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#else
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#define endian_def_s2(e1, e2) \
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volatile unsigned short e2, e1
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#define endian_def_sb2(e1, e2, e3) \
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volatile unsigned char e3, e2;volatile unsigned short e1
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#define endian_def_b2s(e1, e2, e3) \
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volatile unsigned short e3;volatile unsigned char e2, e1
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#define endian_def_b4(e1, e2, e3, e4) \
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volatile unsigned char e4, e3, e2, e1
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#endif
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struct tx3927_pcic_reg {
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endian_def_s2(did, vid);
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endian_def_s2(pcistat, pcicmd);
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endian_def_b4(cc, scc, rpli, rid);
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endian_def_b4(unused0, ht, mlt, cls);
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volatile unsigned long ioba; /* +10 */
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volatile unsigned long mba;
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volatile unsigned long unused1[5];
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endian_def_s2(svid, ssvid);
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volatile unsigned long unused2; /* +30 */
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endian_def_sb2(unused3, unused4, capptr);
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volatile unsigned long unused5;
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endian_def_b4(ml, mg, ip, il);
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volatile unsigned long unused6; /* +40 */
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volatile unsigned long istat;
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volatile unsigned long iim;
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volatile unsigned long rrt;
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volatile unsigned long unused7[3]; /* +50 */
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volatile unsigned long ipbmma;
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volatile unsigned long ipbioma; /* +60 */
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volatile unsigned long ilbmma;
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volatile unsigned long ilbioma;
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volatile unsigned long unused8[9];
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volatile unsigned long tc; /* +90 */
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volatile unsigned long tstat;
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volatile unsigned long tim;
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volatile unsigned long tccmd;
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volatile unsigned long pcirrt; /* +a0 */
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volatile unsigned long pcirrt_cmd;
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volatile unsigned long pcirrdt;
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volatile unsigned long unused9[3];
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volatile unsigned long tlboap;
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volatile unsigned long tlbiap;
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volatile unsigned long tlbmma; /* +c0 */
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volatile unsigned long tlbioma;
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volatile unsigned long sc_msg;
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volatile unsigned long sc_be;
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volatile unsigned long tbl; /* +d0 */
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volatile unsigned long unused10[3];
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volatile unsigned long pwmng; /* +e0 */
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volatile unsigned long pwmngs;
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volatile unsigned long unused11[6];
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volatile unsigned long req_trace; /* +100 */
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volatile unsigned long pbapmc;
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volatile unsigned long pbapms;
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volatile unsigned long pbapmim;
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volatile unsigned long bm; /* +110 */
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volatile unsigned long cpcibrs;
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volatile unsigned long cpcibgs;
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volatile unsigned long pbacs;
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volatile unsigned long iobas; /* +120 */
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volatile unsigned long mbas;
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volatile unsigned long lbc;
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volatile unsigned long lbstat;
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volatile unsigned long lbim; /* +130 */
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volatile unsigned long pcistatim;
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volatile unsigned long ica;
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volatile unsigned long icd;
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volatile unsigned long iiadp; /* +140 */
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volatile unsigned long iscdp;
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volatile unsigned long mmas;
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volatile unsigned long iomas;
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volatile unsigned long ipciaddr; /* +150 */
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volatile unsigned long ipcidata;
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volatile unsigned long ipcibe;
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};
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struct tx3927_ccfg_reg {
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volatile unsigned long ccfg;
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volatile unsigned long crir;
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volatile unsigned long pcfg;
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volatile unsigned long tear;
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volatile unsigned long pdcr;
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};
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/*
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* SDRAMC
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*/
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/*
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* ROMC
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*/
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/*
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* DMA
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*/
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/* bits for MCR */
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#define TX3927_DMA_MCR_EIS(ch) (0x10000000<<(ch))
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#define TX3927_DMA_MCR_DIS(ch) (0x01000000<<(ch))
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#define TX3927_DMA_MCR_RSFIF 0x00000080
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#define TX3927_DMA_MCR_FIFUM(ch) (0x00000008<<(ch))
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#define TX3927_DMA_MCR_LE 0x00000004
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#define TX3927_DMA_MCR_RPRT 0x00000002
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#define TX3927_DMA_MCR_MSTEN 0x00000001
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/* bits for CCRn */
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#define TX3927_DMA_CCR_DBINH 0x04000000
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#define TX3927_DMA_CCR_SBINH 0x02000000
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#define TX3927_DMA_CCR_CHRST 0x01000000
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#define TX3927_DMA_CCR_RVBYTE 0x00800000
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#define TX3927_DMA_CCR_ACKPOL 0x00400000
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#define TX3927_DMA_CCR_REQPL 0x00200000
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#define TX3927_DMA_CCR_EGREQ 0x00100000
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#define TX3927_DMA_CCR_CHDN 0x00080000
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#define TX3927_DMA_CCR_DNCTL 0x00060000
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#define TX3927_DMA_CCR_EXTRQ 0x00010000
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#define TX3927_DMA_CCR_INTRQD 0x0000e000
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#define TX3927_DMA_CCR_INTENE 0x00001000
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#define TX3927_DMA_CCR_INTENC 0x00000800
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#define TX3927_DMA_CCR_INTENT 0x00000400
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#define TX3927_DMA_CCR_CHNEN 0x00000200
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#define TX3927_DMA_CCR_XFACT 0x00000100
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#define TX3927_DMA_CCR_SNOP 0x00000080
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#define TX3927_DMA_CCR_DSTINC 0x00000040
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#define TX3927_DMA_CCR_SRCINC 0x00000020
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#define TX3927_DMA_CCR_XFSZ(order) (((order) << 2) & 0x0000001c)
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#define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2)
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#define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4)
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#define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5)
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#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6)
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#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7)
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#define TX3927_DMA_CCR_MEMIO 0x00000002
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#define TX3927_DMA_CCR_ONEAD 0x00000001
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/* bits for CSRn */
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#define TX3927_DMA_CSR_CHNACT 0x00000100
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#define TX3927_DMA_CSR_ABCHC 0x00000080
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#define TX3927_DMA_CSR_NCHNC 0x00000040
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#define TX3927_DMA_CSR_NTRNFC 0x00000020
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#define TX3927_DMA_CSR_EXTDN 0x00000010
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#define TX3927_DMA_CSR_CFERR 0x00000008
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#define TX3927_DMA_CSR_CHERR 0x00000004
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#define TX3927_DMA_CSR_DESERR 0x00000002
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#define TX3927_DMA_CSR_SORERR 0x00000001
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/*
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* IRC
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*/
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#define TX3927_IR_INT0 0
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#define TX3927_IR_INT1 1
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#define TX3927_IR_INT2 2
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#define TX3927_IR_INT3 3
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#define TX3927_IR_INT4 4
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#define TX3927_IR_INT5 5
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#define TX3927_IR_SIO0 6
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#define TX3927_IR_SIO1 7
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#define TX3927_IR_SIO(ch) (6 + (ch))
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#define TX3927_IR_DMA 8
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#define TX3927_IR_PIO 9
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#define TX3927_IR_PCI 10
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#define TX3927_IR_TMR(ch) (13 + (ch))
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#define TX3927_NUM_IR 16
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/*
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* PCIC
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*/
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/* bits for PCICMD */
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/* see PCI_COMMAND_XXX in linux/pci.h */
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/* bits for PCISTAT */
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/* see PCI_STATUS_XXX in linux/pci.h */
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#define PCI_STATUS_NEW_CAP 0x0010
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/* bits for ISTAT/IIM */
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#define TX3927_PCIC_IIM_ALL 0x00001600
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/* bits for TC */
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#define TX3927_PCIC_TC_OF16E 0x00000020
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#define TX3927_PCIC_TC_IF8E 0x00000010
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#define TX3927_PCIC_TC_OF8E 0x00000008
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/* bits for TSTAT/TIM */
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#define TX3927_PCIC_TIM_ALL 0x0003ffff
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/* bits for IOBA/MBA */
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/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */
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/* bits for PBAPMC */
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#define TX3927_PCIC_PBAPMC_RPBA 0x00000004
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#define TX3927_PCIC_PBAPMC_PBAEN 0x00000002
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#define TX3927_PCIC_PBAPMC_BMCEN 0x00000001
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/* bits for LBSTAT/LBIM */
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#define TX3927_PCIC_LBIM_ALL 0x0000003e
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/* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */
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#define TX3927_PCIC_PCISTATIM_ALL 0x0000f900
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/* bits for LBC */
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#define TX3927_PCIC_LBC_IBSE 0x00004000
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#define TX3927_PCIC_LBC_TIBSE 0x00002000
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#define TX3927_PCIC_LBC_TMFBSE 0x00001000
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#define TX3927_PCIC_LBC_HRST 0x00000800
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#define TX3927_PCIC_LBC_SRST 0x00000400
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#define TX3927_PCIC_LBC_EPCAD 0x00000200
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#define TX3927_PCIC_LBC_MSDSE 0x00000100
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#define TX3927_PCIC_LBC_CRR 0x00000080
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#define TX3927_PCIC_LBC_ILMDE 0x00000040
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#define TX3927_PCIC_LBC_ILIDE 0x00000020
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#define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad) ((ad) - 11)
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#define TX3927_PCIC_MAX_DEVNU TX3927_PCIC_IDSEL_AD_TO_SLOT(32)
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/*
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* CCFG
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*/
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/* CCFG : Chip Configuration */
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#define TX3927_CCFG_TLBOFF 0x00020000
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#define TX3927_CCFG_BEOW 0x00010000
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#define TX3927_CCFG_WR 0x00008000
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#define TX3927_CCFG_TOE 0x00004000
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#define TX3927_CCFG_PCIXARB 0x00002000
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#define TX3927_CCFG_PCI3 0x00001000
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#define TX3927_CCFG_PSNP 0x00000800
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#define TX3927_CCFG_PPRI 0x00000400
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#define TX3927_CCFG_PLLM 0x00000030
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#define TX3927_CCFG_ENDIAN 0x00000004
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#define TX3927_CCFG_HALT 0x00000002
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#define TX3927_CCFG_ACEHOLD 0x00000001
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/* PCFG : Pin Configuration */
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#define TX3927_PCFG_SYSCLKEN 0x08000000
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#define TX3927_PCFG_SDRCLKEN_ALL 0x07c00000
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#define TX3927_PCFG_SDRCLKEN(ch) (0x00400000<<(ch))
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#define TX3927_PCFG_PCICLKEN_ALL 0x003c0000
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#define TX3927_PCFG_PCICLKEN(ch) (0x00040000<<(ch))
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#define TX3927_PCFG_SELALL 0x0003ffff
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#define TX3927_PCFG_SELCS 0x00020000
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#define TX3927_PCFG_SELDSF 0x00010000
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#define TX3927_PCFG_SELSIOC_ALL 0x0000c000
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#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch))
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#define TX3927_PCFG_SELSIO_ALL 0x00003000
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#define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch))
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#define TX3927_PCFG_SELTMR_ALL 0x00000e00
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#define TX3927_PCFG_SELTMR(ch) (0x00000200<<(ch))
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#define TX3927_PCFG_SELDONE 0x00000100
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#define TX3927_PCFG_INTDMA_ALL 0x000000f0
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#define TX3927_PCFG_INTDMA(ch) (0x00000010<<(ch))
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#define TX3927_PCFG_SELDMA_ALL 0x0000000f
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#define TX3927_PCFG_SELDMA(ch) (0x00000001<<(ch))
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#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
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#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
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#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG)
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#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
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#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
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#define tx3927_sioptr(ch) ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
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#define tx3927_pioptr ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG)
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#define TX3927_REV_PCODE() (tx3927_ccfgptr->crir >> 16)
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#define TX3927_ROMC_BA(ch) (tx3927_romcptr->cr[(ch)] & 0xfff00000)
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#define TX3927_ROMC_SIZE(ch) \
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(0x00100000 << ((tx3927_romcptr->cr[(ch)] >> 8) & 0xf))
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#define TX3927_ROMC_WIDTH(ch) (32 >> ((tx3927_romcptr->cr[(ch)] >> 7) & 0x1))
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void tx3927_wdt_init(void);
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void tx3927_setup(void);
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void tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr);
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void tx3927_sio_init(unsigned int sclk, unsigned int cts_mask);
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struct pci_controller;
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void tx3927_pcic_setup(struct pci_controller *channel,
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unsigned long sdram_size, int extarb);
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void tx3927_setup_pcierr_irq(void);
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void tx3927_irq_init(void);
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void tx3927_mtd_init(int ch);
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#endif /* __ASM_TXX9_TX3927_H */
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