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31 lines
848 B
C
31 lines
848 B
C
/*
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* Device Tree binding constants for Exynos7570 clock controller.
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*/
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#ifndef _DT_BINDINGS_CLOCK_EXYNOS_7570_H
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#define _DT_BINDINGS_CLOCK_EXYNOS_7570_H
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/* Refers to clock id (enum exynos7570_clks) clk-exynos7570.c */
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#define OSCCLK 1
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#define CLK_FIN_PLL OSCCLK
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#define CLK_GATE_UART 20
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#define CLK_SCLK_UART 20
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#define CLK_PCLK_UART 360
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#define CLK_MCT 370
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#define CLK_DVFS_MIF 1000
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#define CLK_DVFS_MIF_SW 1001
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#define CLK_DVFS_INT 1002
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#define CLK_DVFS_CAM 1003
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#define CLK_DVFS_DISP 1004
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#define CLK_GATE_MSCL 610 /* see clk-exynos7570.c */
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#define CLK_GATE_JPEG 611 /* see clk-exynos7570.c */
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#define CLK_SYSMMU_BASE 1100
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#define CLK_VCLK_SYSMMU_MFC_MSCL (CLK_SYSMMU_BASE + 0)
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#define CLK_VCLK_SYSMMU_DISP_AUD (CLK_SYSMMU_BASE + 1)
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#define CLK_VCLK_SYSMMU_ISP (CLK_SYSMMU_BASE + 2)
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS_7570_H */
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