mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-08 09:08:05 -04:00
44 lines
1.3 KiB
C
44 lines
1.3 KiB
C
/*
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* Device Tree binding constants for Exynos8890 clock controller.
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*/
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#ifndef _DT_BINDINGS_CLOCK_EXYNOS_7870_H
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#define _DT_BINDINGS_CLOCK_EXYNOS_7870_H
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#define CLK_FIN_PLL 1
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#define CLK_UART_BAUD0 2
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#define CLK_GATE_PCLK0 3
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#define CLK_GATE_PCLK1 4
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#define CLK_GATE_PCLK2 5
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#define CLK_GATE_PCLK3 6
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#define CLK_GATE_PCLK4 7
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#define CLK_GATE_PCLK5 8
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#define CLK_GATE_UART0 9
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#define CLK_GATE_UART1 10
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#define CLK_GATE_UART2 11
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#define CLK_GATE_UART3 12
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#define CLK_GATE_UART4 13
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#define CLK_GATE_UART5 14
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#define CLK_UART0 15
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#define CLK_UART1 16
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#define CLK_UART2 17
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#define CLK_UART3 18
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#define CLK_UART4 19
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#define CLK_UART5 20
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#define CLK_MCT 21
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/* must be greater than maximal clock id */
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#define CLK_NR_CLKS 22
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#define CLK_SYSMMU_BASE 1100
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#define CLK_VCLK_SYSMMU_MFC (CLK_SYSMMU_BASE + 0)
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#define CLK_VCLK_SYSMMU_MSCL (CLK_SYSMMU_BASE + 1)
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#define CLK_VCLK_SYSMMU_ISP0 (CLK_SYSMMU_BASE + 2)
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#define CLK_VCLK_SYSMMU_CAM0 (CLK_SYSMMU_BASE + 3)
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#define CLK_VCLK_SYSMMU_CAM1 (CLK_SYSMMU_BASE + 4)
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#define CLK_VCLK_SYSMMU_AUD (CLK_SYSMMU_BASE + 5)
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#define CLK_VCLK_SYSMMU_DISP0 (CLK_SYSMMU_BASE + 6)
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#define CLK_VCLK_SYSMMU_DISP1 (CLK_SYSMMU_BASE + 7)
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS_8890_H */
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