mirror of
https://github.com/AetherDroid/android_kernel_samsung_on5xelte.git
synced 2025-09-07 16:58:04 -04:00
373 lines
9.6 KiB
C
373 lines
9.6 KiB
C
/* linux/drivers/devfreq/exynos8890_bus_mif.c
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*
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* Copyright (c) 2015 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Samsung EXYNOS8890 SoC MIF devfreq driver
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published
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* by the Free Software Foundation, either version 2 of the License,
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* or (at your option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/version.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/list.h>
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#include <linux/workqueue.h>
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#include <soc/samsung/exynos-devfreq.h>
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#include <soc/samsung/bts.h>
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#include <linux/apm-exynos.h>
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#include <soc/samsung/asv-exynos.h>
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#include "../../../drivers/soc/samsung/pwrcal/pwrcal.h"
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#include "../../../drivers/soc/samsung/pwrcal/S5E8890/S5E8890-vclk.h"
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#include "../governor.h"
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#if 0
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#include "exynos8890_ppmu.h"
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#endif
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#define DEVFREQ_MIF_REBOOT_FREQ (3078000/2)
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#define DEVFREQ_MIF_DIFF_FREQ (962000)
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#define DEVFREQ_MIF_CMOS_FREQ (468000)
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#define DEVFREQ_MIF_SWITCH_FREQ_HI (936000)
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#define DEVFREQ_MIF_SWITCH_FREQ (468000)
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#define SWITCH_CMOS_VOLT_OFFSET (56250)
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u32 sw_volt_table[2];
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int is_dll_on(void)
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{
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return cal_dfs_ext_ctrl(dvfs_mif, cal_dfs_mif_is_dll_on, 0);
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}
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EXPORT_SYMBOL_GPL(is_dll_on);
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static struct exynos_devfreq_data *mif_data;
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static int exynos8890_devfreq_mif_cmu_dump(struct device *dev,
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struct exynos_devfreq_data *data)
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{
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mutex_lock(&data->devfreq->lock);
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cal_vclk_dbg_info(dvfs_mif);
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mutex_unlock(&data->devfreq->lock);
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return 0;
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}
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static int exynos8890_devfreq_mif_reboot(struct device *dev,
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struct exynos_devfreq_data *data)
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{
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u32 freq = DEVFREQ_MIF_REBOOT_FREQ;
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data->max_freq = freq;
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data->devfreq->max_freq = data->max_freq;
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mutex_lock(&data->devfreq->lock);
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update_devfreq(data->devfreq);
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mutex_unlock(&data->devfreq->lock);
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return 0;
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}
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static int exynos8890_devfreq_cl_dvfs_start(struct exynos_devfreq_data *data)
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{
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int ret = 0;
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#ifdef CONFIG_EXYNOS_CL_DVFS_MIF
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ret = exynos_cl_dvfs_start(ID_MIF);
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#endif
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return ret;
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}
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static int exynos8890_devfreq_cl_dvfs_stop(u32 target_idx,
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struct exynos_devfreq_data *data)
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{
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int ret = 0;
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#ifdef CONFIG_EXYNOS_CL_DVFS_MIF
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ret = exynos_cl_dvfs_stop(ID_MIF, target_idx);
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#endif
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return ret;
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}
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static int exynos8890_devfreq_mif_get_switch_freq(u32 cur_freq, u32 new_freq,
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u32 *switch_freq)
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{
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*switch_freq = DEVFREQ_MIF_SWITCH_FREQ;
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if (cur_freq > DEVFREQ_MIF_DIFF_FREQ ||
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new_freq > DEVFREQ_MIF_DIFF_FREQ)
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*switch_freq = DEVFREQ_MIF_SWITCH_FREQ_HI;
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if (cur_freq <= DEVFREQ_MIF_CMOS_FREQ ||
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new_freq <= DEVFREQ_MIF_CMOS_FREQ)
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*switch_freq = DEVFREQ_MIF_SWITCH_FREQ;
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return 0;
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}
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static int exynos8890_devfreq_mif_get_switch_voltage(u32 cur_freq, u32 new_freq,
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struct exynos_devfreq_data *data)
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{
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/* if switching PLL is CMOS I/O mode level, it should be add a voltage offset */
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if (cur_freq <= DEVFREQ_MIF_CMOS_FREQ || new_freq <= DEVFREQ_MIF_CMOS_FREQ) {
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data->switch_volt = sw_volt_table[1] + SWITCH_CMOS_VOLT_OFFSET;
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goto out;
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}
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if (cur_freq > DEVFREQ_MIF_DIFF_FREQ && new_freq > DEVFREQ_MIF_DIFF_FREQ) {
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data->switch_volt = 0;
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goto out;
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}
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if (cur_freq >= new_freq)
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data->switch_volt = data->old_volt;
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else if (cur_freq < new_freq)
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data->switch_volt = data->new_volt;
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out:
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//pr_info("Selected switching voltage: %uuV\n", data->switch_volt);
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return 0;
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}
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static int exynos8890_devfreq_mif_get_freq(struct device *dev, u32 *cur_freq,
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struct exynos_devfreq_data *data)
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{
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*cur_freq = (u32)cal_dfs_get_rate(dvfs_mif);
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if (*cur_freq == 0) {
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dev_err(dev, "failed get frequency from CAL\n");
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return -EINVAL;
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}
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return 0;
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}
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static int exynos8890_devfreq_mif_change_to_switch_freq(struct device *dev,
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struct exynos_devfreq_data *data)
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{
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if (cal_dfs_set_rate_switch(dvfs_mif, data->switch_freq)) {
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dev_err(dev, "failed to set switching frequency by CAL (%uKhz for %uKhz)\n",
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data->switch_freq, data->new_freq);
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return -EINVAL;
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}
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return 0;
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}
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static int exynos8890_devfreq_mif_restore_from_switch_freq(struct device *dev,
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struct exynos_devfreq_data *data)
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{
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if (cal_dfs_set_rate(dvfs_mif, data->new_freq)) {
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dev_err(dev, "failed to set frequency by CAL (%uKhz)\n",
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data->new_freq);
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return -EINVAL;
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}
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return 0;
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}
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static int exynos8890_devfreq_mif_init_freq_table(struct device *dev,
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struct exynos_devfreq_data *data)
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{
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u32 max_freq, min_freq, cur_freq;
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struct dev_pm_opp *target_opp;
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u32 flags = 0;
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int i, ret;
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ret = cal_clk_enable(dvfs_mif);
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if (ret) {
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dev_err(dev, "failed to enable MIF\n");
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return -EINVAL;
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}
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max_freq = (u32)cal_dfs_get_max_freq(dvfs_mif);
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if (!max_freq) {
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dev_err(dev, "failed get max frequency\n");
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return -EINVAL;
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}
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dev_info(dev, "max_freq: %uKhz, get_max_freq: %uKhz\n",
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data->max_freq, max_freq);
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if (max_freq < data->max_freq) {
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rcu_read_lock();
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flags |= DEVFREQ_FLAG_LEAST_UPPER_BOUND;
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target_opp = devfreq_recommended_opp(dev, (unsigned long *)&max_freq, flags);
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if (IS_ERR(target_opp)) {
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rcu_read_unlock();
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dev_err(dev, "not found valid OPP for max_freq\n");
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return PTR_ERR(target_opp);
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}
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data->max_freq = dev_pm_opp_get_freq(target_opp);
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rcu_read_unlock();
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}
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min_freq = (u32)cal_dfs_get_min_freq(dvfs_mif);
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if (!min_freq) {
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dev_err(dev, "failed get min frequency\n");
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return -EINVAL;
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}
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dev_info(dev, "min_freq: %uKhz, get_min_freq: %uKhz\n",
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data->min_freq, min_freq);
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if (min_freq > data->min_freq) {
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rcu_read_lock();
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flags &= ~DEVFREQ_FLAG_LEAST_UPPER_BOUND;
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target_opp = devfreq_recommended_opp(dev, (unsigned long *)&min_freq, flags);
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if (IS_ERR(target_opp)) {
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rcu_read_unlock();
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dev_err(dev, "not found valid OPP for min_freq\n");
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return PTR_ERR(target_opp);
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}
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data->min_freq = dev_pm_opp_get_freq(target_opp);
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rcu_read_unlock();
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}
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dev_info(dev, "min_freq: %uKhz, max_freq: %uKhz\n",
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data->min_freq, data->max_freq);
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cur_freq = cal_dfs_get_rate(dvfs_mif);
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dev_info(dev, "current frequency: %uKhz\n", cur_freq);
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for (i = 0; i < data->max_state; i++) {
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if (data->opp_list[i].freq > data->max_freq ||
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data->opp_list[i].freq < data->min_freq)
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dev_pm_opp_disable(dev, (unsigned long)data->opp_list[i].freq);
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}
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return 0;
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}
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static int exynos8890_devfreq_mif_get_volt_table(struct device *dev, u32 *volt_table,
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struct exynos_devfreq_data *data)
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{
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struct dvfs_rate_volt mif_rate_volt[data->max_state];
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int table_size;
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int i;
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table_size = cal_dfs_get_rate_asv_table(dvfs_mif, mif_rate_volt);
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if (!table_size) {
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dev_err(dev, "failed get ASV table\n");
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return -ENODEV;
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}
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if (table_size != data->max_state) {
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dev_err(dev, "ASV table size is not matched\n");
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return -ENODEV;
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}
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for (i = 0; i < data->max_state; i++) {
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if (data->opp_list[i].freq != (u32)(mif_rate_volt[i].rate)) {
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dev_err(dev, "Freq table is not matched(%u:%u)\n",
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data->opp_list[i].freq, (u32)mif_rate_volt[i].rate);
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return -EINVAL;
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}
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volt_table[i] = (u32)mif_rate_volt[i].volt;
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/* Fill switch voltage table */
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if (!sw_volt_table[0] &&
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data->opp_list[i].freq < DEVFREQ_MIF_SWITCH_FREQ_HI)
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sw_volt_table[0] = (u32)mif_rate_volt[i-1].volt;
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if (!sw_volt_table[1] &&
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data->opp_list[i].freq < DEVFREQ_MIF_SWITCH_FREQ)
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sw_volt_table[1] = (u32)mif_rate_volt[i-1].volt;
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}
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dev_info(dev, "SW_volt %uuV in freq %uKhz\n",
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sw_volt_table[0], DEVFREQ_MIF_SWITCH_FREQ_HI);
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dev_info(dev, "SW_volt %uuV in freq %uKhz\n",
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sw_volt_table[1], DEVFREQ_MIF_SWITCH_FREQ);
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return 0;
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}
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static int exynos8890_mif_ppmu_register(struct device *dev,
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struct exynos_devfreq_data *data)
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{
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#if 0
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int ret;
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struct devfreq_exynos *ppmu_data = (struct devfreq_exynos *)&data->ppmu_data;
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ret = exynos8890_devfreq_register(ppmu_data);
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if (ret) {
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dev_err(dev, "failed ppmu register\n");
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return ret;
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}
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ret = exynos8890_ppmu_register_notifier(MIF, &data->ppmu_nb->nb);
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if (ret) {
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dev_err(dev, "failed ppmu notifier register\n");
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return ret;
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}
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#endif
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return 0;
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}
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static int exynos8890_mif_ppmu_unregister(struct device *dev,
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struct exynos_devfreq_data *data)
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{
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#if 0
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exynos8890_ppmu_unregister_notifier(MIF, &data->ppmu_nb->nb);
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#endif
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return 0;
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}
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static int exynos8890_devfreq_mif_init(struct device *dev,
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struct exynos_devfreq_data *data)
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{
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return 0;
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}
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static int exynos8890_devfreq_mif_exit(struct device *dev,
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struct exynos_devfreq_data *data)
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{
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return 0;
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}
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static int __init exynos8890_devfreq_mif_init_prepare(struct exynos_devfreq_data *data)
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{
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data->ops.init = exynos8890_devfreq_mif_init;
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data->ops.exit = exynos8890_devfreq_mif_exit;
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data->ops.get_volt_table = exynos8890_devfreq_mif_get_volt_table;
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data->ops.ppmu_register = exynos8890_mif_ppmu_register;
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data->ops.ppmu_unregister = exynos8890_mif_ppmu_unregister;
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data->ops.get_switch_freq = exynos8890_devfreq_mif_get_switch_freq;
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data->ops.get_switch_voltage = exynos8890_devfreq_mif_get_switch_voltage;
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data->ops.get_freq = exynos8890_devfreq_mif_get_freq;
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data->ops.change_to_switch_freq = exynos8890_devfreq_mif_change_to_switch_freq;
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data->ops.restore_from_switch_freq = exynos8890_devfreq_mif_restore_from_switch_freq;
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data->ops.init_freq_table = exynos8890_devfreq_mif_init_freq_table;
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data->ops.cl_dvfs_start = exynos8890_devfreq_cl_dvfs_start;
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data->ops.cl_dvfs_stop = exynos8890_devfreq_cl_dvfs_stop;
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data->ops.reboot = exynos8890_devfreq_mif_reboot;
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data->ops.cmu_dump = exynos8890_devfreq_mif_cmu_dump;
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mif_data = data;
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return 0;
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}
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static int __init exynos8890_devfreq_mif_initcall(void)
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{
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if (register_exynos_devfreq_init_prepare(DEVFREQ_MIF,
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exynos8890_devfreq_mif_init_prepare))
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return -EINVAL;
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return 0;
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}
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fs_initcall(exynos8890_devfreq_mif_initcall);
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